Data processing circuit, display driving chip and display device

Abstract

The utility model provides a data processing circuit, a display driving chip and a display device. The data processing circuit comprises a decoding module used for decoding an input signal into a data signal; the oscillation module is used for generating a clock signal with a stable period; the encoding module is used for processing the data signal into an output signal according to the clock signal, the variation trend of the output signal is the same as that of the input signal, the period of the output signal is integral multiple of the period of the clock signal, and the output signal has a preset duty ratio to represent preset data. The data processing circuit provided by the utility model can accurately identify data and reconstruct an output signal with a stable period and a constant duty ratio under the condition that an input signal is unstable.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuit design, and more specifically, to a data processing circuit, a display driving chip and a display device. Background Art

[0002] At present, light-emitting diodes (LEDs) have the advantages of high brightness, high intensity, long life, easy splicing, energy saving, etc., and are widely used in indoor and outdoor displays of various sizes, such as widely used in the fields of sports, advertising, finance, exhibitions, transportation, etc.

[0003] In the design of LED integrated circuits, it is necessary to cascade LED chips to realize large-size LED displays. As Figure 1 shown, the single-line cascaded LED chip cascading system 100 includes a control card 110 and multiple single-line cascaded chips 120. The first chip 120 is directly connected to the control card 110 and receives the data information sent by the control card 110. The subsequent chip receives the signal converted by its previous-stage chip. The converted signal generally adopts a single-line return-to-zero code communication protocol. However, in actual applications, the control signals sent by the control card 110 may adopt protocols with different timings, and their periods and duty cycles are usually variable. The change in frequency may cause phase errors in the signals sent by the chip 120, and the change in duty cycle may cause data recognition errors in the chip 120.

[0004] Therefore, it is desirable to provide an improved data processing circuit to be compatible with protocols with different timings. Summary of the Utility Model

[0005] In view of the above problems, the purpose of the utility model is to provide a data processing circuit, a display driving chip and a display device, so as to provide a stable return-to-zero code signal for cascaded chips.

[0006] According to the first aspect of the utility model, a data processing circuit is provided, including: a decoding module for decoding an input signal into a data signal; an oscillation module for generating a clock signal with a stable period; an encoding module connected to the oscillation module and the decoding module respectively, for processing the data signal into an output signal according to the clock signal with a stable period, wherein the change trend of the output signal is the same as that of the input signal, the period of the output signal is an integer multiple of the period of the clock signal, and the output signal has a predetermined duty cycle to represent predetermined data.

[0007] Optionally, it further includes: an enable signal generation module, connected to the oscillation module, for generating an enable signal according to the input signal and sending the enable signal to the oscillation module, wherein the oscillation module generates a clock signal with a stable period according to the enable signal. In a single data period, when a rising edge appears in the input signal, the enable signal generation module generates the enable signal in an effective state, so that the oscillation module starts to generate the clock signal, and the output signal represents a predetermined data in one data period.

[0008] Optionally, the clock signal has N rising edges in a single data period, where N is an integer greater than or equal to 3. When the first rising edge appears in the clock signal in a single data period, the encoding module is triggered to switch the output signal from a first level to a second level; when the nth rising edge appears in the clock signal in a single data period, if the input signal is in an effective state, the decoding module generates a first data, and the encoding module keeps the output signal at the second level. If the input signal is in an invalid state, the decoding module generates a second data, and the encoding module switches the output signal from the second level to the first level, where n is an integer greater than 1 and less than N; when the Nth rising edge appears in the clock signal in a single data period, the enable signal generation module generates the enable signal in an invalid state and triggers the encoding module to keep the output signal at the first level.

[0009] Optionally, the oscillation module adjusts the duty cycle of the output signal by setting the values of N and n, so that when the duty cycles of the input signal and the output signal represent the same data, the duty cycle of the output signal is less than the duty cycle of the input signal.

[0010] Optionally, the oscillation module sets N to 3 and n to 2. When the input signal represents the first data and the second data respectively, the duration ratio of maintaining the second level is 3:1; when the output signal represents the first data and the second data respectively, the duration ratio of maintaining the second level is 2:1.

[0011] Optionally, the oscillation module sets N to 3 and n to 2. The period of the input signal is greater than 2.5 times the period of the clock signal. When the output signal represents the first data, the duration of the output signal maintaining the second level is greater than 1.5 times the period of the clock signal. When the output signal represents the second data, the duration of the output signal maintaining the second level is less than 1.5 times the period of the clock signal.

[0012] Optionally, it further includes: a driving module for processing the data signal into driving data; and a storage module, whose input end is connected to the decoding module, and output ends are respectively connected to the driving module and the encoding module, for performing pulse width modulation processing on the data signal, and sending the data signal after pulse width modulation processing to the driving module and the encoding module respectively.

[0013] According to a second aspect of the present invention, there is provided a display driving chip including the data processing circuit as described above.

[0014] According to a third aspect of the present invention, there is provided a display device including: an LED display panel; a single-line cascade control device having multi-stage display driving chips, connected to the LED display panel, and at least the first-stage display driving chip includes the data processing circuit as described above.

[0015] Optionally, the LED display panel is selected from any one of a submillimeter light-emitting diode display panel, a micro light-emitting diode display panel, a quantum dot light-emitting diode display panel, and an organic light-emitting diode display panel.

[0016] The data processing circuit, display driving chip, and display device provided by the present invention can accurately decode and identify "1" and "0" data when the input signal provided by the control card is unstable, and reconstruct an output signal with a stable data waveform and send it to the next-stage chip. Since the specific values of the period and duty cycle of the output signal are determined by the clock signal with a stable period provided by the oscillation module, and the data represented by the output signal is determined by the input signal, it can be ensured that the reconstructed output signal is a signal with accurate data, stable period, and constant duty cycle. A constant duty cycle means that the output signal has a constant duty cycle when representing the corresponding data.

[0017] In some embodiments of the data processing circuit, display driving chip, and display device, when the input signal represents the first data and the second data, the duration ratio of the second level maintained is 3:1; while when the reconstructed output signal represents the first data and the second data, the duration ratio of the second level maintained is 2:1, so that a smaller input signal period can be supported, and the fourth rising edge of the clock signal is not required.

[0018] In some embodiments of the data processing circuit, display driving chip, and display device, by setting the values of N and n, the duty cycle of the output signal can be adjusted; further, when N is set to 3 and n is set to 2, within a single data cycle, only 3 rising edges of the clock signal (the duration of the last rising edge maintaining a high level can be very short) are required to decode the input signal and reconstruct the output signal, and the required clock signal frequency is low and the power consumption is small.

[0019] In some embodiments of the data processing circuit, the display driving chip, and the display device, within a single data cycle, the falling edge of the enable signal appears at the last rising edge of the clock signal, which can ensure that both the duty cycle and the period of the output signal are stable and determined values, facilitating the decoding of the output signal by the subsequent-stage circuit / chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0021] Figure 1 A schematic diagram of a display driving system is shown.

[0022] Figure 2 A schematic diagram of a data processing circuit according to an embodiment of the present invention is shown.

[0023] Figure 3 A timing diagram of a data processing circuit according to an embodiment of the present invention is shown.

[0024] Figure 4 A flowchart of a data processing method for a data processing circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, like elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0026] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention may be implemented without these specific details.

[0027] It should be understood that in the embodiments of the present application, the connection / coupling of A and B means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0028] Embodiments of the data processing circuit, the display driving chip, and the display device provided by the present application will be described below with reference to the accompanying drawings.

[0029] Figure 2 A schematic diagram of a data processing circuit according to an embodiment of the present invention is shown.

[0030] As Figure 2As shown, the data processing circuit 200 includes a decoding module 210, an oscillation module 220, and an encoding module 230. In some alternative embodiments, the data processing circuit 200 further includes an enable signal generation module 240. In some alternative embodiments, the data processing circuit 200 further includes a storage module 250 and a driving module 260.

[0031] The decoding module 210 is configured to decode the input signal DIN into a data signal DATA; the oscillation module 220 is configured to generate a clock signal CLK with a stable period; the encoding module 230 is configured to process the data signal DATA into an output signal DOUT according to the clock signal CLK with a stable period, wherein the output signal DOUT has the same change trend as the input signal DIN, the period of the output signal DOUT is an integer multiple of the period of the clock signal CLK, and the output signal DOUT has a predetermined duty cycle to represent predetermined data.

[0032] In this embodiment, the output signal DOUT has the same change trend as the input signal DIN, so the data represented by the output signal DOUT is accurate; the period of the output signal DOUT is an integer multiple of the period of the clock signal CLK, and the output signal DOUT has a predetermined duty cycle to represent predetermined data, so the output signal DOUT is a signal with a stable period and a constant duty cycle. A constant duty cycle means that the output signal DOUT has a constant duty cycle when representing the corresponding data. For example, when the output signal DOUT represents the data "1", the duty cycle is 1 / 2, and when the output signal DOUT represents the data "0", the duty cycle is 1 / 4.

[0033] Specifically, in the data processing circuit 200, an enable signal generation module 240 is further included, which is configured to generate an enable signal OSC_EN according to the input signal DIN. Among them, the oscillation module 220 generates a clock signal CLK with a stable period according to the enable signal OSC_EN. In a single data cycle, when a rising edge appears in the input signal DIN, the enable signal generation module 240 generates an enable signal OSC_EN in an effective state, so that the oscillation module 220 starts to generate the clock signal CLK. The output signal DOUT represents a predetermined data in one data cycle. The data cycle is consistent with the period of the enable signal OSC_EN and also consistent with the period of the output signal DOUT.

[0034] In this embodiment, the clock signal CLK has N rising edges within a single data cycle, where N is an integer greater than or equal to 3. When the first rising edge of the clock signal CLK appears within a single data cycle, it triggers the encoding module 230 to switch the output signal DOUT from the first level (e.g., low level) to the second level (e.g., high level); when the nth rising edge of the clock signal CLK appears within a single data cycle, if the input signal DIN is in a valid state, the decoding module 210 generates the first data (e.g., data "1"), and this first data triggers the encoding module 230 to hold the output signal DOUT at the second level. If the input signal DIN is in an invalid state, the decoding module 210 generates the second data (e.g., data "0"), and this second data triggers the encoding module 230 to switch the output signal DOUT from the second level to the first level. Here, n is an integer greater than 1 and less than N; when the Nth rising edge of the clock signal CLK appears within a single data cycle, the enable signal generation module 240 generates an enable signal OSC_EN in an invalid state, and the clock signal CLK triggers the encoding module 230 to hold the output signal DOUT at the first level.

[0035] In this embodiment, within a single data cycle, the falling edge of the enable signal OSC_EN appears at the last rising edge of the clock signal CLK, which can ensure that both the duty cycle and the period of the output signal DOUT are stable and determined values, facilitating the subsequent circuit / chip to decode the output signal DOUT.

[0036] Optionally, by setting the oscillation module 220, the values of N and n are set to adjust the duty cycle of the output signal DOUT, such that when the duty cycles of the input signal DIN and the output signal DOUT represent the same data, the duty cycle of the output signal DOUT is less than that of the input signal DIN.

[0037] As an example, by setting the oscillation module 220, N is set to 3 and n is set to 2. In this example, the period of the input signal DIN is greater than 2.5 times the period of the clock signal CLK, so as to facilitate the output signal DOUT to have the same change trend as the output signal DIN; when the output signal DOUT represents the first data, the duration for which the output signal DOUT maintains the second level is greater than 1.5 times the period of the clock signal CLK, and when the output signal DOUT represents the second data, the duration for which the output signal DOUT maintains the second level is less than 1.5 times the period of the clock signal CLK; to ensure correct data recognition.

[0038] In this example, within a single data cycle, only 3 rising edges of the clock signal CLK (the duration for which the last rising edge maintains a high level can be very short) are required to decode the input signal DIN and reconstruct the output signal DOUT, and the required clock signal CLK frequency is low and the power consumption is small.

[0039] In this example, when the input signal DIN represents the first data and the second data, the duration ratio of maintaining the second level is 3:1; while when the reconstructed output signal DOUT represents the first data and the second data, the duration ratio of maintaining the second level is 2:1. This can support a smaller input signal period and does not require a clock signal to generate a fourth rising edge.

[0040] In some alternative embodiments, the data processing circuit 200 further includes a storage module 250 and a driving module 260. The storage module 250 is connected to the decoding module 210 and is configured to perform pulse width modulation processing on the data signal DATA, and send the pulse width modulated data signal DATA to the driving module 250 and the encoding module 230 respectively. The driving module 260 is configured to process the data signal DATA into driving data to facilitate driving the LED display panel for display.

[0041] As an example, both the input signal DIN and the output signal DOUT are return-to-zero code signals, and a single-line return-to-zero code communication protocol is used. The decoding module 210 is, for example, a single-line decoding module, configured to identify the received return-to-zero code signal and decode the cycle frequency of the return-to-zero code signal and the data represented within each data cycle to obtain a corresponding data signal; the storage module 250 is, for example, a first-in first-out storage module, which receives and stores the data signal, and sends the data signal to the driving module 260 and the encoding module 230 respectively; the driving module 260 converts the data signal into PWM display data and sends it to the driving end of the display panel to control the display time of constant current driving; the encoding module 230 reconstructs the return-to-zero code signal based on the data signal and sends it to the next-stage circuit / chip.

[0042] The data processing circuit 200 according to the embodiment of the present invention can accurately decode and identify the data signal DATA in the case where the input signal DIN is unstable, and reconstruct an output signal DOUT with a stable data waveform. Since the specific values of the period and duty cycle of the output signal DOUT are determined by the clock signal CLK with a stable period provided by the oscillation module 220, and the data represented by the output signal DOUT is determined by the input signal DIN, it can be ensured that the reconstructed output signal DOUT is a signal with accurate data, stable period and constant duty cycle. Constant duty cycle means that the output signal DOUT has a constant duty cycle when representing the corresponding data. For example, when the output signal DOUT represents the data "1", the duty cycle is 1 / 2, and when the output signal DOUT represents the data "0", the duty cycle is 1 / 4.

[0043] Some examples of the data processing circuit according to the embodiment of the present invention are described above. However, the embodiments of the present invention are not limited thereto, and there may be other ways of extension and deformation.

[0044] For example, it should be understood that the first level and the second level in the foregoing embodiments may be replaced with a zero reference potential, other non-zero reference potentials (with positive or negative voltage amplitudes), or a reference signal with a controlled change in alternative embodiments.

[0045] For another example, the foregoing data processing circuit may be a discrete device, may be used as a circuit unit, or may be combined into a highly efficient and high-precision LED chip cascade system or a single-wire cascade control device.

[0046] Meanwhile, those of ordinary skill in the art can realize that for the structures and methods of the examples described in combination with the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure, but such implementation should not be considered to exceed the scope of this application. And it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of this application are illustrative examples and do not impose any limitations on the embodiments of this application.

[0047] Figure 3 A timing diagram of the data processing circuit according to an embodiment of the present invention is shown. The following Figure 3 will describe in detail the working timing of the data processing circuit 200 according to an embodiment of the present invention. It should be understood that Figure 3 merely as an exemplary timing diagram, the present invention is not limited thereto and should not unduly limit the protection scope of this application. Those skilled in the art can obtain many variations, alternatives, and modifications. For example, when setting different numbers of rising edges of the clock signal CLK, there will be more types of waveforms of the output signal DOUT.

[0048] In Figure 3 , DIN represents an input signal, OSC_EN represents an enable signal, CLK represents a clock signal, DATA represents a data signal, DOUT represents an output signal, T1, T2, and T3 are respectively the rising edge moments of the clock signal CLK, T1H is the duration for which the input signal DIN maintains the second level when representing the first data, T0H is the duration for which the input signal DIN maintains the second level when representing the second data, the first level is a low level, the second level is a high level, and Tdin is the period of the input signal DIN. In some embodiments, the value range of T0H is 0.15 to 0.45 μs, the value range of T1H is 0.75 to 1.05 μs, and the value range of Tdin is 0.9 to 1.5 μs. For example, T0H is 0.3 μs, T1H is 0.9 μs, and Tdin is 1.2 μs.

[0049] Please refer to Figure 2 and Figure 3, the enable signal generation module 240 receives the input signal DIN. When the input signal DIN switches from the first level to the second level, it triggers the enable signal OSC_EN generated by the enable signal generation module 240 to become the active state. The oscillation module 220 receives the enable signal OSC_EN in the active state and starts generating the clock signal CLK. The oscillation module 220 can configure the generation method of the clock signal CLK. For example, when receiving the enable signal OSC_EN in the active state, within one period of the enable signal OSC_EN, the oscillation module 220 generates a clock signal CLK with N rising edges, and the frequency of the clock signal CLK is stable.

[0050] In this embodiment, within one period of the enable signal OSC_EN, that is, within one data period, the number of rising edges of the clock signal CLK is 3. It should be understood that the number of rising edges of the clock signal CLK can also be 4, 5 or more. When the number of rising edges of the clock signal CLK is 3, within a single data period, only 3 rising edges of the clock signal CLK (the duration for which the last rising edge maintains a high level can be very short) are required to decode the input signal DIN and reconstruct the output signal DOUT, and the required frequency of the clock signal CLK is low and the power consumption is small.

[0051] At time T1, the first rising edge of the clock signal CLK appears. At this time, the encoding module 230 detects the first rising edge of the clock signal CLK and raises the output signal DOUT from the first level to the second level.

[0052] At time T2, the second rising edge of the clock signal CLK appears. At this time, the decoding module 210 and the encoding module 230 detect the second rising edge of the clock signal CLK. The decoding module 210 will detect the level state of the input signal DIN at this time to adjust the level state of the data signal DATA, thereby further adjusting the level state of the output signal DOUT. Specifically, if the input signal DIN is at the second level, the decoding module 210 determines it as data "1" and raises the data signal DATA to the second level representing data "1". At this time, the data signal DATA received by the encoding module 230 is at the second level, so the encoding module 23 keeps the output signal DOUT at the second level; if the input signal DIN is at the first level, the decoding module 210 determines it as data "0" and raises the data signal DATA to the first level representing data "0". At this time, the data signal DATA received by the encoding module 230 is at the first level, so the encoding module 23 lowers the output signal DOUT from the second level to the first level.

[0053] At time T3, the clock signal CLK has its third rising edge. At this time, the encoding module 230 detects the third rising edge of the clock signal CLK, and the encoding module 230 will pull down the output signal DOUT of any level and maintain it at the first level. In this stage, the enable signal OSC_EN becomes invalid, and the oscillation module 220 is also turned off, pulling down the clock signal CLK. Therefore, the duration of the last rising edge of the clock signal CLK is very short.

[0054] In this embodiment, the period of the input signal DIN is greater than 2.5 times the period of the clock signal CLK, so that the change trend of the output signal DOUT is consistent with that of the output signal DIN; when the output signal DOUT represents the first data, the duration of the output signal DOUT maintaining the second level is greater than 1.5 times the period of the clock signal CLK, and when the output signal DOUT represents the second data, the duration of the output signal DOUT maintaining the second level is less than 1.5 times the period of the clock signal CLK; to ensure correct data recognition.

[0055] In this embodiment, when the input signal DIN represents the first data and the second data, the duration ratio of maintaining the second level is 3:1, that is, T1H:T0H is 3:1; while when the reconstructed output signal DOUT represents the first data and the second data, the duration ratio of maintaining the second level is 2:1. This can support a smaller input signal period and does not require the clock signal CLK to generate a fourth rising edge.

[0056] In this embodiment, within a single data cycle, the falling edge of the enable signal OSC_EN appears at the last rising edge of the clock signal CLK, which can ensure that both the duty cycle and the period of the output signal DOUT are stable and definite values, facilitating the subsequent circuit / chip to decode the output signal DOUT.

[0057] It should be understood that in some other embodiments, within a data cycle, the number of rising edges of the clock signal CLK can also be 4, 5 or more, such that when the output signal DOUT represents the first data and the second data, the duration ratio of maintaining the second level is any ratio such as 3:1, 3:2, 4:1, 4:2, 4:3, 5:1, 5:2, 5:3, 5:4...

[0058] Figure 4 The flowchart shows a data processing method for a data processing circuit according to an embodiment of the present invention. Figure 4 The shown flowchart is only an example and should not unduly limit the protection scope of the present application. Those skilled in the art can obtain many variations, substitutions and modifications. For example, Figure 4 The various steps shown can be added, removed, substituted, rearranged and repeated.

[0059] In step S1, the input signal is decoded into a data signal.

[0060] Optionally, the data processing method further includes: generating an enable signal according to the input signal, wherein a clock signal with a stable period is generated according to the enable signal, and within a single data period, when a rising edge appears in the input signal, an enable signal in an effective state is generated to start generating the clock signal, and the output signal represents a predetermined data within one data period.

[0061] In step S2, the data signal is processed into an output signal according to the clock signal with a stable period, wherein the change trend of the output signal is the same as that of the input signal, the period of the output signal is an integer multiple of the period of the clock signal, and the output signal has a predetermined duty cycle to represent the predetermined data.

[0062] Optionally, the clock signal has N rising edges within a single data period, N is an integer greater than or equal to 3. When the first rising edge of the clock signal appears within a single data period, the output signal is switched from a first level to a second level; when the nth rising edge of the clock signal appears within a single data period, if the input signal is in an effective state, a first data is generated and the output signal is maintained at the second level, if the input signal is in an invalid state, a second data is generated and the output signal is switched from the second level to the first level, where n is an integer greater than 1 and less than N; when the Nth rising edge of the clock signal appears within a single data period, an enable signal in an invalid state is generated and the output signal is maintained at the first level.

[0063] Optionally, by setting the values of N and n, the duty cycle of the output signal is adjusted so that when the duty cycles of the input signal and the output signal represent the same data, the duty cycle of the output signal is less than that of the input signal.

[0064] Optionally, N is 3 and n is 2, the period of the input signal is greater than 2.5 times the period of the clock signal. When the output signal represents the first data, the duration for which the output signal maintains the second level is greater than 1.5 times the period of the clock signal. When the output signal represents the second data, the duration for which the output signal maintains the second level is less than 1.5 times the period of the clock signal.

[0065] Optionally, the input signal is a return-to-zero code signal with an unstable period and / or an unstable duty cycle, and the output signal is a return-to-zero code signal with a stable period and a stable duty cycle.

[0066] An embodiment of the present invention further provides a display driving chip, including the data processing circuit as Figure 2 shown.

[0067] An embodiment of the present invention also provides a light-emitting diode (LED) chip cascading system, which includes a control card and a plurality of cascaded display driver chips. At least the first-stage display driver chip includes a data processing circuit as shown in Figure 2 . When the connection mode of the plurality of cascaded display driver chips is single-line cascading, the LED chip cascading system can also be referred to as a single-line cascading control device.

[0068] An embodiment of the present invention also provides a display device, which includes an LED display panel and the aforementioned single-line cascading control device. The single-line cascading control device is connected to the LED display panel to control a plurality of LED display panels to emit light and display. Optionally, the LED display panel is selected from any one of a mini light-emitting diode (mini LED) display panel, a micro light-emitting diode (microLED) display panel, a quantum dot light-emitting diode (QD LED) display panel, and an organic light-emitting diode (OLED) display panel.

[0069] In summary, an embodiment of the present invention proposes a data processing circuit and a data processing method applied to an LED display panel, as well as a display driver chip, an LED chip cascading system, and a display device including the data processing circuit and the data processing method. The data processing circuit, the display driver chip, and the display device can accurately decode and identify "1" and "0" data when the input signal provided by the control card is unstable, and reconstruct an output signal with a stable data waveform and send it to the next-stage chip. Since the specific values of the period and duty cycle of the output signal are determined by the clock signal with a stable period provided by the oscillation module, and the data represented by the output signal is determined by the input signal, it can be ensured that the reconstructed output signal is a signal with accurate data, stable period, and constant duty cycle. A constant duty cycle means that the output signal has a constant duty cycle when representing the corresponding data.

[0070] In some embodiments of the data processing circuit, the display driver chip, and the display device, when the input signal represents the first data and the second data, the duration ratio of the second level maintained is 3:1; and when the reconstructed output signal represents the first data and the second data, the duration ratio of the second level maintained is 2:1, so that a smaller input signal period can be supported without the need for a fourth rising edge of the clock signal.

[0071] In some embodiments of the data processing circuit, display driving chip, and display device, by setting the values of N and n, the duty cycle of the output signal can be adjusted; further, when N is set to 3 and n is set to 2, within a single data cycle, only 3 rising edges of the clock signal (the duration for which the last rising edge maintains a high level can be very short) are required to decode the input signal and reconstruct the output signal, and the required clock signal frequency is low and the power consumption is small.

[0072] In some embodiments of the data processing circuit, display driving chip, and display device, within a single data cycle, the falling edge of the enable signal appears at the last rising edge of the clock signal, which can ensure that both the duty cycle and the period of the output signal are stable and definite values, facilitating the decoding of the output signal by the subsequent circuit / chip.

[0073] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article, or device comprising the element.

[0074] As described above in the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A data processing circuit, characterized in that: include: A decoding module, used for decoding an input signal into a data signal; An oscillator module, used for generating a clock signal with a stable period; an encoding module, connected to the oscillation module and the decoding module respectively, for processing the data signal into an output signal according to the clock signal, The output signal has the same change trend as the input signal, the period of the output signal is an integer multiple of the period of the clock signal, and the output signal has a predetermined duty cycle to represent predetermined data.

2. The data processing circuit according to claim 1, further comprising: an enable signal generating module, connected to the oscillation module, for generating an enable signal according to the input signal, and sending the enable signal to the oscillation module, The oscillation module generates a clock signal with a stable period according to the enable signal. In a single data cycle, when a rising edge appears on the input signal, the enable signal generating module generates the enable signal in a valid state, so that the oscillation module starts to generate the clock signal. The output signal represents a predetermined data in one data period.

3. The data processing circuit according to claim 2, wherein: The oscillation module sets the clock signal to have N rising edges in a single data cycle, where N is an integer greater than or equal to 3. When the clock signal has a first rising edge in a single data cycle, the encoding module is triggered to switch the output signal from the first level to the second level; When the clock signal has an nth rising edge in a single data cycle, if the input signal is in a valid state, the decoding module generates first data, and the encoding module maintains the output signal at a second level; if the input signal is in an invalid state, the decoding module generates second data, and the encoding module switches the output signal from the second level to the first level, where n is an integer greater than 1 and less than N; When the clock signal has an Nth rising edge in a single data cycle, the enable signal generating module generates the enable signal in an invalid state and triggers the encoding module to keep the output signal at a first level.

4. The data processing circuit according to claim 3, wherein: The oscillation module adjusts the duty cycle of the output signal by setting the values ​​of N and n, so that when the duty cycles of the input signal and the output signal represent the same data, the duty cycle of the output signal is smaller than the duty cycle of the input signal.

5. The data processing circuit according to claim 4, wherein: The oscillation module sets N to 3 and n to 2, and when the input signal represents the first data and the second data respectively, the ratio of the duration of maintaining the second level is 3:1; when the output signal represents the first data and the second data respectively, the ratio of the duration of maintaining the second level is 2:

1.

6. The data processing circuit according to claim 3, wherein: The oscillation module sets N to 3 and n to 2, the period of the input signal is greater than 2.5 times the period of the clock signal, when the output signal represents the first data, the time length for which the output signal maintains the second level is greater than 1.5 times the period of the clock signal, and when the output signal represents the second data, the time length for which the output signal maintains the second level is less than 1.5 times the period of the clock signal.

7. The data processing circuit according to claim 1, wherein: Also includes: A driving module, used for processing the data signal into driving data; as well as A storage module, whose input end is connected to the decoding module and whose output end is respectively connected to the driving module and the encoding module, is used to perform pulse width modulation processing on the data signal and send the data signal after pulse width modulation processing to the driving module and the encoding module respectively.

8. A display driver chip, characterized in that: The data processing circuit comprises the data processing circuit as claimed in any one of claims 1 to 7.

9. A display device, characterized in that: include: LED display panel; A single-line cascade control device with multi-stage display driver chips is connected to the LED display panel, and at least the first stage display driver chip includes the data processing circuit as described in any one of claims 1 to 7.

10. The display device according to claim 9, wherein: The LED display panel is selected from any one of a sub-millimeter light emitting diode display panel, a micro light emitting diode display panel, a quantum dot light emitting diode display panel and an organic light emitting diode display panel.

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