Display device

Abstract

The utility model relates to a display device. Comprising an inner region and a peripheral region surrounding at least a portion of the inner region, includes: a pixel circuit layer disposed on a base layer and including a lower line, at least a portion of which forms a pixel circuit; and a sub-pixel disposed on the pixel circuit layer and including a light emitting element electrically connected to the pixel circuit. The inner region includes a pixel region in which sub-pixels are disposed, and an outer dam region formed at a periphery of the pixel region. In the outer dam portion region, at least another portion of the lower line is stacked in the thickness direction of the base layer to form a protruding structure.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0097732, filed on July 26, 2023, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing a display device. Background art

[0004] Recently, with the increasing interest in information display, research and development of display devices have been continuously carried out. Summary of the utility model

[0005] The present disclosure provides a display device and a method of manufacturing a display device that can improve productivity and convenience.

[0006] The present disclosure aims to provide a display device and a method of manufacturing a display device that can improve the alignment quality (e.g., the degree of alignment) by more closely aligning a light - emitting element on an alignment electrode.

[0007] According to an embodiment, a display device including an inner region and a peripheral region surrounding at least a part of the inner region may include a pixel circuit layer and sub - pixels. The pixel circuit layer is disposed on a base layer and includes lower lines, at least a part of which forms a pixel circuit. The sub - pixels are disposed on the pixel circuit layer and include a light - emitting element electrically connected to the pixel circuit. The inner region may include a pixel region in which the sub - pixels are disposed and an outer dam region formed at a periphery of the pixel region. In the outer dam region, at least another part of the lower lines may be stacked in the thickness direction of the base layer to form a protruding structure.

[0008] According to an embodiment, in a plan view, the outer dam region may surround an edge of the pixel region and form an annular structure.

[0009] According to an embodiment, the display device may further include a bank disposed on the pixel circuit layer. An upper surface of the bank may be spaced apart from the base layer by a first distance in the outer dam region and may be spaced apart from the base layer by a second distance in the pixel region. The first distance may be greater than the second distance.

[0010] According to an embodiment, the display device may further include a first electrode and a second electrode disposed on the pixel circuit layer and spaced apart from each other. The light - emitting element may be disposed between the first electrode and the second electrode.

[0011] According to an embodiment, the light-emitting element may not be provided in the outer dam portion area, so that sub-pixels are not formed in the outer dam portion area.

[0012] According to an embodiment, the lower layer may include: a lower auxiliary electrode layer provided on the base layer, at least a part of the lower auxiliary electrode layer forming a first dam portion forming line; a first interlayer conductive layer provided on the lower auxiliary electrode layer, at least a part of the first interlayer conductive layer forming a second dam portion forming line; and a second interlayer conductive layer provided on the first interlayer conductive layer, at least a part of the second interlayer conductive layer forming a third dam portion forming line. The first dam portion forming line, the second dam portion forming line, and the third dam portion forming line may form a protruding structure.

[0013] According to an embodiment, the inner area may further include a dummy pixel area provided between the pixel area and the outer dam portion area.

[0014] According to an embodiment, the light-emitting element may not be provided in the dummy pixel area. Dummy lines may be provided in the dummy pixel area.

[0015] According to an embodiment, the outer dam portion area may include a first outer dam portion area and a second outer dam portion area spaced apart from each other. At least a part of the dummy pixel area may be provided between the first outer dam portion area and the second outer dam portion area.

[0016] According to an embodiment, the dummy pixel area may include a first dummy pixel area, a second dummy pixel area, and a third dummy pixel area spaced apart from each other. The first outer dam portion area may be provided between the first dummy pixel area and the second dummy pixel area. The second outer dam portion area may be provided between the second dummy pixel area and the third dummy pixel area.

[0017] According to an embodiment, the display device may include: a pixel circuit layer provided on the base layer, at least a part of the pixel circuit layer including a pixel circuit; a light-emitting element layer provided on the pixel circuit layer and including a light-emitting element electrically connected to the pixel circuit and a bank portion surrounding at least a part of the area where the light-emitting element is provided; a pixel area where the light-emitting element is provided; a dummy pixel area surrounding at least a part of the pixel area in a plan view and in which no light-emitting element is provided; and an outer dam portion area surrounding at least a part of the dummy pixel area in a plan view. The upper surface of the bank portion may be spaced apart from the base layer by a first distance in the outer dam portion area and may be spaced apart from the base layer by a second distance in the dummy pixel area. The first distance may be greater than the second distance.

[0018] According to an embodiment, a method of manufacturing a display device including an inner region and a peripheral region surrounding at least a part of the inner region may include: forming an alignment electrode layer including a first alignment electrode and a second alignment electrode and a bank on a pixel circuit layer; supplying a light-emitting element on the pixel circuit layer; and aligning the light-emitting element between the first alignment electrode and the second alignment electrode. The pixel circuit layer may include lower lines on a base layer. The inner region may include an outer dam portion region formed at an edge of the inner region. In the outer dam portion region, at least a part of the lower lines may be stacked in a thickness direction of the base layer to form a protruding structure.

[0019] According to an embodiment, supplying the light-emitting element may include: providing an ink including the light-emitting element on the pixel circuit layer; and providing a solvent on the pixel circuit layer.

[0020] According to an embodiment, forming the bank may include patterning the bank to form an opening. Providing the ink may include: forming an ink region in which the ink is disposed. The ink region may cover the opening.

[0021] According to an embodiment, providing the solvent may include moving the light-emitting element into each of the openings. The movement of the light-emitting element may be restricted by the protruding structure.

[0022] According to an embodiment, when providing the solvent, an alignment signal may be supplied to the first alignment electrode and the second alignment electrode to form an electric field for holding the position of the light-emitting element.

[0023] According to an embodiment, the inner region may include a pixel region. Providing the solvent may include providing the solvent entirely within the pixel region.

[0024] According to an embodiment, providing the ink may be performed by a first printing device. Providing the solvent may be performed by a second printing device.

[0025] According to an embodiment, providing the ink may be performed by a printing device. Providing the solvent may be performed by a nozzle coater.

[0026] According to an embodiment, the manufacturing method may further include patterning a connection electrode layer including a first connection electrode and a second connection electrode electrically connected to the light-emitting element.

[0027] According to an embodiment of the present disclosure, a display device and a method of manufacturing the display device that can improve process yield and convenience may be provided.

[0028] The present disclosure aims to provide a display device and a method of manufacturing the display device, which can improve alignment quality (e.g., the degree of alignment) by more closely aligning a light-emitting element on an alignment electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic perspective view showing a light-emitting element according to an embodiment.

[0030] Figure 2 is a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0031] Figure 3 is a schematic plan view showing a display device according to an embodiment.

[0032] Figure 4 is a schematic cross-sectional view showing a stacked structure of a display device according to an embodiment.

[0033] Figure 5 and Figure 6 is a schematic view showing a display device according to an embodiment.

[0034] Figure 7 is a schematic cross-sectional view showing a display device according to an embodiment.

[0035] Figures 8 to 10 is a schematic view showing a display device including an outer dam portion area according to an embodiment.

[0036] Figures 11 to 14 is a schematic view showing a display device including an outer dam portion area according to another embodiment.

[0037] Figures 15 to 17 is a schematic view showing a display device including an outer dam portion area according to another embodiment.

[0038] Figure 18 and Figure 19 is a flowchart showing a manufacturing method of a display device according to an embodiment.

[0039] Figures 20 to 31 is a schematic view showing each process step of a manufacturing method of a display device according to an embodiment. Detailed Embodiments

[0040] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit and scope of the present disclosure, and specific embodiments are shown in the drawings and explained in the detailed description. Therefore, as long as the modifications and variations of the present disclosure are within the scope of the present disclosure and its equivalents, the present disclosure is intended to cover the modifications and variations of the present disclosure.

[0041] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0042] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and are thus used to interpret the inherent deviations of measured, calculated and / or provided values that would be recognized by a person of ordinary skill in the art.

[0043] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly" on, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" can refer to physical connection, electrical connection and / or fluid connection with or without intervening elements. Additionally, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element can be "electrically in contact with" or "physically in contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element.

[0044] For descriptive purposes, spatial relative terms such as "below", "beneath", "under", "lower", "above", "upper", "on", "higher", "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another (or others) shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to also encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation above and below. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0045] In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of..." for purposes of its meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of its meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0046] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted as ideal or overly formal unless clearly defined in the specification.

[0047] This disclosure relates to a display device and a method of manufacturing a display device. Hereinafter, a display device and a method of manufacturing a display device according to an embodiment will be described with reference to the accompanying drawings.

[0048] Reference will be made Figure 1 and Figure 2 to describe a light-emitting element LD according to an embodiment. Figure 1 is a schematic perspective view showing a light-emitting element according to an embodiment. Figure 2 is a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0049] The light-emitting element LD can be configured to emit light. The light-emitting element LD can include a first semiconductor layer SCL1, a second semiconductor layer SCL2, and an active layer AL disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. According to an embodiment, the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2 can be stacked in sequence in the length direction of the light-emitting element LD. According to an embodiment, the light-emitting element LD can further include an electrode layer ELL and an insulating film INF.

[0050] The light-emitting element LD can have various shapes. For example, the light-emitting element LD can have a columnar shape extending in one direction. The columnar shape can include a rod-like shape or a bar-like shape that is long in the length direction (e.g., having an aspect ratio greater than 1), such as a circular column or a polygonal column, but the shape of the light-emitting element LD is not particularly limited.

[0051] The light-emitting element LD can have a first end EP1 and a second end EP2. According to an embodiment, the first semiconductor layer SCL1 can be adjacent to the first end EP1 of the light-emitting element LD, and the second semiconductor layer SCL2 can be adjacent to the second end EP2. According to an embodiment, the electrode layer ELL can be adjacent to the first end EP1.

[0052] The light-emitting element LD can be manufactured by sequentially etching the stacked semiconductor layers. The light-emitting element LD can have a size range from the nanoscale to the microscale. For example, each of the diameter D (or width) and the length L of the light-emitting element LD can be at the nanoscale or the microscale. However, the present disclosure is not limited thereto.

[0053] The first semiconductor layer SCL1 can include a semiconductor of a first conductivity type. The first semiconductor layer SCL1 can be disposed on the active layer AL, and the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can include different types of semiconductor layers. For example, the first semiconductor layer SCL1 can include a P-type semiconductor layer. For example, the first semiconductor layer SCL1 can include at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and can be a P-type semiconductor layer doped with a first conductive dopant such as Ga, B, Mg, etc. However, the present disclosure is not limited thereto. The first semiconductor layer SCL1 can include various materials.

[0054] The active layer AL can be disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The active layer AL can include a single quantum well structure or a multi-quantum well structure. The position of the active layer AL is not limited thereto, and can vary according to the type of the light-emitting element LD.

[0055] A cladding layer doped with a conductive dopant can be formed on one side and / or the other side of the active layer AL. For example, the cladding layer can include at least one of AlGaN and InAlGaN. However, the present disclosure is not limited thereto.

[0056] The second semiconductor layer SCL2 can include a semiconductor of a second conductivity type. The second semiconductor layer SCL2 can be disposed on the active layer AL and can include a semiconductor layer of a different type from the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 can include an N-type semiconductor layer. For example, the second semiconductor layer SCL2 can include at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and can include an N-type semiconductor layer doped with a second conductive dopant such as Si, Ge, Sn, etc. However, the present disclosure is not limited thereto. The second semiconductor layer SCL2 can include various materials.

[0057] When a voltage higher than the threshold voltage is applied to the first end portion EP1 and the second end portion EP2 of the light-emitting element LD, electron-hole pairs can recombine with each other in the active layer AL, and the light-emitting element LD can emit light. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source in various devices.

[0058] The insulating film INF can be disposed on the surface of the light-emitting element LD. The insulating film INF can surround the outer surface of the active layer AL and can also surround a part of each of the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The insulating film INF can have a single-layer structure or a multi-layer structure.

[0059] The insulating film INF can expose the first end portion EP1 and the second end portion EP2 of the light-emitting element LD having different polarities. For example, the insulating film INF can expose the end portions of each of the electrode layer ELL and the second semiconductor layer SCL2 adjacent to the first end portion EP1 and the second end portion EP2 of the light-emitting element LD. The insulating film INF can ensure the electrical stability of the light-emitting element LD. The insulating film INF can improve the lifetime and efficiency by minimizing the surface defects of the light-emitting element LD. When a plurality of light-emitting elements LD are disposed close to each other, the insulating film INF can prevent short-circuit defects between the light-emitting elements LD.

[0060] According to an embodiment, the insulating film INF can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), and titanium oxide (TiO x) or at least one of the like. However, the present disclosure is not limited thereto.

[0061] The electrode layer ELL may be disposed on the first semiconductor layer SCL1. The electrode layer ELL may be adjacent to the first end portion EP1. The electrode layer ELL may be electrically connected to the first semiconductor layer SCL1. A part of the electrode layer ELL may be exposed. For example, the insulating film INF may expose the surface of the electrode layer ELL. The electrode layer ELL may be exposed in a region corresponding to the first end portion EP1. According to an embodiment, a side surface of the electrode layer ELL may be exposed. For example, the insulating film INF may cover side surfaces of each of the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2, but may not cover at least a part of the side surface of the electrode layer ELL, and an electrical connection between the electrode layer ELL adjacent to the first end portion EP1 and other constituent elements may be easily established. According to an embodiment, the insulating film INF may expose not only the side surface of the electrode layer ELL, but also a part of the side surface of the first semiconductor layer SCL1 and / or the second semiconductor layer SCL2.

[0062] According to an embodiment, the electrode layer ELL may be an ohmic contact electrode. However, the present disclosure is not limited thereto. For example, the electrode layer ELL may be a Schottky contact electrode.

[0063] According to an embodiment, the electrode layer ELL may include at least one of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides, and their alloys. However, the present disclosure is not limited thereto. According to an embodiment, the electrode layer ELL may be substantially transparent. For example, the electrode layer ELL may include indium tin oxide (ITO). Thus, the electrode layer ELL may transmit the emitted light.

[0064] The structure and shape of the light-emitting element LD are not limited to the above embodiments, and according to an embodiment, the light-emitting element LD may have various structures and shapes. For example, the light-emitting element LD may further include an additional electrode layer disposed on the surface of the second semiconductor layer SCL2 and adjacent to the second end portion EP2.

[0065] Figure 3 is a schematic plan view showing a display device according to an embodiment.

[0066] Reference Figure 3 , the display device DD may include a base layer BSL and pixels PXL disposed on the base layer BSL. Although not shown in the drawings, the display device DD may further include a driving circuit unit (e.g., a scan driver and a data driver), lines, and pads for driving the pixels PXL.

[0067] The display device DD (or the base layer BSL) may include an internal area IA and a peripheral area PA. The peripheral area PA may be an area other than the internal area IA. The peripheral area PA may surround at least a part of the internal area IA.

[0068] The base layer BSL may form the base surface of the display device DD. The base layer BSL may be a rigid or flexible substrate or film. For example, the base layer BSL may be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one layer of insulating layer. The material and / or physical properties of the base layer BSL are not particularly limited. In an embodiment, the base layer BSL may be substantially transparent. Here, "substantially transparent" may mean that light can be transmitted with a certain level or higher level of transmittance. In another embodiment, the base layer BSL may be translucent or opaque. According to an embodiment, the base layer BSL may include a reflective material.

[0069] The internal area IA may include an area where pixels PXL are disposed (e.g., a pixel area PXA (see Figure 8 ). The peripheral area PA may include an area where no pixels PXL are disposed (e.g., a dead zone). Driving circuit units, lines, and pads connected to the pixels PXL in the internal area IA may be disposed in the peripheral area PA.

[0070] According to an embodiment, the pixels PXL (or sub-pixels SPX) may be arranged according to a stripe or array structure, but the present disclosure is not limited thereto, and the pixels PXL (or sub-pixels SPX) may be arranged in various patterns.

[0071] According to an embodiment, the pixels PXL (or sub-pixels SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. At least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may form one pixel unit configured to emit light of various colors.

[0072] For example, each of a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 may emit light of a color. For example, the first sub-pixel SPX1 may be a red pixel that emits red light (e.g., a first color), the second sub-pixel SPX2 may be a green pixel that emits green light (e.g., a second color), and the third sub-pixel SPX3 may be a blue pixel that emits blue light (e.g., a third color). According to an embodiment, the number of the second sub-pixels SPX2 may be greater than the numbers of the first sub-pixels SPX1 and the third sub-pixels SPX3. However, the colors, types, and / or numbers of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 forming each pixel unit are not limited.

[0073] Reference Figures 4 to 7 , a cross-sectional and planar structure of a display device DD according to an embodiment will be described.

[0074] First, with reference to Figure 4 , a stacked structure defined in the display device DD will be described. Figure 4 is a schematic cross-sectional view showing a stacked structure of a display device according to an embodiment. In the Figure 5 subsequent drawings, layers that are the same as the layers described with reference to Figure 4 (e.g., patterned by the same process) may be represented by the same hatching.

[0075] Reference Figure 4 , the stacked structure included in the display device DD according to an embodiment may have a structure in which a base layer BSL, a lower auxiliary electrode layer BML, a buffer layer BFL, an active layer ACT, a gate insulating layer GI, a first interlayer conductive layer ICL1, a first interlayer insulating layer ILD1, a second interlayer conductive layer ICL2, a second interlayer insulating layer ILD2, a protective layer PSV, an alignment electrode layer ELT, a first insulating layer INS1, and a connection electrode layer CNE are stacked in sequence, and at least a part thereof may be patterned.

[0076] According to an embodiment, the lower auxiliary electrode layer BML, the buffer layer BFL, the active layer ACT, the gate insulating layer GI, the first interlayer conductive layer ICL1, the first interlayer insulating layer ILD1, the second interlayer conductive layer ICL2, the second interlayer insulating layer ILD2, and the protective layer PSV may form a pixel circuit layer PCL including a pixel circuit (see Figure 6 ).

[0077] According to an embodiment, the lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2 may form a lower line BPL. The lower line BPL may be a line forming the pixel circuit layer PCL, and may include a line (e.g., a wiring or an electrode) formed lower than the alignment electrode layer ELT.

[0078] In addition to the lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2, the lower line BPL according to the embodiment may further include an additional conductive layer.

[0079] The base layer BSL may form (or configure) the base surface of the display device DD.

[0080] The buffer layer BFL may prevent impurities from diffusing into the active layer ACT or may prevent moisture from permeating. According to an embodiment, the buffer layer BFL may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ). However, the present disclosure is not limited thereto.

[0081] The active layer ACT may include a semiconductor. For example, the active layer ACT may include at least one of polysilicon, low-temperature polysilicon (LTPS), amorphous silicon, and an oxide semiconductor.

[0082] The lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, the second interlayer conductive layer ICL2, the alignment electrode layer ELT, and the connection electrode layer CNE may include a conductive material.

[0083] According to an embodiment, each of the lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2 may include one or more conductive layers. According to an embodiment, each of the lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2 may include at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt). According to an embodiment, the second interlayer conductive layer ICL2 may have a multilayer structure in which titanium (Ti), copper (Cu), and indium tin oxide (ITO) are stacked in sequence. However, the present disclosure is not limited thereto.

[0084] A gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a protective layer PSV, and a first insulating layer INS1 may be provided between these layers to electrically isolate an active layer ACT, a first interlayer conductive layer ICL1, a second interlayer conductive layer ICL2, an alignment electrode layer ELT, and a connection electrode layer CNE from each other. According to an embodiment, the above-mentioned conductive layers may be electrically connected to each other using contact members formed on at least one of the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the protective layer PSV.

[0085] According to an embodiment, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the first insulating layer INS1 may include an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ) or at least one of them. According to an embodiment, the protective layer PSV may include an organic material. For example, the organic material may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB). However, the present disclosure is not limited thereto.

[0086] According to an embodiment, the alignment electrode layer ELT may include a conductive material. For example, the alignment electrode layer ELT may include at least one of molybdenum (Mo), magnesium (Mg), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), copper (Cu), and aluminum (Al). However, the present disclosure is not limited thereto.

[0087] According to an embodiment, the connection electrode layer CNE may include a conductive material. The connection electrode layer CNE may be electrically connected to a light-emitting element LD. According to an embodiment, the connection electrode layer CNE may include a transparent conductive material. For example, the connection electrode layer CNE may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). However, the present disclosure is not limited thereto. The first insulating layer INS1 may be provided between the alignment electrode layer ELT and the connection electrode layer CNE.

[0088] Reference Figures 5 to 7 will be made to the schematic plan and sectional structures of a display device DD according to an embodiment.

[0089] Figure 5 and Figure 6It is a schematic diagram showing a display device according to an embodiment. Figure 5 It is a schematic plan view showing a display device DD according to an embodiment. Figure 6 It is along Figure 5 A schematic cross-sectional view taken along line A-A'. Figure 7 It is a schematic cross-sectional view showing a display device according to an embodiment.

[0090] The display device DD may include a light-emitting area EMA and a non-light-emitting area NEA. The display device DD may include a bank BNK, an alignment electrode layer ELT, a light-emitting element LD, and a connection electrode layer CNE.

[0091] In a plan view, the light-emitting area EMA may overlap with an opening OPN defined by the bank BNK. The light-emitting element LD may be disposed in the light-emitting area EMA. The light-emitting element LD may not be disposed in the non-light-emitting area NEA.

[0092] The bank BNK may form (or include) the opening OPN. For example, the bank BNK may have a shape protruding in the thickness direction of the base layer BSL (e.g., a third direction DR3 intersecting the first direction DR1 and the second direction DR2), and may surround an area in a plan view. According to an embodiment, an ink INK (see Figure 21 ) including the light-emitting element LD may be supplied to the opening OPN defined by the bank BNK so that the light-emitting element LD can be disposed in the opening OPN.

[0093] According to an embodiment, the bank BNK may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not limited thereto.

[0094] The alignment electrode layer ELT may include an electrode for aligning the light-emitting element LD. According to an embodiment, the alignment electrode layer ELT may include a first electrode ELT1 and a second electrode ELT2. According to an embodiment, the first electrode ELT1 may be a first alignment electrode ELTA, and the second electrode ELT2 may be a second alignment electrode ELTG.

[0095] The light-emitting element LD may be disposed (or aligned) on the alignment electrode layer ELT. According to an embodiment, in a plan view, the light-emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2. The light-emitting element LD may form (or configure) a light-emitting unit.

[0096] According to an embodiment, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other in the first direction DR1 in the light-emitting area EMA.

[0097] According to an embodiment, the first electrode ELT1 of the first alignment electrode ELTA may be an electrode to which an alternating current signal can be supplied to align the light-emitting element LD. The first electrode ELT1 may be an electrode to which an anode signal can be supplied so that the light-emitting element LD emits light. The second electrode ELT2 of the second alignment electrode ELTG may be an electrode to which a ground signal can be supplied to align the light-emitting element LD. The second electrode ELT2 may be an electrode to which a cathode signal can be supplied so that the light-emitting element LD emits light.

[0098] The first electrode ELT1 (or the first alignment electrode ELTA) and the second electrode ELT2 (or the second alignment electrode ELTG) may be supplied (or provided) with a first alignment signal and a second alignment signal, respectively, in a process step in which the light-emitting element LD is aligned. For example, ink INK including the light-emitting element LD may be supplied (or provided) to the opening OPN, a first alignment signal may be supplied to the first electrode ELT1, and a second alignment signal may be supplied to the second electrode ELT2. The first alignment signal and the second alignment signal may have different waveforms, electric potentials, and / or phases. For example, the first alignment signal may be an alternating current signal, and the second alignment signal may be a ground signal. However, the present disclosure is not limited to the above examples. An electric field may be formed between the first electrode ELT1 and the second electrode ELT2 (or on the first electrode ELT1 and the second electrode ELT2), and the light-emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 based on the electric field. For example, the light-emitting element LD may be moved (or rotated) by a force (e.g., dielectrophoresis (DEP) force) caused by the electric field and may be aligned (or set) on the first alignment electrode ELTA and the second alignment electrode ELTG.

[0099] The light-emitting element LD may emit light based on the provided electrical signal. For example, the light-emitting element LD may emit light based on a first electrical signal (e.g., an anode signal) provided from the first connection electrode CNE1 and a second electrical signal (e.g., a cathode signal) provided from the second connection electrode CNE2.

[0100] The first end EP1 of the light-emitting element LD may be disposed adjacent to the first electrode ELT1, and the second end EP2 of the light-emitting element LD may be disposed adjacent to the second electrode ELT2.

[0101] The light-emitting element LD may be disposed in the opening OPN. The light-emitting element LD may form a light-emitting region EMA. The light-emitting region EMA may include a region in which the light-emitting element LD is disposed.

[0102] The connection electrode layer CNE can be disposed on the first end portion EP1 and the second end portion EP2 of the light-emitting element LD. The first connection electrode CNE1 can be disposed on the first end portion EP1 and electrically connected to the first end portion EP1 of the light-emitting element LD. The second connection electrode CNE2 can be disposed on the second end portion EP2 and electrically connected to the second end portion EP2 of the light-emitting element LD.

[0103] According to an embodiment, the connection electrode layer CNE can include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 can be an anode connection electrode AE, and the second connection electrode CNE2 can be a cathode connection electrode CE.

[0104] Figure 6 The cross-sectional structure of the display device DD is schematically shown, focusing on the pixel circuit layer PCL forming the pixel circuit and the light-emitting element layer EML provided with the light-emitting element LD.

[0105] Reference Figure 6 , the display device DD can include a pixel circuit layer PCL and a light-emitting element layer EML. For ease of description, Figure 6 the driving transistor TR among the circuit elements forming the pixel circuit is shown focused.

[0106] The base layer BSL can provide a region for disposing the pixel circuit layer PCL and the light-emitting element layer EML.

[0107] The pixel circuit layer PCL can be disposed on the base layer BSL. The pixel circuit layer PCL can include the layers described above with reference to Figure 4 . For example, the pixel circuit layer PCL can include a first lower auxiliary electrode layer 1200, a second lower auxiliary electrode layer 1400, a driving transistor TR, and a second power line PL2.

[0108] The first lower auxiliary electrode layer 1200 and the second lower auxiliary electrode layer 1400 can be formed by the lower auxiliary electrode layer BML. The first lower auxiliary electrode layer 1200 can be electrically connected to the second transistor electrode TE2 of the driving transistor TR and can overlap the driving active layer TACT of the driving transistor TR in a plan view. The second lower auxiliary electrode layer 1400 can be electrically connected to the second power line PL2.

[0109] The buffer layer BFL can be disposed on the base layer BSL. The buffer layer BFL can cover the lower auxiliary electrode layer BML.

[0110] The driving transistor TR can be a thin film transistor. The driving transistor TR can be electrically connected to the light emitting element LD. According to an embodiment, the driving transistor TR can include a driving active layer TACT, a first transistor electrode TE1, a second transistor electrode TE2, and a gate electrode GE.

[0111] The driving active layer TACT can be formed by the active layer ACT and can include a first contact region in contact with the first transistor electrode TE1 and a second contact region in contact with the second transistor electrode TE2. One of the first transistor electrode TE1 and the second transistor electrode TE2 can be a source electrode, and the other of the first transistor electrode TE1 and the second transistor electrode TE2 can be a drain electrode.

[0112] The gate electrode GE can be disposed on the gate insulating layer GI. The position of the gate electrode GE can correspond to the position of the channel region of the driving active layer TACT.

[0113] The gate insulating layer GI can be disposed on the buffer layer BFL. The gate insulating layer GI can cover a part of the driving active layer TACT.

[0114] The first interlayer insulating layer ILD1 can be disposed on the gate insulating layer GI. The first interlayer insulating layer ILD1 can cover the gate electrode GE and the conductive layer 2400. The conductive layer 2400 can be formed by the first interlayer conductive layer ICL1 and can be electrically connected to the second power line PL2.

[0115] The first transistor electrode TE1 and the second transistor electrode TE2 can be disposed on the first interlayer insulating layer ILD1. The second transistor electrode TE2 can be electrically connected to the first power line. The first transistor electrode TE1 can be electrically connected to the first electrode ELT1 through a first contact member that penetrates the second interlayer insulating layer ILD2 and the protective layer PSV.

[0116] The second power line PL2 can be disposed on the first interlayer insulating layer ILD1. The second power line PL2 can be electrically connected to the second lower auxiliary electrode layer 1400 and can be electrically connected to the second electrode ELT2 through a second contact member that penetrates the second interlayer insulating layer ILD2 and the protective layer PSV.

[0117] The second interlayer insulating layer ILD2 can be disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can cover the first transistor electrode TE1, the second transistor electrode TE2, and the second power line PL2.

[0118] The protective layer PSV can be disposed on the second interlayer insulating layer ILD2. According to an embodiment, the protective layer PSV can be a via layer.

[0119] The light-emitting element layer EML may be disposed on the pixel circuit layer PCL. The light-emitting element layer EML may include an insulating pattern INP, an alignment electrode layer ELT, a first insulating layer INS1, a bank BNK, a light-emitting element LD, a second insulating layer INS2, and a connection electrode layer CNE.

[0120] The insulating pattern INP may include a first insulating pattern INP1 and a second insulating pattern INP2. The first insulating pattern INP1 and the second insulating pattern INP2 may be disposed on the protective layer PSV. According to an embodiment, the first insulating pattern INP1 and the second insulating pattern INP2 may have various shapes. In an embodiment, the first insulating pattern INP1 and the second insulating pattern INP2 may protrude in the thickness direction (e.g., the third direction DR3) of the base layer BSL.

[0121] The first insulating pattern INP1 and the second insulating pattern INP2 may form a step such that the light-emitting element LD can be easily aligned in the light-emitting region EMA. According to an embodiment, the first insulating pattern INP1 and the second insulating pattern INP2 may be partition walls. According to an embodiment, the first insulating pattern INP1 and the second insulating pattern INP2 may include at least one organic material and / or inorganic material. However, the present disclosure is not limited thereto.

[0122] The alignment electrode layer ELT may be disposed on the protective layer PSV and / or the first insulating pattern INP1 and the second insulating pattern INP2. The first electrode ELT1 may receive a first alignment signal and / or a first power through a first contact member. The second electrode ELT2 may receive a second alignment signal and / or a second power through a second contact member.

[0123] The first insulating layer INS1 may be disposed on the alignment electrode layer ELT. For example, the first insulating layer INS1 may cover the first electrode ELT1 and the second electrode ELT2.

[0124] The bank BNK may be disposed on the first insulating layer INS1. As described above, the bank BNK may form a space in which the ink INK including the light-emitting element LD can be accommodated.

[0125] The light-emitting element LD may be disposed on the first insulating layer INS1 in a region surrounded by the bank BNK. According to an embodiment, the light-emitting element LD may emit light based on electrical signals (e.g., an anode signal and a cathode signal) provided from the first connection electrode CNE1 and the second connection electrode CNE2.

[0126] The second insulating layer INS2 may be disposed on the light-emitting element LD. The second insulating layer INS2 may cover the active layer AL of the light-emitting element LD. The second insulating layer INS2 may expose at least a part of the light-emitting element LD. For example, the second insulating layer INS2 may not cover the first end portion EP1 and the second end portion EP2 of the light-emitting element LD, and thus, the first end portion EP1 and the second end portion EP2 of the light-emitting element LD may be exposed and electrically connected to the first connection electrode CNE1 and the second connection electrode CNE2, respectively. According to an embodiment, another part of the second insulating layer INS2 may be disposed on the bank BNK and the first insulating layer INS1.

[0127] In the case where the second insulating layer INS2 is formed on the light-emitting element LD after the alignment of the light-emitting element LD is completed, the light-emitting element LD can be prevented from leaving the alignment position.

[0128] The second insulating layer INS2 may have a single-layer structure or a multi-layer structure. The second insulating layer INS2 may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (Al x O y ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x ). However, the present disclosure is not limited thereto.

[0129] The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed on the first insulating layer INS1 and the second insulating layer INS2. The first connection electrode CNE1 may be electrically connected to the first end portion EP1 of the light-emitting element LD. The second connection electrode CNE2 may be electrically connected to the second end portion EP2 of the light-emitting element LD.

[0130] The first connection electrode CNE1 may be electrically connected to the first electrode ELT1 through a first contact portion penetrating the first insulating layer INS1, and the second connection electrode CNE2 may be electrically connected to the second electrode ELT2 through a second contact portion penetrating the first insulating layer INS1. According to an embodiment, the first connection electrode CNE1 may be directly (or electrically) connected to a line of the pixel circuit layer PCL through the first contact portion. The second connection electrode CNE2 may be directly (or electrically) connected to a line of the pixel circuit layer PCL through the second contact portion.

[0131] According to an embodiment, the first connection electrode CNE1 and the second connection electrode CNE2 may be patterned simultaneously in the same process. However, the present disclosure is not limited thereto. After one of the first connection electrode CNE1 and the second connection electrode CNE2 is patterned, the other of the first connection electrode CNE1 and the second connection electrode CNE2 is patterned.

[0132] Figure 7 A cross-sectional structure of the display device DD is schematically shown, focusing on the constituent elements provided on the light-emitting element layer EML.

[0133] Reference Figure 7 , sub-pixel regions SPXA corresponding to the sub-pixels SPX may be formed in the internal region IA. According to an embodiment, the sub-pixel regions SPXA may be included in the pixel region PXA. The sub-pixel regions SPXA may include a first sub-pixel region SPXA1 corresponding to the first sub-pixel SPX1, a second sub-pixel region SPXA2 corresponding to the second sub-pixel SPX2, and a third sub-pixel region SPXA3 corresponding to the third sub-pixel SPX3. The first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 may be arranged in the first direction DR1.

[0134] Additional dams QBNK may be provided between or at the boundaries of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3, and may define a space (or region) overlapping each of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3. The space defined by the additional dams QBNK may be a region where the color conversion layer CCL can be provided.

[0135] The additional dams QBNK may be provided to surround a region in the light-emitting element layer EML in a plan view. The additional dams QBNK may protrude in the thickness direction (e.g., the third direction DR3) of the base layer BSL such that the additional dams QBNK may define a region, and a space where the color conversion layer CCL is formed may be provided in the region.

[0136] The additional dams QBNK may include an organic material. For example, the additional dams QBNK may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB). However, the present disclosure is not limited thereto.

[0137] The color conversion layer CCL can be disposed on the light-emitting element LD in a space surrounded by the additional dike portion QBNK. The color conversion layer CCL can include a first color conversion layer CCL1 disposed in the first sub-pixel SPX1, a second color conversion layer CCL2 disposed in the second sub-pixel SPX2, and a scattering layer LSL disposed in the third sub-pixel SPX3.

[0138] The color conversion layer CCL can be disposed on the light-emitting element LD. The color conversion layer CCL can be configured to change the wavelength of light. According to an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can include light-emitting elements LD that emit light of the same color. For example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can include light-emitting elements LD that emit light of a third color (or blue). The color conversion layer CCL including color conversion particles can be disposed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, so that a full-color image can be displayed.

[0139] The first color conversion layer CCL1 can include first color conversion particles that convert the third-color light emitted from the light-emitting element LD into first-color light. For example, the first color conversion layer CCL1 can include a plurality of first quantum dots QD1 dispersed in a matrix material such as a base resin.

[0140] According to an embodiment, when the light-emitting element LD is a blue light-emitting element that emits blue light and the first sub-pixel SPX1 is a red pixel, the first color conversion layer CCL1 can include first quantum dots QD1 that convert the blue light emitted from the blue light-emitting element into red light. The first quantum dots QD1 can absorb blue light to shift the wavelength according to energy transition, thereby emitting red light. When the first sub-pixel SPX1 is a pixel of another color, the first color conversion layer CCL1 can include first quantum dots QD1 corresponding to the color of the first sub-pixel SPX1.

[0141] The second color conversion layer CCL2 can include second color conversion particles that convert the third-color light emitted from the light-emitting element LD into second-color light. For example, the second color conversion layer CCL2 can include a plurality of second quantum dots QD2 dispersed in a matrix material such as a base resin.

[0142] According to an embodiment, when the light-emitting element LD is a blue light-emitting element that emits blue light and the second sub-pixel SPX2 is a green pixel, the second color conversion layer CCL2 may include second quantum dots QD2 that convert the blue light emitted from the blue light-emitting element into green light. The second quantum dots QD2 may absorb the blue light to shift the wavelength according to energy transitions, thereby emitting green light. When the second sub-pixel SPX2 is a pixel of another color, the second color conversion layer CCL2 may include second quantum dots QD2 corresponding to the color of the second sub-pixel SPX2.

[0143] According to an embodiment, blue light having a relatively short wavelength in the visible light range may be incident on the first quantum dots QD1 and the second quantum dots QD2, thereby increasing the absorption coefficients of the first quantum dots QD1 and the second quantum dots QD2. Therefore, the light efficiency of the light emitted from the first sub-pixel SPX1 and the second sub-pixel SPX2 may be improved, and excellent color reproducibility may be ensured. The light-emitting units of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be composed of light-emitting elements LD of the same color (e.g., blue light-emitting elements), thereby improving the manufacturing efficiency of the display device DD.

[0144] A scattering layer LSL may be provided to effectively use the third color (or blue) light emitted from the light-emitting element LD. For example, when the light-emitting element LD is a blue light-emitting element that emits blue light and the third sub-pixel SPX3 is a blue pixel, the scattering layer LSL may include at least one type of scattering material SCT to effectively use the light emitted from the light-emitting element LD. For example, the scattering material SCT of the scattering layer LSL may include various light-scattering particles or light-scattering materials. For example, the scattering material SCT may include silicon dioxide (SiO x )(e.g., silica beads, hollow silica, etc.), titanium oxide (TiO x ), zirconium oxide (ZrO x ), aluminum oxide (Al x O y ), indium oxide (In x O y ), zinc oxide (ZnO x , which may be ZnO and / or ZnO2), tin oxide (SnO x ), and antimony oxide (Sb x O y ) of at least one. However, the present disclosure is not limited thereto. The scattering material SCT may not only be provided in the third sub-pixel SPX3, and may be included in the first color conversion layer CCL1 or the second color conversion layer CCL2. According to an embodiment, a scattering layer LSL including a transparent polymer may be provided by omitting the scattering material SCT.

[0145] The first capping layer CPL1 can be disposed on the color conversion layer CCL. The first capping layer CPL1 can be disposed over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The first capping layer CPL1 can cover the color conversion layer CCL. The first capping layer CPL1 can prevent impurities such as moisture or air from infiltrating from the outside and damaging or contaminating the color conversion layer CCL.

[0146] The first capping layer CPL1 can be an inorganic layer and can include silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (Al x O y ), titanium oxide (TiO x ), silicon oxynitride (SiOC x C y ) and silicon oxynitride (SiON x N y ) of at least one kind.

[0147] The optical layer OPL can be disposed on the first capping layer CPL1. The optical layer OPL can be used to recycle the light provided by the color conversion layer CCL by total reflection to improve the light extraction efficiency. To this end, the optical layer OPL can have a refractive index relatively lower than that of the color conversion layer CCL.

[0148] The second capping layer CPL2 can be disposed on the optical layer OPL. The second capping layer CPL2 can be disposed over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The second capping layer CPL2 can cover the optical layer OPL. The second capping layer CPL2 can prevent impurities such as moisture or air from infiltrating from the outside and damaging or contaminating the optical layer OPL.

[0149] The second capping layer CPL2 can be an inorganic layer and can include silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (Al x O y ), titanium oxide (TiO x ), silicon oxynitride (SiOC x C y ), and silicon oxynitride (SiON x N y ) of at least one kind.

[0150] The color filter layer CFL may be disposed on the second cover layer CPL2. The color filter layer CFL may include color filters CF1, CF2, and CF3 that match the colors of each pixel PXL. A full-color image may be displayed by setting color filters CF1, CF2, and CF3 that match the colors of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0151] The color filter layer CFL may include: a first color filter CF1 disposed in the first sub-pixel SPX1 and selectively transmitting light emitted from the first sub-pixel SPX1; a second color filter CF2 disposed in the second sub-pixel SPX2 and selectively transmitting light emitted from the second sub-pixel SPX2; and a third color filter CF3 disposed in the third sub-pixel SPX3 and selectively transmitting light emitted from the third sub-pixel SPX3.

[0152] According to an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but are not limited thereto. Hereinafter, the term "color filter" or "a plurality of color filters" may refer to any one of the first color filter CF1, the second color filter CF2, and the third color filter CF3, or may collectively refer to two or more types of color filters.

[0153] The first color filter CF1 may overlap with the first color conversion layer CCL1 in the thickness direction of the base layer BSL (e.g., the third direction DR3). The first color filter CF1 may include a filter material that selectively transmits light of the first color (or red). For example, in the case where the first sub-pixel SPX1 is a red pixel, the first color filter CF1 may include a red filter material.

[0154] The second color filter CF2 may overlap with the second color conversion layer CCL2 in the thickness direction of the base layer BSL (e.g., the third direction DR3). The second color filter CF2 may include a filter material that selectively transmits light of the second color (or green). For example, in the case where the second sub-pixel SPX2 is a green pixel, the second color filter CF2 may include a green filter material.

[0155] The third color filter CF3 may overlap with the scattering layer LSL in the thickness direction of the base layer BSL (e.g., the third direction DR3). The third color filter CF3 may include a filter material that selectively transmits light of the third color (or blue). For example, in the case where the third sub-pixel SPX3 is a blue pixel, the third color filter CF3 may include a blue filter material.

[0156] According to an embodiment, the light blocking layer BM may also be disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3. Accordingly, in the case where the light blocking layer BM is formed between the first color filter CF1, the second color filter CF2, and the third color filter CF3, color mixing defects visible from the front surface or side surface of the display device DD can be prevented. The material of the light blocking layer BM may not be particularly limited and may include various light absorbing materials. For example, the light blocking layer BM may include a black matrix, or may be implemented by stacking the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0157] The outer coating OC may be disposed on the color filter layer CFL. The outer coating OC may be disposed over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The outer coating OC may cover the lower member including the color filter layer CFL. The outer coating OC may prevent moisture or air from penetrating into the lower member. The outer coating OC may protect the lower member from foreign substances such as dust.

[0158] The outer coating OC may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene. However, the present disclosure is not limited thereto, and the outer coating OC may include an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (Al x O y ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), or titanium oxide (TiO x ).

[0159] The outer film layer OFL may be disposed on the outer coating OC. The outer film layer OFL may be disposed on the outside of the display device DD to reduce external influence. The outer film layer OFL may be disposed over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. According to an embodiment, the outer film layer OFL may include at least one of a polyethylene terephthalate (PET) film, a low reflection film, a polarizing film, and a transmittance controllable film, but the present disclosure is not limited thereto. According to an embodiment, the pixel PXL may include an upper substrate instead of the outer film layer OFL.

[0160] Reference Figures 8 to 17 , a display device DD including an outer dam portion area ODA according to an embodiment will be described. For ease of description, repeated descriptions are simply explained or not repeated.

[0161] will refer to Figures 8 to 10 Describe a display device DD including an outer dam portion area ODA according to an embodiment.

[0162] Figures 8 to 10 is a schematic diagram showing a display device including an outer dam portion area according to an embodiment.

[0163] Figure 8 is a schematic plan view showing a display device including an outer dam portion area according to an embodiment. Figure 9 is Figure 8 a schematic enlarged view of the area EA1 of Figure 10 is along Figure 9 a schematic cross-sectional view taken along line B - B' of

[0164] The display device DD according to an embodiment may include a pixel area PXA and an outer dam portion area ODA.

[0165] The pixel area PXA may be an area where sub-pixels SPX are set. The pixel area PXA may include a display area for displaying an image.

[0166] The outer dam portion area ODA may surround at least a part of the pixel area PXA. The outer dam portion area ODA may be formed at the periphery of the pixel area PXA. According to an embodiment, the outer dam portion area ODA may be formed at the edge of the pixel area PXA.

[0167] According to an embodiment, in a plan view, the outer dam portion area ODA may completely surround the pixel area PXA. The outer dam portion area ODA may surround all the edges of the pixel area PXA. The outer dam portion area ODA may form a closed loop in which the pixel area PXA can be set.

[0168] However, the present disclosure is not limited thereto, and according to an embodiment, the outer dam portion area ODA may not be provided at a part of the edge of the pixel area PXA, and may form an open loop in which the pixel area PXA can be set.

[0169] According to an embodiment, the outer dam portion area ODA may be adjacent to the sub-pixels SPX. For example, the outer dam portion area ODA may be directly adjacent to the sub-pixels SPX provided at the outermost edge of the pixel area PXA.

[0170] The sub-pixels SPX may be provided along each of the outer lines OL. The outer lines OL may be pixel row lines or pixel column lines adjacent to the edge of the inner area IA. For ease of description, the following figures will be described based on an embodiment in which the outer lines OL are pixel row lines. Figure 9 subsequent figures.

[0171] The external line OL may include a first external line OL1 and a second external line OL2. The first external line OL1 may be the outermost line among the external lines OL. The first external line OL1 may be disposed between the outer dam portion area ODA and the second external line OL2.

[0172] The sub-pixel SPX may include a sub-pixel SPX disposed on the first external line OL1. The sub-pixel SPX may include a sub-pixel SPX disposed on the second external line OL2.

[0173] A protruding structure may be formed in the outer dam portion area ODA, and the protruding structure protrudes much more than the structure formed in the pixel area PXA.

[0174] According to an embodiment, the protruding structure formed in the outer dam portion area ODA may be formed by stacking at least a part of the lower line BPL in the thickness direction (e.g., the third direction DR3) of the base layer BSL. For example, at least a part of the lower line BPL may be stacked and a dam portion forming line DAL may be formed.

[0175] The dam portion forming line DAL may be formed of the lower line BPL. The dam portion forming line DAL may include two or more of the lower lines BPL. According to an embodiment, the dam portion forming line DAL may include all of the lower lines BPL.

[0176] According to an embodiment, the dam portion forming line DAL may include a plurality of conductive layers. The dam portion forming line DAL may include a first dam portion forming line DAL1, a second dam portion forming line DAL2, and a third dam portion forming line DAL3. The first dam portion forming line DAL1 may be formed of the lower auxiliary electrode layer BML. The second dam portion forming line DAL2 may be formed of the first interlayer conductive layer ICL1. The third dam portion forming line DAL3 may be formed of the second interlayer conductive layer ICL2.

[0177] According to an embodiment, since the dam portion forming line DAL is formed of the lower line BPL, a protruding structure may be formed on the periphery of the pixel area PXA without adding a separate process. Therefore, the process steps may be simplified and the process cost may be reduced.

[0178] Although not shown in the figure, in the case where the lower line BPL further includes an additional conductive layer in addition to the lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2, the dam portion forming line DAL may further include an nth dam portion forming line as a layer formed of the additional conductive layer (here, n is an integer of 3 or more).

[0179] According to an embodiment, since the dam formation line DAL is provided in the outer dam portion area ODA, the uppermost portion of the bank BNK in the outer dam portion area ODA can be formed to be higher than the uppermost portion of the bank BNK in the pixel area PXA.

[0180] For example, in the outer dam portion area ODA, the upper surface of the bank BNK can be spaced apart from the base layer BSL by a first distance L1. In an area other than the outer dam portion area ODA (e.g., the pixel area PXA), the upper surface of the bank BNK can be spaced apart from the base layer BSL by a second distance L2. The first distance L1 can be greater than the second distance L2.

[0181] A protruding structure can be defined in the outer dam portion area ODA, and as described above, the movement (e.g., flow) of the solvent SLV (see Figure 25 ) can be restricted inside the outer dam portion area ODA.

[0182] Since the outer dam portion area ODA for restricting the movement of the solvent SLV is defined, the convenience of the process of supplying the light-emitting element LD to the pixel area PXA can be improved. Details regarding this point will be described with reference to Figure 18 the subsequent drawings.

[0183] According to an embodiment, the outer dam portion area ODA can completely surround the pixel area PXA in a plan view, thereby creating a defined space configured to accommodate a fluid.

[0184] For example, the solvent SLV can be supplied on the pixel circuit layer PCL (e.g., the base layer BSL). According to an embodiment, the outer dam portion area ODA can be formed in an area that accommodates the solvent SLV. The outer dam portion area ODA can be an area that restricts the flow of the solvent SLV.

[0185] For example, the outer dam portion area ODA can be formed at the periphery of the pixel area PXA to form an annular structure surrounding the pixel area PXA and a range in which the flow of the solvent SLV can be restricted by the outer dam portion area ODA. Therefore, the range in which the solvent SLV can flow can be determined to correspond to (e.g., be substantially equal to) the area in which the pixel area PXA is to be formed.

[0186] The sub-pixels SPX can not be formed in the outer dam portion area ODA. For example, the light-emitting element LD can not be provided in the outer dam portion area ODA.

[0187] For example, in order to supply the light-emitting element LD on the pixel circuit layer PCL (e.g., the base layer BSL), the light-emitting element LD can be generally supplied to the area where the pixel region PXA is to be formed, and as more solvent SLV is supplied in subsequent processes, the light-emitting element LD can move throughout the pixel region PXA. Thus, the light-emitting element LD can be disposed throughout the pixel region PXA, but the light-emitting element LD may not be disposed in the outer dam area ODA.

[0188] Reference will be made Figures 11 to 14 to describe a display device DD including an outer dam area ODA according to another embodiment. Figures 11 to 14 is a schematic view showing a display device including an outer dam area according to another embodiment.

[0189] Figure 11 is a schematic plan view showing a display device including an outer dam area according to an embodiment. Figure 12 and Figure 13 is Figure 11 a schematic enlarged view of the area EA2 of Figure 14 is taken along Figure 12 the line C-C' of

[0190] The display device DD according to the present embodiment is different from Figures 8 to 10 the display device DD of

[0191] that this embodiment further includes a dummy pixel region DXA. According to an embodiment, the dummy pixel region DXA can be disposed between the pixel region PXA and the outer dam area ODA. The dummy pixel region DXA can be disposed inside the outer dam area ODA.

[0192] In a plan view, the dummy pixel region DXA can surround at least a part of the pixel region PXA. The dummy pixel region DXA can be formed at the periphery of the pixel region PXA. According to an embodiment, the dummy pixel region DXA can be formed at the edge of the pixel region PXA.

[0193] According to an embodiment, in a plan view, the outer dam area ODA can surround at least a part of the dummy pixel region DXA. In a plan view, the outer dam area ODA can surround at least a part of the edge of the dummy pixel region DXA.

[0194] The dummy pixel region DXA can be directly adjacent to the pixel region PXA. The dummy pixel region DXA can be directly adjacent to the outer dam area ODA.

[0195] Dummy pixels DUM may be provided in a dummy pixel region DXA. A dummy line DL may be a dummy pixel row line or a dummy pixel column line, which is provided outside the pixel region PXA and adjacent to an edge of the inner region IA. For ease of description, an embodiment in which the dummy line DL is a dummy pixel row line will be described Figure 12 in the following figures.

[0196] According to an embodiment, the dummy pixels DUM may be provided along the dummy line DL. The number of the dummy lines DL is not particularly limited. For example, the number of the dummy lines DL may be single or plural.

[0197] According to an embodiment, a light-emitting element LD may not be provided in each of the dummy pixels DUM. For example, a bank BNK including an opening OPN may not be provided in a region where the dummy pixels DUM are formed, and a bank BNK including an opening OPN may be provided in a region where sub-pixels SPX are formed.

[0198] Similar to the previous embodiment, since a dam formation line DAL is provided in an outer dam region ODA, the uppermost portion of the bank BNK in the outer dam region ODA may be formed to be higher than the uppermost portion of the bank BNK in the dummy pixel region DXA.

[0199] For example, in the outer dam region ODA, an upper surface of the bank BNK may be spaced apart from a base layer BSL by a first distance L1. In a region other than the outer dam region ODA (e.g., the dummy pixel region DXA), an upper surface of the bank BNK may be spaced apart from the base layer BSL by a second distance L2. The first distance L1 may be greater than the second distance L2.

[0200] Accordingly, in a plan view, a protruding structure defined in the outer dam region ODA may surround edges of the pixel region PXA and the dummy pixel region DXA.

[0201] Reference will be made to Figures 15 to 17 describe a display device DD including an outer dam region ODA according to another embodiment. Figures 15 to 17 is a schematic diagram showing a display device including an outer dam region according to another embodiment.

[0202] Figure 15 is a schematic plan view showing a display device including an outer dam region according to an embodiment. Figure 16 is Figure 15 a schematic enlarged view of a region EA3 of Figure 17 schematically shows a structure in which a dummy pixel region according to an embodiment is provided outside an outer dam region.

[0203] The display device DD according to the present embodiment may further include a dummy pixel region DXA, but is different from the display device DD according to Figures 11 to 14 the embodiment in that the dummy pixel region DXA is provided between the outer dam portions ODA1 and ODA2.

[0204] According to an embodiment, the outer dam portion ODA may include a plurality of regions spaced apart from each other. For example, the outer dam portion ODA may include a first outer dam portion ODA1 and a second outer dam portion ODA2. The number of regions forming the outer dam portion ODA is not particularly limited.

[0205] When the outer dam portion ODA includes a plurality of regions spaced apart from each other and the solvent SLV is supplied onto the pixel circuit layer PCL (e.g., the base layer BSL), the outer dam portion ODA can more tightly remove the space in which the solvent SLV is accommodated. For example, even when some of the solvent SLV moves beyond the second outer dam portion ODA2 to the dummy pixel region DXA, the movement of the moved solvent SLV can be restricted by the first outer dam portion ODA1.

[0206] According to an embodiment, the dummy pixel region DXA may be provided between the first outer dam portion ODA1 and the second outer dam portion ODA2. For example, the first side of the dummy pixel region DXA may face the first outer dam portion ODA1, and the second side of the dummy pixel region DXA may face the second outer dam portion ODA2. According to an embodiment, the second outer dam portion ODA2 may be provided between the pixel region PXA and the dummy pixel region DXA.

[0207] According to an embodiment, referring to Figure 17 showing the edge region EDGE of the internal region IA, the dummy pixel region DXA may include two or more dummy lines DL. The outer dam portion ODA may be provided between the dummy lines DL, respectively. For example, the dummy lines DL may include a first dummy line DL1 (e.g., a first dummy pixel row or a first dummy pixel column), a second dummy line DL2 (e.g., a second dummy pixel row or a second dummy pixel column), a third dummy line DL3 (e.g., a third dummy pixel row or a third dummy pixel column), and a fourth dummy line DL4 (e.g., a fourth dummy pixel row or a fourth dummy pixel column).

[0208] According to an embodiment, two or more dummy lines DL2 and DL3 may be provided between the outer dam portions ODA1 and ODA2. The number of dummy lines DL formed between the outer dam portions ODA1 and ODA2 is not particularly limited.

[0209] According to an embodiment, the first outer dam portion region ODA1 may be disposed between a first dummy pixel region DXA1 in which a first dummy line DL1 is formed and a second dummy pixel region DXA2 in which a second dummy line DL2 and a third dummy line DL3 are formed. The second outer dam portion region ODA2 may be disposed between the second dummy pixel region DXA2 in which the second dummy line DL2 and the third dummy line DL3 are formed and a third dummy pixel region DXA3 in which a fourth dummy line DL4 is formed.

[0210] Reference Figures 18 to 31 , a method of manufacturing a display device DD according to an embodiment will be described. For ease of description, repeated descriptions are simply explained or not repeated. For ease of description, the method of manufacturing the display device DD will be described based on the display device DD according to the embodiment described with reference to Figures 11 to 14 The method of manufacturing the display device DD will be described.

[0211] Figure 18 and Figure 19 are flowcharts showing a method of manufacturing a display device according to an embodiment. Figures 20 to 31 is a schematic diagram showing each process step of a method of manufacturing a display device according to an embodiment.

[0212] Figure 18 Shows the steps of a method of manufacturing a display device DD according to an embodiment. Figure 19 is a flowchart showing the supply of a light-emitting element LD (S200) according to an embodiment.

[0213] Figure 20 , Figure 21 , Figure 25 , Figure 28 and Figure 31 may represent process steps based on the cross-sectional structure shown in Figure 6 . Figure 22 , Figure 26 and Figure 29 may represent process steps based on the planar structure shown in Figure 12 . Figure 23 , Figure 27 and Figure 30 may represent process steps based on the planar structure shown in Figure 13 . Figure 24 may represent process steps based on the cross-sectional structure shown in Figure 14 .

[0214] Reference Figure 18, a method of manufacturing a display device DD according to an embodiment may include: forming an alignment electrode layer including a first alignment electrode and a second alignment electrode and a bank on a pixel circuit layer (S100); supplying a light-emitting element on a base layer (S200); aligning the light-emitting element between the first alignment electrode and the second alignment electrode (S300); and forming a connection electrode layer (S400).

[0215] Reference Figure 19 , supplying a light-emitting element on a base layer (S200) may include providing an ink including the light-emitting element and a solvent (S220) and providing a solvent (S240).

[0216] Reference Figure 18 and Figure 20 , when forming an alignment electrode layer including a first alignment electrode and a second alignment electrode and a bank on a pixel circuit layer (S100), a pixel circuit layer PCL may be manufactured, and the first alignment electrode ELTA, the second alignment electrode ELTG, and the bank BNK may be patterned on the pixel circuit layer PCL.

[0217] A conductive layer or an insulating layer on the base layer BSL may be formed based on a process for manufacturing a semiconductor device. For example, a conductive layer or an insulating layer on the base layer BSL may be formed by a photolithography process, and may be deposited by various methods (e.g., sputtering, chemical vapor deposition, etc.). The present disclosure is not necessarily limited to a specific embodiment.

[0218] According to an embodiment, a plurality of base layers BSL may be provided, and the base layer BSL may be provided as a mother substrate coupled to each other. For example, a manufacturing method according to an embodiment may be applied to a mother substrate including the base layer BSL, and the base layer BSL may be separated and prepared into each display device DD.

[0219] In this step, a lower line BPL including a lower auxiliary electrode layer BML, a first interlayer conductive layer ICL1, and a second interlayer conductive layer ICL2 may be patterned on the base layer BSL.

[0220] As described above, the lower auxiliary electrode layer BML, the first interlayer conductive layer ICL1, and the second interlayer conductive layer ICL2 may be arranged to overlap each other in a plan view in some regions where an outer dam portion region ODA is to be formed.

[0221] In this step, an insulating pattern INP can be patterned on the pixel circuit layer PCL, and an alignment electrode layer ELT can be patterned on the insulating pattern INP. Accordingly, the first alignment electrode ELTA and the second alignment electrode ELTG can be set to be spaced apart from each other such that the light-emitting element LD can be aligned. A first insulating layer INS1 can be provided on the alignment electrode layer ELT, and a bank BNK including an opening OPN can be patterned on the first insulating layer INS1.

[0222] Reference Figure 18 、 Figure 19 and Figures 21 to 23 , when supplying the light-emitting element (S200) on the base layer, providing an ink (S220) including the light-emitting element and a solvent may be performed.

[0223] In this step, an ink INK including the light-emitting element LD and a solvent SLV can be supplied onto the pixel circuit layer PCL (e.g., the base layer BSL). For example, the first printing device 20 can eject the ink INK.

[0224] According to an embodiment, the solvent SLV may include an organic solvent. For example, the solvent SLV may be at least one of propylene glycol methyl ether acetate (PGMEA), dipropylene glycol n-propyl ether (DGPE), and triethylene glycol n-butyl ether (TGBE). However, the present disclosure is not limited thereto.

[0225] The first printing device 20 may include an inkjet printer configured to eject a fluid. For example, the first printing device 20 may include a nozzle unit through which the ink INK is ejected, an ink channel fluidly connected to the nozzle unit, and an ink reservoir fluidly connected to the ink channel, and the first printing device 20 may move parallel to the pixel circuit layer PCL. Accordingly, the first printing device 20 can locally eject the ink INK onto each of some regions of the pixel circuit layer PCL.

[0226] In this step, the ink INK can be supplied to some regions where the pixel region PXA is to be formed. For example, the ink INK can be locally supplied to some regions in the pixel region PXA. The regions to which the ink INK is supplied may be defined as ink regions INKA.

[0227] According to an embodiment, based on the resolution of the display device DD to be manufactured, etc., the concentration of the light-emitting elements LD included in the ink INK (for example, the number of light-emitting elements LD per unit volume) can be determined according to the number of light-emitting elements LD of each sub-pixel SPX. According to an embodiment, the ink area INKA may not be individually controlled based on each of the sub-pixels SPX, and only the solvent SLV may be supplied in subsequent processes, so that the light-emitting elements LD included in the ink INK can be manufactured at a high concentration. Therefore, the number of process steps in the inkjet printing process can be reduced, and the process steps can be simplified.

[0228] Even when multiple base layers BSL are provided and the ink INK is ejected onto the mother substrate and each of the display devices DD to be manufactured is manufactured at a different resolution from each other, the manufacturing method according to the present embodiment is applicable thereto. For example, different numbers of light-emitting elements LD can be relatively easily supplied to each of the mother substrates by the first printing device 20.

[0229] The ink area INKA can completely cover a single sub-pixel SPX (for example, the opening OPN for the sub-pixel SPX). For example, the ink area INKA can cover two or more sub-pixels SPX. The ink areas INKA can be spaced apart from each other so as to be formed in each of these areas. The ink area INKA can be formed to overlap the pixel area PXA in a plan view.

[0230] According to an embodiment, the first printing device 20 may not eject the ink INK based on each of the sub-pixels SPX, and the first printing device 20 may eject the ink INK into each of some areas of the pixel area PXA.

[0231] For example, the inkjet printing process of ejecting the ink INK may not be controlled based on each sub-pixel SPX, but may be controlled based on a local area in the pixel area PXA, and the process convenience can be significantly improved.

[0232] For example, experimentally, when the inkjet printing process is performed based on each sub-pixel SPX, it may be difficult to finely control the movement of the first printing device 20 due to hardware problems of the first printing device 20. However, the movement of the first printing device 20 can be controlled based on a relatively wide area, and in subsequent processes, the light-emitting elements LD can be moved so that the light-emitting elements LD can be supplied to each of the sub-pixels SPX. Therefore, the process efficiency can be improved, and the process difficulty can be reduced.

[0233] According to an embodiment, the ink INK may be ejected such that the ink region INKA at least overlaps with the pixel region PXA, and the ink region INKA may or may not overlap with the dummy pixel region DXA in a plan view.

[0234] According to an embodiment, the ink region INKA may not overlap with the outer dam portion region ODA in a plan view. For example, an inkjet printing process for ejecting the ink INK may be controlled such that the ink INK is not supplied to the outer dam portion region ODA.

[0235] Reference Figure 18 、 Figure 19 and Figures 24 to 30 When supplying a light-emitting element (S200) on a base layer, providing a solvent (S240) may be performed.

[0236] According to an embodiment, after ejecting the ink INK including the light-emitting element LD, a process of ejecting a solvent SLV as a fluid substantially not including the light-emitting element LD may be performed separately.

[0237] As described above, the ink INK may be ejected based on a region rather than each of the sub-pixels SPX. The light-emitting element LD included in the ink INK may need to be moved to an opening OPN corresponding to each of the sub-pixels SPX.

[0238] According to an embodiment, when providing the solvent (S240) is performed, the light-emitting element LD may be moved to the opening OPN of each of the sub-pixels SPX. For example, the provided solvent SLV may fill at least a part of the interior of the region surrounded by the outer dam portion region ODA. According to an embodiment, the solvent SLV may move in the pixel region PXA, and a part of the solvent SLV may be disposed in the dummy pixel region DXA.

[0239] For example, providing the solvent (S240) according to an embodiment may include providing the light-emitting element LD to the opening OPN of each of the sub-pixels SPX. Accordingly, the light-emitting element LD disposed in the ink region INKA may be moved to and disposed in the entire pixel region PXA. According to an embodiment, as the outer dam portion region ODA is formed and the solvent SLV is supplied, the light-emitting element LD may be moved to the opening OPN of each of the sub-pixels SPX without a process of supplying the light-emitting element LD to each of the sub-pixels SPX. Accordingly, a method of manufacturing a display device DD with improved process convenience may be provided.

[0240] During the provision of the solvent (S240) according to the embodiment, an alignment signal may be supplied to a first alignment electrode ELTA and a second alignment electrode ELTG defined in each of the sub-pixels SPX. For example, the alignment signal supplied in this step may form an electric field that holds the position of the light-emitting element LD in some of the sub-pixels SPX. In the regions of at least some of the sub-pixels SPX, a position-holding electric field may be formed to hold the position of the light-emitting element LD, thereby preventing excessive displacement of the light-emitting element LD. The number of light-emitting elements LD for each sub-pixel SPX may be designed to be substantially uniform.

[0241] According to the embodiment, the region to which the solvent SLV is supplied in this step may be defined based on a relatively large region. For example, the solvent SLV may be completely supplied in the pixel region PXA. Experimentally, in the case where the region for supplying the ink INK is defined based on each of the sub-pixels SPX, the ink INK may be supplied in a relatively narrow region, such that the height of the ink INK (e.g., ink droplets) may be non-uniform. For example, in a narrow region, the ink INK may have a lower height toward the outside. For this reason, the electric field for aligning the light-emitting element LD may be non-uniformly formed in subsequent processes. However, according to the embodiment, since the solvent SLV is supplied based on a large region, after the solvent SLV is supplied, the height of the entire ink INK can generally be uniform. The electric field for aligning the light-emitting element LD can be uniformly formed, thereby improving the alignment degree of the light-emitting element LD.

[0242] According to the embodiment, the provision of the solvent (S240) may be performed in various ways.

[0243] For example (see Figures 25 to 27 ), the provision of the solvent (S240) may be performed by the second printing device 40. The second printing device 40 may include an inkjet printer configured to eject a fluid. For example, the second printing device 40 may include a nozzle unit through which the solvent SLV is ejected, a solvent channel fluidly connected to the nozzle unit, and a solvent reservoir fluidly connected to the solvent channel, and the second printing device 40 may move parallel to the pixel circuit layer PCL. Thus, the second printing device 40 may eject the solvent SLV onto the pixel circuit layer PCL.

[0244] For example (see Figures 28 to 30) The supply of the solvent (S240) can be performed by the nozzle coater 60. The nozzle coater 60 can be moved using a gantry adjacent to the base layer BSL (or mother substrate), and when the nozzle coater 60 is moved in one direction, the solvent SLV can be ejected onto each of different regions. In the case of using the nozzle coater 60, the process apparatus can be maintained relatively simply, and relatively high process productivity can be achieved. Compared to the second printing apparatus 40, the nozzle coater 60 can supply the solvent SLV to a larger area at one time.

[0245] In the case of using the nozzle coater 60, the light-emitting element LD can not be mixed with the solvent SLV ejected by the nozzle coater 60, so the solvent SLV can have a viscosity suitable for the nozzle coater 60.

[0246] Reference Figure 18 and Figure 31 and, when aligning the light-emitting element (S300) between the first alignment electrode and the second alignment electrode, an alignment signal can be applied to the first alignment electrode ELTA and the second alignment electrode ELTG. The light-emitting element LD can be aligned based on the correspondingly formed electric field.

[0247] Reference Figure 18 and Figure 31 and, forming the connection electrode layer (S400) can be performed such that the connection electrode layer CNE can be electrically connected to each end of the light-emitting element LD.

[0248] For example, before performing this step, the solvent SLV can be removed (e.g., by a drying process), and the first connection electrode CNE1 and the second connection electrode CNE2 can be patterned. According to an embodiment, the second insulating layer INS2 can be provided on the light-emitting element LD before patterning the connection electrode layer CNE.

[0249] Thereafter, according to an embodiment, the constituent elements on the light-emitting element layer EML can be sequentially provided, and the display device DD according to the embodiment can be manufactured.

[0250] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the above-described embodiments of the present disclosure can be implemented alone or in combination with each other.

[0251] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized in that, An internal region and a peripheral region surrounding at least a part of the internal region, the display device comprising: A pixel circuit layer disposed on a base layer and including lower lines, at least a part of the lower lines forming a pixel circuit; and Sub-pixels disposed on the pixel circuit layer and including light-emitting elements electrically connected to the pixel circuit, wherein, The internal region includes: A pixel region in which the sub-pixels are disposed; and An outer dam portion region formed at a periphery of the pixel region, and In the outer dam portion region, at least another part of the lower lines is stacked in a thickness direction of the base layer to form a protruding structure.

2. The display device according to claim 1, wherein In a plan view, the outer dam portion region surrounds an edge of the pixel region and forms an annular structure.

3. The display device according to claim 1, characterized in that, Further comprising: A bank portion disposed on the pixel circuit layer, wherein, An upper surface of the bank portion is spaced apart from the base layer by a first distance in the outer dam portion region and is spaced apart from the base layer by a second distance in the pixel region, and The first distance is greater than the second distance.

4. The display device according to claim 1, wherein Further comprising A first electrode and a second electrode disposed on the pixel circuit layer and spaced apart from each other, wherein, The light-emitting element is disposed between the first electrode and the second electrode.

5. The display device according to claim 4, wherein The light-emitting element is not disposed in the outer dam portion region such that the sub-pixels are not formed in the outer dam portion region.

6. The display device according to claim 1, wherein The lower lines include: A lower auxiliary electrode layer disposed on the base layer, at least a part of the lower auxiliary electrode layer forming a first dam portion forming line; A first interlayer conductive layer disposed on the lower auxiliary electrode layer, the At least a part of the first interlayer conductive layer forming a second dam portion forming line; and A second interlayer conductive layer disposed on the first interlayer conductive layer, at least a part of the second interlayer conductive layer forming a third dam portion forming line, and The first dam portion forming line, the second dam portion forming line and the third dam portion forming line form the protruding structure.

7. The display device according to claim 1, wherein The internal region further includes: A dummy pixel region disposed between the pixel region and the outer dam portion region.

8. The display device according to claim 7, wherein The light-emitting element is not disposed in the dummy pixel region, and Dummy lines are disposed in the dummy pixel region.

9. The display device according to claim 8, wherein The outer dam portion region includes a first outer dam portion region and a second outer dam portion region spaced apart from each other, and At least a part of the dummy pixel region is disposed between the first outer dam portion region and the second outer dam portion region.

10. The display device according to claim 9, wherein The dummy pixel region includes a first dummy pixel region, a second dummy pixel region and a third dummy pixel region spaced apart from each other, The first outer dam portion region is disposed between the first dummy pixel region and the second dummy pixel region, and The second outer dam portion region is disposed between the second dummy pixel region and the third dummy pixel region.

11. A display device, characterized in that, Comprising: A pixel circuit layer is disposed on a base layer, and at least a part of the pixel circuit layer includes pixel circuits; A light-emitting element layer is disposed on the pixel circuit layer and includes a light-emitting element electrically connected to the pixel circuit and a bank portion disposed around at least a part of a region where the light-emitting element is disposed therein; A pixel region, wherein the light-emitting element is disposed in the pixel region; A dummy pixel region surrounds at least a part of the pixel region in a plan view, and the light-emitting element is not disposed in the dummy pixel region; And An outer bank portion region surrounds at least a part of the dummy pixel region in a plan view, wherein an upper surface of the bank portion is spaced apart from the base layer by a first distance in the outer bank portion region and is spaced apart from the base layer by a second distance in the dummy pixel region, and the first distance is greater than the second distance.

Images