Display device

Abstract

A display device is provided. The display device includes a first substrate, a transistor on the first substrate, a pixel electrode disposed on the transistor and connected to the transistor, a pixel defining layer on the pixel electrode, a spacer on the pixel defining layer, and a second substrate on the spacer. The spacers include a first spacer disposed at a center of the first substrate in a plan view and a second spacer disposed at an edge of the first substrate, and the second spacer has a width gradually increasing in a direction from the first substrate toward the second substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0113977, filed with the Korean Intellectual Property Office (KIPO) on August 29, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device capable of preventing darkening of pixels. Background art

[0004] An organic light - emitting display device has a self - emitting characteristic, and different from a liquid - crystal display device, the organic light - emitting display device does not require a separate light source, thereby reducing thickness and weight. Due to high - quality characteristics such as low power consumption, high brightness, and high response speed, the organic light - emitting display device has received attention as a next - generation display device for portable electronic devices. Summary of the utility model

[0005] Aspects of the present disclosure provide a display device capable of preventing darkening of pixels.

[0006] According to an embodiment of the present disclosure, a display device may include a first substrate, a transistor located on the first substrate, a pixel electrode disposed on the transistor and connected to the transistor, a pixel defining layer located on the pixel electrode, a spacer located on the pixel defining layer, and a second substrate located on the spacer. The spacer may include a first spacer disposed at the center of the first substrate in a plan view and a second spacer disposed at the edge of the first substrate, and the second spacer may have a width that gradually increases in a direction from the first substrate toward the second substrate.

[0007] In an embodiment, the first spacer may have a width that gradually decreases in that direction.

[0008] In an embodiment, an inner angle of the second spacer may be an obtuse angle.

[0009] In an embodiment, an inner angle of the first spacer may be an acute angle.

[0010] In an embodiment, the display device may further include a filler located between the first substrate and the second substrate.

[0011] In an embodiment, the second spacer may have a groove.

[0012] In an embodiment, the second spacer and the filler may be in contact with each other through the groove of the second spacer.

[0013] In an embodiment, the display device may further include a sealant disposed between an edge of the first substrate and an edge of the second substrate and surrounding the filler and the spacer.

[0014] In an embodiment, the spacer may be integrally formed with the pixel defining layer.

[0015] In an embodiment, each of the first spacer and the second spacer may be integrally formed with the pixel defining layer.

[0016] In an embodiment, the filler may be formed of a silicon-based material.

[0017] According to an embodiment of the present disclosure, a display device may include a first substrate, a transistor located on the first substrate, a pixel electrode disposed on the transistor and connected to the transistor, a pixel defining layer located on the pixel electrode, and a first spacer disposed on the pixel defining layer at an edge of the first substrate in a plan view. The first spacer may have a width that gradually increases in a direction from the first substrate toward the second substrate.

[0018] In an embodiment, an inner angle of the first spacer may be an obtuse angle.

[0019] In an embodiment, the display device may further include a second spacer disposed on the pixel defining layer at a center of the first substrate in a plan view. The second spacer may have a width that gradually decreases in the direction.

[0020] In an embodiment, an inner angle of the second spacer may be an acute angle.

[0021] In an embodiment, the display device may further include a filler located between the first substrate and the second substrate.

[0022] In an embodiment, the first spacer may have a groove.

[0023] In an embodiment, the first spacer and the filler may be in contact with each other through the groove of the first spacer.

[0024] In an embodiment, the display device may further include a sealant disposed between an edge of the first substrate and an edge of the second substrate and surrounding the filler, the first spacer, and the second spacer.

[0025] In an embodiment, each of the first spacer and the second spacer may be integrally formed with the pixel defining layer.

[0026] In the display device according to the present disclosure, darkening of pixels may be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and the above and other aspects and features of the present disclosure will become more apparent. In the drawings:

[0028] Figure 1 is a plan view of a display device according to an embodiment;

[0029] Figure 2 is shown separately Figure 1 a schematic diagram of the spacer in;

[0030] Figure 3 is along Figure 1 a schematic cross-sectional view taken along line I-I';

[0031] Figure 4 is Figure 1 a schematic plan view of a unit pixel of;

[0032] Figure 5 is along Figure 4 a schematic cross-sectional view taken along line II-II';

[0033] Figure 6 is a schematic diagram for explaining the movement path of the filler caused by the damage of the first spacer; and

[0034] Figure 7 is a schematic diagram for explaining the movement path of the filler caused by the damage of the second spacer. Detailed Description of the Embodiments

[0035] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0036] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For this reason, the term “connected” can refer to physical, electrical, and / or fluid connections with or without intervening elements. Additionally, when an element is referred to as being “in contact” or “contacted” with another element, etc., the element can be “electrically in contact” or “physically in contact” with the other element; or “indirectly in contact” or “directly in contact” with the other element. Throughout the specification, like reference numerals refer to like components. In the accompanying drawings, for clarity, the thickness of layers and regions is exaggerated.

[0037] Although terms such as “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Thus, the first element discussed below can be referred to as the second element without departing from the teachings of one or more embodiments. The description of an element as a “first” element may not require or imply the existence of a second element or other elements. Terms such as “first,” “second,” etc. may also be used herein to distinguish different categories or sets of elements. For brevity, the terms “first,” “second,” etc. may represent “first category (or first set),” “second category (or second set),” etc., respectively.

[0038] In the specification and claims, for purposes of their meaning and interpretation, the phrase “at least one of...” is intended to include the meaning of “at least one selected from the group of...” For example, “at least one of A and B” can be understood to mean “A, B, or A and B.”

[0039] The features of the various embodiments of the present disclosure can be combined in part or in whole. As will be clearly recognized by those skilled in the art, various interactions and operations are possible technically. The various embodiments can be practiced individually or in combination.

[0040] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.

[0041] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a plan view of a display device 100 according to an embodiment, Figure 2 shows separately Figure 1 a spacer SPC in, and Figure 3 is a schematic cross-sectional view taken along the Figure 1 line I-I' of.

[0043] As Figures 1 to 3 shown in, the display device 100 may include a display substrate 110, a package substrate 210, a sealant 350, a filler 310, and a plurality of spacers SPC.

[0044] The display substrate 110 may include a first substrate 111, a driving circuit layer 500 disposed on the first substrate 111, and a light-emitting element layer 600 disposed on the driving circuit layer 500. The display substrate 110 may include a plurality of pixels PX arranged in a display area of the display substrate 110. The pixel PX may include a plurality of transistors and a light-emitting element connected to at least one of the transistors. The transistors may be disposed in the driving circuit layer 500 described above, and the light-emitting elements may be disposed in the light-emitting element layer 600 described above. Three adjacent pixels PX may provide light of different colors, and the three pixels PX may form a unit pixel UPX.

[0045] The package substrate 210 may be disposed opposite to the display substrate 110 and cover the light-emitting element layer 600 and the driving circuit layer 500 of the display substrate 110. The package substrate 210 may include a second substrate 211.

[0046] The sealant 350 may be disposed along the edges of the display substrate 110 and the package substrate 210 to join the display substrate 110 and the package substrate 210 and seal the display substrate 110 and the package substrate 210. For example, the sealant 350 may be disposed between the edge of the first substrate 111 and the edge of the second substrate 211. In a plan view, the sealant 350 may have a closed curve shape surrounding the pixels PX, spacers SPC, and filler 310 to be described below.

[0047] The filler 310 may be disposed in a space between the display substrate 110 and the package substrate 210. The filler 310 may fill the empty space between the display substrate 110 and the package substrate 210 to improve the mechanical strength of the display device 100. For example, the filler 310 may improve the durability of the display device 100 against external impacts by filling the empty space inside the display device 100. In an embodiment, the filler 310 may be formed of a silicon-based material.

[0048] The spacer SPC can be disposed on at least one of the display substrate 110 and the encapsulation substrate 210 to maintain a gap between the display substrate 110 and the encapsulation substrate 210.

[0049] The spacer SPC can include a plurality of first spacers SPC1 disposed at the center of the first substrate 111 and a plurality of second spacers SPC2 disposed at the edge of the first substrate 111. For example, as Figure 2 shown, the spacer SPC can include a first spacer SPC1 disposed in a region A corresponding to the center of the first substrate 111 and a second spacer SPC2 disposed in a region B corresponding to the edge of the first substrate 111. The second spacer SPC2 can be disposed closer to the sealant 350 than the first spacer SPC1. In other words, the distance between the second spacer SPC2 and the sealant 350 can be less than the distance between the first spacer SPC1 and the sealant 350.

[0050] The first spacer SPC1 and the second spacer SPC2 can have different shapes. For example, the first spacer SPC1 can have a width that gradually decreases in the direction from the first substrate 111 to the second substrate 211 (e.g., the third direction DR3). The second spacer SPC2 can have a width that gradually increases in the third direction DR3 described above. For example, in a cross-sectional view, the second spacer SPC2 can have an inverted conical shape or a hanging shape. Here, the width of each of the spacers SPC1 and SPC2 can be a dimension in the first direction DR1 or the second direction DR2, for example.

[0051] The inner angle θ1 of the first spacer SPC1 can be an acute angle. For example, the inner angle θ1 of the first spacer SPC1 can be less than 90 degrees. The inner angle θ1 of the first spacer SPC1 can be, for example, an angle formed by a first virtual surface parallel to the first direction DR1 (or the second direction DR2) and a second virtual surface parallel to the side surface of the first spacer SPC1. Similarly, the inner angle θ2 of the second spacer SPC2 can be an angle formed by the first virtual surface and the second virtual surface described above.

[0052] The first spacer SPC1 and the second spacer SPC2 can be used to support a mask (e.g., a fine metal mask (FMM)) used during the deposition process of the light-emitting layer. When the mask is disposed on the display substrate 110, the mask may sag toward the display substrate 110 due to its own weight. Due to the sagging of the mask, the spacer supporting the mask may be damaged, and the filler may penetrate into the emission region of the pixel through the damaged portion of the spacer, which may cause a problem of dimming the pixel. The sagging of the mask may occur at the edge of the display substrate 110, and thus damage may occur in the second spacer SPC2 disposed at the edge of the display substrate 110. However, since the second spacer SPC2 according to the embodiment has an inverted conical shape (or a hanging shape), the hole transport layer and the electron transport layer described below can be disconnected by the second spacer SPC2 for each pixel. Accordingly, even when damage occurs in the second spacer SPC2, the filler 310 may not penetrate into the emission region of the pixel. Accordingly, even when damage occurs in the second spacer SPC2, dimming of the pixel can be prevented.

[0053] A method of manufacturing the display device 100 according to an embodiment will be described below.

[0054] First, the sealant 350 may be coated along the edge of the display substrate 110 or the encapsulation substrate 210, and the filler 310 may be loaded on the display substrate 110 or the encapsulation substrate 210 coated with the sealant 350. The filler 310 may be dropped inside the sealant 350. For example, the filler 310 may be dropped from the center of the display substrate 110 or the encapsulation substrate 210.

[0055] The display substrate 110 and the encapsulation substrate 210 may be joined to each other by a vacuum bonding method with the sealant 350 and the filler 310 interposed between the display substrate 110 and the encapsulation substrate 210. The sealant 350 may be cured while the display substrate 110 and the encapsulation substrate 210 are joined together.

[0056] Hereinafter, with reference to Figure 4 and Figure 5 a pixel of the display device 100 according to an embodiment will be described.

[0057] Figure 4 is Figure 1 a schematic plan view of a unit pixel, and Figure 5 is Figure 4 a schematic cross-sectional view taken along line II-II' of

[0058] The display substrate 110 may include a switching transistor 10, a driving transistor 20, a storage element 80, and a light-emitting element 70 formed for each pixel. The light-emitting element 70 may be, for example, an organic light-emitting diode (OLED). The display substrate 110 may further include gate lines 151 extending in one direction, data lines 171 insulated from and intersecting the gate lines 151, and a common power supply line 172. A pixel may be defined by the gate line 151, the data line 171, and the common power supply line 172, but the present disclosure is not necessarily limited thereto.

[0059] The light-emitting element 70 may include a pixel electrode 710, a light-emitting layer 720 disposed on the pixel electrode 710, and a common electrode 730 disposed on the light-emitting layer 720. The pixel electrode 710 may correspond to a positive (+) electrode as a hole injection electrode, and the common electrode 730 may correspond to a negative (−) electrode as an electron injection electrode. However, the present disclosure is not necessarily limited thereto, and depending on the driving method of the display device 100, the pixel electrode 710 may correspond to the negative electrode, and the common electrode 730 may correspond to the positive electrode.

[0060] Holes and electrons may be injected into the light-emitting layer 720 from the pixel electrode 710 and the common electrode 730, respectively. Light emission may occur when excitons, which are a combination of the injected holes and electrons, fall back from an excited state to a ground state.

[0061] In the display device 100 according to an embodiment, the light-emitting element 70 may emit light in a direction opposite to the pixel electrode 710 direction (e.g., the common electrode 730 direction) from the light-emitting layer 720 and display an image. In other words, the display device 100 according to an embodiment may be a top-emission display device.

[0062] The storage element 80 may include a first capacitor plate 158 and a second capacitor plate 178, and a gate insulating layer 140 may be interposed between the first capacitor plate 158 and the second capacitor plate 178. The gate insulating layer 140 may serve as a dielectric of the storage element 80. In the storage element 80, the storage amount of the storage element 80 may be determined by the voltage between the two storage plates 158 and 178 and the stored charge.

[0063] The switching transistor 10 may include a switching semiconductor layer 131, a switching gate electrode 152, a switching source electrode 173, and a switching drain electrode 174, and the driving transistor 20 may include a driving semiconductor layer 132, a driving gate electrode 155, a driving source electrode 176, and a driving drain electrode 177.

[0064] The switching transistor 10 can be used as a switching element for selecting a pixel that emits light. The switching gate electrode 152 can be connected to the gate line 151. The switching source electrode 173 can be connected to the data line 171. The switching drain electrode 174 can be spaced apart from the switching source electrode 173 and connected to the first capacitor plate 158 through the contact hole 181.

[0065] The driving transistor 20 can apply a driving power supply to the pixel electrode 710 to cause the light-emitting layer 720 of the light-emitting element 70 in the selected pixel to emit light. The driving gate electrode 155 can be connected to the first capacitor plate 158. The driving source electrode 176 and the second capacitor plate 178 can each be connected to the common power supply line 172. The driving drain electrode 177 can be connected to the pixel electrode 710 of the light-emitting element 70 through the contact hole 182.

[0066] With this structure, the switching transistor 10 can be turned on by the gate voltage applied to the gate line 151, and the data voltage from the data line 171 can be transmitted to the driving transistor 20 through the turned-on switching transistor 10. The differential voltage corresponding to the difference between the common voltage applied to the driving transistor 20 from the common power supply line 172 and the data voltage transmitted from the switching transistor 10 can be stored in the storage element 80, and the current corresponding to the voltage stored in the storage element 80 can flow through the driving transistor 20 to the light-emitting element 70, allowing the light-emitting element 70 to emit light.

[0067] Hereinafter, the structure of the display device 100 according to an embodiment will be described in detail in the stacking order. Hereinafter, the structure of the transistor will be described focusing on the driving transistor 20. In addition, only the differences between the switching transistor 10 and the driving transistor 20 will be briefly described.

[0068] The first substrate 111 of the display substrate 110 can be an insulating substrate made of glass, quartz, ceramic, plastic, etc., but the present disclosure is not limited thereto. For example, the first substrate 111 can be a metal substrate made of stainless steel or the like.

[0069] The buffer layer 120 can be disposed on the first substrate 111. The buffer layer 120 can be used to prevent the penetration of impurity elements and planarize the surface, and can be formed of a material capable of performing this function. For example, the buffer layer 120 can be formed of a silicon nitride (SiN x ) layer, a silicon oxide (SiO x ) layer, or a silicon oxynitride (SiO x N y ) layer. However, the present disclosure is not limited thereto, and depending on the type of the first substrate 111 and the process conditions, the buffer layer 120 can be omitted.

[0070] The driving semiconductor layer 132 may be disposed on the buffer layer 120. The driving semiconductor layer 132 may be formed of a polysilicon layer. The driving semiconductor layer 132 may include a channel region 135 that is not doped with impurities, and a source region 136 and a drain region 137 that are formed by p+ doping on the sides of the channel region 135. The ionic material to be doped may be a P-type impurity such as boron (B), and for example, B2H6 may be used. The impurities may vary according to the type of thin film transistor.

[0071] In an embodiment, a thin film transistor having a PMOS structure using a P-type impurity may be used as the driving transistor 20, but the present disclosure is not limited thereto. For example, a thin film transistor having an NMOS structure or a CMOS structure may be used as the driving transistor 20.

[0072] Figure 5 The driving transistor 20 shown in may be a polycrystalline thin film transistor including a polysilicon layer, and Figure 5 the switching transistor 10 not shown in may be a polycrystalline thin film transistor or an amorphous thin film transistor including an amorphous silicon layer.

[0073] A gate insulating layer 140 formed of silicon nitride (SiN x ) or silicon oxide (SiO x ) may be disposed on the driving semiconductor layer 132. A gate conductive layer including a driving gate electrode 155 may be formed on the gate insulating layer 140. The gate conductive layer may further include a gate line 151, a first capacitor plate 158, and other lines. In a plan view, the driving gate electrode 155 may overlap at least a part of the driving semiconductor layer 132, specifically, the channel region 135.

[0074] An interlayer insulating layer 160 covering the driving gate electrode 155 may be disposed on the gate insulating layer 140. The gate insulating layer 140 and the interlayer insulating layer 160 may have contact holes exposing the source region 136 and the drain region 137 of the driving semiconductor layer 132.

[0075] Similar to the gate insulating layer 140, the interlayer insulating layer 160 may be formed of silicon nitride (SiN x ) or silicon oxide (SiO x ).

[0076] A data conductive layer including a driving source electrode 176 and a driving drain electrode 177 may be formed on the interlayer insulating layer 160. The data conductive layer may further include a data line 171, a common power supply line 172, a second capacitor plate 178, and other lines. The driving source electrode 176 and the driving drain electrode 177 may be connected to the source region 136 and the drain region 137 of the driving semiconductor layer 132 through the contact holes of the interlayer insulating layer 160 and the gate insulating layer 140, respectively.

[0077] A planarization layer 180 covering the data conductive layer may be disposed on the interlayer insulating layer 160. The planarization layer 180 may be used to remove steps and planarize the steps to improve the light-emitting efficiency of the light-emitting element 70 to be formed thereon.

[0078] In addition, the planarization layer 180 may have a contact hole 182 exposing a part of the driving drain electrode 177.

[0079] The planarization layer 180 may be formed of at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0080] In an embodiment, one of the planarization layer 180 and the interlayer insulating layer 160 may be omitted.

[0081] The pixel electrode 710 of the light-emitting element 70 may be disposed on the planarization layer 180. For example, the display device 100 may include a plurality of pixel electrodes 710 respectively disposed for each pixel, and the pixel electrodes 710 may be arranged to be spaced apart from each other. The pixel electrode 710 may be connected to the driving drain electrode 177 through the contact hole 182 of the planarization layer 180.

[0082] A pixel defining layer 190 having a plurality of openings 199 exposing each of the pixel electrodes 710 may be disposed on the planarization layer 180. For example, the opening 199 of the pixel defining layer 190 may be formed for each pixel. In addition, the pixel electrodes 710 may be arranged to correspond to the openings 199 of the pixel defining layer 190. However, the arrangement of the pixel electrodes 710 is not necessarily limited thereto, and a part of the pixel electrodes 710 may be located below the pixel defining layer 190 so as to overlap the pixel defining layer 190 in a plan view. The pixel defining layer 190 may correspond to the non-emitting region of the pixel, and the opening 199 of the pixel defining layer 190 may correspond to the emitting region of the pixel.

[0083] Spacers SPC1 and SPC2 (see Figure 2 ) may be disposed on the pixel defining layer 190. For example, the spacers SPC1 and SPC2 may be placed in the non-emitting region of the pixel. The spacers SPC1 and SPC2 may maintain the gap between the display substrate 110 and the encapsulation substrate 210 to prevent contact with each other.

[0084] The pixel defining layer 190 and the spacers SPC1 and SPC2 can be formed of a resin such as polyacrylate resin or polyimide or a silica-based inorganic material. The pixel defining layer 190 and the spacers SPC1 and SPC2 can be integrally formed by a photolithography process or a lithography process. For example, the pixel defining layer 190 and the spacers SPC1 and SPC2 can be formed together by a halftone exposure process. However, the present disclosure is not limited thereto, and for example, the pixel defining layer 190 and the spacers SPC1 and SPC2 can be formed sequentially or separately, and different materials can be used for formation.

[0085] The light emitting layer 720 can be disposed on the pixel electrode 710, and the common electrode 730 can be disposed on the light emitting layer 720.

[0086] The light emitting layer 720 can be disposed between the pixel electrode 710 and the common electrode 730 in the opening 199 of the pixel defining layer 190 and provide light. The common electrode 730 can be disposed on the light emitting layer 720, the pixel defining layer 190, and the spacers SPC1 and SPC2.

[0087] The light emitting layer 720 can be made of a low molecular organic material or a high molecular organic material. The light emitting layer 720 can be formed of one or more of a plurality of layers including a light providing layer LPL (see Figure 6 ), a hole injection layer, a hole transport layer HTL (see Figure 6 ), an electron transport layer ETL (see Figure 6 ), and an electron injection layer. In the case of including all of the above, the hole injection layer can be disposed on the pixel electrode 710 as a positive electrode, and the hole transport layer, the light providing layer, the electron transport layer, and the electron injection layer can be sequentially stacked on the pixel electrode 710.

[0088] In Figure 5 , the light emitting layer 720 can be disposed only in the opening 199 of the pixel defining layer 190, but the present disclosure is not limited thereto. For example, the light emitting layer 720 can be formed on the pixel electrode 710 located in the opening 199 of the pixel defining layer 190, and can also be disposed between the pixel defining layer 190 and the common electrode 730. For example, in the case where the light emitting layer 720 includes, for example, a hole injection layer, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer, and a light providing layer LPL (see Figure 6In the case of multiple layers of [[ID=]], during the manufacturing process, by using an opening mask, the remaining layers except for the light-providing layer LPL (e.g., the hole injection layer, the hole transport layer HTL, the electron transport layer ETL, and the electron injection layer) can be formed not only on the pixel electrode 710 but also on the pixel defining layer 190, just like the common electrode 730. In other words, one or more of the layers belonging to the light-emitting layer 720 can be arranged between the pixel defining layer 190 and the common electrode 730.

[0089] Each of the pixel electrode 710 and the common electrode 730 can be formed of a transparent conductive material or a transmissive-reflective or reflective conductive material. Depending on the type of material forming the pixel electrode 710 and the common electrode 730, the display device 100 can be one of a top-emission type, a bottom-emission type, and a dual-emission type.

[0090] The display device 100 according to an embodiment can be a top-emission type display device. For example, the light-emitting element 70 can display an image by emitting light in the direction toward the encapsulation substrate 210 (e.g., the third direction DR3).

[0091] Transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) can be used. Reflective and transmissive-reflective materials such as lithium (Li), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al), silver (Ag), magnesium (Mg), or gold (Au) can be used.

[0092] The encapsulation substrate 210 can be arranged on the common electrode 730. For example, the encapsulation substrate 210 can face the display substrate 110 and cover the switching transistor 10, the driving transistor 20, the storage element 80, and the organic light-emitting element 70 to seal them from the outside.

[0093] The encapsulation substrate 210 can include a second substrate 211. The display substrate 110 and the encapsulation substrate 210 can be joined to each other by a sealant 350 disposed along the edges of the display substrate 110 and the encapsulation substrate 210, and thus the display device 100 can be sealed.

[0094] Figure 6 is a schematic diagram for explaining the movement path of the filler 310 due to the damage of the first spacer SPC1.

[0095] Due to the sagging of the mask, damage may occur in the first spacer SPC1 that supports the mask. For example, as Figure 6As shown, damage may occur in region C, causing damage to the common electrode 730, the electron transport layer ETL, the hole transport layer HTL, and the first spacer SPC1. The filler 310 may penetrate into the emission region of the pixel through the damaged portion, which may cause a problem of dimming of the pixel.

[0096] Figure 7 is a schematic diagram for explaining the movement path of the filler 310 caused by the damage of the second spacer SPC2.

[0097] Due to the sagging of the mask, damage may occur in the second spacer SPC2 that supports the mask. For example, as Figure 7 shown, damage may occur in region C', causing damage to the common electrode 730, the hole transport layer HTL, and the second spacer SPC2. Since the inner angle of the second spacer SPC2 is an obtuse angle, the hole transport layer HTL and the electron transport layer ETL can be disconnected for each pixel in region D. Accordingly, even when damage occurs in region C', the filler 310 cannot penetrate into the emission region of the pixel due to the disconnection in region D. Therefore, even when the second spacer SPC2 is damaged, dimming of the pixel can be prevented. In region C', the second spacer SPC2 and the filler 310 can be in contact with each other through the groove of the second spacer SPC2.

[0098] Since the sagging of the mask described above may occur at the edge of the display substrate 110, damage to the spacer may occur at the edge of the display substrate 110 described above. According to the embodiment, since the first spacer SPC1 is disposed at the center of the display substrate 110 where the mask does not sag, and the second spacer SPC2 is disposed at the edge of the display substrate 110 where the mask may sag, dimming of the pixel can be prevented even when the second spacer SPC2 disposed at the edge of the display panel is damaged.

[0099] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0100] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are intended to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the appended claims and should be interpreted as including all technical spirits within the equivalent scope in the present disclosure.

Claims

1. A display device, characterized in that, Comprising: A first substrate; A transistor located on the first substrate; A pixel electrode disposed on the transistor and connected to the transistor; A pixel defining layer located on the pixel electrode; A spacer located on the pixel defining layer; And A second substrate located on the spacer, wherein the spacer includes a first spacer disposed at the center of the first substrate in a plan view and a second spacer disposed at the edge of the first substrate, and the second spacer has a width that gradually increases in a direction from the first substrate toward the second substrate.

2. The display device according to claim 1, wherein The first spacer has a width that gradually decreases in the direction.

3. The display device according to claim 1, wherein An inner angle of the second spacer is an obtuse angle.

4. The display device according to claim 1, wherein An inner angle of the first spacer is an acute angle.

5. The display device according to claim 1, characterized in that, Further comprising: A filler located between the first substrate and the second substrate.

6. The display device according to claim 5, wherein The second spacer has a groove.

7. The display device according to claim 6, wherein The second spacer and the filler are in contact with each other through the groove of the second spacer.

8. The display device according to claim 5, wherein Further comprising: A sealant disposed between the edge of the first substrate and the edge of the second substrate and surrounding the filler and the spacer.

9. The display device according to claim 1, wherein The spacer is integrally formed with the pixel defining layer.

10. The display device according to claim 9, characterized in that, Each of the first spacer and the second spacer is integrally formed with the pixel defining layer.

Images