Multi-section type dovetail groove and porous grabbing rubber MOS (Metal Oxide Semiconductor) tube frame and packaging structure

Abstract

The utility model discloses a multi-segment dovetail groove and porous grabbing rubber MOS tube frame and a packaging structure, the MOS tube frame comprises a lead frame, a base island and a connecting pin, the lead frame is provided with a packaging area, the base island is arranged in the packaging area, the lead frame is provided with a packaging wire, and the packaging wire is connected with the connecting pin. A plurality of sections of dovetail grooves are formed in the upper part of the packaging area, are positioned above the front surfaces of the base islands and are close to the packaging lines; the plurality of connecting pins are arranged in the packaging area, and a plurality of through holes are formed in the positions, close to the packaging line, of the lower portion of the packaging area on the connecting pins. According to the utility model, the main innovative design lies in the multi-section design of the dovetail groove and the design of a plurality of through hole glue grabbing, so that the combining capacity of the lead frame and the packaging part (epoxy) is greatly improved, the layering phenomenon is avoided, and the product stability and quality are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor chips, and particularly relates to a multi-section dovetail groove, a porous glue-gripping MOS transistor frame and a packaging structure. Background Art

[0002] With the rapid development of the electronic industry, higher requirements are put forward for the reliability of electronic products. In the field of semiconductor packaging, the materials of various components of the product are particularly important, and the combination between materials is also involved. Especially the combination between the encapsulation material epoxy and the copper frame is more important for improving the product reliability.

[0003] In the design of the semiconductor copper frame of the MOS field effect transistor chip, the traditional design is often a planar design or a V-groove design. In the process of realizing the utility model, the applicant found that the packaging structure of the existing MOS field effect transistor chip has at least the following problems:

[0004] 1. In the packaging process, the bonding force between the frame and the epoxy is relatively weak. Especially when the whole product is stamped into single products, the phenomenon of product delamination is likely to occur, and the delamination position is mainly concentrated between the encapsulation material epoxy and the copper frame.

[0005] 2. For products with large-size packaging, after the product is epoxy encapsulated and then the whole product is stamped into single products, the bonding force between the epoxy and the copper frame weakens, and the delamination phenomenon is also likely to occur, thus affecting the product quality of the MOS field effect transistor chip and causing chip failure.

[0006] In view of this, how to solve the problem that the bonding force between the epoxy and the copper frame in the existing packaging structure of the MOS field effect transistor chip, especially for products with large-size packaging, is weak and the delamination phenomenon is likely to occur, becomes the subject to be studied and solved by the utility model. Summary of the Utility Model

[0007] The purpose of the utility model is to provide a multi-section dovetail groove, a porous glue-gripping MOS transistor frame and a packaging structure, which are used to solve the problems existing in the existing packaging structure and process of the MOS field effect transistor chip.

[0008] To achieve the above purpose, the first aspect of the utility model provides a multi-section dovetail groove and a porous glue-gripping MOS transistor packaging structure. The MOS transistor frame includes a lead frame, a base island and connecting pins.

[0009] The lead frame has a packaging area, the base island is arranged in the packaging area, the lead frame has a packaging line, and a multi-section dovetail groove is arranged at the upper part of the packaging area and near the packaging line above the front of the base island.

[0010] A plurality of the connection pins are arranged within the encapsulation area, and a plurality of through holes are provided on the connection pins at a lower position within the encapsulation area near the encapsulation line.

[0011] To achieve the above object, a second aspect of the present utility model provides a multi-segment dovetail groove and multi-hole glue-gripping MOS transistor encapsulation structure. The MOS transistor encapsulation structure includes a substrate and a plurality of encapsulation units provided on the substrate. Each encapsulation unit is provided with a MOS transistor frame as described in the first aspect of the present utility model. Each encapsulation unit is further provided with an encapsulation portion. The encapsulation portion covers the encapsulation area, and the encapsulation portion fills the inside of each dovetail groove and through hole.

[0012] The related content of the present utility model is explained as follows:

[0013] 1. In the above technical solution of the present utility model, aiming at the phenomenon that the bonding force between the MOS transistor frame and epoxy is relatively weak in the encapsulation process and the bonding force between the epoxy and the copper frame weakens after the whole product is stamped into single products in the subsequent process of large-size encapsulation, resulting in product delamination, research and design are specifically carried out on the bonding part between the frame and epoxy. Among them, the innovative design includes a multi-segment dovetail groove, a multi-hole glue-gripping MOS transistor frame and an encapsulation structure. Among them, on the base island of the MOS transistor frame, a multi-segment dovetail groove is provided at an upper part within the encapsulation area and above the front of the base island near the encapsulation line. On the connection pins of the MOS transistor frame, a plurality of through holes are provided on the connection pins at a lower position within the encapsulation area near the encapsulation line. During subsequent encapsulation, the encapsulating material epoxy can flow into the plurality of dovetail grooves and the plurality of through holes, so as to strengthen the bonding force between the epoxy and the frame and reduce peeling. Among them, the dovetail groove adopts a multi-segment dovetail groove, and the through holes adopt a plurality of through holes, both of which can improve the glue-gripping ability on the premise of ensuring the structural strength of the MOS transistor frame itself.

[0014] 2. In the technical solution of the above first aspect, the encapsulation line is arranged along the horizontal and vertical directions on the periphery of the encapsulation area, with a reasonable structure, which is convenient for subsequent encapsulation.

[0015] 3. In the technical solution of the above first aspect, the number of the dovetail grooves is three. The three dovetail grooves are arranged at equal intervals in the upper part of the encapsulation area parallel to the horizontal encapsulation line on the same horizontal line. The number is set reasonably, and the position and structure are arranged reasonably, which can improve the glue-gripping ability on the premise of ensuring the structural strength of the MOS transistor frame itself.

[0016] 4. In the technical solution of the above first aspect, the overall depth of the dovetail groove is 0.1 m to 0.2 mm. The depth dimension is set reasonably, which can ensure the glue-gripping ability without weakening the structural strength.

[0017] 5. In the technical solution of the first aspect described above, the number of the through-holes is three or four, and the three or four through-holes are arranged in a same horizontal line parallel to the lateral encapsulation line at the lower part of the encapsulation area. With a reasonable number setting and a reasonable position and structure arrangement, the gum-gripping ability can be improved on the premise of ensuring the structural strength of the MOS transistor frame itself.

[0018] 6. In the technical solution of the first aspect described above, the surface of the base island near the dovetail groove is a burr surface, thereby further improving the gum-gripping ability of the dovetail groove part and the periphery of the dovetail groove and enhancing the bonding strength.

[0019] 7. In the technical solution of the first aspect described above, the dovetail groove includes a stepped part on the outer side and a dovetail part on the inner side, so that the encapsulation part first enters the stepped part and then flows into the dovetail part. This kind of structure further strengthens the bonding strength.

[0020] 8. In the technical solution of the second aspect described above, a chip is placed on the base island, and the chip has a gate and a source; a plurality of the connection pins are arranged on the periphery of the base island, and the gate and the source are connected to their respective corresponding connection pins by wire bonding.

[0021] 9. In the technical solution of the second aspect described above, a downward stepped part is provided on the back surface of the base island, and the encapsulation part fills the stepped part, thereby strengthening the bonding strength between the encapsulation part and the base island.

[0022] 10. In the present utility model, unless otherwise clearly defined and limited, terms such as "installation", "connection", "connection", "fixation" and the like should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium. It may be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0023] 11. In the present utility model, the orientation or positional relationship indicated by terms such as "upper", "lower", "bottom", "inner", "outer" and the like is based on the orientation or positional assembly relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0024] 12. In addition, in the description of the present utility model, it should be noted that if terms such as "first" and "second" are used to define components in this text, those skilled in the art should understand that the use of terms such as "first" and "second" is only for facilitating the description of the present utility model and simplifying the description. Without additional statements, the above terms have no special meanings.

[0025] Due to the application of the above solution, the present utility model has the following advantages and effects compared with the prior art:

[0026] In the present utility model, aiming at the phenomenon that the bonding force between the MOS transistor frame and epoxy is relatively weak in the encapsulation process and the bonding force between epoxy and copper frame weakens after the whole product is stamped into single products in the subsequent process of large-size packaging, resulting in product delamination, the bonding part between the frame and epoxy is specifically researched and designed. The innovative design includes a multi-segment dovetail groove and a porous glue-gripping MOS transistor frame and packaging structure. Among them, on the base island of the MOS transistor frame, a multi-segment dovetail groove is arranged at the upper part of the encapsulation area and near the encapsulation line above the front of the base island. On the connection lead of the MOS transistor frame, a plurality of through holes are arranged at the lower part of the connection lead near the encapsulation line in the encapsulation area. During subsequent encapsulation, the encapsulating material epoxy can flow into the plurality of dovetail grooves and the plurality of through holes, thereby strengthening the bonding force between epoxy and the frame and reducing peeling. Among them, the dovetail groove adopts a multi-segment dovetail groove, and the through holes adopt a plurality of through holes, both of which can improve the glue-gripping ability on the premise of ensuring the structural strength of the MOS transistor frame itself, thereby improving product quality and the stability of service performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the MOS field effect transistor chip packaging structure according to an embodiment of the present utility model;

[0028] Figure 2 It is a schematic diagram of the encapsulation unit according to an embodiment of the present utility model;

[0029] Figure 3 It is a schematic diagram of the base island, connection lead, and encapsulation part according to an embodiment of the present utility model;

[0030] Figure 4 It is a schematic diagram of the dovetail groove part of the base island according to an embodiment of the present utility model.

[0031] The parts in the above drawings are represented as follows:

[0032] 100 Substrate

[0033] 200 Encapsulation unit

[0034] 1 Lead frame

[0035] 11 Encapsulation area

[0036] 12 Encapsulation line

[0037] 2 Base island

[0038] 21 Step portion

[0039] 22 Burr surface

[0040] 3 Chip

[0041] 31 Gate

[0042] 32 Source

[0043] 4 Connection pin

[0044] 41 Through hole

[0045] 5 Encapsulation part

[0046] 6 Lead

[0047] 7 Dovetail groove

[0048] 71 Dovetail part

[0049] 72 Step portion. Detailed implementation manners

[0050] To make the above objects, features, and advantages of the present application more obvious and understandable, the following detailed description of the specific implementation manners of the present application will be given in conjunction with the accompanying drawings. Many specific details are set forth in the following description to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0051] Embodiment 1. The present utility model discloses a multi - segment dovetail groove 7 and a porous glue - catching MOS transistor frame. As Figure 2 shown, the MOS transistor frame includes a lead frame 1, a base island 2, and a connection pin 4.

[0052] The lead frame 1 has an encapsulation area 11, the base island 2 is disposed within the encapsulation area 11, the lead frame 1 has an encapsulation line 12, and a multi - segment dovetail groove 7 is provided at a position above the upper part of the encapsulation area 11 and near the encapsulation line 12 above the front surface of the base island 2.

[0053] A plurality of the connection pins 4 are arranged within the encapsulation area 11, and a plurality of through holes 41 are provided on the connection pins 4 at a position near the encapsulation line 12 in the lower part of the encapsulation area 11.

[0054] In the first embodiment of the present utility model, the encapsulation line 12 is arranged along the horizontal and vertical directions on the periphery of the encapsulation area 11, with a reasonable structure, which is convenient for subsequent encapsulation.

[0055] In the first embodiment of the present utility model, the number of the dovetail grooves 7 is three, and the three dovetail grooves 7 are arranged at equal intervals in the upper part of the encapsulation area 11 in the same horizontal line parallel to the horizontal encapsulation line 12. The number is reasonably set, and the position structure is reasonably arranged. On the premise of ensuring the structural strength of the MOS transistor frame itself, the glue grasping ability can be improved. Specifically, the surface of the base island 2 near the dovetail groove 7 is a burr surface 22, so as to further improve the glue grasping ability of the dovetail groove 7 part and the surrounding area of the dovetail groove 7, and improve the bonding strength. Further, the dovetail groove 7 includes a step portion 7221 on the outer side and a dovetail portion 71 on the inner side, so that the encapsulation portion 5 first enters the step portion 7221 and then flows into the dovetail portion 71. This structure further strengthens the bonding strength.

[0056] In the first embodiment of the present utility model, the overall depth of the dovetail groove 7 is 0.1m to 0.2mm, and the depth dimension is reasonably set. On the premise of not weakening the structural strength, the glue grasping ability is ensured.

[0057] In the first embodiment of the present utility model, the number of the through holes 41 is three or four, and the three or four through holes 41 are arranged in the lower part of the encapsulation area 11 in the same horizontal line parallel to the horizontal encapsulation line 12. The number is reasonably set, and the position structure is reasonably arranged. On the premise of ensuring the structural strength of the MOS transistor frame itself, the glue grasping ability can be improved.

[0058] Embodiment 2: The second embodiment of the present utility model proposes a multi-stage dovetail groove 7 and a multi-hole glue-grasping MOS transistor encapsulation structure. The MOS transistor encapsulation structure includes a substrate 100 and a plurality of encapsulation units 200 arranged on the substrate 100. The MOS transistor frames as described in the first embodiment of the present utility model are arranged on each encapsulation unit 200, and an encapsulation portion 5 is further arranged on each encapsulation unit 200. The encapsulation portion 5 covers the encapsulation area 11, and the encapsulation portion 5 fills the inside of each dovetail groove 7 and through hole 41.

[0059] In the second embodiment of the present utility model, a chip 3 is placed on the base island 2, and the chip 3 has a gate 31 and a source 32; a plurality of the connection pins 4 are arranged on the periphery of the base island 2, and the gate 31 and the source 32 are connected to their respective corresponding connection pins 4 by wire bonding through a lead 6. Further, a downward step portion 7221 is arranged on the back surface of the base island 2, and the encapsulation portion 5 fills the step portion 7221, so as to strengthen the bonding strength between the encapsulation portion 5 and the base island 2.

[0060] Through the implementation of Embodiment 1 and Embodiment 2 of the present utility model, the innovative design includes a multi-segment dovetail groove 7, a porous glue-gripping MOS transistor frame and a packaging structure. Among them, on the base island 2 of the MOS transistor frame, a multi-segment dovetail groove 7 is arranged above the upper part of its packaging area 11 and near the packaging line 12 above the front of the base island 2. On the connection pin 4 of the MOS transistor frame, a plurality of through holes 41 are arranged near the packaging line 12 at the lower part of the connection pin 4 in the packaging area 11. During subsequent packaging, the encapsulating material epoxy can flow into the plurality of dovetail grooves 7 and the plurality of through holes 41, so as to strengthen the bonding force between the epoxy and the frame and reduce peeling. Among them, the dovetail groove 7 adopts a multi-segment dovetail groove 7, and the through holes 41 adopt a plurality of through holes 41, which can improve the glue-gripping ability on the premise of ensuring the structural strength of the MOS transistor frame itself, so as to improve the product quality and the stability of the use performance.

[0061] Next, each structure of the embodiment of the present utility model will be described in detail according to the respective drawings.

[0062] As Figure 1 shown, a multi-segment dovetail groove 7 and a porous glue-gripping MOS transistor packaging structure of an embodiment of the present utility model includes a substrate 100, and a plurality of packaging units 200 are arranged on the substrate 100. Figure 1 Only some of the packaging units 200 are shown therein.

[0063] As Figure 2 shown, on each packaging unit 200 of the embodiment of the present utility model, a MOS transistor frame and a packaging part 5 are arranged. The MOS transistor frame includes a lead frame 1, a base island 2, and a connection pin 4. The lead frame 1 has a packaging area 11, the base island 2 is arranged in the packaging area 11, the lead frame 1 has a packaging line 12, the packaging part 5 covers the packaging area 11, and a plurality of the connection pins 4 are arranged in the packaging area 11. A multi-segment dovetail groove 7 is arranged above the upper part of the packaging area 11 and near the packaging line 12 above the front of the base island 2; a plurality of through holes 41 are arranged near the packaging line 12 at the lower part of the connection pin 4 in the packaging area 11.

[0064] As Figure 3 shown, this is a schematic diagram of the packaged packaging unit 200. The packaging part 5 enters each dovetail groove 7, each through hole 41 and the step part 7221 on the back of the base island 2, so as to ensure glue locking, and make the packaging part 5 firmly and reliably combined with the base island 2, thereby avoiding the occurrence of delamination.

[0065] As Figure 4As shown, this is a schematic structural diagram of the dovetail groove 7 on the base island 2. The dovetail groove 7 includes a stepped portion 7221 on the outer side and a dovetail portion 71 on the inner side. The surface of the base island 2 near the dovetail groove 7 is a burr surface 22, so as to further improve the glue gripping ability and the bonding strength.

[0066] As can be seen from the above embodiments, the main innovative design of the present utility model lies in the multi-segment design of the dovetail groove 7 and the design of multiple through holes 41 for glue gripping, so as to greatly improve the bonding ability between the lead frame 1 and the encapsulation part 5 (epoxy), avoid delamination, improve the product stability and quality, and thus achieve the purpose of the present invention.

[0067] The above embodiments are only for illustrating the technical concept and features of the present utility model, and the purpose is to enable those who are familiar with this technology to understand the content of the present utility model and implement it accordingly, and it cannot be used to limit the protection scope of the present utility model. Any equivalent changes or modifications made according to the spirit and essence of the present utility model should be covered within the protection scope of the present utility model.

Claims

1. A multi - section dovetail groove (7) and a porous glue - grasping MOS transistor frame, characterized in that: The MOS transistor frame includes a lead frame (1), a base island (2), and connecting pins (4); The lead frame (1) has a packaging area (11), the base island (2) is arranged in the packaging area (11), the lead frame (1) has a packaging wire (12), and a multi - section dovetail groove (7) is arranged at the upper part of the packaging area (11) and near the packaging wire (12) above the front of the base island (2); A plurality of the connecting pins (4) are arranged in the packaging area (11), and a plurality of through - holes (41) are arranged on the connecting pins (4) near the packaging wire (12) at the lower part of the packaging area (11).

2. The multi-stage dovetail groove (7) and the porous glue-gripping MOS transistor frame according to claim 1, characterized in that: The packaging wire (12) is arranged along the horizontal and vertical directions on the periphery of the packaging area (11).

3. The multi-stage dovetail groove (7) and the porous glue-gripping MOS tube frame according to claim 2, characterized in that: The number of the dovetail grooves (7) is three, and the three dovetail grooves (7) are arranged at equal intervals in the upper part of the packaging area (11) in a horizontal line parallel to the horizontal packaging wire (12).

4. The multi-segment dovetail groove (7) and the porous glue-gripping MOS tube frame according to claim 3, characterized in that: The overall depth of the dovetail groove (7) is 0.1m - 0.2mm.

5. The multi-stage dovetail groove (7) and the porous glue-gripping MOS tube frame according to claim 3, characterized in that: The number of the through - holes (41) is three or four, and the three or four through - holes (41) are arranged in a horizontal line parallel to the horizontal packaging wire (12) in the lower part of the packaging area (11).

6. The multi-stage dovetail groove (7) and the porous glue-gripping MOS tube frame according to claim 1, characterized in that: The surface of the base island (2) near the dovetail groove (7) is a burr surface (22).

7. The multi-stage dovetail groove (7) and the porous glue-gripping MOS tube frame according to claim 1, characterized in that: The dovetail groove (7) includes a step part (72)(21) on the outer side and a dovetail part (71) on the inner side.

8. A multi-segment dovetail groove (7) and a porous glue-gripping MOS tube packaging structure, characterized in that: The MOS transistor packaging structure includes a substrate (100) and a plurality of packaging units (200) arranged on the substrate (100). Each packaging unit (200) is provided with a MOS transistor frame as described in any one of claims 1 to 6. Each packaging unit (200) is also provided with a packaging part (5). The packaging part (5) covers the packaging area (11), and the packaging part (5) fills the inside of each dovetail groove (7) and through - hole (41).

9. The multi-stage dovetail groove (7) and the porous grab-glue MOS transistor packaging structure according to claim 8, characterized in that: A chip (3) is placed on the base island (2), and the chip (3) has a gate (31) and a source (32); a plurality of the connecting pins (4) are arranged on the periphery of the base island (2), and the gate (31) and the source (32) are connected to their respective corresponding connecting pins (4) by wire bonding.

10. The multi-stage dovetail groove (7) and the porous glue-gripping MOS transistor packaging structure according to claim 9, characterized in that: A downward - facing step part (72)(21) is arranged on the back of the base island (2), and the packaging part (5) fills the step part (72)(21).

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