Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate comprises an SD layer, a VITO layer, a grid layer, a first via hole and a second via hole. The gate layer is in lap joint with the VITO layer through a first via hole, the VITO layer is in lap joint with the SD layer through a second via hole, and the arrangement direction of the first via hole and the second via hole coincides with the direction of a gate metal wire of the gate layer. According to the display device and the display device, the via hole for the lap joint of the gate layer and the VITO layer and the via hole for the lap joint of the VITO layer and the SD layer are arranged in the direction overlapped with the gate metal wire of the gate layer, so that the distance between two adjacent gate lines is shortened, the space is saved, the frame of the display device is narrower, and the product competitiveness is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display panels, and particularly relates to an array substrate and a display device. Background Art

[0002] With the development of panel technology, consumers have higher and higher requirements for the bezel of the display screen. Narrow bezel display panels with a larger screen-to-bezel ratio are gradually becoming the mainstream and are developing towards borderless displays.

[0003] In the existing display screen, the connection between metals in the bezel area is through VITO connection, that is, the connection between Gate metal (also called M1 metal) and SD metal (also called M2 metal) is bridged through VITO. That is, VITO is connected to Gate through via CON, and VITO is then connected to SD through via CON, so that Gate and SD are connected.

[0004] However, the area occupied by the via area of the above existing display screen is relatively large, resulting in limited wiring space. Summary of the Utility Model

[0005] In the existing display screen, the area occupied by the via area is too large, which limits the wiring in the bezel area and is not conducive to improving the product competitiveness.

[0006] In view of the above problems, an array substrate and a display device are proposed. By arranging the vias for overlapping the gate layer and the VITO layer and the vias for overlapping the VITO layer and the SD layer in the direction coinciding with the gate metal lines of the gate layer, the distance between two adjacent gate lines is shortened, saving space, which is conducive to making the bezel of the display device narrower and improving the product competitiveness.

[0007] In a first aspect, an array substrate includes:

[0008] SD layer;

[0009] VITO layer;

[0010] Gate layer;

[0011] First via;

[0012] Second via;

[0013] The gate layer overlaps with the VITO layer through the first via, and the VITO layer overlaps with the SD layer through the second via, and:

[0014] The arrangement direction of the first via and the second via coincides with the direction of the gate metal lines of the gate layer.

[0015] In the first possible implementation manner in combination with the array substrate of the present utility model, the array substrate further sequentially includes:

[0016] An isolation layer;

[0017] An insulating layer;

[0018] A planarization layer;

[0019] A passivation layer;

[0020] The isolation layer is fabricated between the insulating layer and the glass substrate;

[0021] The planarization layer is fabricated between the insulating layer and the passivation layer;

[0022] The first via hole passes through the insulating layer, and the second via hole passes through the planarization layer and the insulating layer.

[0023] In the second possible implementation manner in combination with the first possible implementation manner of the present utility model, the gate layer is fabricated in the insulating layer, the SD layer is fabricated in the planarization layer, and the VITO layer is fabricated in the passivation layer.

[0024] In the third possible implementation manner in combination with the second possible implementation manner of the present utility model, the array substrate further includes:

[0025] A PITO layer;

[0026] The PITO layer is fabricated on the passivation layer.

[0027] In the fourth possible implementation manner in combination with the third possible implementation manner of the present utility model, the array substrate further includes:

[0028] A polysilicon layer;

[0029] The polysilicon layer is fabricated in the isolation layer.

[0030] In the fifth possible implementation manner in combination with the fourth possible implementation manner of the present utility model, the array substrate further includes:

[0031] A third via hole;

[0032] The third via hole passes through the passivation layer, the planarization layer, the insulating layer, and the isolation layer to lap the PITO layer and the polysilicon layer.

[0033] In the sixth possible implementation manner in combination with the fifth possible implementation manner of the present utility model, the array substrate further sequentially includes:

[0034] A buffer layer;

[0035] A glass substrate;

[0036] The buffer layer is disposed between the isolation layer and the glass substrate.

[0037] In a second aspect, a display device includes the array substrate described in the first aspect.

[0038] By implementing the array substrate and the display device of the present utility model, the vias for overlapping the gate layer and the VITO layer and the vias for overlapping the VITO layer and the SD layer are disposed in a direction coinciding with the gate metal lines of the gate layer, shortening the distance between two adjacent gate lines, saving space, which is conducive to making the border of the display device narrower and improving the product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0040] Figure 1 FIG. 17 is a schematic structural diagram among the gate layer, the VITO layer, and the SD layer in an array substrate of the prior art;

[0041] Figure 2 FIG. 21 is a schematic structural diagram among the gate layer, the VITO layer, and the SD layer in the array substrate of the present application;

[0042] Figure 3 FIG. 25 is a schematic structural diagram of the array substrate of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The technical solutions in the present utility model will be clearly and completely described below with reference to the drawings in the present utility model. Obviously, the described embodiments are only some of the embodiments of the present utility model, rather than all of them. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present utility model.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0045] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0046] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0047] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0048] In the existing display screen, the area occupied by the via region is too large, which limits the wiring in the border region and is not conducive to improving the product competitiveness. For example Figure 1 , Figure 1 FIG. 13 is a schematic structural diagram among a gate layer 500, a VITO layer 900, and an SD layer 800 in an array substrate of the prior art;

[0049] The connection between the gate layer 500 (Gate metal) (also referred to as M1 metal) and the SD layer 800 (SD metal, also referred to as M2 metal) is bridged through the VITO layer 900, that is, the VITO layer 900 is connected to the gate layer 500 (Gate layer) through a first via 101 (via CON), and the VITO layer 900 is then connected to the SD layer 800 through a second via 102 (via CON), so that the gate layer 500 (Gate layer) is connected to the SD layer 800. To prevent short circuits between the gate layers 500 (Gate metal) of the same layer, a certain space is avoided.

[0050] Figure 1 In FIG. 13, the pitch between two Gate metals is A. In this case, the more wiring and the more vias there are, the more wiring space and the more space are required.

[0051] To address the above problems, an array substrate and a display device are proposed.

[0052] In a first aspect, asFigure 2 , Figure 2 It is a schematic diagram of the structure among the gate layer 500, the VITO layer 900, and the SD layer 800 in the array substrate of the present application; an array substrate includes an SD layer 800, a VITO layer 900, a gate layer 500, a first via 101, and a second via 102; the gate layer 500 is overlapped with the VITO layer 900 through the first via 101, the VITO layer 900 is overlapped with the SD layer 800 through the second via 102, and the arrangement directions of the first via 101 and the second via 102 coincide with the direction of the gate metal line of the gate layer 500. By arranging the via for overlapping the gate layer 500 and the VITO layer 900 and the via for overlapping the VITO layer 900 and the SD layer 800 in the direction coinciding with the gate metal line of the gate layer 500, the distance between two adjacent gate lines is shortened, space is saved, which is beneficial to making the border of the display device narrower and improving the product competitiveness.

[0053] As Figure 3 , the array substrate in the present application sequentially includes: a glass substrate 100, a buffer layer 200, a polysilicon layer 300, an isolation layer 105, an insulating layer 400, a gate layer 500, a planarization layer 600, a passivation layer 700, an SD layer 800, a VITO layer 900, a first via 101, a second via 102, a third via 103, and a PITO layer 104.

[0054] The polysilicon layer 300 is disposed in the isolation layer 105, the gate layer 500 is disposed in the insulating layer 400, the SD layer is disposed in the planarization layer 600, and the VITO layer is disposed in the passivation layer 700. The PITO layer is disposed on the passivation layer 700.

[0055] Further, as Figure 3 , Figure 3 It is a schematic diagram of the structure of the array substrate of the present application. The array substrate further sequentially includes an isolation layer 105, an insulating layer 400, a planarization layer 600, and a passivation layer 700; the isolation layer 105 is fabricated between the insulating layer 400 and the glass substrate 100; the planarization layer 600 is fabricated between the insulating layer 400 and the passivation layer 700; the first via penetrates through the insulating layer 400, and the second via penetrates through the planarization layer 600 and the insulating layer 400.

[0056] Further, the gate layer 500 is fabricated in the insulating layer 400, the SD layer 800 is fabricated in the planarization layer 600, and the VITO layer 900 is fabricated in the passivation layer 700.

[0057] Further, the array substrate further includes a PITO layer 104; the PITO layer 104 is fabricated on the passivation layer 700.

[0058] Further, the array substrate further includes a polysilicon layer 300; the polysilicon layer 300 is fabricated in the isolation layer 105.

[0059] Further, the array substrate further includes a third via hole 103; the third via hole 103 passes through the passivation layer 700, the planarization layer 600, the insulating layer 400, and the isolation layer 105 to overlap the PITO layer 104 with the polysilicon layer 300.

[0060] Further, the array substrate further includes a buffer layer 200 and a glass substrate 100 in sequence; the buffer layer 200 is disposed between the isolation layer 105 and the glass substrate 100.

[0061] In a second aspect, a display device includes the array substrate of the first aspect.

[0062] Implementing the array substrate and the display device of the present utility model, by arranging the via holes for overlapping the gate layer 500 with the VITO layer 900 and the via holes for overlapping the VITO layer 900 with the SD layer 800 in the direction coinciding with the gate metal lines of the gate layer 500, the distance between two adjacent gate lines is shortened, space is saved, which is conducive to making the border of the display device narrower and improving the product competitiveness.

[0063] The above are only the preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An array substrate, characterized in that, Comprising: SD layer; VITO layer; Gate layer; First via; Second via; The gate layer is overlapped with the VITO layer through the first via, and the VITO layer is overlapped with the SD layer through the second via, and: The arrangement direction of the first via and the second via coincides with the direction of the gate metal line of the gate layer.

2. The array substrate according to claim 1, wherein The array substrate further sequentially includes: Isolation layer; Insulating layer; Flat layer; Passivation layer; The isolation layer is fabricated between the insulating layer and the glass substrate; The flat layer is fabricated between the insulating layer and the passivation layer; The first via passes through the insulating layer, and the second via passes through the flat layer and the insulating layer.

3. The array substrate according to claim 2, characterized in that, The gate layer is fabricated in the insulating layer, the SD layer is fabricated in the flat layer, and the VITO layer is fabricated in the passivation layer.

4. The array substrate according to claim 3, wherein The array substrate further includes: PITO layer; The PITO layer is fabricated on the passivation layer.

5. The array substrate according to claim 4, wherein The array substrate further includes: Polycrystalline silicon layer; The polycrystalline silicon layer is fabricated in the isolation layer.

6. The array substrate according to claim 5, wherein The array substrate further includes: Third via; The third via passes through the passivation layer, flat layer, insulating layer and isolation layer to overlap the PITO layer and the polycrystalline silicon layer.

7. The array substrate according to claim 6, wherein The array substrate further sequentially includes: Buffer layer; Glass substrate; The buffer layer is disposed between the isolation layer and the glass substrate.

8. A display device, characterized in that, An array substrate according to any one of claims 1-7.

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