Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate comprises a display area and a non-display area located on at least one side of the display area. The array substrate comprises a substrate body, at least one first transistor and at least one second transistor, the first transistor and the second transistor are located on the substrate body, the first transistor is located in the display area, and the second transistor is located in the non-display area; the first transistor comprises a first active layer, and the first active layer has a first mobility; the second transistor comprises a second active layer, and the second active layer has a second mobility; wherein the second migration rate is larger than the first migration rate, and the problems of sand grains, cross grains and the like of an existing array substrate in the high-temperature and high-humidity long-time reliability process can be solved.

Description

Technical Field

[0001] The utility model relates to, but is not limited to, the field of display technologies, and particularly relates to an array substrate and a display device. Background Art

[0002] A liquid crystal display (LCD) is a common type of display currently. The LCD display uses two pieces of polarizing materials, and between them is a liquid crystal solution. When an electric current passes through the liquid, it causes the crystals to rearrange so that light cannot pass through them. Therefore, each crystal acts like a shutter, allowing light to pass through or blocking it. Currently, liquid crystal displays (LCDs) are developing towards the goals of being light, thin, short, and small.

[0003] Existing liquid crystal displays will have problems such as horizontal stripes and sand grains during a long-term reliability process under high temperature and high humidity. Summary of the Utility Model

[0004] Embodiments of the utility model provide an array substrate and a display device, which can solve problems such as horizontal stripes and sand grains that occur in an existing array substrate during a long-term reliability process under high temperature and high humidity.

[0005] On the one hand, embodiments of the utility model provide an array substrate, including a display area and a non-display area located on at least one side of the display area; the array substrate includes a substrate and at least one first transistor and at least one second transistor located on the substrate, and the first transistor is located in the display area, and the second transistor is located in the non-display area; the first transistor includes a first active layer, and the first active layer has a first mobility; the second transistor includes a second active layer, and the second active layer has a second mobility; wherein, the second mobility is greater than the first mobility.

[0006] In some exemplary embodiments, the first active layer is a single-layer structure or a composite-layer structure, and the second active layer is a single-layer structure or a composite-layer structure; in a state where the first active layer is a composite-layer structure, each film layer constituting the composite-layer structure has a mobility, and the first mobility is the maximum mobility among multiple mobilities; in a state where the second active layer is a composite-layer structure, each film layer constituting the composite-layer structure has a mobility, and the second mobility is the maximum mobility among multiple mobilities.

[0007] In some exemplary embodiments, at least part of the film layer of the first active layer and at least part of the film layer of the second active layer are of the same layer structure.

[0008] In some exemplary embodiments, the second active layer includes a first sub-layer and a second sub-layer stacked on top of each other, with the first sub-layer closer to the substrate than the second sub-layer; the mobility of the first sub-layer is greater than that of the second sub-layer.

[0009] In some exemplary embodiments, the materials of the first sub-layer and the second sub-layer are both indium gallium zinc oxide, and the indium content in the first sub-layer and the second sub-layer is different.

[0010] In some exemplary embodiments, the thickness of the second sub-layer is greater than that of the first sub-layer.

[0011] In some exemplary embodiments, the thickness of the second sub-layer is 4 to 10 times that of the first sub-layer.

[0012] In some exemplary embodiments, the thickness range of the first sub-layer is from 100 Å to 200 Å; the thickness range of the second sub-layer is from 800 Å to 1000 Å.

[0013] In some exemplary embodiments, the mobility of the second sub-layer is the same as the first mobility.

[0014] In some exemplary embodiments, the second sub-layer and the first active layer have the same layer structure.

[0015] In some exemplary embodiments, the first active layer has a first dimension, which refers to the minimum dimension between the first pole and the second pole of the first transistor along the extension direction of the first active layer; the second active layer has a second dimension, which refers to the maximum dimension between the first pole and the second pole of the second transistor along the extension direction of the second active layer; wherein, the first dimension is the same as the second dimension.

[0016] In some exemplary embodiments, the first active layer has a first dimension, which refers to the minimum dimension between the first pole and the second pole of the first transistor along the extension direction of the first active layer; the second active layer has a second dimension, which refers to the maximum dimension between the first pole and the second pole of the second transistor along the extension direction of the second active layer; wherein, the second dimension is less than the first dimension.

[0017] In some exemplary embodiments, the second dimension is 0.5 μm to 1.0 μm smaller than the first dimension.

[0018] In some exemplary embodiments, the range of the first dimension is from 5.0 micrometers to 6.0 micrometers, and the range of the second dimension is from 4.0 micrometers to 5.0 micrometers.

[0019] On the other hand, an embodiment of the present invention provides a display device, including the array substrate described in any one of the foregoing embodiments.

[0020] Other features and advantages of the present invention will be described in the following description, and some of them will be obvious from the description, or can be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the description. Together with the embodiments of the present invention, they are used to explain the technical solutions of the present invention, and do not constitute a limitation to the technical solutions of the present invention.

[0022] Figure 1 is a front view schematic diagram of an array substrate according to an embodiment of the present invention;

[0023] Figure 2 is a partial plan view schematic diagram of a display area of an array substrate according to an embodiment of the present invention;

[0024] Figure 2A is Figure 2 a schematic enlarged cross-sectional view at the marked A-A in

[0025] Figure 3 is a partial plan view schematic diagram of a second non-display area of an array substrate according to an embodiment of the present invention;

[0026] Figure 3A is Figure 3 a schematic enlarged cross-sectional view at the marked B-B in

[0027] Figure 4A is a cross-sectional schematic diagram of an array substrate after forming a first conductive layer pattern according to an embodiment of the present invention;

[0028] Figure 4B is a cross-sectional schematic diagram of an array substrate after forming a first semiconductor thin film according to an embodiment of the present invention;

[0029] Figure 4C is a cross-sectional schematic diagram of an array substrate after forming a first photoresist layer according to an embodiment of the present invention;

[0030] Figure 4D is a cross-sectional schematic diagram of an array substrate after forming a first semiconductor layer pattern according to an embodiment of the present invention;

[0031] Figure 4E A cross-sectional schematic view of an array substrate after forming a second photoresist layer according to an embodiment of the present invention;

[0032] Figure 4F A cross-sectional schematic view of an array substrate after forming a second semiconductor layer pattern according to an embodiment of the present invention;

[0033] Figure 4G A cross-sectional schematic view of an array substrate after forming a second conductive layer pattern according to an embodiment of the present invention;

[0034] Figure 4H A cross-sectional schematic view of an array substrate after forming a fourth insulating layer according to an embodiment of the present invention;

[0035] Figure 5A A characteristic test curve graph of a transistor in the display area of an array substrate;

[0036] Figure 5B A comparison graph of characteristic test curves of transistors in the display area of an array substrate;

[0037] Figure 6 A comparison graph of characteristic test curves of transistors in the second non-display area of an array substrate. Detailed implementation manners

[0038] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manner and content can be transformed into one or more forms without departing from the gist and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other arbitrarily.

[0039] In the accompanying drawings, sometimes for clarity, the sizes, thicknesses of layers or regions of one or more constituent elements are exaggerated. Therefore, one aspect of the present invention is not necessarily limited to this size, and the shapes and sizes of one or more components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one aspect of the present invention is not limited to the shapes or values shown in the drawings.

[0040] The ordinal numbers such as "first", "second", "third", etc. in the present invention are set to avoid confusion of constituent elements, rather than to limit in terms of quantity. The "multiple" in the present invention includes two and more than two quantities.

[0041] In the present utility model, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the constituent elements with reference to the attached drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction of describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0042] In the present utility model, unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present utility model can be understood according to the situation.

[0043] In the present utility model, "electrically connected" includes the situation where the constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0044] In the present utility model, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present utility model, the channel region refers to the region where current mainly flows.

[0045] In the present utility model, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in the present utility model, the "source electrode" and "drain electrode" can be interchanged.

[0046] In the present utility model, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus may include a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus may include a state where the angle is more than 85° and less than 95°.

[0047] In the present utility model, "film" and "layer" can be interchanged. For example, sometimes the "conductive layer" can be changed to the "conductive film". Similarly, sometimes the "insulating film" can be changed to the "insulating layer".

[0048] "About" and "substantially" in the present utility model refer to values that do not strictly define the boundaries and allow values within the process and measurement error ranges.

[0049] In the present utility model, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges, and deformations, etc.

[0050] Thin film transistor liquid crystal displays (TFT-LCDs) have occupied a dominant position in the current flat panel display market due to their characteristics such as small size, low power consumption, and no radiation. The key core of TFT-LCD lies in the preparation of TFTs on the array substrate and ensuring TFT-related characteristics. In practical applications, the opening and closing of TFTs are controlled by controlling the magnitude of the gate voltage to achieve the transmission of voltage from the data line to the pixel electrode, thereby meeting the voltage requirements of the pixel electrode to satisfy different display brightnesses.

[0051] In the TFT characteristic curve, the ratio Ion / Ioff of the current Ion when the gate is open to the current Ioff when the gate is closed is required to be ≥10 6 . Currently, the main materials for the active layer constituting TFTs are amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and oxides (IGZO, ZnO, etc.). TFTs with an oxide active layer (oxide TFTs) have been studied more and more in recent years due to their advantages such as high mobility and large on / off ratio, and the applications of corresponding products are also becoming more and more extensive.

[0052] The characteristics of oxide TFTs are that their long-term reliability stability under high temperature and high humidity is worse than that of amorphous silicon (a-Si) TFTs. Through research, it is found that due to the right drift of the TFTs in the GOA region (border region), the current Ion when the gate is opened decreases. The TFT characteristics in the GOA region can be improved by increasing the mobility of the active layer. However, increasing the mobility of the active layer will cause particle defects in the AA region (display region). Through research, it is found that during the high-temperature and high-humidity lighting process, the TFT curve in the AA region drifts to the left, resulting in a significant increase in the current Ioff when the gate is closed. The higher the temperature and the longer the time, the more serious the left drift of the TFT characteristics in the AA region.

[0053] During the long-term lighting process of high-temperature and high-humidity reliability, the voltages applied to the gates of the TFTs in the AA region and the GOA region are different. The GOA region mainly applies the VGH voltage for a long time, and the AA region mainly applies the VGL voltage for a long time. Usually, the VGH voltage value is between 15 volts and 20 volts, and the VGL voltage value is between -7.5 volts and -13 volts. Therefore, the TFT characteristic curve in the GOA region is prone to right drift, and the TFT characteristic curve in the AA region is prone to left drift. Using TFTs with a low-mobility active layer is beneficial to improving particle defects in the AA region, but not beneficial to display defects in the GOA region. Using TFTs with a high-mobility active layer is beneficial to improving display defects in the GOA region, but not beneficial to particle defects in the AA region.

[0054] An embodiment of the present invention provides an array substrate, which includes a display region and a non-display region located on at least one side of the display region; the array substrate includes a substrate and at least one first transistor and at least one second transistor located on the substrate, and the first transistor is located in the display region, and the second transistor is located in the non-display region; the first transistor includes a first active layer, and the first active layer has a first mobility; the second transistor includes a second active layer, and the second active layer has a second mobility; wherein, the second mobility is greater than the first mobility.

[0055] In the embodiment of the present invention, by differentiating the design of the first active layer and the second active layer and defining that the second mobility is greater than the first mobility, the problems of particle phenomena in the display region and display defects in the non-display region can be solved.

[0056] Figure 1 It is a front view schematic diagram of the array substrate according to an embodiment of the present invention. As Figure 1As shown, the array substrate may include a display area AA and a non-display area BB located on at least one side of the display area AA. The non-display area BB may include a first non-display area B1 located on one side of the display area AA and a second non-display area B2 located on the remaining sides of the display area AA. For example, the first non-display area B1 may include the lower border of the array substrate, and the second non-display area B2 may include the upper border, left border, and right border of the array substrate.

[0057] In an exemplary embodiment, as Figure 1 shown, the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be arranged in sequence along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be arranged in sequence along the first direction X. Among them, the first direction X and the second direction Y may intersect. For example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers. For example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate.

[0058] In an exemplary embodiment, as Figure 1 shown, the plurality of data lines DL and the plurality of gate lines GL may intersect to form a plurality of sub-pixel regions. The region defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel region. One sub-pixel may be correspondingly disposed within the sub-pixel region. The sub-pixel region may include an opening region and a non-opening region surrounding the opening region. The non-opening region may be a region blocked by the black matrix of the counter substrate of the array substrate, and the opening region may be a region not blocked by the black matrix of the counter substrate. The adjacent gate lines GL and data lines DL may both be located within the non-opening region. The array substrate of the embodiment of the present invention may be used to implement a display function, and the opening region of each sub-pixel region may be configured for display. The non-opening region surrounds the opening region and does not perform display. However, the embodiment of the present invention is not limited thereto. In some examples, the array substrate may be used to implement other functions.

[0059] In an exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (for example, a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along the first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged in sequence in the order of the blue sub-pixel, the red sub-pixel, and the green sub-pixel. As Figure 1 shown, at least one sub-pixel may include: a pixel electrode 10 and a common electrode ( Figure 1not shown), and the positive projection of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may overlap. The common electrodes of the multiple sub-pixels in the display area AA may be an integrated structure. Exemplarily, the common electrode may be located on the side of the pixel electrode 10 away from the substrate. The sub-pixel may further include a first transistor 11. The first transistor 11 may be adjacent to the intersection of the data line DL and the gate line GL. The first transistor 11 may include a first gate, a first pole, and a second pole. The first gate may be electrically connected to the gate line GL, the first pole of the first transistor 11 may be electrically connected to the data line DL, and the second pole may be electrically connected to the pixel electrode 10 of a sub-pixel. The first transistor 11 may be configured to provide the data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0060] In an exemplary embodiment, the second non-display area B2 may at least include a gate driving circuit (for example, including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to multiple gate lines GL in the display area AA. The gate driving circuit may further include a second transistor. The second transistor may include a second gate, a first pole, and a second pole. In the present invention, the first pole may be a drain electrode, the second pole may be a source electrode, or the first pole may be a source electrode, and the second pole may be a drain electrode.

[0061] The liquid crystal display device has various display modes, such as ADS (Advanced Super Dimension Switch, in-plane switching) mode, TN (Twisted Nematic) mode, and VA (Vertical Alignment) mode, etc. In the ADS mode, both the pixel electrode and the common electrode are located on one side of the array substrate. In the TN mode and the VA mode, the pixel electrode and the common electrode are respectively disposed on opposite sides of the liquid crystal layer, the pixel electrode is located on one side of the array substrate, and the common electrode is located on one side of the counter substrate.

[0062] Figure 2 It is a partial plan view of the display area of the array substrate according to an embodiment of the present invention. Figure 2A is Figure 2 the enlarged cross-sectional view at the marked A-A in Figure 2 、 Figure 2AAs shown, the array substrate may include a substrate 20, and a first conductive layer 21, a first insulating layer 31, a semiconductor layer 30, a second conductive layer 22, a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34 that are sequentially stacked on the substrate 20. In an embodiment of the present invention, the first insulating layer may also be referred to as a gate insulating (GI) layer, the second insulating layer may also be referred to as a first passivation (PVX1) layer, the third insulating layer may also be referred to as a planarization (PLN) layer, and the fourth insulating layer may also be referred to as a second passivation (PVX2) layer.

[0063] In the display area, the first conductive layer 21 may include a first gate 11-3 of the first transistor 11. For example, the orthographic projection of the first gate 11-3 on the plane where the substrate 20 is located may be a square. The semiconductor layer 30 may include a first active layer 11-4 of the first transistor 11. For example, the orthographic projection of the first active layer 11-4 on the plane where the substrate 20 is located may be a rectangle. The second conductive layer 22 may include a first pole 11-1 and a second pole 11-2 of the first transistor. For example, the orthographic projections of the first pole 11-1 and the second pole 11-2 of the first transistor on the plane where the substrate 20 is located may both be rectangles.

[0064] In some exemplary embodiments, the first active layer 11-4 has a first dimension L1. The first dimension L1 refers to the minimum dimension between the first pole 11-1 and the second pole 11-2 of the first transistor along the extension direction of the first active layer 11-4. The first dimension L1 is also the dimension of the channel region of the first active layer 11-4.

[0065] In some exemplary embodiments, the first active layer 11-4 may be a single-layer structure or a composite-layer structure. For example, the first active layer 11-4 is a single-layer structure. The first active layer 11-4 has a first mobility. In the design where the first active layer 11-4 is a composite-layer structure, each layer constituting the composite-layer structure has a mobility, and the first mobility is the maximum mobility among the multiple mobilities.

[0066] In some exemplary embodiments, the thickness range of the first active layer 11-4 may be between 800 angstroms and 1000 angstroms.

[0067] Figure 3 It is a partial plan view of the second non-display area of the array substrate according to an embodiment of the present invention. Figure 3A is Figure 3 the enlarged cross-sectional view at the position marked B-B in Figure 3 、 Figure 3AAs shown, the array substrate may include a substrate 20, and a first conductive layer 21, a first insulating layer 31, a semiconductor layer 30, a second conductive layer 22, a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34 that are sequentially stacked on the substrate 20. In the second non-display area, the first conductive layer 21 may include a second gate 12-3 of the second transistor 12. For example, the orthographic projection of the second gate 12-3 on the plane where the substrate 20 is located may be a square. The semiconductor layer 30 may include a second active layer 12-4 of the second transistor 12. For example, the orthographic projection of the second active layer 12-4 on the plane where the substrate 20 is located may be a rectangle. The second conductive layer 22 may include a first pole 12-1 of the second transistor and a second pole 12-2 of the second transistor. For example, the orthographic projections of the first pole 12-1 of the second transistor and the second pole 12-2 of the second transistor on the plane where the substrate 20 is located may both be rectangles.

[0068] In some exemplary embodiments, in the second non-display area, the second conductive layer 22 may further include a first connection portion 12-5, and the first poles 12-1 of multiple second transistors may all be connected to the first connection portion 12-5. For example, the first poles 12-1 of multiple second transistors and the first connection portion 12-5 may be an integrally connected structure.

[0069] In some exemplary embodiments, in the second non-display area, the second conductive layer 22 may further include a second connection portion 12-6, and the second poles 12-2 of multiple second transistors may all be connected to the second connection portion 12-6. For example, the second poles 12-2 of multiple second transistors and the second connection portion 12-6 may be an integrally connected structure.

[0070] In some exemplary embodiments, the second active layer 12-4 has a second dimension L2, and the second dimension L2 refers to the maximum dimension between the first pole 12-1 of the second transistor and the second pole 12-2 of the second transistor along the extension direction of the second active layer 12-4. The second dimension L2 is also the dimension of the channel region of the second active layer 12-4.

[0071] In some exemplary embodiments, the first dimension and the second dimension may be equal. For example, it may be in the range of 4.0 micrometers to 6.0 micrometers, such as 5.0 micrometers. Alternatively, the second dimension is less than the first dimension, and the second dimension is 0.5 micrometers to 1.0 micrometers smaller than the first dimension. For example, the range of the first dimension may be in the range of 5.0 micrometers to 6.0 micrometers, and the range of the second dimension may be in the range of 4.0 micrometers to 5.0 micrometers. Reducing the dimension of the channel region of the second transistor can reduce the right drift of the characteristic curve of the second transistor and improve the display defect. Increasing the dimension of the channel region of the first transistor can reduce the left drift of the characteristic curve of the first transistor and improve the sand grain defect.

[0072] In some exemplary embodiments, the second active layer 12-4 may be a single-layer structure or a composite-layer structure. For example, the second active layer 12-4 is a composite-layer structure. The second active layer 12-4 has a second mobility. In the design where the second active layer 12-4 is a composite-layer structure, each layer constituting the composite-layer structure has a mobility, and the second mobility is the maximum mobility among the multiple mobilities.

[0073] In some exemplary embodiments, the second active layer 12-4 includes a first sub-layer 12a and a second sub-layer 12b which are stacked, and the first sub-layer 12a is closer to the substrate 20 than the second sub-layer 12b. The mobility of the first sub-layer 12a is greater than that of the second sub-layer 12b.

[0074] In some exemplary embodiments, the thickness of the second sub-layer 12b is greater than that of the first sub-layer 12a, and the thickness of the second sub-layer 12b may be 4 to 10 times the thickness of the first sub-layer 12a. For example, the thickness range of the first sub-layer 12a may be from 100 Å to 200 Å. The thickness range of the second sub-layer 12b may be from 800 Å to 1000 Å.

[0075] In some exemplary embodiments, the materials of the first sub-layer 12a and the second sub-layer 12b may both be indium gallium zinc oxide, and the indium contents in the first sub-layer 12a and the second sub-layer 12b are different.

[0076] In some exemplary embodiments, the second mobility is greater than the first mobility. For example, the second mobility may be twice the first mobility.

[0077] In some exemplary embodiments, at least part of the film layer of the first active layer 11-4 and at least part of the film layer of the second active layer 12-4 are of the same layer structure. For example, both the first active layer 11-4 and the second active layer 12-4 are two-layer composite-layer structures, and the film layer on the side of the first active layer 11-4 away from the substrate 20 and the film layer on the side of the second active layer 12-4 away from the substrate 20 may be of the same layer structure. With such a design, the preparation process of the array substrate can be simplified, and the preparation cost can be reduced.

[0078] The structure of the array substrate will be described below by way of an example of the preparation process of the array substrate. The "patterning process" in the embodiments of the present invention, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. The deposition process can be any one or more of sputtering, evaporation, and chemical vapor deposition. The coating process can be any one or more of spraying, spin coating, and inkjet printing. The etching process can be any one or more of dry etching and wet etching. The present invention does not make any limitations. A "thin film" refers to a thin film of a certain material formed on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "same-layer structure of A and B" mentioned in the present invention means that A and B are formed by the same patterning process.

[0079] The preparation process of the array substrate may include the following steps:

[0080] (01) Form a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive thin film on one side of the substrate 20, and patterning the first conductive thin film through a patterning process to form a first conductive layer pattern on one side of the substrate 20. The first conductive layer 21 may include a first gate 11-3 and a second gate 12-3. As Figure 4A shown, the first gate 11-3 is located in the display area AA, and the second gate 12-3 is located in the second non-display area B2.

[0081] In some exemplary embodiments, the material of the first conductive layer 21 may include a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Or, it may be an alloy material of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), for example, aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), molybdenum nickel titanium alloy (MoNiTi). The first conductive layer 21 may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti or Mo / Nb / Cu or MoNiTi / Cu or MoNb / Cu / MoNiTi or MoNiTi / Cu / MoNiTi, etc.

[0082] (02) Form a first semiconductor thin film. Forming the first semiconductor thin film may include: sequentially depositing a first insulating layer 31 and a first semiconductor thin film 30-1 on one side of the substrate 20 having the aforementioned pattern, asFigure 4B As shown. The orthographic projection of the first insulating layer 31 on the plane where the substrate 20 is located includes the orthographic projection of the first conductive layer 21 on the plane where the substrate 20 is located.

[0083] In an exemplary embodiment, the material of the first insulating layer 31 may include an inorganic material. Examples of inorganic materials include silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide (SiO x ), etc., one or more of them. The first insulating layer 31 may be a single-layer or composite-layer structure.

[0084] (03) Form a first photoresist layer. Forming the first photoresist layer may include: forming a first photoresist layer 35 on one side of the substrate 20 formed with the foregoing pattern, as Figure 4C shown. The orthographic projection of the first photoresist layer 35 on the plane where the substrate 20 is located includes the orthographic projection of the first semiconductor thin film 30-1 on the plane where the substrate 20 is located. Exemplarily, the material of the first photoresist layer 35 may be a positive photoresist or a negative photoresist. In the embodiment of the present invention, a positive photoresist is taken as an example.

[0085] Subsequently, ultraviolet light is used to irradiate the first photoresist layer 35 through the first mask plate 41, and the first photoresist layer 35 not covered by the first mask plate 41 is sensitized, and the sensitized part is as Figure 4C shown by the dashed box in.

[0086] (04) Form a first semiconductor layer pattern. Forming the first semiconductor layer pattern may include: removing the foregoing sensitized first photoresist layer 35 through a developer to form a required first photoresist layer pattern. Subsequently, the first semiconductor thin film 30-1 is etched by a wet etching or dry etching process so that the first semiconductor thin film 30-1 forms a first sub-layer 12a. Subsequently, the first photoresist layer pattern is peeled off, as Figure 4D shown.

[0087] (05) Form a second photoresist layer. Forming the second photoresist layer may include: sequentially forming a second semiconductor thin film 30-2 and a second photoresist layer 36 on one side of the substrate 20 formed with the foregoing pattern, as Figure 4E shown. The orthographic projection of the second photoresist layer 36 on the plane where the substrate 20 is located includes the orthographic projection of the second semiconductor thin film 30-2 on the plane where the substrate 20 is located. Exemplarily, the material of the second photoresist layer 36 may be a positive photoresist or a negative photoresist. In the embodiment of the present invention, a positive photoresist is taken as an example.

[0088] Subsequently, ultraviolet light is used to irradiate the second photoresist layer 36 through the second mask plate 42, so that the second photoresist layer 36 not covered by the second mask plate 42 is exposed to light, and the exposed part is as shown by the dashed line frame in Figure 4E as shown.

[0089] (06) Form a second semiconductor layer pattern. Forming the second semiconductor layer pattern may include: removing the aforementioned exposed second photoresist layer 36 through a developer to form a required second photoresist layer pattern. Subsequently, the second semiconductor thin film 30-2 is etched through a wet etching or dry etching process, so that the second semiconductor thin film 30-2 forms a second sub-layer 12b and a first active layer 11-4. Subsequently, the second photoresist layer pattern is stripped, as shown in Figure 4F as shown. The first sub-layer 12a and the second sub-layer 12b constitute the second active layer. The first semiconductor layer pattern and the second semiconductor layer pattern constitute the semiconductor layer pattern.

[0090] In an exemplary embodiment, the materials of the first semiconductor thin film 30-1 and the second semiconductor thin film 30-2 may include one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth doped oxide (Ln-OS). The mobility of the first semiconductor thin film 30-1 is greater than that of the second semiconductor thin film 30-2.

[0091] (07)Form a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive thin film on one side of the substrate 20 formed with the aforementioned pattern, and patterning the second conductive thin film through a patterning process to form a second conductive layer pattern on the side of the semiconductor layer pattern away from the substrate 20. The second conductive layer 22 may include the first pole 11-1 of the first transistor, the second pole 11-2 of the first transistor, the first pole 12-1 of the second transistor, and the second pole 12-2 of the second transistor, as shown in Figure 4G as shown. The first pole 11-1 and the second pole 11-2 of the first transistor are located in the display area AA, and the first pole 12-1 and the second pole 12-2 of the second transistor are located in the second non-display area B2.

[0092] (08)Form a fourth insulating layer. Forming the fourth insulating layer may include: sequentially depositing a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34 on one side of the substrate 20 formed with the aforementioned pattern, as shown in Figure 4H as shown.

[0093] In an exemplary embodiment, the materials of the second insulating layer 32 and the fourth insulating layer 34 may include inorganic materials. Examples of inorganic materials include silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide (SiO x ), or one or more of the like. The second insulating layer 32 and the fourth insulating layer 34 may be of a single-layer or composite-layer structure.

[0094] In an exemplary embodiment, the material of the third insulating layer 33 may include organic materials. Examples of organic materials include any one or several of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc. The third insulating layer 33 may be of a single-layer or composite-layer structure.

[0095] Figure 5A It is a characteristic test curve graph of a transistor in the display area of an array substrate. As Figure 5A shown, curve ① represents the characteristic test curve of the transistor in the initial state, and curve ② represents the characteristic test curve of the transistor during high-temperature and high-humidity lighting. It can be seen that during the high-temperature and high-humidity lighting process of the transistors in the display area of the existing array substrate, the characteristic curves of the transistors shift to the left.

[0096] Figure 5B It is a comparison graph of the characteristic test curves of the transistors in the display area of an array substrate. As Figure 5B shown, curve ① represents the characteristic test curve of the transistor in the initial state, and curve ② represents the characteristic test curve of the transistor during high-temperature and high-humidity lighting. It can be seen that during the high-temperature and high-humidity lighting process of the transistors in the display area of the existing array substrate, the characteristic curves of the transistors shift to the left. Curve ③ represents the characteristic test curve of the transistors in the display area during high-temperature and high-humidity lighting using the array substrate provided by the embodiment of the present invention. It can be seen that using the array substrate provided by the embodiment of the present invention can improve the left-shift problem of the transistors in the display area and can improve the sand grain problem.

[0097] Figure 6 It is a comparison graph of the characteristic test curves of the transistors in the second non-display area of an array substrate. As Figure 6As shown, curve ① represents the initial state characteristic test curve of the transistor, and curve ② represents the characteristic test curve of the transistor during the high-temperature and high-humidity lighting process. It can be seen that during the high-temperature and high-humidity lighting process of the transistor in the second non-display area of the existing array substrate, the characteristic curve of the transistor drifts to the right. Curve ③ represents the characteristic test curve of the transistor in the second non-display area of the array substrate provided by the embodiment of the present invention during the high-temperature and high-humidity lighting process. It can be seen that by using the array substrate provided by the embodiment of the present invention, the right drift problem of the transistor in the second non-display area can be improved, and the problem of poor display can be improved.

[0098] The embodiment of the present invention also provides a display device. The display device includes the array substrate described in any one of the foregoing embodiments. The display device can be: a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. The embodiment of the present invention does not limit this.

[0099] Although the disclosed embodiments of the present invention are as above, the content described is only the embodiments adopted for facilitating the understanding of the present invention and is not used to limit the present invention. Any person skilled in the art within the scope of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention. However, the patent protection scope of the present invention shall still be defined by the appended claims.

Claims

1. An array substrate, characterized in that, It includes a display area and a non-display area located on at least one side of the display area; the array substrate includes a substrate and at least one first transistor and at least one second transistor located on the substrate, the first transistor is located in the display area, and the second transistor is located in the non-display area; the first transistor includes a first active layer, and the first active layer has a first mobility; the second transistor includes a second active layer, and the second active layer has a second mobility; wherein, the second mobility is greater than the first mobility.

2. The array substrate according to claim 1, wherein The first active layer is a single-layer structure or a composite-layer structure, and the second active layer is a single-layer structure or a composite-layer structure; in the state where the first active layer is a composite-layer structure, each film layer constituting the composite-layer structure has a mobility, and the first mobility is the maximum mobility among the multiple mobilities; In the state where the second active layer is a composite-layer structure, each film layer constituting the composite-layer structure has a mobility, and the second mobility is the maximum mobility among the multiple mobilities.

3. The array substrate according to claim 2, wherein At least a part of the film layer of the first active layer and at least a part of the film layer of the second active layer are of the same-layer structure.

4. The array substrate according to claim 1, characterized in that The second active layer includes a first sub-layer and a second sub-layer arranged in a stacked manner, and the first sub-layer is closer to the substrate than the second sub-layer; the mobility of the first sub-layer is greater than that of the second sub-layer.

5. The array substrate according to claim 4, wherein The materials of the first sub-layer and the second sub-layer are both indium gallium zinc oxide, and the indium contents in the first sub-layer and the second sub-layer are different.

6. The array substrate according to claim 4, characterized in that The thickness of the second sub-layer is greater than that of the first sub-layer.

7. The array substrate according to claim 6, wherein The thickness of the second sub-layer is 4 to 10 times that of the first sub-layer.

8. The array substrate according to claim 7, wherein The thickness range of the first sub-layer is from 100 Å to 200 Å; the thickness range of the second sub-layer is from 800 Å to 1000 Å.

9. The array substrate according to any one of claims 4 to 8, wherein The mobility of the second sub-layer is the same as the first mobility.

10. The array substrate according to any one of claims 4 to 8, characterized in that, The second sub-layer and the first active layer are of the same-layer structure.

11. The array substrate according to any one of claims 1 to 8, characterized in that, The first active layer has a first dimension, which refers to the minimum dimension between the first pole and the second pole of the first transistor along the extension direction of the first active layer; the second active layer has a second dimension, which refers to the maximum dimension between the first pole and the second pole of the second transistor along the extension direction of the second active layer; wherein, the first dimension is the same as the second dimension.

12. The array substrate according to any one of claims 1 to 8, characterized in that, The first active layer has a first dimension, which refers to the minimum dimension between the first pole and the second pole of the first transistor along the extension direction of the first active layer; the second active layer has a second dimension, which refers to the maximum dimension between the first pole and the second pole of the second transistor along the extension direction of the second active layer; wherein, the second dimension is less than the first dimension.

13. The array substrate according to claim 12, wherein The second dimension is 0.5 μm to 1.0 μm smaller than the first dimension.

14. The array substrate according to claim 13, wherein The range of the first dimension is from 5.0 micrometers to 6.0 micrometers, and the range of the second dimension is from 4.0 micrometers to 5.0 micrometers.

15. A display device, characterized in that, Comprising the array substrate according to any one of claims 1 to 14.

Images