Detector, isolator and communication system

Abstract

The utility model discloses a wave detector, an isolator and a communication system, and relates to the signal processing field, the wave detector comprises a reduction module, a first time delay module, a second time delay module and a first OR gate, the reduction module receives a pair of differential signals obtained after single-end-to-differential processing is carried out on an actual input signal, and the first OR gate is connected with the first time delay module; the first input signal and the second input signal are restored for the first time, and the differential signal is converted into an approximately continuous level signal corresponding to the actual input signal, so that the recognition rate of signal change is improved, the time delay is reduced, and the recognition efficiency is improved. The falling edge delay processing is carried out on the first input signal and the second input signal through the first delay module, the second delay module and the first OR gate, so that the missing part of the signals is recovered, the actual reduction signal is obtained, the waveform distortion between the input signal and the output signal of the isolator is reduced, and the detection efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the field of signal processing, and particularly to a detector, an isolator and a communication system. Background Art

[0002] As a key component in the isolator, the detector is used to extract or recover the original information signal from the modulated signal for further processing. Different modulation methods and different application scenarios require different detection schemes. The currently commonly used detection scheme is to amplify a specific carrier signal by an operational amplifier, and then perform voltage comparison on the level after the capacitor charges and discharges to obtain the final transmitted signal. However, this detection scheme is relatively cumbersome, and the charge and discharge of the capacitor and the response of the amplifier will introduce certain delays. Especially when using multiple cascaded amplifiers, the delays will accumulate, resulting in a relatively large delay, causing a time difference between the received signal and the transmitted signal, leading to signal waveform distortion and affecting signal integrity.

[0003] Therefore, how to provide a solution to the above technical problems is an issue that those skilled in the art need to solve currently. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a detector, an isolator and a communication system, which can improve the recognition rate of signal changes, reduce the delay, reduce the waveform distortion between the input signal and the output signal of the isolator, and improve the detection efficiency.

[0005] On the one hand, the utility model provides a detector, including:

[0006] A reduction module with multiple receiving ends respectively accessing a first input signal and a second input signal, and configured to output a reference signal according to the comparison result of the difference between the first input signal and the second input signal and a preset threshold; wherein, when the difference is greater than the preset threshold, the reference signal is a high-level signal, and when the difference is less than a second threshold in the preset threshold, the reference signal is a low-level signal, and the first input signal and the second input signal are a pair of differential signals obtained by performing single-ended to differential processing on the actual input signal;

[0007] A first delay module with a first receiving end connected to the output end of the reduction module and a second receiving end accessing the first input signal, and configured to perform falling-edge delay processing on the first input signal according to the reference signal to output a first restored signal;

[0008] A second delay module with a first receiving end connected to the output end of the reduction module and a second receiving end accessing the second input signal, and configured to perform falling-edge delay processing on the second input signal according to the reference signal to output a second restored signal;

[0009] The first receiving end is connected to the output end of the first delay module, the second receiving end is connected to the output end of the second delay module, and a first OR gate for performing a logical OR operation on the first restored signal and the second restored signal to output an actual restored signal.

[0010] Optionally, the restoration module includes a first comparator, a second comparator, and a second OR gate. The multiple receiving ends of the restoration module include the non-inverting input end of the first comparator, the inverting input end of the first comparator, the non-inverting input end of the second comparator, and the inverting input end of the second comparator, where:

[0011] The non-inverting input end of the first comparator and the inverting input end of the second comparator are both connected to the first input signal, the inverting input end of the first comparator and the non-inverting input end of the second comparator are both connected to the second input signal, the output end of the first comparator is connected to the first input end of the second OR gate, the output end of the second comparator is connected to the second input end of the second OR gate, and the output end of the second OR gate serves as the output end of the restoration module;

[0012] Both the first comparator and the second comparator are configured to output a high-level signal when the difference between the first input signal and the second input signal is greater than the first threshold among the preset thresholds, and output a low-level signal when the difference between the first input signal and the second input signal is less than the second threshold of the preset threshold.

[0013] Optionally, the first delay module includes a first AND gate and a first delay unit, where:

[0014] The first input end of the first AND gate serves as the first receiving end of the first delay module, the second input end of the first AND gate serves as the second receiving end of the first delay module, and the output end of the first AND gate is used to perform a logical AND operation on the reference signal and the first input signal to obtain a first signal to be processed;

[0015] The input end of the first delay unit is connected to the first signal to be processed, and the output end of the first delay unit serves as the output end of the first delay module, for outputting a first restored signal delayed by a preset delay time.

[0016] Optionally, the first delay unit includes an even number of first inverters connected in series;

[0017] The number of the first inverters is determined according to the preset delay time.

[0018] Optionally, the second delay module includes a second AND gate and a second delay unit, where:

[0019] The first input terminal of the second AND gate serves as the first receiving terminal of the second delay module, the second input terminal of the second AND gate serves as the second receiving terminal of the second delay module, and the output terminal of the second AND gate is used to perform a logical AND operation on the reference signal and the second input signal to obtain a second signal to be processed;

[0020] The input terminal of the second delay unit receives the second signal to be processed, and the output terminal of the second delay unit serves as the output terminal of the second delay module for outputting a second restored signal delayed by a preset delay time.

[0021] Optionally, the second delay unit includes an even number of second inverters connected in series;

[0022] The number of the second inverters is determined according to the preset delay time.

[0023] On the other hand, the present invention further provides an isolator, including:

[0024] A transmitting-end isolation component for performing single-ended-to-differential processing on an actual input signal to obtain a first input signal and a second input signal;

[0025] A receiving-end isolation component includes a detector as described in any one of the above, for receiving the first input signal and the second input signal and outputting an actual restored signal.

[0026] On the other hand, the present invention further provides a communication system, including a transmitting device, a receiving device, and an isolator as described above provided between the transmitting device and the receiving device.

[0027] The utility model provides a detector, which includes a restoration module, a first delay module, a second delay module, and a first OR gate. Among them, after the restoration module receives a pair of differential signals obtained by performing single-ended to differential processing on the actual input signal, namely the first input signal and the second input signal, it outputs a reference signal according to the comparison result between the difference of the first input signal and the second input signal and a preset threshold, and performs the first restoration on the first input signal and the second input signal, converting the differential signal into a level signal approximately consistent with the actual input signal, improving the recognition rate of signal changes and reducing the delay. Since the restoration module outputs a low-level signal when the difference of the differential signals is less than the preset threshold, resulting in partial loss of the detection signal, therefore, the utility model also separately sets a first delay module, a second delay module, and a first OR gate, and restores the missing part of the signal by performing falling-edge delay processing on the first input signal and the second input signal to obtain the actual restored signal, reducing the waveform distortion between the input signal and the output signal of the isolator and improving the detection efficiency. The utility model also provides an isolator and a communication system, which have the same beneficial effects as the above-mentioned detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present utility model, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 It is a schematic structural diagram of the first detector provided by the present utility model;

[0030] Figure 2 It is a schematic structural diagram of the second detector provided by the present utility model;

[0031] Figure 3 It is a working waveform diagram of the first detector provided by the present utility model;

[0032] Figure 4 It is a schematic structural diagram of the third detector provided by the present utility model;

[0033] Figure 5 It is a schematic structural diagram of the fourth detector provided by the present utility model;

[0034] Figure 6 It is a working waveform diagram of the first detector provided by the present utility model;

[0035] Figure 7 It is a schematic structural diagram of an isolator provided by the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The core of the present utility model is to provide a detector, an isolator and a communication system, which can improve the recognition rate of signal changes, reduce the delay, reduce the waveform distortion between the input signal and the output signal of the isolator, and improve the detection efficiency.

[0037] To make the objectives, technical solutions and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0038] In a first aspect, please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a detector provided by the present utility model. The detector includes:

[0039] A reduction module 1 with multiple receiving ends respectively connected to a first input signal and a second input signal, and used for outputting a reference signal according to the comparison result between the difference of the first input signal and the second input signal and a preset threshold; wherein, when the difference is greater than a first threshold in the preset threshold, the reference signal is a high-level signal, and when the difference is less than a second threshold in the preset threshold, the reference signal is a low-level signal. The first input signal and the second input signal are a pair of differential signals obtained after single-ended to differential processing of an actual input signal;

[0040] A first delay module 2 with a first receiving end connected to the output end of the reduction module 1 and a second receiving end connected to the first input signal, and used for performing falling-edge delay processing on the first input signal according to the reference signal to output a first reduced signal;

[0041] A second delay module 3 with a first receiving end connected to the output end of the reduction module 1 and a second receiving end connected to the second input signal, and used for performing falling-edge delay processing on the second input signal according to the reference signal to output a second reduced signal;

[0042] A first OR gate OR1 with a first receiving end connected to the output end of the first delay module 2 and a second receiving end connected to the output end of the second delay module 3, and used for performing logical OR operation on the first reduced signal and the second reduced signal to output an actual reduced signal.

[0043] In this embodiment, the detector is disposed in the receiving end of the isolator. The transmitting end of the isolator is used to receive the actual input signal. To enhance the anti-interference ability of signal transmission, the actual input signal received at the transmitting end of the isolator is converted into a pair of differential signals. At the receiving end of the isolator, the detector is required to restore the differential signals back to the original input signal (i.e., the actual input signal) for subsequent processing.

[0044] The detector includes a restoration module 1. The restoration module 1 is used to convert a pair of differential signals into a reference signal, which is an approximately continuous level signal corresponding to the actual input signal. Assuming the actual input signal is a continuous high-level signal, the reference signal generated after being processed by the restoration module 1 is an approximately continuous high-level signal. Correspondingly, assuming the actual input signal is a continuous low-level signal, the reference signal generated after being processed by the restoration module 1 is an approximately continuous low-level signal. Specifically, the restoration module 1 is provided with multiple receiving ends, and the multiple receiving ends respectively receive the first input signal and the second input signal transmitted from the transmitting end of the isolator. The restoration module 1 is used to obtain the difference between the first input signal and the second input signal. Assuming the first input signal is signal A and the second input signal is signal B, and calculate the difference between A and B, and compare the difference with a preset threshold. The preset threshold in this embodiment includes a first threshold and a second threshold, and the first threshold is greater than the second threshold. If the difference between the two is greater than the first threshold, then the restoration module 1 outputs a high level. If the difference between the two is less than the second threshold, then the restoration module 1 outputs a low level. After such processing, a pair of differential signals can be converted into an approximately continuous high-level signal or low-level signal. Among them, the first restoration module 1 is built in the form of selecting elements, circuits, chips or combinations thereof with the above functions.

[0045] Since the restoration module 1 outputs a low-level signal when the difference between the first input signal and the second input signal is less than the preset threshold, therefore, the frequencies other than the carrier frequency are filtered out in the approximately continuous high-level signal or low-level signal generated by the restoration module 1, which may cause partial loss of the actual input signal. For this reason, a first delay module 2 and a second delay module 3 are also provided in this embodiment.

[0046] The first delay module 2 identifies the falling edge of the first input signal through a reference signal, and then delays the falling edge of the first input signal to obtain a first restored signal. Similarly, the second delay module 3 identifies the falling edge of the second input signal through a reference signal, and then delays the falling edge of the second input signal to obtain a second restored signal to ensure the consistency of the actually restored signal after restoration. Then, the first restored signal and the second restored signal are input into the first OR gate OR1. After performing a logical OR operation on the first restored signal and the second restored signal, the first OR gate OR1 outputs an actually restored signal that is basically consistent with the actual input signal, completing the detection of the signal. The first delay time aims to make the waveform distortion of the input signal and the output signal approximate or close to 0, and then the connection and quantity of the corresponding delay elements can be adjusted according to actual engineering needs. This is not specifically limited in this embodiment, and the same applies to the second delay module 3.

[0047] Among them, both the first delay module 2 and the second delay module 3 can be built in the form of selecting elements, circuits, chips or combinations thereof with the above functions.

[0048] In an exemplary implementation, the preset threshold is determined according to the amplitude of the actual input signal.

[0049] It can be seen that in this embodiment, it includes a restoration module 1, a first delay module 2, a second delay module 3, and a first OR gate OR1. Among them, after the restoration module 1 receives a pair of differential signals obtained by performing single-ended to differential processing on the actual input signal, that is, the first input signal and the second input signal, it outputs a reference signal according to the comparison result between the difference between the first input signal and the second input signal and the preset threshold, and performs the first restoration on the first input signal and the second input signal, converting the differential signal into a level signal corresponding to the actual input signal and approximately continuous, improving the recognition rate of signal changes and reducing the delay. Since the restoration module 1 outputs a low-level signal when the difference between the differential signals is less than the preset threshold, resulting in partial loss of the detection signal, therefore, the present invention also separately sets a first delay module 2, a second delay module 3, and a first OR gate OR1. By performing a falling-edge delay process on the first input signal and the second input signal, the missing part of the signal is restored to obtain an actually restored signal, reducing the waveform distortion between the input signal and the output signal of the isolator and improving the detection efficiency.

[0050] Based on the above embodiment:

[0051] In an exemplary implementation, referring to Figure 2 , the restoration module 1 includes a first comparator U1, a second comparator U2, and a second OR gate OR2. The multiple receiving ends of the restoration module 1 include the non-inverting input terminal of the first comparator U1, the inverting input terminal of the first comparator U1, the non-inverting input terminal of the second comparator U2, and the inverting input terminal of the second comparator U2, where:

[0052] The non-inverting input terminal of the first comparator U1 and the inverting input terminal of the second comparator U2 are both connected to the first input signal. The inverting input terminal of the first comparator U1 and the non-inverting input terminal of the second comparator U2 are both connected to the second input signal. The output terminal of the first comparator U1 is connected to the first input terminal of the second OR gate OR2, and the output terminal of the second comparator U2 is connected to the second input terminal of the second OR gate OR2. The output terminal of the second OR gate OR2 serves as the output terminal of the restoration module 1;

[0053] Both the first comparator U1 and the second comparator U2 are configured to output a high-level signal when the difference between the first input signal and the second input signal is greater than the first threshold among the preset thresholds, and output a low-level signal when the difference between the first input signal and the second input signal is less than the second threshold of the preset threshold.

[0054] In this embodiment, the restoration module 1 is mainly built by the first comparator U1, the second comparator U2, and the second OR gate OR2. Among them, the first input signal is respectively connected to the non-inverting input terminal of the first comparator U1 and the inverting input terminal of the second comparator U2, and the second input signal is respectively connected to the inverting input terminal of the first comparator U1 and the non-inverting input terminal of the second comparator U2. The output terminals of the two comparators are correspondingly connected to the two input terminals of the second OR gate OR2. Taking the actual input signal as a continuous high-level signal as an example, after performing a single-ended to differential operation on the actual input signal, the first input signal and the second input signal are obtained. The amplitudes of the first input signal and the second input signal are the same, and the phases differ by 180°.

[0055] Both the first comparator U1 and the second comparator U2 in this embodiment can be selected as hysteresis comparators. In a hysteresis comparator, there are two hysteresis thresholds, namely the rising threshold and the falling threshold. The working principles of the first comparator U1 and the second comparator U2 are as follows: when the level of the non-inverting input terminal of the comparator is higher than the level of its inverting input terminal, and the difference between the two exceeds the rising threshold, the output of the comparator will change from low level to high level; when the level of the non-inverting input terminal is lower than the level of the inverting input terminal, and the difference between the two exceeds the falling threshold, the output of the comparator will change from high level to low level. In this embodiment, the first threshold is the rising threshold of the comparator, and the second threshold is the falling threshold of the comparator. By reasonably configuring the hysteresis thresholds, the part of the first input signal below the carrier frequency is filtered out. The working principle of the second comparator U2 is the same.

[0056] It can be understood that if the current output of the comparator is high, then the output of the comparator will change from high to low only when the level at the inverting input terminal is higher than the level at the non-inverting input terminal and the difference between the two exceeds the falling threshold. If the current output of the comparator is low, then the output of the comparator will change from low to high only when the level at the non-inverting input terminal is higher than the level at the inverting input terminal and the difference between the two exceeds the rising threshold.

[0057] Exemplarily, referring to Figure 3 As shown, it is assumed that within the time period T1 - T2, the difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the first comparator U1 is greater than the first threshold. At this time, a high-level signal is output at the output terminal of the first comparator U1. The difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the second comparator U2 is less than the second threshold. At this time, a low-level signal is output at the output terminal of the first comparator U1. Correspondingly, the reference signal output by the second OR gate OR2 is a high-level signal. Within the time period T2 - T3, due to the decrease in the level of the first input signal, when the difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the first comparator U1 is less than the second threshold, at this time, a low-level signal is output at the output terminal of the first comparator U1. At the same time, the difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the second comparator U2 is not greater than the first threshold. Therefore, the level at the output terminal of the second comparator U2 will not flip. At this time, the output terminal of the second comparator U2 remains low. At this time, the reference signal output by the second OR gate OR2 is a low-level signal. Within the time period T3 - T4, the difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the second comparator U2 is greater than the first threshold. At this time, a high-level signal is output at the output terminal of the second comparator U2. The difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the first comparator U1 is less than the second threshold. At this time, the output at the output terminal of the first comparator U1 changes from a high-level signal to a low-level signal. At this time, the reference signal output by the second OR gate OR2 is a high-level signal. Within the time period T4 - T5, the level of the second input signal decreases. When the difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the second comparator U2 is less than the second threshold, a low-level signal is output at the output terminal of the second comparator U2. At this time, since the difference between the level at the non-inverting input terminal and the level at the inverting input terminal of the first comparator U1 is not less than the second threshold, the first comparator U1 still outputs a low-level signal. At this time, the reference signal output by the second OR gate OR2 is a low-level signal. For other time periods, it is the same reason.

[0058] This embodiment combines the hysteresis characteristic of the comparator and a relatively fast switching speed, ensuring the stability of the signal output by the comparator and enabling it to quickly respond to changes in the input signal. Specifically, due to the existence of hysteresis, only when the input signals at both ends exceed the set threshold and there is a certain amplitude difference, will the output of the comparator change its state. This reduces false triggering caused by noise or small fluctuations in the signal. The fast reverse rate means that the comparator can follow the edge changes of the input signal faster, providing a clearer and more accurate signal edge, which provides a basis for improving the detection efficiency. As an alternative embodiment, when setting the hysteresis threshold, the rising threshold can be set according to 10% - 30% of the amplitude of the input signal, and the falling threshold can be set according to 50% - 70% of the amplitude of the input signal. Assuming the oscillation period Tosc of the internal crystal oscillator, the hysteresis range is at least greater than 5 Tosc. The smaller the set time, the less the final delay.

[0059] In an exemplary implementation, referring to Figure 4 , the first delay module 2 includes a first AND gate AND1 and a first delay unit 21, where:

[0060] The first input terminal of the first AND gate AND1 serves as the first receiving terminal of the first delay module 2, the second input terminal of the first AND gate AND1 serves as the second receiving terminal of the first delay module 2, and the output terminal of the first AND gate AND1 is used to perform a logical AND operation on the reference signal and the first input signal to obtain a first signal to be processed;

[0061] The input terminal of the first delay unit 21 is connected to the first signal to be processed, and the output terminal of the first delay unit 21 serves as the output terminal of the first delay module 2, for outputting a first restored signal delayed by a preset delay time.

[0062] In this embodiment, the first delay module 2 includes a first AND gate AND1 and a first delay unit 21. The first AND gate AND1 performs a logical AND operation on the first input signal and the reference signal. Since the reference signal is an approximately continuous high-level signal / low-level signal corresponding to the actual level signal, therefore, by performing a logical AND operation on the reference signal and the first input signal, the interference of noise signals can be avoided, and the reliability of the signal can be improved. At the same time, when the reference signal is a low-level signal, it is used to indicate the falling edge of the first input signal and the second input signal. Therefore, when a logical AND operation is performed on the first input signal and the reference signal, a delay can be performed on the falling edge of the first input signal. After performing a logical AND operation on the reference signal and the first input signal, a first signal to be processed is obtained. The input end of the first delay unit 21 is connected to the output end of the first AND gate AND1, and the output end of the first delay unit 21 is connected to the first input end of the first OR gate OR1. After the first delay unit 21 receives the first signal to be processed, it will output a delayed first restored signal to ensure the shape and characteristics of the signal and avoid signal distortion.

[0063] The first delay unit 21 in this embodiment can be a delay unit with adjustable delay time.

[0064] In an exemplary embodiment, the second delay module 3 includes a second AND gate AND2 and a second delay unit 31, where:

[0065] The first input end of the second AND gate AND2 serves as the first receiving end of the second delay module 3, the second input end of the second AND gate AND2 serves as the second receiving end of the second delay module 3, and the output end of the second AND gate AND2 is used to perform a logical AND operation on the reference signal and the second input signal to obtain a second signal to be processed;

[0066] The input end of the second delay unit 31 receives the second signal to be processed, and the output end of the second delay unit 31 serves as the output end of the second delay module 3 to output a second restored signal delayed by a preset delay time.

[0067] In this embodiment, the second delay module 3 includes a second AND gate AND2 and a second delay unit 31. The second AND gate AND2 performs a logical AND operation on the second input signal and the reference signal. Since the reference signal is an approximately continuous high-level signal / low-level signal corresponding to the actual level signal, therefore, by performing a logical AND operation on the reference signal and the second input signal, the interference of noise signals can be avoided, and the reliability of the signal can be improved. At the same time, when the reference signal is a low-level signal, it is used to indicate the falling edge of the first input signal and the second input signal. Therefore, when the second input signal and the reference signal perform a logical AND operation, the falling edge of the second input signal can be delayed. After performing a logical AND operation on the reference signal and the second input signal, a second signal to be processed is obtained. The input end of the second delay unit 31 is connected to the output end of the second AND gate AND2, and the output end of the second delay unit 31 is connected to the second input end of the first OR gate OR1. After the second delay unit 31 receives the second signal to be processed, it will output a delayed second restored signal to ensure the shape and characteristics of the signal and avoid signal distortion.

[0068] The second delay unit 31 in this embodiment can be a delay unit with adjustable delay time.

[0069] In an exemplary embodiment, referring to Figure 5 as shown, the first delay unit 21 includes an even number of first inverters I1 connected in series;

[0070] The number of the first inverters I1 is determined according to the preset delay time.

[0071] In an exemplary embodiment, the second delay unit 31 includes an even number of second inverters I2 connected in series;

[0072] The number of the second inverters I2 is determined according to the preset delay time.

[0073] In this embodiment, the number of the first inverters I1 in the first delay unit 21 is the same as that of the second inverters I2 in the second delay unit 31. Different numbers of inverters can provide different delay times. Connecting an even number of inverters in series can provide symmetric rising-edge and falling-edge delays. After connecting an even number of inverters in series, it is possible to generate a delay without changing the original signal. Moreover, in the differential signal path of this embodiment, an even number of inverters can ensure the phase consistency of the two signal paths, and at the same time can help improve signal integrity and reduce reflection and crosstalk of the signal during transmission.

[0074] As an optional embodiment, each inverter can be selectively connected to the delay circuit. Specifically, a plurality of switches are connected in parallel with a plurality of inverters one by one, and the on or off of the switches is controlled according to the required delay time, so as to realize whether the inverter is connected to the delay circuit and improve the detection flexibility.

[0075] As shown in reference to Figure 6 shown below Figure 6 is the waveform diagram of each signal adopting the Figure 5 scheme shown below

[0076] In summary, the utility model can minimize the delay that appears in the transmission channel. At the same time, by reasonably designing the threshold of the comparator and the delay time of the delay module, the pulse width distortion time can be maintained within 0.1 ns. Utilizing the characteristic of the relatively fast reverse rate of the comparator, the driving delay time of the rising edge and the falling edge can be shortened to within 1 ns, providing the possibility for higher-frequency system applications in the later stage. Instead of using a multi-stage operational amplifier and the method of charging a capacitor for detection, the characteristic of the comparator is utilized to detect high-frequency signals, achieving the effect of quickly and accurately translating the primary-side transmission signal.

[0077] In a second aspect, please refer to Figure 7 , Figure 7 which is a schematic structural diagram of an isolator provided by the utility model. The isolator includes:

[0078] A transmitting-end isolation component, which is used to perform single-ended to differential processing on the actual input signal to obtain a first input signal and a second input signal;

[0079] A receiving-end isolation component, including a detector described in any one of the above embodiments, which is used to receive the first input signal and the second input signal and output an actual restored signal.

[0080] For the introduction of an isolator provided by the utility model, please refer to the above embodiments, and the utility model will not be elaborated herein.

[0081] An isolator provided by the utility model has the same beneficial effects as the above detector.

[0082] In a third aspect, the utility model provides a communication system, which includes a transmitting device, a receiving device, and an isolator as described above provided between the transmitting device and the receiving device.

[0083] This communication system can be a BMS (Battery Management System) system, a traction system, a DC-DC system, an OBC (On-Board Charger) system, a motor control system, etc.

[0084] For the introduction of a communication system provided by the utility model, please refer to the above embodiments, and the utility model will not be elaborated herein.

[0085] A communication system provided by the utility model has the same beneficial effects as the above-described detector.

[0086] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0087] The above description of the disclosed embodiments enables those skilled in the art to implement or use the utility model. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the utility model. Therefore, the utility model will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A geophone, characterized in that, Including: A restoration module with multiple receivers respectively accessing a first input signal and a second input signal, and being used to output a reference signal according to a comparison result between a difference value of the first input signal and the second input signal and a preset threshold value; wherein, when the difference value is greater than a first threshold value among the preset threshold values, the reference signal is a high-level signal, and when the difference value is less than a second threshold value among the preset threshold values, the reference signal is a low-level signal, the first input signal and the second input signal are a pair of differential signals obtained by performing single-ended to differential processing on an actual input signal, and the first threshold value is greater than the second threshold value; A first delay module with a first receiver connected to an output end of the restoration module and a second receiver accessing the first input signal, and being used to perform falling-edge delay processing on the first input signal according to the reference signal to output a first restored signal; A second delay module with a first receiver connected to an output end of the restoration module and a second receiver accessing the second input signal, and being used to perform falling-edge delay processing on the second input signal according to the reference signal to output a second restored signal; A first OR gate with a first receiver connected to an output end of the first delay module and a second receiver connected to an output end of the second delay module, and being used to perform logical OR operation on the first restored signal and the second restored signal to output an actual restored signal; 2. The geophone according to claim 1, characterized in that, The restoration module includes a first comparator, a second comparator and a second OR gate, and multiple receivers of the restoration module include a non-inverting input end of the first comparator, an inverting input end of the first comparator, a non-inverting input end of the second comparator and an inverting input end of the second comparator, wherein: The non-inverting input end of the first comparator and the inverting input end of the second comparator are both connected to the first input signal, the inverting input end of the first comparator and the non-inverting input end of the second comparator are both connected to the second input signal, an output end of the first comparator is connected to a first input end of the second OR gate, an output end of the second comparator is connected to a second input end of the second OR gate, and an output end of the second OR gate serves as an output end of the restoration module; Both the first comparator and the second comparator are used to output a high-level signal when a difference value between the first input signal and the second input signal is greater than the first threshold value among the preset threshold values, and output a low-level signal when the difference value between the first input signal and the second input signal is less than the second threshold value of the preset threshold value.

3. The geophone according to claim 1, wherein The first delay module includes a first AND gate and a first delay unit, wherein: A first input end of the first AND gate serves as a first receiver of the first delay module, a second input end of the first AND gate serves as a second receiver of the first delay module, and an output end of the first AND gate is used to perform logical AND operation on the reference signal and the first input signal to obtain a first signal to be processed; The input end of the first delay unit is connected to the first signal to be processed, and the output end of the first delay unit serves as the output end of the first delay module for outputting a first restored signal delayed by a preset delay time.

4. The geophone according to claim 3, characterized in that, The first delay unit includes an even number of first inverters connected in series; The number of the first inverters is determined according to the preset delay time.

5. The geophone according to claim 1, wherein, The second delay module includes a second AND gate and a second delay unit, where: The first input end of the second AND gate serves as the first receiving end of the second delay module, the second input end of the second AND gate serves as the second receiving end of the second delay module, and the output end of the second AND gate is used to perform a logical AND operation on the reference signal and the second input signal to obtain a second signal to be processed; The input end of the second delay unit is connected to the second signal to be processed, and the output end of the second delay unit serves as the output end of the second delay module for outputting a second restored signal delayed by a preset delay time.

6. The geophone according to claim 5, wherein The second delay unit includes an even number of second inverters connected in series; The number of the second inverters is determined according to the preset delay time.

7. An isolator, characterized in that, Comprising: A transmitting end isolation component for performing single-ended to differential processing on an actual input signal to obtain a first input signal and a second input signal; A receiving end isolation component, including the detector according to any one of claims 1-6, for receiving the first input signal and the second input signal and outputting an actual restored signal.

8. A communication system, characterized in that, Comprising a transmitting device, a receiving device, and the isolator according to claim 7 provided between the transmitting device and the receiving device.

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