Display substrate

Abstract

The utility model discloses a display substrate, which is provided with a plurality of sub-pixels arranged in multiple rows and multiple columns, and comprises a substrate, a plurality of data lines and a plurality of first data line leads, the substrate comprises a display area and a non-display area, the sub-pixels are arranged in the display area, and the data lines are arranged on the substrate, at least located in the display area, extend in the first direction and are configured to provide data signals for the sub-pixels. The multiple first data line leads are arranged on the substrate and extend from the display area to the non-display area in the first direction, and at least parts of the multiple data lines are electrically connected with the multiple first data line leads respectively so as to obtain data signals from the non-display area; at least one of the first data line leads comprises a first lead part and a second lead part, the first lead part is located on the first conductive layer, the second lead part is located on the second conductive layer, and the first lead part and the second lead part are electrically connected through a via hole.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate. Background Art

[0002] Organic Light Emitting Diode (OLED) display devices have a series of advantages such as self-luminescence, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. They have become one of the key development directions of the new generation of display devices and have thus received increasing attention. Summary of the Utility Model

[0003] At least one embodiment of the present disclosure provides a display substrate having a plurality of sub-pixels arranged in multiple rows and columns, and including a substrate, a plurality of data lines, and a plurality of first data line leads; the substrate includes a display area and a non-display area, wherein the plurality of sub-pixels are disposed in the display area, the plurality of data lines are disposed on the substrate and at least located in the display area, extending along a first direction, configured to provide data signals to the plurality of sub-pixels, the plurality of first data line leads are disposed on the substrate and extend from the display area to the non-display area along the first direction, wherein at least a part of the plurality of data lines are respectively electrically connected to the plurality of first data line leads to obtain data signals from the non-display area, at least one of the plurality of first data line leads includes a first lead portion and a second lead portion, the first lead portion is located in a first conductive layer, the second lead portion is located in a second conductive layer, and the first lead portion and the second lead portion are electrically connected through a via.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, one or two first data line leads are provided between two adjacent data lines in a direction parallel to the substrate.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer is located on a side of the first conductive layer away from the substrate, and the plurality of data lines are located in the second conductive layer.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, a first insulating layer is provided between the second conductive layer and the first conductive layer, the via includes a first via and a second via penetrating through the first insulating layer, and two ends of the first lead portion are respectively connected to the second lead portion through the first via and the second via.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, for an adjacent first data line lead and a data line, a third via hole overlapping with the data line in a direction perpendicular to the substrate is further provided in the first insulating layer, and in the first direction, the third via hole is located between the first via hole and the second via hole.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two data lines are located between the two first data line leads, or the two first data line leads are located between the two data lines.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the two data lines are symmetrically arranged, and the third via holes corresponding to the two data lines are symmetrically arranged; the two first data line leads are symmetrically arranged, and the first via holes and the second via holes corresponding to the two first data line leads are symmetrically arranged.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines; in the first direction, the first via holes and the second via holes corresponding to the two first data line leads are arranged alternately at intervals.

[0011] For example, the display substrate provided by at least one embodiment of the present disclosure further includes: a second data line lead, located in the first conductive layer and extending along a second direction different from the first direction, wherein at least one of the two first data line leads is connected to the second data line lead through a first jumper wire, the first jumper wire is located in the first conductive layer, and at least partially overlaps with the at least one first data line lead in a direction perpendicular to the substrate.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second lead portions of the two first data line leads respectively include bent portions bent in a direction approaching each other.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines; in the first direction, the first via holes and the second via holes corresponding to the two first data line leads are located on the same straight line.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the substrate, two data lines are provided between two adjacent columns of sub-pixels, and a first data line lead is provided between the two data lines. The display substrate further includes: a second data line lead located in the first conductive layer and extending in a second direction different from the first direction. The first data line lead is connected to the second data line lead through a second jumper wire located in the first conductive layer. In a direction perpendicular to the substrate, the second jumper wire at least partially overlaps with one of the two data lines.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the substrate, two data lines are provided between two adjacent columns of sub-pixels, and two first data line leads are provided between the two data lines; or two first data line leads are provided between two adjacent columns of sub-pixels, and two data lines are provided between the two first data line leads. The display substrate further includes: a plurality of second data line leads located in the first conductive layer and extending in a second direction different from the first direction. The first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads, and the first second data line lead is connected to the first first data line lead spaced from the first data line by at least one sub-pixel; the second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads, and the second second data line lead is connected to the second first data line lead spaced from the second data line by at least one sub-pixel.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third jumper wire. In a direction perpendicular to the substrate, the first data line at least partially overlaps with the third jumper wire; the second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads through a fourth jumper wire. In a direction perpendicular to the substrate, the second data line at least partially overlaps with the fourth jumper wire.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third jumper wire. In a direction perpendicular to the substrate, the third jumper wire and the first data line lead adjacent to the first data line at least partially overlap; the second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads through a fourth jumper wire. In a direction perpendicular to the substrate, the fourth jumper wire and the first data line lead adjacent to the second data line at least partially overlap.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first second data line lead is connected to the first first data line lead that is at least one sub-pixel away from the first data line through a fifth jumper wire. In a direction perpendicular to the substrate, the fifth jumper wire and the data line adjacent to the first first data line lead at least partially overlap; the second second data line lead is connected to the second first data line lead that is at least one sub-pixel away from the second data line through a sixth jumper wire. In a direction perpendicular to the substrate, the sixth jumper wire and the data line adjacent to the second first data line lead at least partially overlap.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first second data line lead is directly connected to the first first data line lead that is at least one sub-pixel away from the first data line through a fourth via hole; the second second data line lead is directly connected to the second first data line lead that is at least one sub-pixel away from the second data line through a fifth via hole.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first data line, the first second data line lead, and the first first data line lead form a first data line network, the second data line, the second second data line lead, and the second first data line lead form a second data line network, and the second data line network is located outside the first data line network.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the two first data line leads located between the two data lines include a disconnected portion that is disconnected from the first data line network and the second data line network, and the display substrate further includes a first power line, and the disconnected portion is connected to the first power line.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction perpendicular to the substrate, the disconnected position overlaps with the first conductive layer or the second conductive layer.

[0023] For example, in the display substrate provided by at least one embodiment of the present disclosure, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device. The light-emitting device includes a first electrode connected to the pixel driving circuit, a second electrode spaced apart from the first electrode, and a light-emitting layer between the first electrode and the second electrode. The second electrode is electrically connected to the first power line.

[0024] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel driving circuit includes a transistor. The transistor includes a gate and a source-drain electrode. The source-drain electrode is electrically connected to the first electrode through a connection electrode. The source-drain electrode is located in the first conductive layer, and the connection electrode is located in the second conductive layer.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the substrate, two data lines are provided between adjacent first-column sub-pixels and second-column sub-pixels. A reset voltage line is provided between the two data lines. Two first data line leads are provided between adjacent second-column sub-pixels and third-column sub-pixels.

[0026] For example, in the display substrate provided by at least one embodiment of the present disclosure, the data line adjacent to the second-column sub-pixels and the first data line lead are electrically connected through a first second data line lead. The data line adjacent to the first-column sub-pixels and the first data line lead adjacent to the third-column sub-pixels are electrically connected through a second second data line lead.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, two second power lines are further provided between adjacent second-column sub-pixels and third-column sub-pixels. The two first data line leads are located between the two second power lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0029] Figure 1 It is a plan view of the display substrate provided by at least one embodiment of the present disclosure;

[0030] Figure 2 It is a plan layout diagram of partial traces in the display substrate provided by at least one embodiment of the present disclosure;

[0031] Figure 3 For Figure 2 the cross-sectional view of the traces along line aa in

[0032] Figure 4 Another planar layout schematic diagram of some traces in the display substrate provided by at least one embodiment of the present disclosure;

[0033] Figure 5A and Figure 5B are respectively Figure 2 and Figure 4 Planar schematic diagrams of the partial traces overlapping with the first electrode in

[0034] Figure 6 Another planar layout schematic diagram of some traces in the display substrate provided by at least one embodiment of the present disclosure;

[0035] Figure 7 Planar layout schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0036] Figures 8 - 11 Multiple planar layout schematic diagrams of some traces in the display substrate provided by at least one embodiment of the present disclosure;

[0037] Figure 12 Planar layout schematic diagram of the display substrate provided by at least one embodiment of the present disclosure under the 2 - in - 1 design of the first data line lead;

[0038] Figure 13 Another planar layout schematic diagram of the display substrate provided by at least one embodiment of the present disclosure under the 2 - in - 1 design of the first data line lead;

[0039] Figure 14 and Figure 15 Planar layout schematic diagram of the display substrate provided by at least one embodiment of the present disclosure under the 1 - in - 1 design of the first data line lead;

[0040] Figure 16 is Figure 14 An enlarged schematic diagram of the dashed box in

[0041] Figure 17 is Figure 16 Planar schematic diagram of the partial traces overlapping with the first electrode in

[0042] Figure 18 Schematic diagram of the connection of the data line, the first data line lead, and the second data line lead in the display substrate provided by at least one embodiment of the present disclosure;

[0043] Figure 19 Schematic diagram of the connection of the first data line lead and the second data line lead in the display substrate provided by at least one embodiment of the present disclosure;

[0044] Figure 20 is Figure 19 Planar schematic diagram of the partial traces overlapping with the first electrode in

[0045] Figure 21A Schematic diagram of the connection between the data line and the second data line lead in the display substrate provided by at least one embodiment of the present disclosure;

[0046] Figure 21B Another schematic diagram of the connection between the data line and the second data line lead in the display substrate provided by at least one embodiment of the present disclosure;

[0047] Figure 22 Another schematic diagram of the connection between the first data line lead and the second data line lead in the display substrate provided by at least one embodiment of the present disclosure;

[0048] Figure 23 and Figure 24 Another planar layout schematic diagram of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure under the 1-in-1 design;

[0049] Figure 25 Another planar layout schematic diagram of the first data line lead and the data line in the display substrate provided by at least one embodiment of the present disclosure;

[0050] Figure 26 and Figure 27 Another planar layout schematic diagram of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure under the 1-in-1 design;

[0051] Figure 28 is Figure 27 Planar schematic diagram of partial traces in [] overlapping with the first electrode;

[0052] Figure 29 Partial cross-sectional schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0053] Figure 30 Circuit diagram of the pixel driving circuit of the display substrate provided by at least one embodiment of the present disclosure;

[0054] Figure 31 is Figure 30 Working timing diagram of the pixel driving circuit in [];

[0055] Figure 32 Schematic diagram of the binding of the data line and the first data line lead in the non-display area of the display substrate provided by at least one embodiment of the present disclosure;

[0056] Figure 33 Another schematic diagram of the binding of the data line and the first data line lead in the non-display area of the display substrate provided by at least one embodiment of the present disclosure; and

[0057] Figure 34 and Figure 35Another schematic diagram of the planar layout of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure under the 1-in-1 design. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0059] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0060] With the pursuit of narrow bezels for display devices, such as mobile phones, a series of design solutions dedicated to shortening the bezels have emerged. The FIP technology (Fanout In Pixel) is a good method for reducing the bezel. In the FIP technology, the space occupied by Fanout at the lower corners of the display device can be effectively reduced by means of Fanout routing in the display area, achieving the purpose of narrowing the bezel.

[0061] In the display substrate, the routing layout based on the FIP technology is an important factor determining the display effect, manufacturing difficulty, and manufacturing yield of the display substrate. Therefore, how to optimize the routing layout is a topic that those skilled in the art have been continuously researching.

[0062] A display substrate provided by at least one embodiment of the present disclosure has a plurality of sub-pixels arranged in multiple rows and columns, and includes a substrate, a plurality of data lines, and a plurality of first data line leads; the substrate includes a display area and a non-display area, wherein the plurality of sub-pixels are arranged in the display area, the plurality of data lines are arranged on the substrate and located in the display area, extending along a first direction, configured to provide data signals to the plurality of sub-pixels, the plurality of first data line leads are arranged on the substrate and extend from the display area to the non-display area along the first direction, wherein at least part of the plurality of data lines are respectively electrically connected to the plurality of first data line leads to obtain data signals from the non-display area, and at least one of the plurality of first data line leads includes a first lead portion and a second lead portion, the first lead portion is located in a first conductive layer, the second lead portion is located in a second conductive layer, and the first lead portion and the second lead portion are electrically connected through a via hole.

[0063] In an embodiment of the present disclosure, a first conductive layer and a second conductive layer are used for routing the first data line leads, and the first data line leads are designed to adopt a jumper design in the first conductive layer and the second conductive layer. On the one hand, compared with single-conductive layer routing, the above design can prevent electrostatic discharge (ESD) during the manufacturing process and improve the manufacturing yield of the display substrate; on the other hand, using double-layer metal layer routing can reduce the manufacturing cost and the routing difficulty compared with more-layer routing, and can simultaneously achieve a narrow border and thinning of the display substrate.

[0064] The display substrate provided by the embodiments of the present disclosure will be described below through several specific embodiments.

[0065] At least one embodiment of the present disclosure provides a display substrate, Figure 1 showing a planar schematic diagram of the display substrate, Figure 2 showing a planar layout schematic diagram of partial traces in the display substrate, Figure 3 showing Figure 2 a cross-sectional schematic diagram of the trace in Figures 1 - 3 along line aa, as shown in

[0066] As shown in Figures 1 - 3As shown, the substrate 10 includes a display area AA and a non-display area NA. A plurality of sub-pixels SP are disposed in the display area AA for display. A plurality of data lines Da are disposed on the substrate 10 and at least located in the display area AA. For example, in some embodiments, they also extend to the non-display area NA. The plurality of data lines Da extend along a first direction R1, and are, for example, electrically connected to the plurality of sub-pixels SP, configured to provide data signals to the plurality of sub-pixels SP. A plurality of first data line leads DL1 are disposed on the substrate 10 and extend from the display area AA to the non-display area NA along the first direction R1. For example, they extend to the non-display area NA below the display area AA to be bonded in this area and connected to an integrated circuit IC (not shown in the figure). At least a part of the plurality of data lines Da are respectively electrically connected to at least one of the plurality of first data line leads DL1 to obtain data signals from the non-display area NA.

[0067] For example, in some embodiments, a part of the plurality of data lines Da obtains data signals from the non-display area NA by being electrically connected to the first data line leads DL1, and another part of the plurality of data lines Da directly extends to the non-display area NA to obtain data signals from the non-display area NA. At this time, the plurality of first data line leads DL1 can be used to plan the position where a part of the plurality of data lines Da is led out to the non-display area NA, thereby facilitating the bonding of the plurality of data lines Da for transmitting data signals and the plurality of first data line leads DL1 in the non-display area NA. For example, the bonding positions are more concentrated to achieve a narrow border.

[0068] As Figure 2 and Figure 3 As shown, at least one of the plurality of first data line leads DL1 (for example, the plurality of first data line leads DL1, for example, all the first data line leads DL1) includes a first lead portion DL11 and a second lead portion DL12. The first lead portion DL11 is located in the first conductive layer M1, and the second lead portion DL12 is located in the second conductive layer M2. The first lead portion DL11 and the second lead portion DL12 are electrically connected through vias (for example, the first via V1 and the second via V2, which will be introduced in detail later).

[0069] Thus, the first data line lead DL1 adopts a jumper design in the first conductive layer M1 and the second conductive layer M2, which can prevent adverse phenomena such as electrostatic discharge (ESD) during the manufacturing process and improve the manufacturing yield of the display substrate.

[0070] For example, in some embodiments, in a direction parallel to the substrate 10, at least one first data line lead DL1, for example, one or two first data line leads DL1, is disposed between two adjacent data lines Da. Figure 2As an example, two first data line leads DL1 are provided between two adjacent data lines Da. The case where one first data line lead DL1 is provided between two adjacent data lines Da will be described in detail later.

[0071] For example, in some embodiments, as Figure 3 shown, the second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 10, and multiple data lines Da are located in the second conductive layer M2. For example, in some other embodiments, the first conductive layer M1 may also be located on the side of the second conductive layer M2 away from the substrate 10.

[0072] For example, in some embodiments, as Figure 3 shown, a first insulating layer 11 is provided between the second conductive layer M2 and the first conductive layer M1 to insulate the conductive patterns in the second conductive layer M2 and the first conductive layer M1. The vias for connecting the first lead portion DL11 and the second lead portion DL12 include a first via V1 and a second via V2 that penetrate the first insulating layer 11. The two ends of the first lead portion DL11 are respectively connected to the second lead portion DL12 through the first via V1 and the second via V2, thereby realizing a jumper design.

[0073] For example, in Figure 3 , a film layer X is provided on the substrate 10. The film layer X may include a stack of multiple conductive layers and multiple insulating layers, which will be described in detail later with reference to Figure 29 for details.

[0074] For example, in some embodiments, as Figure 2 shown, for an adjacent first data line lead DL1 and a data line Da, the first insulating layer 11 further has a third via V3 that overlaps the data line Da in a direction perpendicular to the substrate 10 for the electrical connection of the data line Da. For example, for connecting the data line Da to a pixel driving circuit of a sub-pixel SP (described in detail later), or connecting the data line Da to the first data line lead DL1 or the second data line lead DL2 (described in detail later); in the first direction R1, the third via V3 is located between the first via V1 and the second via V2. Thus, the third via V3 is arranged in a staggered manner with the first via V1 and the second via V2, and the distance between the adjacent first data line lead DL1 and the data line Da can be arranged closer to save layout space.

[0075] For example, in some embodiments, two data lines Da and two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP. For example, as Figure 2 shown, the two first data line leads DL1 are located between the two data lines Da; or, as Figure 4As shown, two data lines Da are located between two first data line leads DL1, or two first data line leads DL1 and two data lines Da are arranged in sequence, or arranged alternately in sequence. For example, it can be the first data lead DL1, one data line Da, the first data lead DL1, one data line Da, or one data line Da, the first data lead DL1, one data line Da, the first data lead DL1.

[0076] Thus, Figure 2 and Figure 4 The technical solution of... adopts a design where each column of sub-pixels SP corresponds to one data line Da and one first data line lead DL1, which is hereinafter referred to as the 1-in-1 design. Compared with the design where every two columns of sub-pixels SP correspond to two data lines Da and one first data line lead DL1, hereinafter referred to as the 2-in-1 design, the number of first data line leads DL1 in the 1-in-1 design is more, which is convenient for routing connection, can shorten the total length of the first data line lead DL1 and the second data line lead DL2, reduce the resistance and overlapping capacitance of the data line leads, reduce data signal loss, and reduce the data line number load (Loading); in addition, the 1-in-1 design can also increase the density of the connection lines (part DL0 in the following text, to be introduced later) of, for example, the first power supply line VSS by about one time, better reduce the voltage drop of the first power supply line VSS, and reduce the screen power consumption; furthermore, the 1-in-1 design can also connect data signals through multiple first data line leads DL1 located in the middle of the display area AA, so as to narrow the Fanout connection width below the display area AA, reduce the bonding space of the data line Da and the first data line lead DL1 for binding and transmitting data signals in the non-display area NA below the display area AA, and achieve a narrow bezel design (to be described in detail later).

[0077] For example, in some embodiments, as Figure 2 and Figure 4 shown, two data lines Da between adjacent two columns of sub-pixels SP are symmetrically arranged, and the third vias V3 corresponding to the two data lines Da are symmetrically arranged; for example, two first data line leads DL1 between adjacent two columns of sub-pixels SP are symmetrically arranged, and the first via V1 and the second via V2 corresponding to the two first data line leads DL1 are also symmetrically arranged.

[0078] For example, for the design of Figure 2 , after the first electrode 1041 (for example, the anode of the light-emitting device EM of the sub-pixel SP, to be introduced in detail later) is fabricated on the side of the second conductive layer M2 away from the substrate 10, as Figure 5A shown, the first electrode 1041 may overlap with the first via V1 and the second via V2 corresponding to the first data line lead DL1; for Figure 4In the design, after the first electrode 1041 is fabricated on the side of the second conductive layer M2 away from the substrate 10, as Figure 5B shown, the first electrode 1041 can avoid the first vias V1 and the second vias V2 corresponding to the first data line leads DL1, thereby improving the flatness of the first electrode 1041.

[0079] For example, in some embodiments, the two first data line leads DL1 can also adopt other arrangement manners, such as an asymmetric arrangement manner. For example, as Figure 6 shown, when the two first data line leads DL1 are located between two data lines Da, the two first data line leads DL1 are arranged in a straight line along the first direction R1, and, in the first direction R1, the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 can be arranged at intervals alternately, or called staggered arrangement. For example, in the first direction, from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 corresponding to the right first data line lead DL1, the second via V2 corresponding to the left first data line lead DL1, and the second via V2 corresponding to the right first data line lead DL1 are arranged in sequence. At this time, the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 are left-right asymmetric, and this design can reduce the lateral arrangement space occupied by the first vias V1 and the second vias V2, making the arrangement of the two first data line leads DL1 more compact.

[0080] For example, in some embodiments, as Figure 7 shown, the display substrate may further include a second data line lead DL2, the second data line lead DL2 is located in the first conductive layer M1 and extends along the second direction R2, the second direction R2 is different from the first direction R1, for example, the second direction R2 is perpendicular to the first direction R1. For example, the second data line lead DL2 can be used to connect the data line Da and the first data line lead DL1 having a certain distance in the second direction R2.

[0081] For example, as Figure 7 shown, at least one of the two first data line leads DL1 between two adjacent columns of sub-pixels SP is connected to the second data line lead DL2 through a first jumper wire Z1, the first jumper wire Z1 can be located in the first conductive layer M1, and in the direction perpendicular to the substrate 10, the first jumper wire Z1 and at least one first data line lead DL1 at least partially overlap, so that the first jumper wire Z1 is blocked, thereby avoiding defects such as screen-off mura (a bad phenomenon of showing strip traces when the display substrate is in the screen-off state) on the display substrate.

[0082] For example, as Figure 7 shown, the first jumper wire Z1 is linear, inFigure 7 In the embodiment, the first data line lead DL1 and the second data line lead DL2 are connected along the first direction R1, that is, along the vertical direction in the figure. Thereby, the length of the patch cord can be shortened, the overlapping capacitance of the patch cord can be reduced, and when both first data line leads DL1 are connected to the second data line lead DL2 through the first patch cord Z1, the first patch cord Z1 and the second data line lead DL2 are substantially symmetric left and right. Thereby, after the first electrode 1041 is fabricated on the second conductive layer M2, the flatness of the first electrode 1041 can be optimized; in addition, the first patch cord Z1 and the first data line lead DL1 overlap at least partially, so that the first data line lead DL1 can block the first patch cord Z1, thereby reducing the off-screen mura, and Figure 7 The layout of the wiring in the embodiment has less change compared with the wiring layout of the 2-in-1 design.

[0083] For example, in some embodiments, such as Figure 8 shown, the second lead portions DL12 of the two first data line leads DL1 between two adjacent columns of sub-pixels SP may each include a bent portion B that bends in a direction approaching each other. Compared with Figure 6 the embodiment, the two first data line leads DL1 are retracted in a direction approaching each other, which can further save the lateral space. The saved lateral space can be used to widen the width of, for example, the second power supply line VDD (introduced in detail later) to reduce the voltage drop of the second power supply line VDD. For example, Figure 8 the situation shown in the embodiment can also be applied to Figure 7 the connection relationship.

[0084] For example, in some embodiments, such as Figures 9 - 11 shown, in the first direction R1, the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 between two adjacent columns of sub-pixels SP may be located on the same straight line. Thereby, the lateral space occupied by the two first data line leads DL1 and the first vias V1 and the second vias V2 can be further reduced. For example, Figures 9 - 11 the embodiments respectively adopt different jumper wire arrangements.

[0085] For example, in Figure 9 the embodiment, such as Figure 9 shown, in the first direction R1, the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. In the direction from top to bottom, the first vias V1 and the second vias V2 corresponding to the left first data line lead DL1 and the first vias V1 and the second vias V2 corresponding to the right first data line lead DL1 are arranged in sequence; compared with Figure 6 and Figure 8 the embodiments, Figure 9In the embodiment, the arrangement of the first vias V1 and the second vias V2 is more regular and symmetrical, thereby improving the flatness of the first electrode 1041 formed above the second conductive layer M2 subsequently; moreover, the first lead portions DL11 of the two first data line leads DL1 are also located on the same straight line, such that the lateral arrangement space of the first lead portions DL11 is smaller, which is suitable for the case where there are more traces in the first conductive layer M1, facilitating the arrangement of the traces in the first conductive layer M1.

[0086] For example, in Figure 10 the embodiment, as Figure 10 shown, in the first direction R1, the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. In the direction from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 corresponding to the right first data line lead DL1, the second via V2 corresponding to the left first data line lead DL1, and the second via V2 corresponding to the right first data line lead DL1 are arranged in sequence; at this time, both the first lead portion DL11 and the second lead portion DL12 have bent portions. Compared with Figure 9 the embodiment, the portions protruding left and right of the second lead portion DL12 in the second conductive layer M2 are less, saving the arrangement space of the second conductive layer M2, which is suitable for the case where there are more traces in the second conductive layer M2.

[0087] For example, in Figure 11 the embodiment, as Figure 11 shown, in the first direction R1, the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. In the direction from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 and the second via V2 corresponding to the right first data line lead DL1, and the second via V2 corresponding to the left first data line lead DL1 are arranged in sequence; compared with Figure 9 and Figure 10 the embodiments, in the first conductive layer M1, the first lead portion DL11 only protrudes to the left, and in the second conductive layer M2, the second lead portion DL12 only protrudes to the right, which is suitable for the case where multiple sub-pixels SP are not symmetrically designed left and right.

[0088] For example, in each of the above embodiments, the positions of the first data line lead DL1 and the data line Da can be interchanged, and the arrangement manners of adjacent first data line leads DL1 and their vias can also be interchanged. The embodiments of the present disclosure will not be elaborated one by one herein.

[0089] In the above embodiments of the present disclosure, the first data line lead DL1 is arranged with a double-layer conductive layer and a jumper design is adopted, thereby avoiding adverse phenomena such as electrostatic discharge during the preparation of the display substrate, improving the preparation yield of the display substrate, and saving costs; in addition, the above 1-in-1 design can shorten the total length of the data line leads, reduce the resistance and overlapping capacitance of the data line leads, reduce data signal loss, reduce the load, narrow the border, and reduce costs.

[0090] For example, in some embodiments, the display substrate may also adopt a 2-in-1 design. For example, Figure 12 FIG. shows a schematic plan view of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure with a 2-in-1 design, such as Figure 12 shown, in the direction parallel to the substrate 10, two data lines Da are provided between adjacent two columns of sub-pixels SP, and a first data line lead DL1 is provided between the two data lines Da. At this time, two data lines Da and a first data line lead DL1 are correspondingly provided for each two columns of sub-pixels SP. The data lines Da and the first data line lead DL1 extend along the first direction R1.

[0091] For example, as Figure 12 shown, the display substrate may further include a second data line lead DL2. The second data line lead DL2 is located in the first conductive layer M1 and extends along the second direction R2. The second direction R2 is different from the first direction R1. For example, the second direction R2 is perpendicular to the first direction R1. For example, the second data line lead DL2 can be used to connect the data lines Da and the first data line lead DL1 that have a certain distance in the second direction R2. For example, the first data line lead DL1 is connected to the second data line lead DL2 through a second jumper wire Z2. The second jumper wire Z2 is located in the first conductive layer M1. In the direction perpendicular to the substrate 10, the second jumper wire Z2 at least partially overlaps with one of the two data lines Da ( Figure 12 the rightmost data line Da in ) so that the second jumper wire Z2 is blocked.

[0092] For example, as Figure 12 shown, a break DS can be designed in the first data line lead DL1 or the second data line lead DL2 to disconnect the part of the first data line lead DL1 or the second data line lead DL2 for connecting different data lines Da, or disconnect the part for connecting the data lines Da and the part for connecting the first power supply VSS to prevent signal crosstalk.

[0093] For example, in some embodiments, the second data line lead DL2 is located in the first conductive layer M1, and the break DS of the second data line lead DL2 can overlap with the conductive pattern in the second conductive layer M2 to be blocked by the conductive pattern in the second conductive layer M2. For exampleFigure 12 is blocked by the second power supply line VDD in the second conductive layer M2; for example, the first data line lead DL1 is located in the second conductive layer M2, and the break ( Figure 12 not shown) in the first data line lead DL1 can overlap with the conductive pattern in the first conductive layer M1 to be blocked by the conductive pattern in the first conductive layer M1. Blocking the break can prevent defects such as light leakage on the display substrate.

[0094] For example, in the above embodiment, a longitudinally extending first data line lead DL1 is inserted between every two columns of sub-pixels SP. The first data line lead DL1 is connected to a laterally extending second data line lead DL2 through a second jumper wire Z2. The second jumper wire Z2 at least partially overlaps with the data line Da, so as to be blocked by the data line Da, which can prevent defects such as screen-off mura on the display substrate. At the same time, the second jumper wire Z2 can also avoid structures such as the source-drain electrodes SD of the transistors (described in detail later) of the pixel driving circuit of the sub-pixel SP, as Figure 12 shown. For example, the second data line lead DL2 can overlap with signal lines in other conductive layers except the first conductive layer M1, so as to be blocked / shielded by signal lines in other conductive layers except the first conductive layer M1, such as reset voltage lines or scan signal lines, etc., to prevent defects such as screen-off mura.

[0095] For example, in some embodiments, a part of the longitudinally extending first data line lead DL1 and the laterally extending second data line lead DL2 is used to transmit data signals, that is, connected to the data line Da, and another part can be used to connect to the first power supply line VSS to transmit the first power signal, so as to reduce the voltage drop of the first power supply line VSS. At this time, the part for transmitting data signals and the part for transmitting the first power signal are disconnected through a break (such as break DS and breaks DS1, DS2, etc. in the following text) to prevent signal crosstalk.

[0096] For example, in some embodiments, as Figure 13 shown, there can be two jumper wires ZS for connecting the first data line lead DL1 and the second data line lead DL2, and the two jumper wires ZS can be symmetrically arranged. When this part of the first data line lead DL1 and the second data line lead DL2 is used to connect to the first power supply line VSS, this design can increase the access points of the first power supply line VSS, further reduce the voltage drop, reduce the overall power consumption, and optimize the flatness of the first electrode 1041 formed subsequently.

[0097] For example, Figure 14 is a schematic plan view of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure with a 1-in-1 design. As Figure 14As shown, in the 1-in-1 design, in the direction parallel to the substrate 10, two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP, two data lines Da are provided between two adjacent columns of sub-pixels SP, and the two first data line leads DL1 are provided between the two data lines Da; alternatively, in some other embodiments, the positions of the data lines Da and the first data line leads DL1 can be interchanged, and two data lines Da are provided between the two first data line leads DL1. The following takes Figure 14 the case where two first data line leads DL1 are provided between the two data lines Da shown as an example for introduction.

[0098] For example, as Figure 14 shown, the display substrate may further include a plurality of second data line leads DL2, and the second data line leads DL2 are located in the first conductive layer M1 and extend along the second direction R2. The first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the plurality of second data line leads DL2, and the first second data line lead 1DL2 is connected to the first first data line lead 1DL1 that is at least one sub-pixel SP (two sub-pixels SP are spaced in the figure) away from the first data line Da1; the second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the plurality of second data line leads DL2, and the second second data line lead 2DL2 is connected to the second first data line lead 2DL1 that is at least one sub-pixel SP (two sub-pixels SP are spaced in the figure) away from the second data line Da2.

[0099] For example, in the Figure 14 embodiment, the first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the plurality of second data line leads DL2 through the third jumper wire Z3. In the direction perpendicular to the substrate 10, the first data line Da1 and the third jumper wire Z3 at least partially overlap, for example, almost completely overlap, so that the third jumper wire Z3 is blocked; the second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the plurality of second data line leads DL2 through the fourth jumper wire Z4. In the direction perpendicular to the substrate 10, the second data line Da and the third jumper wire Z3 at least partially overlap, for example, almost completely overlap, so that the fourth jumper wire Z4 is blocked. For example, both the third jumper wire Z3 and the fourth jumper wire Z4 are located in the first conductive layer M1, and the blocking of the third jumper wire Z3 and the fourth jumper wire Z4 can prevent defects such as screen-off mura on the display substrate.

[0100] For example, in Figure 14In an embodiment, the first second data line lead 1DL2 is connected to the first first data line lead 1DL1 that is at least one sub-pixel SP (two sub-pixels SP are spaced in the figure) away from the first data line Da through the fifth jumper wire Z5. In a direction perpendicular to the substrate 10, the fifth jumper wire Z5 and the data line Da adjacent (on the left side) to the first first data line lead 1DL1 at least partially overlap, so that the fifth jumper wire Z5 is at least partially blocked; the second second data line lead DL2 is connected to the second first data line lead 2DL1 that is at least one sub-pixel SP (two sub-pixels SP are spaced in the figure) away from the second data line Da2 through the sixth jumper wire Z6. In a direction perpendicular to the substrate 10, the sixth jumper wire Z6 and the data line Da adjacent (on the right side) to the second first data line lead 2DL1 at least partially overlap, so that the sixth jumper wire Z6 is at least partially blocked. For example, both the fifth jumper wire Z5 and the sixth jumper wire Z6 are located in the first conductive layer M1. The blocking of the fifth jumper wire Z5 and the sixth jumper wire Z6 can prevent defects such as black screen mura on the display substrate.

[0101] For example, in Figure 14 's embodiment, the display substrate further includes a first power supply line VSS. Part DL0 of the first data line lead DL1 and the second data line lead DL2 is used to connect to the first power supply line VSS. At this time, part DL0 is disconnected from the parts of the first data line lead DL1 and the second data line lead DL2 that are used to transmit data signals through the break DS / DS1. Part DL0 can reduce the voltage drop of the first power supply line VSS, thereby improving the display uniformity of the display substrate.

[0102] For example, Figure 16 shows Figure 14 an enlarged schematic view of the dashed box in Figure 16 As shown, the first data line lead DL1 and the second data line lead DL2 are connected through the jumper wire Z0. The two jumper wires Z0 are symmetrically arranged, and the data line Da bypasses the position of the via hole. Thus, as Figure 17 shown, after the first electrode 1041 of the light-emitting device EM is formed subsequently, the data line leads, jumper wires, via holes, etc. under the first electrode 1041 are all symmetrically designed, thereby improving the flatness of the first electrode 1041.

[0103] For example, in Figure 14 , in order to highlight the connection relationship between the data line Da, the first data line lead DL1, and the second data line lead DL2, Figure 14 the connections of these traces are shown in bold (lines for transmitting data signals) / weakened (lines for transmitting the first power signal) to clearly show these connection relationships, and the clean version of the circuit layout diagram without the highlighted connection relationships is as shown in Figure 15As shown, for details, please refer to Figure 15 .

[0104] For example, as Figure 14 shown, the first data line Da1, the first second data line lead 1DL2, and the first first data line lead 1DL1 form the first data line network G1, the second data line Da2, the second second data line lead 2DL2, and the second first data line lead 2DL1 form the second data line network G2, and the second data line network G2 is located outside the first data line network G1. For example, the second data line network G2 surrounds the first data line network G1. For example, the first data line network G1 and the second data line network G2 extend to the non-display area NA at the lower part of the display substrate at a position close to the middle of the display substrate (shown as the right side in the figure) for bonding in the non-display area NA. For example, the display substrate may further include more data line networks located outside the second data line network G2, and these data line networks are wound layer by layer and extend to the non-display area NA at the lower part of the display substrate at a position close to the middle of the display substrate (shown as the right side in the figure) for bonding in the non-display area NA.

[0105] In the embodiments of the present disclosure, the above winding method can reduce the bonding width of the traces for transmitting data signals below the display area AA, or referred to as the Fanout access width, so as to save the space occupied by bonding in the non-display area NA.

[0106] For example, as Figure 14 shown, the two first data line leads DL1 located between the two data lines Da include a disconnected part DL0 disconnected from the first data line network G1 and the second data line network G2. The disconnected position, that is, the break, is shown as a virtual coil DS1. For example, the disconnected part DL0 is connected to the first power supply line VSS to reduce the voltage drop of the first power supply line VSS. For example, in the direction perpendicular to the substrate 10, the disconnected position overlaps with the first conductive layer M1 or the second conductive layer M2, that is, overlaps with the conductive pattern in the first conductive layer M1 or the second conductive layer M2, or overlaps with the structure in other conductive layers, so that the break is blocked to prevent bad phenomena such as light leakage.

[0107] For example, in some examples, when the break DS1 of the first data line lead DL1 is located in the first lead part DL11, since the first lead part DL11 is located in the first conductive layer M1, at this time, the break DS1 can overlap with the second conductive layer M2, that is, be blocked by the conductive pattern in the second conductive layer M2; or, when the break DS1 is located in the second lead part DL12, the second lead part DL12 is located in the second conductive layer M2, at this time, the break DS1 can overlap with the first conductive layer M1, that is, be blocked by the conductive pattern in the first conductive layer M1.

[0108] For example, inFigures 14 - 17 In the embodiment of Figures 14 - 17 , the first data line lead DL1 extends along the first direction R1 and has no bent portion to maximize the use of the layout space; as Figure 17 shown, the jumper line Z0 bypasses the source-drain electrodes SD of the transistor around the left and right, and each jumper line is located in the first conductive layer M1, and the traces in other conductive layers can be used for shielding; compared with the FIP 2-in-1 design, the 1-in-1 design can shorten the total length of the data line leads (including the first data line lead DL1 and the second data line lead DL2), reduce the lead resistance and overlapping capacitance, reduce the data signal loss, and reduce the data signal load; in addition, the 1-in-1 design can also increase the density of the connection lines (such as part of DL0) of the first power supply line VSS by, for example, twice, so as to better control the voltage drop of the first power supply line VSS and reduce the screen power consumption; and, the 1-in-1 design can also reduce the bonding width of the traces for transmitting data signals below the display area AA, saving the space occupied by bonding in the non-display area NA.

[0109] For example, Figure 32 shows a schematic diagram of the bonding of the data line Da and the first data line lead DL1 in the non-display area NA in the 2-in-1 design. As Figure 32 shown, one square represents two sub-pixels P, and two sub-pixels P are correspondingly provided with two data lines Da and one first data line lead DL1. In Figure 32 it shows 16 data lines Da and 8 first data line leads DL1 corresponding to 16 sub-pixels P in total, a total of 24 signal lines. That is, 24 signal lines need to access the lower bonding area through the space corresponding to 16 sub-pixels P, and the vertical space occupied by the connection part SL is certain. Figure 33 shows a schematic diagram of the bonding of the data line Da and the first data line lead DL1 in the non-display area NA in the 1-in-1 design. One square represents two sub-pixels P, and two sub-pixels P are correspondingly provided with two data lines Da and two first data line leads DL1. In Figure 32 it shows 12 data lines Da and 12 first data line leads DL1 corresponding to 12 sub-pixels P in total, a total of 24 signal lines. That is, 24 signal lines need to access the lower bonding area through the space corresponding to 12 sub-pixels P; the vertical space occupied by the connection part SL is relatively smaller. Thus, the space occupied by bonding in the non-display area NA is saved.

[0110] For example, in some other embodiments, the data line Da, the first data line lead DL1, and the second data line lead DL2 can also adopt different connection methods. For example, as Figure 18As shown, the data line Da can also be connected to the second data line lead DL2 through the first data line lead DL1. In this case, the data line Da is first connected to the first data line lead DL1 through the adapter line Z21, and then connected to the second data line lead DL2 through the adapter line Z22. Figure 18 As shown, the adapter wires Z21 and Z22 used by two adjacent data lines Da can be arranged symmetrically.

[0111] For example, Figure 18 As shown, there is also a break DS in the second data line lead DL2 to separate the part of the second data line lead DL2 used to transmit the data signal and the part used to transmit the first power signal. For example, the second data line lead DL2 is located in the first conductive layer M1, and the break DS in the second data line lead DL2 at least partially overlaps with the conductive pattern in the second conductive layer M2 so as to be blocked by the conductive pattern in the second conductive layer M2, for example, blocked by the second power line VDD in the second conductive layer M2, thereby preventing adverse phenomena such as light leakage from occurring on the display substrate.

[0112] For example, Figure 19 A schematic diagram of the connection between a first data line lead and a second data line lead in a display substrate provided in at least one embodiment of the present disclosure; Figure 19 As shown, in other embodiments, two first data line leads DL1 are arranged between two adjacent columns of sub-pixels SP, and two data lines Da are arranged between the two first data line leads DL1. For example, the data line Da extends straight along the first direction R1, the first data line lead DL1 has a bent portion at the position of the third via hole V3 of the data line Da to avoid the third via hole V3, and the first data line lead DL1 is electrically connected to the second data line lead DL2 through the transfer hole V0 and the transfer line Z23.

[0113] For example, Figure 19 Examples and Figure 14 Compared with the embodiment of the present invention, the first data line lead DL1 and the data line Da are swapped, and the two data lines Da are placed between the two first data line leads DL1, thereby reducing the impact of data signal jumps on surrounding signal lines; Figure 20 As shown, after the first electrode 1041 is disposed on the second conductive layer M2 , the first electrode 1041 can avoid the transfer hole V0 and the third via hole V3 , thereby improving the flatness of the first electrode 1041 .

[0114] For example, in the embodiment of the present disclosure, the data line Da may be connected to the second data line lead DL2 in different ways. Figure 21A and Figure 21B Schematic diagrams showing different situations of connection between the data line Da and the second data line lead wire, such as Figure 21AAs shown, the data line Da is electrically connected to the second data line lead DL2 through the third via V3 and the adapter line Z24. The adapter line Z24 is located in the first conductive layer M1 and at least partially overlaps with the data line Da and the first data line lead DL1, so that the adapter line Z24 can be blocked by the data line Da and the first data line lead DL1 to prevent defects such as screen mura.

[0115] For example, Figure 21B As shown, the data line Da is first connected to the adjacent first data line lead DL1 through the third via V3 and the adapter line Z25, and the first data line lead DL1 is then connected to the second data line lead DL2 through the via V31 and the adapter line Z26. For example, the adapter line Z25 and the adapter line Z26 are both located in the first conductive layer M1, and the adapter line Z25 and the adapter line Z26 at least partially overlap with the first data line lead DL1, so that the adapter line Z25 and the adapter line Z26 can be shielded by the first data line lead DL1 to prevent defects such as screen mura.

[0116] Figure 21B Examples and Figure 21A Compared with the embodiment of the present invention, the first data line lead DL1 and the data line Da can share the adapter line, saving the layout space, and through the design of multiple break points DS2, it is possible to disconnect the transmission network that transmits different signals, for example, disconnect the part used to transmit the data signal and the part used to transmit the first power signal, and the adapter patterns of the two parts are not much different, which is conducive to improving the uniformity of the film layer; Figure 21A Examples and Figure 21B Compared with the embodiment, the switching path of the data line Da is shorter, and there is no need to borrow a section of the first data line lead DL1, thereby not wasting the adjacent first data line lead DL1, and also reducing the data signal loading and the overlapping capacitance, which can correspondingly increase the setting density of the part used to transmit the first power signal.

[0117] For example, in other embodiments, Figure 22 As shown, the second data line lead DL2 can be directly connected to the first data line lead DL1 through the transfer hole V4. Figure 19 Compared with the above embodiments, the electrical connection is no longer made by using a transfer wire. In this case, it is no longer necessary to provide a via in the first insulating layer 11. This can reduce the length of the transfer path, eliminate the need to specially design a wiring layout to shield the transfer wire and the break, and simplify the arrangement of the break and the transfer line.

[0118] For example, if the second data line lead DL2 needs to be transferred to the longitudinal first data line lead DL1, the transfer line can be replaced by a transfer hole, referring to Figure 35The via hole V36 therein retains the first conductive layer M1 and the second conductive layer M2, and retains the via layer, that is, the layer where vias are provided, namely the first insulating layer 11, thereby saving space for jumper wires. For example, if it is necessary to keep the first data line lead DL1 unbroken and the second data line lead DL2 also unbroken, the via layer can be removed, that is, no via hole is provided, and the conductive patterns of the first conductive layer M1 and the second conductive layer M2 are retained. Refer to Figure 35 the part shown by the dashed circle 1 in Figure 35 ; for example, if it is necessary to set the break position of the first data line lead DL1, the via layer can be removed, that is, no via hole is provided, and only the conductive pattern of the first conductive layer M1 is retained. Refer to Figure 35 the part shown by the dashed circle 3 in

[0119] For example, Figure 21A 、 Figure 21B and Figure 22 The connection method can be used in the wire routing arrangement provided by any embodiment of the present disclosure.

[0120] For example, Figure 23 is another planar layout diagram of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure. In some embodiments, as Figure 23 shown, two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP, and two data lines Da are provided between the two first data line leads DL1. For example, the first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the plurality of second data line leads DL2 through the third jumper wire Z3. In the direction perpendicular to the substrate 10, the third jumper wire Z3 and the first data line lead DL1 adjacent to the first data line Da1 at least partially overlap, and for example, also at least partially overlap with the first data line Da1, so that the third jumper wire Z3 is blocked; the second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the plurality of second data line leads DL2 through the fourth jumper wire Z4. In the direction perpendicular to the substrate 10, the fourth jumper wire Z4 and the first data line lead DL1 adjacent to the second data line Da at least partially overlap, and for example, also at least partially overlap with the second data line Da2, so that the fourth jumper wire Z4 is blocked.

[0121] For example, as Figure 23As shown, the first second data line lead 1DL2 is directly connected to the first first data line lead 1DL1 that is at least one sub-pixel SP apart from the first data line Da (shown as two sub-pixels SP apart in the figure) through the fourth via V4; the second second data line lead DL2 is directly connected to the second first data line lead 2DL1 that is at least one sub-pixel SP apart from the second data line Da (shown as two sub-pixels SP apart in the figure) through the fifth via V5. Thus, the design and layout of the jumper wire are saved.

[0122] For example, as Figure 23 shown, the first data line lead 1DL1 and the second data line lead DL2 also have a portion DL0 for connecting the first power signal, and the portion DL0 is disconnected from the portions of the first data line lead 1DL1 and the second data line lead DL2 for connecting the data signal through the break DS3. For example, in Figure 23 the embodiment, in the portion DL0 of the first data line lead 1DL1 and the second data line lead DL2 for connecting the first power signal, the first data line lead 1DL1 and the second data line lead DL2 are electrically connected through the via V41.

[0123] For example, in Figure 23 the embodiment, the first data line Da1, the first second data line lead 1DL2, and the first first data line lead 1DL1 form the first data line network G1, the second data line Da2, the second second data line lead 2DL2, and the second first data line lead 2DL1 form the second data line network G2, and the second data line network G2 is located on the periphery of the first data line network G1. For example, the second data line network G2 surrounds the first data line network G1. For example, the first data line network G1 and the second data line network G2 can extend to the non-display area NA at the lower part of the display substrate at a position close to the middle of the display substrate (shown as the right side in the figure) for bonding in the non-display area NA. For example, the display substrate may further include more data line networks located on the periphery of the second data line network G2, and these data line networks are wound layer by layer and extend to the non-display area NA at the lower part of the display substrate at a position close to the middle of the display substrate (such as shown as the right side in the figure) for bonding in the non-display area NA.

[0124] For example, in Figure 23 , in order to highlight the connection relationship between the data line Da, the first data line lead DL1, and the second data line lead DL2, Figure 23 the connections of these traces are highlighted to clearly show these connection relationships, and the clean version of the circuit layout diagram without the highlighted connection relationships is as Figure 24 shown, and specifically, reference can be made to Figure 24 .

[0125] For example, in some other embodiments, the display data line Da and the first data line lead DL1 may also adopt other arrangements. For example, Figure 25 FIG. is a schematic diagram of another planar arrangement of the first data line lead and the data line in the display substrate provided by at least one embodiment of the present disclosure. As Figure 25 shown, in the direction parallel to the substrate 10, two data lines Da are provided between the adjacent first column of sub-pixels SP1 and the second column of sub-pixels SP2, and a reset voltage line Vint (to be introduced in detail later) is provided between the two data lines Da. Two first data line leads DL1 are provided between the adjacent second column of sub-pixels SP2 and the third column of sub-pixels SP3.

[0126] For example, Figure 26 FIG. is a schematic diagram of another planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure with a 1-in-1 design. Figure 26 shows the connection relationship between the data line Da, the first data line lead DL1, and the second data line lead DL2. As Figure 26 shown, the data line Da1 (the first data line Da1 on the left side of the second column of sub-pixels SP2) adjacent to the second column of sub-pixels SP2 and the first data line lead DL1 (the first first data line lead 1DL1 on the right side of the second column of sub-pixels SP2) are electrically connected through the first second data line lead 1DL2. For example, the first data line Da1 is electrically connected to the first second data line lead 1DL2 through the seventh jumper wire Z7. For example, the seventh jumper wire Z7 at least partially overlaps with the data line Da1 so that the seventh jumper wire Z7 is blocked. For example, the first second data line lead 1DL2 is electrically connected to the first first data line lead 1DL1 through the eighth jumper wire Z8. For example, the eighth jumper wire Z8 at least partially overlaps with the first first data line lead 1DL1 so that the eighth jumper wire Z8 is blocked. Alternatively, in some other embodiments, the first second data line lead 1DL2 may also be directly electrically connected to the first data line lead DL1 through a via; or the first data line Da1 may also be directly electrically connected to the first second data line lead 1DL2 through a via.

[0127] For example, as Figure 26As shown, the data line Da2 adjacent to the first column of sub-pixels SP (the second data line Da2 to the right of the second column of sub-pixels SP2) and the first data line lead DL1 adjacent to the third column of sub-pixels SP (the second first data line lead 2DL1 to the left of the third column of sub-pixels SP) are electrically connected through the second second data line lead 2DL2. For example, the data line Da2 is electrically connected to the second second data line lead 2DL2 through the ninth jumper wire Z9. For example, the ninth jumper wire Z9 at least partially overlaps with the second data line Da2 so that the ninth jumper wire Z9 is blocked. For example, the second second data line lead 2DL2 is electrically connected to the first data line lead DL1 through the tenth jumper wire Z10. For example, the tenth jumper wire Z10 at least partially overlaps with the second second data line lead 2DL2 so that the tenth jumper wire Z10 is blocked. Alternatively, in some other embodiments, the second second data line lead 2DL2 can also be directly electrically connected to the second first data line lead 2DL1 through a via; or the data line Da2 can also be directly electrically connected to the second second data line lead 2DL2 through a via.

[0128] For example, as Figure 26 shown, the first data line lead DL1 has a break DS1. Figure 26 Shown as an example in the first first data line lead 1DL1 having a break DS1, the break DS1 disconnects the part of the first first data line lead 1DL1 for transmitting data signals from the part for transmitting the first power signal. For example, the disconnected part of the first first data line lead 1DL1 is the first lead part DL11. Since the first lead part DL11 is located in the first conductive layer M1, at this time, the break DS1 can overlap with the second conductive layer M2, that is, be blocked by the conductive pattern in the second conductive layer M2; or the disconnected part of the first first data line lead 1DL1 is the second lead part DL12, and the second lead part DL12 is located in the second conductive layer M2. At this time, the break DS1 can overlap with the first conductive layer M1, that is, be blocked by the conductive pattern in the first conductive layer M1.

[0129] For example, as Figure 26 shown, two second power supply lines VDD are also provided in the adjacent second column of sub-pixels SP and third column of sub-pixels SP, that is, the second column of sub-pixels SP corresponds to one second power supply line VDD, and the third column of sub-pixels SP corresponds to one second power supply line VDD. For example, the two first data line leads DL1 can be located between the two second power supply lines VDD.

[0130] For example, in Figure 26 order to highlight the connection relationship between the data line Da, the first data line lead DL1, and the second data line lead DL2. Figure 26The connections of these traces are highlighted to clearly show these connections, while the clean version of the circuit layout without the highlighted connections is shown in FIG. Figure 27 For details, please refer to Figure 27 .

[0131] For example, Figure 28 Shows Figure 26 and Figure 27 A schematic plan view of a first electrode 1041 disposed on the second conductive layer M2 in an embodiment of the present invention is shown in FIG. Figure 28 As shown, the first electrode 1041 can avoid the third via hole V3 of the data line Da, thereby improving the flatness of the first electrode 1041.

[0132] For example, in Figure 26 and Figure 27 In the embodiment, compared to Figure 23 and Figure 24 In the embodiment, the positions of the two first data line leads DL1 and the reset voltage line Vint are interchanged, the reset voltage line Vint is located between the two data lines Da, and the two first data line leads DL1 are located between the two second power lines VDD; thereby, the switching paths between the display data line Da, the first data line lead DL1 and the second data line lead DL2 are short, the break is well designed, and it is easy to be shielded by other conductive layers, and the third via hole V3 and other via holes can avoid the first electrode 1041 to improve the flatness of the first electrode 1041.

[0133] For example, Figure 34 Another schematic diagram of another planar arrangement of the first data line lead in the display substrate provided in at least one embodiment of the present disclosure using a 1-in-1 design. In some embodiments, as Figure 34 As shown, two first data line leads DL1 are arranged between two adjacent columns of sub-pixels SP, and two data lines Da are arranged between the two first data line leads DL1. For example, the first data line Da1 of the two data lines Da is connected to the first first data line lead 1DL1 and the first second data line lead 1DL2 through the transfer hole V35, the transfer line Z35 and the transfer hole V36. At this time, the first data line Da1 is connected to the first first data line lead 1DL1 adjacent to it and located in the same sub-pixel SP.

[0134] For example, in a direction perpendicular to the base substrate 10 , the adapter line Z35 and the first data line lead 1DL1 at least partially overlap, so that the adapter line Z35 is shielded.

[0135] For example, Figure 34As shown, in the portion DL0 of the first data line lead DL1 and the second data line lead DL2 for transmitting the first power signal, the two first data line leads DL1 are respectively connected to the second data line lead DL2 through two via holes V34 to form a transmission network for the first power signal.

[0136] For example, in Figure 34 , in order to highlight the connection relationship between the data line Da, the first data line lead DL1, and the second data line lead DL2, Figure 34 the connections of these traces are highlighted to clearly show these connection relationships, and the clean version of the circuit layout diagram with the highlighted connection relationships removed is as shown in Figure 35 shown, and specifically, reference can be made to Figure 35 .

[0137] For example, Figure 29 shows a partial cross-sectional schematic diagram of a display substrate, as shown in Figure 29 , each of the multiple sub-pixels SP includes a light-emitting device EM and a pixel driving circuit for driving the light-emitting device EM. The light-emitting device EM includes a first electrode 1041 connected to the pixel driving circuit, a second electrode 1043 spaced apart from the first electrode 1041, and a light-emitting layer 1042 between the first electrode 1041 and the second electrode 1043. For example, the first electrode 1041 is the anode of the light-emitting device EM and is used to receive the second power signal provided by the second power line VDD. For example, the second power signal is a high-level signal. For example, the second electrode 1043 is the cathode of the light-emitting device EM and is electrically connected to the first power line VSS and is used to receive the first power signal. For example, the first power signal is a low-level signal.

[0138] For example, as shown in Figure 29 , the pixel driving circuit includes a transistor T and a storage capacitor C. The transistor T includes an active layer 1021, a gate 1022, a first source-drain 1023, and a second source-drain 1024. The first source-drain 1023 is electrically connected to the first electrode 1041 through a connection electrode CEL. The first source-drain 1023 and the second source-drain 1024 are located in the first conductive layer M1, and the first conductive layer M1 can also be referred to as the SD1 conductive layer. The connection electrode CEL is located in the second conductive layer M2, and the second conductive layer M2 can also be referred to as the SD2 conductive layer.

[0139] For example, as shown in Figure 29As shown, the display substrate may further include more conductive layers, such as a third conductive layer M3 and a fourth conductive layer M4. The fourth conductive layer M4 is disposed on a side of the third conductive layer M3 away from the substrate 10, and the first conductive layer M1 is disposed on a side of the fourth conductive layer M4 away from the substrate 10. For example, the storage capacitor C includes a first capacitor electrode C1 and a second capacitor electrode C2. For example, the first capacitor electrode C1 and the first gate 1022 are disposed on the third conductive layer M3, and the third conductive layer M3 may also be referred to as the Gate1 conductive layer. The second capacitor electrode C2 is disposed on the fourth conductive layer M4, and the fourth conductive layer M4 may also be referred to as the Gate2 conductive layer.

[0140] For example, as Figure 29 shown, the display substrate may further include at least one barrier layer 1012 and at least one buffer layer 1013 disposed on the substrate 10. Figure 29 One barrier layer 1012 and one buffer layer 101 are shown as an example. The barrier layer 1012 and the buffer layer 1013 can prevent impurities in the substrate 10 from entering the multiple functional layers on the display substrate, thereby playing a protective role. For example, the barrier layer 1012 and the buffer layer 1013 can be made of one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0141] For example, as Figure 29 shown, the display substrate may further include a first gate insulating layer GI1 disposed on a side of the active layer 1021 away from the substrate 11, a second gate insulating layer GI2 disposed on a side of the gate 1022 and the first capacitor electrode C1 away from the substrate 11, and an interlayer insulating layer IDL disposed on a side of the second capacitor electrode C2 away from the substrate 11. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IDL can be made of one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0142] For example, as Figure 29 shown, a first insulating layer 11 is disposed on a side of the first source-drain 1023 and the second source-drain 1024 away from the substrate 11. The first insulating layer 11 can serve as a planarization layer to planarize the pixel driving circuit, thereby forming a relatively flat surface for facilitating the setting of the light-emitting device EM. For example, the display substrate may further include a second insulating layer 12 disposed on a side of the connection electrode CEL away from the substrate 10. The second insulating layer 12 can also be a planarization layer to further planarize the pixel driving circuit and the connection electrode CEL.

[0143] For example, the display substrate may further include a pixel defining layer PDL disposed on a side of the first electrode 1041 away from the substrate 10. The pixel defining layer PDL has a plurality of sub-pixel openings OP to expose the first electrodes 1041 of the plurality of sub-pixels SP and define the light-emitting regions of the plurality of sub-pixels SP. For example, the display substrate may further include a spacer layer PS disposed on a side of the pixel defining layer PDL away from the substrate 10. The spacer layer PS has a plurality of spacers to perform a supporting and isolating function.

[0144] For example, the first insulating layer 11, the second insulating layer, and the spacer layer PS may be made of an organic insulating material such as resin or polyimide. The pixel defining layer PDL may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride; or, in some other embodiments, the pixel defining layer PDL may also be made of an organic insulating material such as resin or polyimide.

[0145] For example, as Figure 29 shown, the display substrate may further include a packaging layer EN disposed on a side of the light-emitting device EM away from the substrate 10. The packaging layer EN may be a composite packaging layer including a stack of an inorganic packaging layer EN1 and an organic packaging layer EN2. The inorganic packaging layer EN1 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The organic packaging layer EN2 may be made of an organic insulating material such as resin or polyimide.

[0146] For example, in the embodiments of the present disclosure, the substrate 10 may be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The active layer 1021 of each transistor may be a semiconductor layer in various forms such as an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer. For example, the polysilicon may be high-temperature polysilicon or low-temperature polysilicon, and the oxide semiconductor may be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO), etc.

[0147] For example, the gate 1022 of each transistor may be made of a metal material such as copper (Cu), aluminum (Al), or titanium (Ti), or an alloy material, and may be formed, for example, as a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure of titanium / aluminum / titanium, etc. The source / drain electrodes 1023 / 1024 of each transistor may be made of a metal material such as copper (Cu), aluminum (Al), or titanium (Ti), or an alloy material, and may be formed, for example, as a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure of titanium / aluminum / titanium, etc.

[0148] For example, the material of the first electrode 1041 may be a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), etc., and the second electrode 1043 may be made of a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc. The embodiments of the present disclosure do not specifically limit the materials of each structure.

[0149] For example, the pixel driving circuit in the embodiments of the present disclosure may be various forms of pixel driving circuits such as 3T1C (i.e., including 3 transistors and 1 storage capacitor), 7T1C (i.e., including 7 transistors and 1 storage capacitor), 8T1C (i.e., including 8 transistors and 1 storage capacitor), or 8T2C (i.e., including 8 transistors and 2 storage capacitors). Figure 30 FIG. is an equivalent circuit diagram of an 8T1C pixel driving circuit provided by at least one embodiment of the present disclosure. Hereinafter, taking the 8T1C pixel driving circuit as an example, the connection relationship and functions of the transistors and signal lines in the pixel driving circuit will be described.

[0150] For example, as Figure 30 shown, the pixel driving circuit may include 8 transistors (the first transistor T1 to the eighth transistor T8), 1 storage capacitor C, and multiple signal lines (such as data line Da, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first reset voltage line INIT1, second reset voltage line INIT2, second power supply line VDD, first power supply line VSS, and light emission control signal line Em, etc.).

[0151] For example, the gate of the first transistor T1 is connected to the reset control signal line Reset, the first pole of the first transistor T1 is connected to the second reset voltage line INIT2, and the second pole of the first transistor T1 is connected to the fifth node N5.

[0152] For example, the gate of the second transistor T2 is connected to the first scan signal line Gate, the first pole of the second transistor T2 is connected to the fifth node N5, and the second pole of the second transistor T2 is connected to the third node N3.

[0153] For example, the gate of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3.

[0154] For example, the gate of the fourth transistor T4 is connected to the first scan signal line Gate, the first pole of the fourth transistor T4 is connected to the data line Da, and the second pole of the fourth transistor T4 is connected to the second node N2.

[0155] For example, the gate of the fifth transistor T5 is connected to the light emission control signal line Em, the first pole of the fifth transistor T5 is connected to the second power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2.

[0156] For example, the gate of the sixth transistor T6 is connected to the light emission control signal line Em, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode 1041 of the light emitting device EM).

[0157] For example, the gate of the seventh transistor T7 is connected to the first scan signal line Gate or the reset control signal line Reset, the first pole of the seventh transistor T7 is connected to the first reset voltage line INIT1, and the second pole of the seventh transistor T7 is connected to the fourth node N4.

[0158] For example, the gate of the eighth transistor T8 is connected to the second scan signal line GateN, the first pole of the eighth transistor T8 is connected to the fifth node N5, and the second pole of the eighth transistor T8 is connected to the first node N1.

[0159] For example, the first capacitive electrode C1 of the storage capacitor C is connected to the second power supply line VDD, and the second capacitive electrode C2 of the storage capacitor C is connected to the first node N1.

[0160] For example, the first transistor T1 to the seventh transistor T7 can be N-type thin film transistors, and the eighth transistor T8 can be a P-type thin film transistor; alternatively, the first transistor T1 to the seventh transistor T7 can be P-type thin film transistors, and the eighth transistor T8 can be an N-type thin film transistor.

[0161] For example, the first transistor T1 to the seventh transistor T7 can be low temperature poly-silicon (LTPS) thin film transistors (TFTs), and the eighth transistor T8 can be an indium gallium zinc oxide (IGZO) thin film transistor.

[0162] In the above embodiments, compared with the low temperature poly-silicon thin film transistor, the indium gallium zinc oxide thin film transistor generates less leakage current. Therefore, setting the eighth transistor T8 as an indium gallium zinc oxide thin film transistor can significantly reduce the generation of leakage current, thereby improving the problem of low-frequency and low-brightness flicker of the display panel. In addition, the first transistor T1 and the second transistor T2 do not need to be set as indium gallium zinc oxide thin film transistors. Since the size of the low temperature poly-silicon thin film transistor is generally smaller than that of the indium gallium zinc oxide thin film transistor, the occupied space of the pixel driving circuit of the embodiment of the present disclosure is relatively small, which is beneficial to improving the resolution of the display panel.

[0163] The above pixel driving circuit provided by the embodiments of the present disclosure combines the good switching characteristics of LTPS-TFT and the low leakage characteristics of Oxide-TFT, and can achieve low-frequency driving (1 Hz to 60 Hz), greatly reducing the power consumption of the display screen.

[0164] In some embodiments, the second electrode 1043 of the light-emitting device EM is connected to the first power supply line VSS, the signal of the first power supply line VSS is a continuously provided low-level signal, and the signal of the second power supply line VDD is a continuously provided high-level signal. The signal of the first scan signal line Gate is the scan signal in the pixel driving circuit of the current display row, and the signal of the reset control signal line Reset is the scan signal in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n - 1). The signal of the reset control signal line Reset of the current display row and the signal of the first scan signal line Gate in the pixel driving circuit of the previous display row can be the same signal to reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0165] For example, Figure 31 is Figure 30 the timing diagram of the pixel driving circuit in Figure 31 As shown, in some embodiments, the working process of the pixel driving circuit can be divided into the following several stages.

[0166] In the first stage t1, called the reset stage, the signals of the first scan signal line Gate, the reset control signal line Reset, the second scan signal line GateN, and the light-emitting control signal line Em are all high-level signals, and the signal of the reset control signal line Reset is a low-level signal. The high-level signal of the light-emitting control signal line Em turns off the fifth transistor T5 and the sixth transistor T6. The high-level signal of the second scan signal line GateN turns on the eighth transistor T8. The low-level signal of the reset control signal line Reset turns on the first transistor T1. Therefore, the voltage of the first node N1 is reset to the second reset voltage Vinit2 provided by the second reset voltage line INIT2, and then the electrical position of the reset control signal line Reset is raised, and the first transistor T1 is turned off. Since the fifth transistor T5 and the sixth transistor T6 are turned off, the light-emitting device EL does not emit light in this stage.

[0167] The second stage t2, called the data writing stage, the signal of the first scanning signal line Gate is a low-level signal, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, the data line Da outputs a data voltage, and the voltage of the fourth node N4 is reset to the first reset voltage Vinit1 provided by the first reset voltage line INIT1, completing the initialization. In this stage, since the first node N1 is at a low level, the third transistor T3 is turned on. The conduction of the fourth transistor T4 and the second transistor T2 causes the data voltage output by the data line Da to pass through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the eighth transistor T8 to be provided to the first node N1, and the sum of the data voltage output by the data line Da and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The signal of the light emission control signal line Em is a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off to ensure that the light emitting device EM does not emit light.

[0168] The third stage t3, called the light emission stage, the signals of the first scanning signal line Gate and the reset control signal line Reset are high-level signals, and the signals of the light emission control signal line EM and the second scanning signal line GateN are both low-level signals. The high-level signal of the reset control signal line Reset turns off the seventh transistor T7, and the low-level signal of the light emission control signal line Em turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the second power supply line VDD provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light emitting device EM through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light emitting device EM to emit light.

[0169] For example, Figure 25 and Figure 26 the reset voltage line Vint in the embodiments of can be the above-mentioned first reset voltage line INIT1 and / or the second reset voltage line INIT2 to achieve the corresponding functions.

[0170] There are also the following points to note:

[0171] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0172] (2) For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is enlarged or reduced, that is, these drawings are not drawn according to the actual ratio. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element or there can be an intermediate element.

[0173] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0174] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized in that, It has a plurality of sub-pixels arranged in multiple rows and columns, and includes: A substrate, including a display area and a non-display area, wherein the plurality of sub-pixels are disposed in the display area, A plurality of data lines, disposed on the substrate and at least located in the display area, extending in a first direction, configured to provide data signals to the plurality of sub-pixels, and A plurality of first data line leads, disposed on the substrate and extending from the display area to the non-display area in the first direction, Wherein at least part of the plurality of data lines are electrically connected to the plurality of first data line leads respectively to obtain data signals from the non-display area, At least one of the plurality of first data line leads includes a first lead portion and a second lead portion, the first lead portion is located in a first conductive layer, the second lead portion is located in a second conductive layer, and the first lead portion and the second lead portion are electrically connected through a via hole.

2. The display substrate according to claim 1, wherein In a direction parallel to the substrate, one or two first data line leads are disposed between adjacent two data lines.

3. The display substrate according to claim 1, wherein The second conductive layer is located on a side of the first conductive layer away from the substrate, and the plurality of data lines are located in the second conductive layer.

4. The display substrate according to any one of claims 1-3, characterized in that, There is a first insulating layer between the second conductive layer and the first conductive layer. The via hole includes a first via hole and a second via hole penetrating through the first insulating layer, and two ends of the first lead portion are respectively connected to the second lead portion through the first via hole and the second via hole.

5. The display substrate according to claim 4, characterized in that, For an adjacent first data line lead and a data line, there is also a third via hole in the first insulating layer overlapping with the data line in a direction perpendicular to the substrate, In the first direction, the third via hole is located between the first via hole and the second via hole.

6. The display substrate according to claim 5, wherein Two data lines and two first data line leads are disposed between adjacent two columns of sub-pixels, The two data lines are located between the two first data line leads, or The two first data line leads are located between the two data lines.

7. The display substrate according to claim 6, wherein The two data lines are symmetrically arranged, and the third via holes corresponding to the two data lines are symmetrically arranged; The two first data line leads are symmetrically arranged, and the first via holes and the second via holes corresponding to the two first data line leads are symmetrically arranged.

8. The display substrate according to claim 4, wherein Two data lines and two first data line leads are disposed between adjacent two columns of sub-pixels, and the two first data line leads are located between the two data lines; In the first direction, the first via holes and the second via holes corresponding to the two first data line leads are alternately arranged at intervals.

9. The display substrate according to claim 6 or 8, characterized in that, It further includes: A second data line lead, located in the first conductive layer, extending in a second direction different from the first direction, Wherein at least one of the two first data line leads is connected to the second data line lead through a first jumper wire, the first jumper wire is located in the first conductive layer, and at least partially overlaps with the at least one first data line lead in a direction perpendicular to the substrate.

10. The display substrate according to claim 8, wherein The second lead portions of the two first data line leads respectively include bent portions bent in a direction approaching each other.

11. The display substrate according to claim 4, wherein Two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines; In the first direction, the first vias and the second vias corresponding to the two first data line leads are located on the same straight line.

12. The display substrate according to any one of claims 1-3, characterized in that, In a direction parallel to the substrate, two data lines are provided between two adjacent columns of sub-pixels, and a first data line lead is provided between the two data lines. The display substrate further includes: a second data line lead, located in the first conductive layer and extending in a second direction different from the first direction. The first data line lead is connected to the second data line lead through a second jumper wire. The second jumper wire is located in the first conductive layer, and in a direction perpendicular to the substrate, the second jumper wire at least partially overlaps with one of the two data lines.

13. The display substrate according to any one of claims 1-3, wherein In a direction parallel to the substrate, two data lines are provided between two adjacent columns of sub-pixels, and two first data line leads are provided between the two data lines; or two first data line leads are provided between two adjacent columns of sub-pixels, and two data lines are provided between the two first data line leads. The display substrate further includes: a plurality of second data line leads, located in the first conductive layer and extending in a second direction different from the first direction. The first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads, and the first second data line lead is connected to the first first data line lead that is at least one sub-pixel away from the first data line. The second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads, and the second second data line lead is connected to the second first data line lead that is at least one sub-pixel away from the second data line.

14. The display substrate according to claim 13, wherein The first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third jumper wire. In a direction perpendicular to the substrate, the first data line at least partially overlaps with the third jumper wire. The second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads through a fourth jumper wire. In a direction perpendicular to the substrate, the second data line at least partially overlaps with the fourth jumper wire.

15. The display substrate according to claim 13, wherein The first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third jumper wire. In a direction perpendicular to the substrate, the third jumper wire at least partially overlaps with the first data line lead adjacent to the first data line. The second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads through a fourth jumper wire. In a direction perpendicular to the substrate, the fourth jumper wire at least partially overlaps with the first data line lead adjacent to the second data line.

16. The display substrate according to claim 13, wherein The first second data line lead is connected to a first first data line lead that is at least one sub-pixel away from the first data line through a fifth jumper wire. In a direction perpendicular to the substrate, the fifth jumper wire and the data line adjacent to the first first data line lead at least partially overlap. The second second data line lead is connected to a second first data line lead that is at least one sub-pixel away from the second data line through a sixth jumper wire. In a direction perpendicular to the substrate, the sixth jumper wire and the data line adjacent to the second first data line lead at least partially overlap.

17. The display substrate according to claim 13, wherein The first second data line lead is directly connected to a first first data line lead that is at least one sub-pixel away from the first data line through a fourth via hole. The second second data line lead is directly connected to a second first data line lead that is at least one sub-pixel away from the second data line through a fifth via hole.

18. The display substrate according to claim 13, wherein The first data line, the first second data line lead, and the first first data line lead form a first data line network. The second data line, the second second data line lead, and the second first data line lead form a second data line network. The second data line network is located outside the first data line network.

19. The display substrate according to claim 18, wherein Two first data line leads located between the two data lines include a disconnected portion that is disconnected from the first data line network and the second data line network. The display substrate further includes a first power supply line, and the disconnected portion is connected to the first power supply line.

20. The display substrate according to claim 19, wherein, In a direction perpendicular to the substrate, the disconnected position overlaps with the first conductive layer or the second conductive layer.

21. The display substrate according to claim 19, wherein Each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device. The light-emitting device includes a first electrode connected to the pixel driving circuit, a second electrode spaced apart from the first electrode, and a light-emitting layer between the first electrode and the second electrode. The second electrode is electrically connected to the first power supply line.

22. The display substrate according to claim 21, wherein, The pixel driving circuit includes a transistor. The transistor includes a gate and a source-drain electrode. The source-drain electrode is electrically connected to the first electrode through a connection electrode. The source-drain electrode is located in the first conductive layer, and the connection electrode is located in the second conductive layer.

23. The display substrate according to any one of claims 1-3, characterized in that, In a direction parallel to the substrate, two data lines are provided between adjacent first column sub-pixels and second column sub-pixels. A reset voltage line is provided between the two data lines. Two first data line leads are provided between adjacent second column sub-pixels and third column sub-pixels.

24. The display substrate according to claim 23, wherein, The data line adjacent to the second column sub-pixels and the first data line lead are electrically connected through a first second data line lead. The data line adjacent to the first column sub-pixels and the first data line lead adjacent to the third column sub-pixels are electrically connected through a second second data line lead.

25. The display substrate according to claim 24, wherein, Two second power supply lines are further provided between adjacent second column sub-pixels and third column sub-pixels. The two first data line leads are located between the two second power supply lines.

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