Scanning driving circuit and display device

Abstract

The utility model discloses a scanning drive circuit and a display device. The scanning driving circuit comprises a plurality of shift registers which are arranged in a cascading manner; the shift register comprises a driving control module and a scanning output module. The driving control module is used for controlling the potentials of the first output end and the second output end of the driving control module according to the input signal; and the scanning output module is connected with the first output end and the second output end and is connected with a frequency switching control signal, the scanning output module is used for outputting a scanning signal, and the frequency switching control signal is used for controlling the frequency of a conduction pulse in the scanning signal output by the scanning output module so as to realize display of partition frequency division.

Description

[0001] This application claims priority to patent application number 202310935856.7 (the filing date of the prior application is July 27, 2023, and the invention name is scanning drive circuit, display device and driving method thereof) Technical Field

[0002] The utility model relates to the technical field of display, in particular to a scanning drive circuit and a display device. Background Art

[0003] With the development of display technology, the application scenarios of display devices are increasing, and users' display requirements for display devices are becoming more and more diverse. Based on the release of products such as foldable phones and foldable laptops, the application scenarios of display devices have been further expanded. In response to users' demand for simultaneous display of multiple applications on terminal products, some interfaces in the display screen (such as game interfaces) need to be displayed at high frequency to ensure the smoothness of the picture, while some interfaces can meet the display requirements at low frequency. This part is expected to use low-frequency display to reduce product power consumption. However, in the prior art, there is no good solution to achieve zone-by-zone frequency division. Utility Model Content

[0004] The utility model provides a scanning driving circuit and a display device to realize the zone-by-zone and frequency-by-frequency display of a display panel.

[0005] In a first aspect, an embodiment of the utility model provides a scan driving circuit, comprising: a plurality of shift registers arranged in cascade;

[0006] The nth stage shift register of the plurality of shift registers comprises:

[0007] A driving control module, used for controlling the potential of the first output terminal and the second output terminal of the driving control module according to the input signal connected to the shift register;

[0008] A scanning output module, the scanning output module comprising:

[0009] A transmission control unit, comprising an internal node and a third connection terminal, wherein the internal node is used to control whether the second output terminal and the third connection terminal are connected;

[0010] A scan output unit, wherein the first control end of the scan output unit is connected to the third connection end, and the second control end of the scan output unit is connected to the first output end; the scan output unit is used to output a scan signal according to the potentials of the first control end and the second control end; wherein n is an integer greater than 0;

[0011] A voltage stabilizing unit, the first end of the voltage stabilizing unit is connected to the internal node of the transmission control unit, and the voltage stabilizing unit is used to store the potential of the internal node of the transmission control unit.

[0012] Optionally, the transmission control unit further includes a first connection end and a second connection end. The first connection end of the transmission control unit is connected to the second output end, and the second connection end of the transmission control unit accesses a frequency switching control signal. The transmission control unit is used to control the potential of the third connection end of the transmission control unit according to the potentials of the first connection end and the second connection end.

[0013] The frequency switching control signal is used to control the frequency at which conduction pulses appear in the scan signal output by the scan output module.

[0014] Optionally, the second end of the voltage stabilizing unit is connected to the output end of the scan output unit, and the voltage stabilizing unit is used to transmit a first potential signal to the output end of the scan output unit when the scan signal outputs a non-conduction pulse. Wherein, the potential corresponding to the conduction pulse of the scan signal is a second potential signal, and the first potential signal and the second potential signal are high and low level signals with respect to each other.

[0015] Optionally, the nth stage shift register among the multiple shift registers further includes: a stage transmission output module, which is respectively connected to the first output end and the second output end, and is used to output a stage transmission signal in response to the potentials of the first output end and the second output end. The stage transmission signal serves as the input signal of the (n + s)th stage shift register.

[0016] Wherein, s is an integer greater than 0.

[0017] Preferably, s = 1.

[0018] Optionally, the conduction pulse output by the scan output unit is a high potential.

[0019] The transmission control unit includes: a first transistor and a second transistor. The gate of the first transistor is connected to the output end of the stage transmission output module, the first pole of the first transistor accesses the frequency switching control signal, and the second pole of the first transistor is connected to the gate of the second transistor. The first pole of the second transistor is connected to the first connection end, the first connection end is connected to the second output end, and the second pole of the second transistor is connected to the third connection end.

[0020] The scanning output unit includes: a third transistor, a fourth transistor, and a first capacitor; the gate of the third transistor is connected to the first output terminal, the first pole of the third transistor accesses a first potential signal, and the second pole of the third transistor is connected to the output terminal of the scanning output unit; the gate of the fourth transistor is connected to the third connection terminal, the first pole of the fourth transistor accesses a second potential signal, and the second pole of the fourth transistor is connected to the output terminal of the scanning output unit; the first capacitor is connected between the gate and the first pole of the fourth transistor;

[0021] The voltage stabilizing unit includes: a third capacitor and a twelfth transistor, the first end of the third capacitor accesses a fixed potential signal, and the second end of the third capacitor is connected to the second pole of the first transistor;

[0022] The gate of the twelfth transistor is connected to the second pole of the first transistor, the first pole of the twelfth transistor accesses the first potential signal, and the second pole of the twelfth transistor is connected to the output terminal of the scanning output unit; the twelfth transistor has a channel type different from that of the second transistor;

[0023] Preferably, the transmission control unit further includes a fifth transistor; the gate of the fifth transistor is connected to the first output terminal, the first pole of the fifth transistor accesses the second potential signal, and the second pole of the fifth transistor is connected to the third connection terminal.

[0024] Optionally, the drive control module includes:

[0025] A first input unit, connected to the first output terminal, for responding to a first clock signal and transmitting the input signal to the first output terminal;

[0026] A first control unit, for responding to the first clock signal and transmitting the first potential signal to the output terminal of the first control unit;

[0027] A second control unit, connected between the output terminal of the first control unit and the second output terminal, for controlling the potential of the second output terminal according to a second clock signal and the potential of the output terminal of the first control unit;

[0028] A first node control unit, respectively connected to the first output terminal and the output terminal of the first control unit, for controlling the potential of the output terminal of the first control unit according to the potential of the first output terminal;

[0029] A second node control unit, respectively connected to the first output terminal and the output terminal of the first control unit, for controlling the potential of the first output terminal according to the potential of the output terminal of the first control unit;

[0030] A third node control unit, which is respectively connected to the first output end and the second output end, is configured to control the potential of the second output end according to the potential of the first output end;

[0031] The stage transmission output module includes:

[0032] A first output unit, which is connected to the first output end, is configured to respond to the potential of the first output end and transmit the first potential signal to the output end of the stage transmission output module;

[0033] A second output unit, which is connected to the second output end, is configured to respond to the potential of the second output end and transmit the second potential signal to the output end of the stage transmission output module.

[0034] Optionally, each of the shift registers is connected to a row of pixel circuits;

[0035] Each of the frequency-cutting control signals controls the frequency at which the conduction pulse appears in the scan signal output by the scan output unit connected to the pixel circuit above the display partition position to be different from the frequency at which the conduction pulse appears in the scan signal output by the scan output unit connected to the pixel circuit below the display partition position according to the display partition position of the display panel in the column direction.

[0036] Optionally, each transmission control unit accesses the same frequency-cutting control signal;

[0037] The frequency-cutting control signal undergoes a potential jump in at least some display frames, so that the frequencies at which the conduction pulse appears in the scan signals output by at least two scan output units are different;

[0038] Preferably, each of the scan output units is respectively connected to the same functional module of each row of pixel circuits. In a second aspect, an embodiment of the present invention provides a scan driving circuit, including: a plurality of shift registers cascaded;

[0039] The nth-stage shift register among the plurality of shift registers includes:

[0040] A driving control module, which is configured to control the potentials of the first output end and the second output end of the driving control module according to the input signal accessed by the shift register;

[0041] At least two scan output modules, the scan output modules are connected to the first output end and the second output end and access a frequency-cutting control signal, and the scan output modules are configured to output scan signals; wherein, different scan output modules access different frequency-cutting control signals, and different frequency-cutting control signals are respectively used to control the frequency at which the conduction pulse appears in the scan signals output by the corresponding scan output modules, where n is an integer greater than 0.

[0042] Optionally, the n-th stage shift register among the multiple shift registers further includes: a stage transfer output module, respectively connected to the first output end and the second output end, for outputting a stage transfer signal in response to the potentials of the first output end and the second output end; the stage transfer signal serves as an input signal of the (n + s)-th stage shift register;

[0043] wherein, s is an integer greater than 0;

[0044] Preferably, s = 1.

[0045] Optionally, at least two of the scan output modules in the same stage of the shift register are respectively connected to at least two rows of pixel circuits, and some of the scan output modules in at least two stages of the shift register are connected to the same row of pixel circuits;

[0046] Each of the frequency division control signals controls the frequency at which the conduction pulse appears in the scan signal output by the scan output module connected to the pixel circuit above the display partition position to be different from the frequency at which the conduction pulse appears in the scan signal output by the scan output module connected to the pixel circuit below the display partition position according to the display partition position of the display panel in the column direction.

[0047] Optionally, one scan output group in the scan driving circuit includes one scan output module in each stage of the shift register, and different scan output modules in the same stage of the shift register belong to different scan output groups; each of the scan output modules in the same scan output group is connected to the same frequency division control signal;

[0048] wherein, for any one of the scan output groups, the frequency division control signal undergoes a potential jump in at least some display frames, so that the frequencies at which the conduction pulse appears in the scan signals output by at least two scan output modules in the scan output group are different;

[0049] Preferably, each of the scan output modules in the same scan output group is respectively connected to the same functional module of each row of pixel circuits; multiple scan output modules connected to different functional modules in the same pixel circuit belong to different scan output groups.

[0050] Optionally, one stage of the shift register includes two scan output modules, namely a first scan output module and a second scan output module;

[0051] The output terminal of the first scan output module of the nth stage is connected to the pixel circuit of the nth row, and the conduction pulse output by the first scan output module of the nth stage acts on the first stage of the pixel circuit of the nth row; the output terminal of the second scan output module of the (n + m)th stage is connected to the pixel circuit of the nth row, and the conduction pulse output by the second scan output module of the (n + m)th stage acts on the second stage of the pixel circuit of the nth row; wherein, for the same pixel circuit, in the same display frame, the first stage occurs before the second stage, and m is an integer greater than 0;

[0052] Preferably, the first stage is a reset stage, and the second stage is a data writing stage;

[0053] Preferably, m = 1.

[0054] Preferably, in one frame display, when the scan signals output by the first scan output modules from the ith stage to the (i + k)th stage have the conduction pulse, the scan signals output by the second scan output modules from the (i + m)th stage to the (i + m + k)th stage have the conduction pulse; wherein, both i and k are integers greater than 0.

[0055] Preferably, the frequency division control signal accessed by the first scan output module is defined as the first frequency division control signal, and the frequency division control signal accessed by the second scan output module is defined as the second frequency division control signal;

[0056] When the display partition position is between the pixel circuit of the ith row and the pixel circuit of the (i + 1)th row, in some display frames, the first frequency division control signal undergoes a potential jump before the conduction pulse is output by the first scan output module of the ith stage, so that the frequency of the conduction pulse appearing in the scan signal output by the first scan output module of the ith stage is different from the frequency of the conduction pulse appearing in the scan signal output by the first scan output module of the (i + 1)th stage, realizing partitioned frequency division display of the display panel in the column direction; i is an integer greater than 0;

[0057] And, corresponding to the display frame in which the first frequency division control signal undergoes the potential jump, the second frequency division control signal undergoes a potential jump before the conduction pulse is output by the second scan output module of the (i + m)th stage, so that the frequency of the conduction pulse appearing in the scan signal output by the second scan output module connected to each row of pixel circuits is the same as the frequency of the conduction pulse appearing in the scan signal output by the first scan output module connected to the corresponding row of pixel circuits.

[0058] Optionally, the scan output module includes:

[0059] A transmission control unit, a first connection end of the transmission control unit is connected to one of the first output end and the second output end, and a second connection end of the transmission control unit accesses the frequency switching control signal; the transmission control unit is configured to control a potential of a third connection end of the transmission control unit according to potentials of the first connection end and the second connection end;

[0060] A scan output unit, a first control end of the scan output unit is connected to the third connection end, and a second control end of the scan output unit is connected to the other of the first output end and the second output end; the scan output unit is configured to output the scan signal according to potentials of the first control end and the second control end.

[0061] Optionally, the conduction pulse output by the scan output module is a high potential;

[0062] The transmission control unit includes: a first transistor and a second transistor; a gate of the first transistor is connected to an output end of the stage transmission output module, a first pole of the first transistor accesses the frequency switching control signal, and a second pole of the first transistor is connected to a gate of the second transistor; a first pole of the second transistor is connected to the first connection end, the first connection end is connected to the second output end, and a second pole of the second transistor is connected to the third connection end;

[0063] The scan output unit includes: a third transistor, a fourth transistor and a first capacitor; a gate of the third transistor is connected to the first output end, a first pole of the third transistor accesses a first potential signal, and a second pole of the third transistor is connected to an output end of the scan output unit; a gate of the fourth transistor is connected to the third connection end, a first pole of the fourth transistor accesses a second potential signal, and a second pole of the fourth transistor is connected to the output end of the scan output unit; the first capacitor is connected between the gate and the first pole of the fourth transistor;

[0064] Preferably, the transmission control unit further includes a fifth transistor; a gate of the fifth transistor is connected to the first output end, a first pole of the fifth transistor accesses the second potential signal, and a second pole of the fifth transistor is connected to the third connection end;

[0065] Preferably, at least one of the at least two scan output modules further includes: a third capacitor; a first end of the third capacitor accesses a fixed potential signal, and a second end of the third capacitor is connected to the second pole of the first transistor;

[0066] Preferably, at least one of the at least two scan output modules further includes: a twelfth transistor; a gate of the twelfth transistor is connected to a second pole of the first transistor, a first pole of the twelfth transistor accesses the first potential signal, and a second pole of the twelfth transistor is connected to an output end of the scan output unit; the twelfth transistor and the second transistor have different channel types.

[0067] Preferably, the drive control module includes:

[0068] A first input unit, connected to the first output end, for responding to a first clock signal and transmitting the input signal to the first output end;

[0069] A first control unit, for responding to the first clock signal and transmitting the first potential signal to an output end of the first control unit;

[0070] A second control unit, connected between the output end of the first control unit and the second output end, for controlling the potential of the second output end according to a second clock signal and the potential of the output end of the first control unit;

[0071] A first node control unit, respectively connected to the first output end and the output end of the first control unit, for controlling the potential of the output end of the first control unit according to the potential of the first output end;

[0072] A second node control unit, respectively connected to the first output end and the output end of the first control unit, for controlling the potential of the first output end according to the potential of the output end of the first control unit;

[0073] A third node control unit, respectively connected to the first output end and the second output end, for controlling the potential of the second output end according to the potential of the first output end;

[0074] The stage transmission output module includes:

[0075] A first output unit, connected to the first output end, for responding to the potential of the first output end and transmitting the first potential signal to an output end of the stage transmission output module;

[0076] A second output unit, connected to the second output end, for responding to the potential of the second output end and transmitting the second potential signal to an output end of the stage transmission output module.

[0077] Optionally, the conduction pulse output by the scan output module is at a low potential;

[0078] The transmission control unit includes: a sixth transistor; a gate of the sixth transistor is connected to the frequency switching control signal, a first pole of the sixth transistor is connected to the first connection end, the first connection end is connected to the first output end, and a second pole of the sixth transistor is connected to the third connection end;

[0079] The scan output unit includes: a seventh transistor, an eighth transistor, and a second capacitor; a gate of the seventh transistor is connected to the third connection end, a first pole of the seventh transistor is connected to a third clock signal, and a second pole of the seventh transistor is connected to an output end of the scan output unit; the second capacitor is connected between the gate and the second pole of the seventh transistor; a gate of the eighth transistor is connected to the second output end, a first pole of the eighth transistor is connected to a second potential signal, and a second pole of the eighth transistor is connected to the output end of the scan output unit;

[0080] Preferably, the transmission control unit further includes: a ninth transistor; a gate of the ninth transistor is connected to a first switch signal, a first pole of the ninth transistor is connected to the second potential signal, and a second pole of the ninth transistor is connected to the third connection end;

[0081] Preferably, the transmission control unit further includes: a tenth transistor; a gate of the tenth transistor is connected to a second switch signal, a first pole of the tenth transistor is connected to a first potential signal, and a second pole of the tenth transistor is connected to the third connection end;

[0082] Preferably, the transmission control unit further includes: an eleventh transistor; the eleventh transistor is connected between the second pole of the sixth transistor and the third connection end, and a gate of the eleventh transistor is connected to the first potential signal.

[0083] Preferably, the drive control module includes:

[0084] A second input unit, connected to the first output end, for responding to a fourth clock signal and transmitting the input signal to the first output end;

[0085] A third control unit, connected to the second output end, for responding to the fourth clock signal and transmitting the first potential signal to the second output end;

[0086] A fourth node control unit, respectively connected to the first output end and the second output end, for responding to a potential of the first output end and transmitting the fourth clock signal to the second output end;

[0087] The fifth node control unit, which is respectively connected to the first output terminal and the second output terminal, is configured to respond to the third clock signal and the potential of the second output terminal, and transmit the second potential signal to the first output terminal;

[0088] The stage transmission output module includes:

[0089] A third output unit, connected to the first output terminal, is configured to respond to the potential of the first output terminal and transmit the third clock signal to the output terminal of the stage transmission output module;

[0090] A fourth output unit, connected to the second output terminal, is configured to respond to the potential of the second output terminal and transmit the second potential signal to the output terminal of the stage transmission output module.

[0091] In a third aspect, an embodiment of the present invention further provides a display device, including: a pixel circuit and the scan driving circuit provided in any embodiment of the present invention.

[0092] Preferably, each stage of the shift register includes two of the scan output modules;

[0093] The pixel circuit includes: a driving module, a threshold compensation module, and a gate reset module; the gate reset module is connected to the control end of the driving module, and the threshold compensation module is connected between the control end and the output end of the driving module;

[0094] One of the scan output modules of the shift register is connected to the control end of the gate reset module in one row of the pixel circuit, and the other scan output module of the shift register is connected to the control end of the threshold compensation module in another row of the pixel circuit;

[0095] Preferably, the pixel circuit further includes a data writing module and an anode reset module, the data writing module is connected to the input end of the driving module; the anode reset module is connected to the anode of the light emitting device; the data writing module, the anode reset module, the gate reset module, and the threshold compensation module include transistors of the same channel type; the shift register further includes a stage transmission output module, and the stage transmission output module is further connected to the control end of the data writing module and / or the control end of the anode reset module;

[0096] Preferably, the two scan output modules include a first scan output module and a second scan output module; the output end of the first scan output module of the nth stage is connected to the control end of the gate reset module in the nth row of the pixel circuit, and the output end of the second scan output module of the (n + m)th stage is connected to the control end of the threshold compensation module in the nth row of the pixel circuit; both n and m are integers greater than 0;

[0097] Preferably, m = 1.

[0098] The scanning driving circuit provided by the embodiment of the present invention includes a plurality of cascaded shift registers 30. Each stage of the shift register 30 includes: a driving control module 11 and a scanning output module 13. By controlling the potential jump of the frequency-cutting control signal accessed in the shift register connected to at least one row of pixel circuits, the frequency of the conduction pulse in the scanning signal OUT changes, realizing the partition frequency division display of the display panel in the column direction.

[0099] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0101] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0102] Figure 2 is a schematic structural diagram of a shift register provided by an embodiment of the present invention;

[0103] Figure 3 is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0104] Figure 4 is a driving timing diagram of a shift register provided by an embodiment of the present invention;

[0105] Figure 5 is a driving timing diagram of another shift register provided by an embodiment of the present invention;

[0106] Figure 6 is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0107] Figure 7 is a schematic structural diagram of an existing display panel;

[0108] Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0109] Figure 9It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0110] Figure 10 It is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention;

[0111] Figure 11 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0112] Figure 12 It is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0113] Figure 13 It is a schematic diagram of the driving timing of another shift register provided by an embodiment of the present invention;

[0114] Figure 14 It is a schematic structural diagram of yet another shift register provided by an embodiment of the present invention;

[0115] Figure 15 It is a schematic diagram of the driving timing of yet another display panel provided by an embodiment of the present invention;

[0116] Figure 16 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0117] Figure 17 It is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present invention;

[0118] Figure 18 It is a schematic structural diagram of yet another shift register provided by an embodiment of the present invention;

[0119] Figure 19 It is a schematic structural diagram of yet another shift register provided by an embodiment of the present invention;

[0120] Figure 20 It is a schematic diagram of the driving timing of another shift register provided by an embodiment of the present invention;

[0121] Figure 21 It is a schematic diagram of the driving timing of another display panel provided by an embodiment of the present invention;

[0122] Figure 22 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0123] Figure 23 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0124] To enable those skilled in the art to better understand the solution of the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0125] It should be noted that the terms "first", "second", etc. in the description and claims of the present utility model and the above-mentioned accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0126] The embodiment of the present utility model provides a scan driving circuit to enable a display device to support the function of displaying in different frequencies in different regions of a screen, while ensuring the stability of the output signal. Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present utility model, Figure 2 is a schematic structural diagram of a shift register provided by an embodiment of the present utility model. Refer to Figure 1 and Figure 2 , the scan driving circuit includes: a plurality of cascaded shift registers 30;

[0127] The nth shift register among the plurality of shift registers 30 includes:

[0128] A driving control module 11, configured to control the potentials of the first output terminal N1 and the second output terminal N2 of the driving control module 11 according to the input signal IN accessed by the shift register 30;

[0129] A scan output module 13, and the scan output module 13 includes:

[0130] A transmission control unit 1301, including an internal node and a third connection terminal, and the internal node is used to control whether the second output terminal and the third connection terminal are conducted. Optionally, the transmission control unit 1301 further includes a first connection terminal and a second connection terminal. The first connection terminal of the transmission control unit 1301 is connected to the second output terminal N2, the second connection terminal of the transmission control unit 1301 accesses a frequency switching control signal SW; the transmission control unit 1301 is configured to control the potential of the third connection terminal N3 of the transmission control unit 1301 according to the potentials of the first connection terminal and the second connection terminal;

[0131] A scan output unit 1302, a first control terminal of the scan output unit 1302 is connected to a third connection terminal N3, and a second control terminal of the scan output unit 1302 is connected to a first output terminal N1; the scan output unit 1302 is configured to output a scan signal according to potentials of the first control terminal and the second control terminal; a frequency switching control signal SW is used to control a frequency at which conduction pulses appear in the scan signal output by the scan output module 1302, where n is an integer greater than 0;

[0132] A voltage stabilizing unit 1303, a first end of the voltage stabilizing unit 1303 is connected to an internal node N4 of the transmission control unit 1301, and the voltage stabilizing unit 1303 is configured to store the potential of the internal node N4 of the transmission control unit 1301;

[0133] A second end of the voltage stabilizing unit 1303 is connected to an output terminal of the scan output unit 1302, and the voltage stabilizing unit 1303 is configured to transmit a first potential signal VGL to the output terminal of the scan output unit 1302 when the scan signal outputs a non-conduction pulse; where a potential corresponding to the conduction pulse of the scan signal is a second potential signal VGH, and the first potential signal VGL and the second potential signal VGH are high and low level signals with respect to each other.

[0134] In this embodiment, the same functional modules in different row pixel circuits 02 are cascade-connected between shift registers. Taking the pixel circuit 02 including a data writing module as an example, one shift register is connected to the data writing modules in one row of pixel circuits 02, and different shift registers 30 are cascade-connected. The shift register realizes the frequency at which conduction pulses appear in the scan signal output by the scan output module 1302 through the frequency switching control signal SW, thereby realizing zoned frequency division display.

[0135] Exemplarily, the scan output module 13 selects whether to perform a shift output of an input signal IN under the common control of potentials of the first output terminal N1 and the second output terminal N2, and the frequency switching control signal SW. Exemplarily, the frequency switching control signal SW can be used to control whether the potential of the second output terminal N2 can be transmitted to the third connection terminal N3, so as to control whether the scan output unit 1302 can output a conduction potential, so as to control the frequency at which conduction pulses appear in the scan signal. The conduction pulse can be understood as a pulse composed of potentials capable of controlling the conduction of a functional module connected to the scan signal. For example, when the functional module includes an N-type transistor, the conduction pulse is a high potential pulse.

[0136] The scan output module 13 may include a transmission control unit 1301 and a scan output unit 1302. In addition to including two control terminals, the scan output unit 1302 may further include a conduction potential input terminal, a cut-off potential input terminal, and an output terminal. The potential of the first control terminal is used to control whether the conduction potential input terminal is connected to the output terminal, and the potential of the second control terminal is used to control whether the cut-off potential input terminal is connected to the output terminal, so that the unit can control the output signal of its output terminal to be a conduction potential or a cut-off potential based on the potentials of its two control terminals. Among them, the conduction potential is the second potential signal VGH, and the cut-off potential is the first potential signal VGL.

[0137] The transmission control unit 1301 can control the on / off of its internal circuit based on the frequency switching control signal SW, so as to control whether the first control terminal of the scan driving unit 1302 can be connected to the driving control module 11 through the transmission control unit 1301, so as to control whether the scan output unit 1302 can output a conduction potential, thereby controlling the frequency of the conduction pulse in the scan signal. Specifically, the transmission control unit 1301 can control the frequency of the conduction pulse in the scan signal output by the scan output unit 1302 by controlling the potential of its third connection terminal N3.

[0138] The potential of the internal node of the transmission control unit 1301 controls whether the third connection terminal N3 is connected to the second output terminal N2. The voltage stabilizing unit 1303 is used to reliably maintain the potential of the internal node N4, so as to avoid coupling other potential signals due to the floating potential of the internal node N4, which affects the connection situation between the third connection terminal N3 and the second output terminal N2. At the same time, the voltage stabilizing unit 1303 is also used to output the cut-off potential, that is, the first potential signal VGL, to the output terminal of the scan output unit 1302 when the cut-off potential input terminal of the scan output unit is connected to the output terminal, so as to ensure that the output terminal of the scan output unit 1302 stably outputs the first potential signal VGL.

[0139] Based on the above embodiments, optionally, as Figure 2 shown, the nth-stage shift register 30 may further include a stage transmission output module 12, which is respectively connected to the first output terminal N1 and the second output terminal N2 in the nth-stage shift register 30, and is used to output a stage transmission signal Carry in response to the potentials of the first output terminal N1 and the second output terminal N2; the stage transmission signal Carry can be used as the input signal IN of the (n + s)th-stage shift register 30; where s is an integer greater than 0; optionally, s = 1.

[0140] Exemplarily, the stage transfer output module 12 is directly controlled by the potentials of the first output terminal N1 and the second output terminal N2 to achieve the shifted output of the input signal IN. Since the stage shift registers 30 are cascaded through the stage transfer output module 12, when the input signal connected to the first-stage shift register contains a conduction pulse, the conduction pulse of the first-stage input signal can be shifted and output stage by stage through each stage transfer output module 12, providing a high-frequency stage transfer signal sequence with the same frequency as the first-stage input signal. In this way, conditions can be provided for each scan output module 13 in each stage shift register 30 to select whether to output a conduction pulse based on the control of the corresponding frequency-cutting control signal SW. In the following explanation process, the shift register 30 including the drive control module 11, the stage transfer control module 12, and the scan output module 13 is taken as an example for explanation.

[0141] Specifically, under the control of the frequency-cutting control signal SW, each scan output module 13 can have the following two working modes:

[0142] The first working mode: In one frame display, the frequency-cutting control signal SW keeps the potential of the second output terminal N2 transmitted to the potential of the third connection terminal N3, making the scan output unit 1302 have the same output state as the stage transfer output module 12. When the stage transfer output module 12 outputs a conduction potential, the scan signal output by the scan output unit 1302 is also a conduction potential. Therefore, in this mode, both the stage transfer signal Carry and the scan signal OUT have conduction pulses.

[0143] The second working mode: In one frame display, the frequency-cutting control signal SW undergoes a potential jump, so that when the stage transfer output module 12 outputs a conduction potential, the potential of the second output terminal N2 cannot be transmitted to the third connection terminal N3, resulting in the scan output unit 1302 having a different output state from the stage transfer output module 12, and the scan signal output by the scan output unit 1302 does not contain a conduction potential. Therefore, in this mode, only the stage transfer signal Carry has a conduction pulse, and the scan signal OUT does not have a conduction pulse.

[0144] When a certain scan output module 13 operates in the first operating mode in each display frame, the frequency of the conduction pulses appearing in the scan signal OUT output by the scan output module 13 is the same as the frequency of the conduction pulses appearing in the carry signal Carry output by the stage transfer output module 12 in the shift register 30 where it is located; when a certain scan output module 13 is in the second operating mode in at least some display frames, the frequency of the conduction pulses appearing in the scan signal OUT output by the scan output module 13 is lower than the frequency of the conduction pulses appearing in the carry signal Carry output by the stage transfer output module 12 in the shift register 30 where it is located. Therefore, by controlling the potential jump time of each frequency-cutting control signal SW in each display frame, the frequency of the conduction pulses appearing in the scan signal OUT output by each scan output module 13 can be controlled separately.

[0145] Each shift register 30 is connected to a row of pixel circuits. Each frequency-cutting control signal SW controls, according to the display partition position of the display panel in the column direction, the frequency of the conduction pulses appearing in the scan signal OUT output by the scan output unit 1302 connected to the pixel circuit 20 above the display partition position to be different from the frequency of the conduction pulses appearing in the scan signal OUT output by the scan output unit 1302 connected to the pixel circuit 20 below the display partition position, so as to achieve sub-region frequency division display of the display panel in the column direction.

[0146] Specifically, when the display partition position is between the pixel circuits 20 in the i-th (i is an integer greater than 0) row and the pixel circuits 20 in the i + 1-th row, in some display frames, the frequency-cutting control signal SW accessed by the i-th stage transfer control unit 1301 undergoes a potential jump before the i-th stage scan output unit 1302 outputs a conduction pulse, so that the frequency of the conduction pulses appearing in the scan signal output by the i-th stage scan output unit 1302 is different from the frequency of the conduction pulses appearing in the scan signal output by the (i + 1)-th stage scan output unit 1302, realizing sub-region frequency division display of the display panel in the column direction.

[0147] In the scanning driving circuit provided by the embodiment of the present utility model, a plurality of cascaded shift registers 30 are included. Each shift register 30 includes: a driving control module 11 and a scanning output module 13. By controlling the potential jump of the frequency cutting control signal accessed in the shift register connected to at least one row of pixel circuits, the frequency of the conduction pulse in the scanning signal OUT changes, realizing the partition frequency division display of the display panel in the column direction. At the same time, a voltage stabilizing unit is used to reliably maintain the potential of the internal node N4, avoiding the coupling of other potential signals due to the floating potential of the internal node N4, which affects the connection between the third connection end N3 and the second output end N2. At the same time, the voltage stabilizing unit 1303 is also used to output the cut-off potential, that is, the first potential signal VGL, to the output end of the scanning output unit 1302 when the cut-off potential input end and the output end of the scanning output unit are connected, ensuring that the output end of the scanning output unit 1302 stably outputs the first potential signal VGL.

[0148] On the basis of the above embodiments, optionally, each transmission control unit 1301 accesses the same frequency cutting control signal SW;

[0149] The frequency cutting control signal SW undergoes a potential jump in at least some display frames, so that the frequencies of the conduction pulses in the scanning signals output by at least two scanning output units 1302 are different.

[0150] Each scanning output unit 1302 is respectively connected to the same functional module of each row of pixel circuits. It can be set that each transmission control unit 1301 connected to the same functional module in different pixel circuits accesses the same frequency cutting control signal SW, so as to simplify the structure of the scanning driving circuit, simplify the wiring of the display panel, and at the same time reduce the output ports of the driving chip, making the scanning driving circuit easy to implement and popularize. On this basis, the frequency cutting control signal SW undergoes a potential jump in at least some display frames, so that in this display frame, the frequencies of the conduction pulses in the scanning signals output by at least two scanning output units 1302 corresponding to the frequency cutting control signal are different, so as to realize the partition different frequency display of the display panel in the column direction.

[0151] In this embodiment, the conduction pulse output by the scanning output unit is a high potential. Refer to Figure 2, in one embodiment, optionally, the driving control module 11 controls the potentials of the first output terminal N1 and the second output terminal N2 in response to the first clock signal ECK1, the second clock signal ECK2, the input signal IN, the first potential signal VGL, and the second potential signal VGH. The stage transmission output module 12 outputs the first potential signal VGL or the second potential signal VGH as the stage transmission signal Carry according to the potentials of the first output terminal N1 and the second output terminal N2. In the scan output module 13, the transmission control unit 1301 is configured to control whether the potential of the second output terminal N2 is transmitted to the third connection terminal N3 of the transmission control unit 1301 according to the frequency switching control signal SW and the stage transmission signal Carry. The scan output unit 1302 is configured to output the first potential signal VGL or the second potential signal VGH as the scan signal in response to the potentials of the first output terminal N1 and the third connection terminal N3.

[0152] Exemplarily, the first potential signal VGL and the second potential signal VGH may be DC voltage signals with different potential levels. For example, the first potential signal VGL is a low potential, and the second potential signal VGH is a high potential. Both the first clock signal ECK1 and the second clock signal ECK2 are clock signals with alternating high and low potentials.

[0153] Figure 3 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 3 , the driving control module 11 includes: a first input unit 111, a first control unit 112, a second control unit 113, a first node control unit 114, a second node control unit 115, and a third node control unit 116.

[0154] The first input unit 111 includes a transistor M21. The gate of the transistor M21 is connected to the first clock signal ECK1, the first pole is connected to the input signal IN, and the second pole is connected to the first output terminal N1. The first input unit 111, connected to the first output terminal N1, is configured to transmit the input signal IN to the first output terminal N1 in response to the first clock signal ECK1.

[0155] The first control unit 112 includes a transistor M12. The gate of the transistor M12 is connected to the first clock signal ECK1, the first pole is connected to the first potential signal VGL, and the second pole is connected to the output terminal of the first control unit 112. The first control unit 112 is configured to transmit the first potential signal VGL to the output terminal of the first control unit 112 in response to the first clock signal ECK1.

[0156] The second control unit 113 includes transistors M17 and M18, and a capacitor C13. The gate of transistor M17 is connected to the output terminal of the first control unit 112, the first pole is connected to the second clock signal ECK2, and the second pole is connected to the first pole of transistor M18. The gate of transistor M18 is connected to the second clock signal ECK2, and the second pole is connected to the second output terminal N2. The capacitor C13 is connected between the gate and the second pole of transistor M17. The second control unit 113 is configured to control the potential of the second output terminal N2 according to the second clock signal ECK2 and the potential of the output terminal of the first control unit 112.

[0157] The first node control unit 114 includes a transistor M13. The gate of transistor M13 is connected to the first output terminal N1, the first pole is connected to the first clock signal ECK1, and the second pole is connected to the output terminal of the first control unit 112. The first node control unit 114 is configured to control the potential of the output terminal of the first control unit 112 according to the potential of the first output terminal N1.

[0158] The second node control unit 115 includes transistors M14 and M15. The gate of transistor M14 is connected to the output terminal of the first control unit 112, the first pole is connected to the second potential signal VGH, and the second pole is connected to the first pole of transistor M15. The gate of transistor M15 is connected to the second clock signal ECK2, and the second pole is connected to the first output terminal N1. The second node control unit 115 is configured to control the potential of the first output terminal N1 according to the potential of the output terminal of the first control unit 112.

[0159] The third node control unit 116 includes a transistor M19. The gate of transistor M19 is connected to the first output terminal N1, the first pole is connected to the second potential signal VGH, and the second stage is connected to the second output terminal N2. The third node control unit 116 is configured to control the potential of the second output terminal N2 according to the potential of the first output terminal N1.

[0160] The stage transfer output module 12 includes: a first output unit 121 and a second output unit 122.

[0161] Among them, the first output unit 121 may include a transistor M31. The gate of transistor M31 is connected to the first output terminal N1, the first pole is connected to the first potential signal VGL, and the second pole is connected to the output terminal of the stage transfer output module 12. The first output unit 121 is configured to respond to the potential of the first output terminal N1 and output the first potential signal VGL as the carry signal Carry. Further, the first output unit 121 may further include a capacitor C14. The first end of the capacitor C14 is connected to the second clock signal ECK2, and the second end is connected to the first output terminal N1. The capacitor C14 is configured to reduce the potential of the first output terminal N1 based on the coupling effect at the falling edge of the second clock signal ECK2, so that the transistor M31 can be fully turned on.

[0162] The second output unit 122 may include a transistor M32 and a capacitor C12. The gate of the transistor M32 is connected to the second output terminal N2, the first pole accesses the second potential signal VGH, and the second pole is connected to the output terminal of the stage transmission module 12; the capacitor C12 is connected between the gate and the first pole of the transistor M32. The second output unit 122 is configured to output the second potential signal VGH as the stage transmission signal Carry in response to the potential of the second output terminal N2.

[0163] Based on the above embodiments, optionally,

[0164] The transmission control unit 1301 includes: a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is connected to the output terminal of the stage transmission module 12, the first pole of the first transistor M1 accesses the frequency switching control signal, and the second pole of the first transistor M1 is connected to the gate of the second transistor M2; the first pole of the second transistor M2 is connected to the first connection terminal of the transmission control unit 1301, this first connection terminal is connected to the second output terminal N2, and the second pole of the second transistor M2 is connected to the third connection terminal N3.

[0165] The scan output unit 1302 includes: a third transistor M3, a fourth transistor M4 and a first capacitor C1; the gate of the third transistor M3 is connected to the first output terminal N1, the first pole of the third transistor M3 accesses the first potential signal VGL, and the second pole of the third transistor M3 is connected to the output terminal of the scan output unit 1302; the gate of the fourth transistor M4 is connected to the third connection terminal N3, the first pole of the fourth transistor M4 accesses the second potential signal CGH, and the second pole of the fourth transistor M4 is connected to the output terminal of the scan output unit 1302; the first capacitor C1 is connected between the gate and the first pole of the fourth transistor M4.

[0166] The voltage stabilizing unit 1303 includes: a third capacitor C93 and a twelfth transistor M92. The first terminal of the third capacitor C93 is connected to a fixed potential signal, and the second terminal is connected to the second pole of the first transistor M1 (i.e., connected to the gate of the second transistor M2). Exemplarily, any DC voltage signal required by the shift register 30 can be multiplexed as the fixed potential signal to simplify the wiring of the display panel. For example, the first potential signal VGL or the second potential signal VGH is used as the above-mentioned fixed potential signal. The third capacitor C93 is used to reliably hold the gate potential of the second transistor M2 when the first transistor M1 is turned off, avoiding the gate of the second transistor M2 being coupled with other potential signals due to floating potential, which affects the conduction state of the second transistor M2. The gate of the twelfth transistor M92 is connected to the second pole of the first transistor M1, the first pole of the twelfth transistor M92 is connected to the first potential signal VGL, and the second pole of the twelfth transistor M92 is connected to the output terminal of the scan output unit 1302. Among them, the channel type of the twelfth transistor M92 is different from that of the second transistor M2, so that the potential of the second pole of the first transistor M1 can control the twelfth transistor M92 to conduct while controlling the second transistor M2 to turn off. Exemplarily, the second transistor M2 is a P-type transistor, and the twelfth transistor M92 is an N-type transistor. The twelfth transistor M92 can ensure that the output terminal of the scan output unit 1302 stably outputs a cut-off potential (i.e., a low potential) when the second transistor M2 is turned off.

[0167] Figure 4 FIG. is a driving timing diagram of a shift register provided by an embodiment of the present invention. Based on Figure 3 the structure of the shift register 30 therein, taking each transistor in the shift register 30 as a P-type transistor as an example, combined with Figure 4 to illustrate the driving process of the shift register 30. Exemplarily, the working process of the shift register 30 includes:

[0168] In the first stage T11, the first clock signal ECK1 and the frequency switching control signal SW are at low potential, and the second clock signal ECK2 and the input signal IN are at high potential. The transistors M21 and M12 are turned on, and the transistors M15 and M18 are turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 through the transistor M21, making the potential VN1 of the first output terminal N1 at high potential, and controlling the transistors M13, M19, M31, and the third transistor M3 to be turned off. The low potential of the first potential signal VGL is transmitted to the output terminal of the first control unit 112 through the transistor M12, turning on the transistors M14 and M17. Due to the storage effect of the capacitor C12, the potential VN2 of the second output terminal N2 remains at the high potential of the previous stage, turning off the transistor M32. Therefore, the carry signal Carry remains at the low potential of the previous stage. The carry signal Carry controls the first transistor M1 to turn on, and the low potential of the frequency switching control signal SW is transmitted to the gate of the second transistor M2, controlling the second transistor M2 to turn on. The high potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to turn off. Therefore, the scan signal OUT also remains at the low potential of the previous stage.

[0169] In the second stage T12, the second clock signal ECK2 and the frequency switching control signal SW are at low potential, and the first clock signal ECK1 and the input signal IN are at high potential. The transistors M15 and M18 are turned on, and the transistors M21 and M12 are turned off. Due to the storage effect of the capacitor C13, the output terminal of the first control unit 112 remains at the low potential of the previous stage, turning on the transistors M14 and M17. The high potential of the second potential signal VGH is transmitted to the first output terminal N1 through the transistors M14 and M15, maintaining the off state of the transistors M13, M19, M31, and the third transistor M3. The low potential of the second clock signal ECK2 is transmitted to the second output terminal N2 through the transistors M17 and M18, changing the potential VN2 of the second output terminal N2 to low potential, turning on the transistor M32, and the second potential signal VGH is output through the transistor M32, making the carry signal Carry become high potential. The carry signal Carry controls the first transistor M1 to turn off, and the low potential of the frequency switching control signal SW cannot be transmitted to the gate of the second transistor M2. The gate of the second transistor M2 remains at the low potential of the previous stage, controlling the second transistor M2 to turn on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to turn on, and the second potential signal VGH is output through the fourth transistor M4, making the scan signal OUT also become high potential.

[0170] In the third stage T13, the first clock signal ECK1 and the frequency switching control signal SW are at low potential, and the second clock signal ECK2 and the input signal IN are at high potential. The transistors M21 and M12 are turned on, and the transistors M15 and M18 are turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 through the transistor M21, turning off the transistors M13, M19, M31, and the third transistor M3. The low potential of the first potential signal VGL is transmitted to the output terminal of the first control unit 112 through the transistor M12, turning on the transistors M14 and M17. The high potential of the second clock signal ECK2 is output through the transistor M17, but since the transistor M18 is turned off, this high potential cannot be transmitted to the second output terminal N2. Due to the storage effect of the capacitor C12, the second output terminal N2 remains at the low potential of the previous stage, keeping the transistor M32 turned on and the carry signal Carry at high potential. The carry signal Carry controls the first transistor M1 to turn off, and the low potential of the frequency switching control signal SW cannot be transmitted to the gate of the second transistor M2, and the gate of the second transistor M2 continues to maintain a low potential, controlling the second transistor M2 to turn on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to turn on, and the second potential signal VGH is output through the fourth transistor M4, keeping the scan signal OUT at high potential as well.

[0171] In the fourth stage T14, the first clock signal ECK1 is at high potential, and the second clock signal ECK2, the frequency switching control signal SW, and the input signal IN are at low potential. The transistors M21 and M12 are turned off, and the transistors M15 and M18 are turned on. Due to the storage effect of the capacitor C13, the output terminal of the first control unit 112 remains at the low potential of the previous stage, turning on the transistors M14 and M17. The high potential of the second potential signal VGH is transmitted to the first output terminal N1 through the transistors M14 and M15, keeping the transistors M13, M19, M31, and the third transistor M3 in the off state. The low potential of the second clock signal ECK2 is transmitted to the second output terminal N2 through the transistors M17 and M18, turning on the transistor M32. The high potential of the second potential signal VGH is transmitted through the transistor M32, and the carry signal Carry remains at high potential. The carry signal Carry still controls the first transistor M1 to turn off, and the gate of the second transistor M2 continues to maintain a low potential, controlling the second transistor M2 to turn on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to turn on, and the second potential signal VGH is output through the fourth transistor M4, keeping the first scan signal OUT1 at high potential as well.

[0172] In the fifth stage T15, the second clock signal ECK2 is at a high potential, while the first clock signal ECK1, the frequency switching control signal SW, and the input signal IN are at low potentials. Transistors M21 and M12 are turned on, and transistors M15 and M18 are turned off. The low potential of the input signal IN is transmitted through transistor M21 to the first output terminal N1, causing the potential VN1 of the first output terminal N1 to change to a low potential, which controls transistors M13, M19, M31, and the third transistor M3 to be turned on. The low potential of the first clock signal ECK1 is transmitted through transistor M13 to the output terminal of the first control unit 112, turning on transistors M14 and M17. The high potential of the second clock signal ECK2 is output through transistor M17, but since transistor M18 is turned off, this high potential cannot be transmitted to the second output terminal N2. The high potential of the second potential signal VGH is transmitted through transistor M19 to the second output terminal N2, causing the potential VN2 of the second output terminal N2 to change to a high potential, which controls transistor M32 to be turned off. The low potential of the first potential signal VGL is output through transistor M31, and the carry signal Carry becomes a low potential. The carry signal Carry controls the first transistor M1 to be turned on, and the low potential of the frequency switching control signal SW is transmitted to the gate of the second transistor M2, controlling the second transistor M2 to be turned on. The high potential of the second output terminal N2 is transmitted through the second transistor M2 to the third connection terminal N3, controlling the fourth transistor M4 to be turned off. The low potential of the first potential signal VGL is transmitted through the third transistor M3, so the scan signal OUT also changes to a low potential.

[0173] In the sixth stage T16, the first clock signal ECK1 is at a high potential, while the second clock signal ECK2, the frequency switching control signal SW, and the input signal IN are at low potentials. Transistors M15 and M18 are turned on. Due to the coupling effect of capacitor C14, as the second clock signal ECK2 changes to a low potential, the potential of the first output terminal N1 becomes an even lower low potential than in the fifth stage T15, causing transistors M31 and the third transistor M3 to conduct more fully; the high potential of the first clock signal ECK1 is transmitted through transistor M13 to the output terminal of the first control unit 112, turning off transistors M17 and M14. The high potential of the second potential signal VGH is transmitted through transistor M19 to the second output terminal N2, keeping transistor M32 turned off. The low potential of the first potential signal VGL is output through transistor M31, and the carry signal Carry remains at a low potential; at the same time, the low potential of the first potential signal VGL is output through the third transistor M3, and the scan signal OUT also remains at a low potential.

[0174] Subsequently, the fifth stage T15 and the sixth stage T16 are repeated, and both the carry signal Carry and the scan signal OUT remain at low potentials until the input signal IN changes to a high potential again.

[0175] In the above-described embodiment, when the scanning output module 13 operates in the first operating mode, the switching frequency control signal SW remains at the low potential VL throughout the display frame, but this is not a limitation on the present invention. In other embodiments, when the scanning output module 13 operates in the first operating mode, the switching frequency control signal SW may also have a potential jump, and may include at least one high potential holding stage, as long as it can control the gate potential of the second transistor M2 to remain at the low potential before and after each potential jump edge of the second output terminal N2, so that the third connection terminal N3 can follow the potential VN2 of the second output terminal N2 to change, and the driving process of the first operating mode can be achieved.

[0176] Figure 5 Another driving timing diagram of the shift register provided by the embodiment of the present invention is shown in reference to Figure 3 and Figure 5 , and the control method of the scanning output module 13 in the second operating mode will be described below. The following mainly describes the differences in the driving processes between the second operating mode and the first operating mode, and the same parts will not be repeated.

[0177] Specifically, in the second operating mode, the rising edge of the switching frequency control signal SW occurs before the rising edge of the carry signal Carry (i.e., before the falling edge of the potential VN2 of the second output terminal N2, for example, set at any position in the first stage T11), and the high potential holding stage of the switching frequency control signal SW covers the falling edge of the potential VN2 of the second output terminal N2. In this way, before the rising edge of the carry signal Carry, during the period when the first transistor M1 remains conducting, the high potential of the switching frequency control signal SW can be transmitted to the gate of the second transistor M2 in advance, and this signal transmission process continues until the rising edge of the carry signal Carry arrives; during the high potential holding stage of the carry signal Carry, the first transistor M1 is turned off, and the gate of the second transistor M2 maintains the high potential. Therefore, the gate potential of the second transistor M2 changes to the high potential before the rising edge of the carry signal Carry. Before the gate potential of the second transistor M2 changes to the high potential, the second output terminal N2 remains at the high potential. Therefore, until the second transistor M2 is turned off due to the increase in the gate potential, the third connection terminal N3 remains at the same high potential as the second output terminal N2. In the stage where the second transistor M2 is turned off due to the increase in the gate potential, the potential jump of the second output terminal N2 cannot be transmitted to the third connection terminal N3. Therefore, the third connection terminal N3 remains at the high potential in this display frame, always controlling the fourth transistor M4 to remain cut off, so that the scanning output unit cannot output the high potential of the second potential signal VGH. Therefore, in this display frame, the scanning signal OUT always remains at the low potential.

[0178] In the above embodiments, it is exemplarily shown that in the second operating mode, the falling edge of the switching frequency control signal SW occurs before the falling edge of the carry signal Carry, but this is not a limitation on the present invention. In other embodiments, exemplarily, the falling edge of the switching frequency control signal SW may also occur after the falling edge of the carry signal Carry, or even the switching frequency control signal SW may not include a falling edge in the display frame. Then, after the falling edge of the carry signal Carry, the first transistor M1 is turned on again, and the switching frequency control signal SW can be transmitted to the gate of the second transistor M2. At this time, if the switching frequency control signal SW is at a high potential, the second transistor M2 remains in the off state, and the third connection terminal N3 remains at a high potential; if the switching frequency control signal SW is at a low potential, the second transistor M2 is turned on, and the high potential of the second output terminal N2 is transmitted to the third connection terminal N3. Therefore, after the falling edge of the carry signal Carry, regardless of the potential of the switching frequency control signal SW, it does not affect the high potential of the third connection terminal N3 to be maintained, and the control process in the second operating mode can be achieved.

[0179] Continue to refer to Figure 3 , based on the above embodiments, optionally, the drive control module 11 may further include a transistor M20. The second pole of the transistor M21 can be connected to the first output terminal N1 through the transistor M20, and the gate of the transistor M20 is connected to the first potential signal VGL. The transistor M20 is used to prevent the too low potential of the first output terminal N1 from being transmitted to the first pole N11 of the transistor M20, and to avoid damage to the transistors connected to the first pole N11 of the transistor M20 due to excessive voltage stress. Exemplarily, both the first node control unit 114 and the second node control unit 115 are connected to the first output terminal N1 through the transistor M20.

[0180] Based on the same principle, a transistor M16 may also be provided in the second control unit 113 to avoid the too low potential of the gate of the transistor M17 from being transmitted forward. The transistor M16 is connected between the output terminal of the first control unit 112 and the gate of the transistor M17, and the gate of the transistor M16 is connected to the first potential signal VGL.

[0181] Continue to refer to Figure 3, based on the above embodiments, optionally, the transmission control unit 1301 may further include a fifth transistor M5; the gate of the fifth transistor M5 is connected to the first output terminal N1, the first pole of the fifth transistor M5 accesses the second potential signal VGH, and the second pole of the fifth transistor M5 is connected to the third connection terminal N3. The fifth transistor M5 provided in this embodiment can play a role similar to that of the third node control unit 116. Specifically, the fifth transistor M5 is used to conduct when the first output terminal N1 is at a low potential, and stably transmit the high potential of the second potential signal VGH to the third connection terminal N3, so that the fourth transistor M4 remains cut off, ensuring the accuracy of the potential of the scan signal OUT. On this basis, when the scan output module 13 needs to operate in the first operating mode, the high potential holding stage of the corresponding frequency switching signal SW can cover the falling edge of the stage transfer signal Carry. After the falling edge of the stage transfer signal Carry, the fifth transistor M5 can stably provide the high potential of the second potential signal VGH to the third connection terminal N3.

[0182] Figure 6 This is a driving timing diagram of a display panel provided by an embodiment of the present invention. When using Figure 3 the shift register 30 structure shown, in cooperation with Figure 1 the display panel structure shown, the driving timing of the display panel can be referred to Figure 6 . Figure 6 exemplarily shows a case where the refresh frequencies of the pixel circuits 20 in the first row and the third row are both higher than the refresh frequency of the pixel circuit 20 in the second row. Figure 6 The shaded areas filled with dots in

[0183] represent the stages of data refreshing of the corresponding row pixel circuits 20. Figure 6 As can be seen from

[0184] In the display frame F2, the pixel circuits 20 in the first row and the third row perform data refreshing, and the corresponding scanning signals all include conduction pulses; the pixel circuits 20 in the second row do not perform data refreshing, and the corresponding scanning signals do not include conduction pulses. The rising edge of the switching frequency control signal SW occurs between the rising edge of the first-stage carry signal Carry1 and the rising edge of the second-stage carry signal Carry2, so that the first scanning signal OUT12 of the second stage has no conduction pulse. The falling edge of the switching frequency control signal SW occurs between the rising edge of the second-stage carry signal Carry2 and the rising edge of the third-stage carry signal Carry3, so that the first scanning signal OUT13 of the third stage resumes outputting conduction pulses.

[0185] In summary, by controlling the potential transition time of the switching frequency control signal SW, the frequency of the conduction pulses appearing in the scanning signal OUT output by the scanning output module 13 in each stage of the shift register 30 can be controlled, so as to realize the display of different frequencies in the column direction of the display panel.

[0186] In this embodiment, as Figure 3 described, except for the twelfth transistor M92 in the shift register 30, the rest of the transistors are all P-type transistors. In other embodiments, the types of some transistors can be changed and the driving timing can be adjusted accordingly so that the shift register region outputs the same Figure 4 scanning signal OUT as shown. Exemplarily, the second transistor M2 can be replaced with an N-type transistor. Correspondingly, when the scanning output module 13 operates in the first operating mode, the timing of the switching frequency control signal SW connected to the first transistor M1 is opposite to that in Figure 4 , and when the scanning output module 13 operates in the second operating mode, the timing of the switching frequency control signal SW connected to the first transistor M1 is opposite to that in Figure 5 .

[0187] In addition, to achieve the sub-region frequency division control of the display panel, a complex driving circuit structure needs to be designed in the border region of the display panel to provide each scanning signal to the pixel circuit. The reasons for the above problems will be described below in conjunction with Figure 7 .

[0188] Figure 7 is a schematic structural diagram of an existing display panel. Refer to Figure 7, in the current display panel structure, in order to narrow the border of the display panel, a scheme is designed in which the scan lines connecting different functional modules in different rows of pixel circuits 02 are connected to the same - stage shift register 01 in the scan driving circuit 010. However, based on this connection method, when performing zonal control on the display panel, at least the last - row pixel circuits 02 in each display zone cannot achieve their complete functions, affecting the display effect. For example: the output signal OUT of the current - stage shift register 01 serves as the first scan signal S01 required by the pixel circuits 02 in this row and the second scan signal S02 required by the pixel circuits 02 in the previous row respectively; the pixel circuits 02 can perform the gate reset operation of the driving transistor under the control of the first scan signal S01 and perform the data writing operation under the control of the second scan signal S02. Taking the display zone position of the display panel being between the second - row and third - row pixel circuits 02 as an example, if the first two - stage shift registers 01 are controlled to output conduction pulses and the other - stage shift registers 01 do not output conduction pulses, the first scan signal S01 received by the second - row pixel circuits 02 has conduction pulses, and the gate reset operation of the second - row pixel circuits 02 can be normally executed, but the second scan signal S02 received by the second - row pixel circuits 02 does not have conduction pulses, and the data writing operation of the second - row pixel circuits 02 cannot be normally executed, affecting the normal display of the second - row pixel circuits 02.

[0189] Therefore, based on the requirements of zonal frequency - division control of the display panel, in order to avoid the abnormal display of the last - row pixel circuits in the display area above the display zone position, it is necessary to design multiple groups of scan driving circuits for different functional modules in the pixel circuits respectively. It is impossible to use the same shift register to provide scan signals for different - row pixel circuits with different purposes, and it is impossible to achieve the function multiplexing of the same scan driving circuit for different functional modules of different - row pixel circuits. The excessive number of groups of scan driving circuits results in a complex overall structure of the driving circuits in the border area of the display panel, which is not conducive to the realization of a narrow border of the display panel.

[0190] To solve the above problems, an embodiment of the present utility model provides another scan driving circuit, so that the same - stage shift register in the scan driving circuit can provide at least two scan signals with different frequencies of conduction pulses, providing conditions for connecting different - row pixel circuits to the same - stage shift register, which is conducive to reducing the number of groups of scan driving circuits in the display panel and is conducive to the realization of a narrow border of the display panel. Figure 8 It is a schematic structural diagram of another display panel provided by an embodiment of the present utility model. Refer to Figure 8 , the display panel may include a display area AA and a non - display area NAA surrounding the display area AA. Pixel circuits 20 arranged in an array may be provided in the display area AA, and a scan driving circuit 100 may be provided in the non - display area NAA for providing scan signals to each row of pixel circuits 20.

[0191] The scan driving circuit 100 includes: a plurality of cascaded shift registers 10. The nth (n is an integer greater than 0) stage shift register 10 of the plurality of shift registers 10 includes: a driving control module 11 and at least two scan output modules 13. Among them, the driving control module 11 is used to control the potentials of the first output terminal N1 and the second output terminal N2 of the driving control module 11 according to the input signal IN accessed by the shift register 10. The scan output module 13 is connected to the first output terminal N1 and the second output terminal N2 and accesses the frequency cutting control signal SW. The scan output module 13 is used to output the scan signal OUT. Among them, different scan output modules 13 in the same stage shift register 10 access different frequency cutting control signals SW, and different frequency cutting control signals SW are respectively used to control the frequency of the conduction pulses appearing in the scan signal OUT output by the corresponding scan output module 13.

[0192] Figure 8 Exemplarily, each stage shift register 10 includes two scan output modules 13. The two scan output modules 13 actually have the same circuit structure. Here, for the convenience of distinction, one of the scan output modules is called the first scan output module and marked as 131; and the other scan output module is called the second scan output module and marked as 132. Correspondingly, the frequency cutting control signal accessed by the first scan output module 131 is denoted as the first frequency cutting control signal SW1, and the output scan signal is denoted as the first scan signal OUT1; the frequency cutting control signal accessed by the second scan output module 132 is denoted as the second frequency cutting control signal SW2, and the output scan signal is denoted as the second scan signal OUT2.

[0193] Exemplarily, the scan output module 13 selects whether to perform the shift output of the input signal IN under the joint control of the potentials of the first output terminal N1 and the second output terminal N2 and the frequency cutting control signal SW. Exemplarily, the frequency cutting control signal SW can be used to control whether the potentials of the first output terminal N1 and / or the second output terminal N2 can be transmitted to the internal node of the scan output module 13, so as to control whether the scan output module 13 can output the conduction potential, so as to control the frequency of the conduction pulses appearing in the scan signal. The conduction pulse can be understood as a pulse composed of the potentials that can control the conduction of the functional module accessing the scan signal. For example, when the functional module includes an N-type transistor, the conduction pulse is a high-potential pulse.

[0194] Since different scan output modules 13 in the same stage shift register 10 access different frequency cutting control signals SW, based on each frequency cutting control signal SW, the separate control of different scan output modules 13 in the same stage shift register 10 can be realized, so that the frequencies of the conduction pulses appearing in the multiple scan signals OUT output by the same shift register 10 can be freely matched according to actual needs and do not affect each other.

[0195] Based on the above embodiments, optionally, as Figure 8 shown, the nth - stage shift register 10 may further include a carry output module 12, which is respectively connected to the first output terminal N1 and the second output terminal N2 in the nth - stage shift register 10, and is used to output a carry signal Carry in response to the potentials of the first output terminal N1 and the second output terminal N2; the carry signal Carry can be used as the input signal IN of the (n + s)th - stage shift register 10; where s is an integer greater than 0; Figure 8 The case of s = 1 is exemplarily shown in

[0196] Exemplarily, the carry output module 12 is directly controlled by the potentials of the first output terminal N1 and the second output terminal N2 to realize the shifted output of the input signal IN. Since the shift registers 10 of each stage are cascaded through the carry output module 12, when the input signal connected to the first - stage shift register contains a conduction pulse, the conduction pulse of the first - stage input signal can be realized to be shifted output stage by stage through each carry output module 12, providing a high - frequency carry signal sequence with the same frequency as the first - stage input signal. In this way, conditions can be provided for each scan output module 13 in the shift registers 10 of each stage to select whether to output a conduction pulse based on the control of the corresponding frequency - cutting control signal SW. In the following explanation process, the shift register 10 including the drive control module 11, the carry control module 12, and two scan output modules 13 is taken as an example for explanation.

[0197] Specifically, under the control of the frequency - cutting control signal SW, each scan output module 13 can have the following two working modes:

[0198] The first working mode: In one - frame display, the frequency - cutting control signal SW maintains a potential that enables at least one of the potentials of the first output terminal N1 and the second output terminal N2 to be transmitted to the internal node of the scan output module 13, so that the scan output module 13 has the same output state as the carry output module 12. When the carry output module 12 outputs a conduction potential, the scan signal output by this scan output module 13 is also a conduction potential. Therefore, in this mode, both the carry signal Carry and the scan signal OUT have conduction pulses.

[0199] The second working mode: In one - frame display, the frequency - cutting control signal SW undergoes a potential jump, so that when the carry output module 12 outputs a conduction potential, at least one of the potentials of the first output terminal N1 and the second output terminal N2 cannot be transmitted to the internal node of the scan output module 13, resulting in the scan output module 13 having an output state different from that of the carry output module 12, and the scan signal output by this scan output module 13 does not contain a conduction potential. Therefore, in this mode, only the carry signal Carry has a conduction pulse, and the scan signal OUT does not have a conduction pulse.

[0200] When a certain scan output module 13 operates in the first operating mode in each display frame, the frequency of the conduction pulses appearing in the scan signal OUT output by the scan output module 13 is the same as the frequency of the conduction pulses appearing in the carry signal Carry output by the stage transmission output module 12 in the shift register 10 where it is located; when a certain scan output module 13 is in the second operating mode in at least some display frames, the frequency of the conduction pulses appearing in the scan signal OUT output by the scan output module 13 is lower than the frequency of the conduction pulses appearing in the carry signal Carry output by the stage transmission output module 12 in the shift register 10 where it is located. Therefore, by controlling the potential jump time of each frequency switching control signal SW in each display frame, the frequency of the conduction pulses appearing in the scan signal OUT output by each scan output module 13 can be controlled respectively, providing conditions for the function multiplexing of different functional modules in different row pixel circuits 20 by the same scan driving circuit 100.

[0201] Exemplarily, in a display panel, the output ends of at least two scan output modules 13 in the same stage shift register 10 are respectively connected to at least two rows of pixel circuits 20, and the output ends of some scan output modules 13 in at least two stages of shift registers 10 are connected to different functional modules in the same row of pixel circuits 20. Exemplarily, some scan output modules 13 in the current stage shift register 10 and some scan output modules 13 in the previous stage (one or more previous stages) of the shift register 10 are connected to the same row of pixel circuits 20, and the other scan output modules 13 in the current stage shift register 10 are connected to other rows (one or more rows) of pixel circuits 20. Specifically, the output end of the first scan output module 131 in the nth stage is connected to the nth row of pixel circuits 20, and the conduction pulse output by the first scan output module 131 in the nth stage acts on the first stage of the nth row of pixel circuits 20; the output end of the second scan output module 132 in the (n + m)th stage is connected to the nth row of pixel circuits 20, and the conduction pulse output by the second scan output module 132 in the (n + m)th stage acts on the second stage of the nth row of pixel circuits 20; where, for the same pixel circuit 20, in the same display frame, the first stage occurs before the second stage; m is an integer greater than 0. For example Figure 8As shown, when m = 1, the output terminals of the two scan output modules 13 in the r-th shift register 10 are respectively connected to the pixel circuits 20 in the (r - 1)-th row and the r-th row, where r is an integer greater than 1. Also, the first scan output module 131 in the j-th shift register 10 and the second scan output module 132 in the (j + 1)-th shift register 10 are both connected to the pixel circuit 20 in the j-th row. The first scan signal OUT1 of the j-th stage serves as the first control signal S1 required by the pixel circuit 20 in the j-th row, and the second scan signal OUT2 of the (j + 1)-th stage serves as the second control signal S2 required by the pixel circuit 20 in the j-th row, where j is an integer greater than 0. Among them, the first control signal S1 is used, for example, to control the gate reset process of the driving transistor in the pixel circuit 20, that is, the first stage corresponds to the reset stage in the driving process of the pixel circuit 20; the second control signal S2 is used, for example, to control the data writing process in the pixel circuit 20, that is, the second stage corresponds to the data writing stage in the driving process of the pixel circuit 20.

[0202] Each frequency-cutting control signal SW controls the frequency at which a conduction pulse appears in the scan signal OUT output by the scan output module 13 connected to the pixel circuit 20 above the display partition position according to the display partition position of the display panel in the column direction, which is different from the frequency at which a conduction pulse appears in the scan signal OUT output by the scan output module 13 connected to the pixel circuit 20 below the display partition position, so as to achieve partitioned frequency display of the display panel in the column direction. Among them, the frequencies at which conduction pulses appear in the scan signals OUT output by multiple scan output modules 13 connected to the same row of pixel circuits 20 are the same, so as to ensure that the pixel circuits 20 in this row can work properly throughout the display process.

[0203] Specifically, when the display partition position is between the pixel circuits 20 in the i-th (i is an integer greater than 0) row and the pixel circuits 20 in the (i + 1)-th row, in some display frames, the first frequency-cutting control signal SW1 undergoes a potential jump before the conduction pulse is output by the first scan output module 131 in the i-th stage, so that the frequency at which a conduction pulse appears in the scan signal output by the first scan output module 131 in the i-th stage is different from the frequency at which a conduction pulse appears in the scan signal output by the first scan output module 131 in the (i + 1)-th stage, realizing partitioned frequency display of the display panel in the column direction. Also, corresponding to the display frame in which the first frequency-cutting control signal SW1 undergoes a potential jump, the second frequency-cutting control signal SW2 undergoes a potential jump before the conduction pulse is output by the second scan output module 132 in the (i + m)-th stage, so that the frequency at which a conduction pulse appears in the second scan signal OUT2 output by the second scan output module 132 connected to each row of pixel circuits 20 is the same as the frequency at which a conduction pulse appears in the first scan signal OUT1 output by the first scan output module 131 connected to the corresponding row of pixel circuits 20, which can effectively ensure the normal display of each row of pixel circuits 20.

[0204] For the multi-line pixel circuit 20, in one frame display, when the first scan signal OUT1 output by the first scan output module 131 from the i-th level to the (i + k)-th level does not have a conduction pulse, the second scan signal OUT2 output by the second scan output module 132 from the (i + m)-th level to the (i + m + k)-th level also does not have a conduction pulse; when the first scan signal OUT1 output by the first scan output module 131 from the i-th level to the (i + k)-th level has a conduction pulse, the second scan signal OUT2 output by the second scan output module 132 from the (i + m)-th level to the (i + m + k)-th level also has a conduction pulse. In this way, it can effectively ensure that the frequencies of the conduction pulses appearing in the scan signals OUT output by the multiple scan output modules 13 connected to the same pixel circuit 20 are the same, so as to ensure that the pixel circuit 20 can work normally; both i and k are integers greater than 0.

[0205] Still taking Figure 8 the specific connection relationship between the middle scan driving circuit 100 and the pixel circuit 20 as an example, when the position of the target display partition is between the first row of pixel circuits 20 and the second row of pixel circuits 20, for example, if the data refresh frequency of the first row of pixel circuits 20 is higher than that of the second row of pixel circuits 20, it can be controlled that the frequency of the conduction pulse appearing in the first scan signal OUT1 output by the first scan output module 131 in the first stage shift register is the same as the frequency of the conduction pulse appearing in the second scan signal OUT2 output by the second scan output module 132 in the second stage shift register, and both are greater than the frequency of the conduction pulse appearing in the first scan signal OUT1 output by the first scan output module 131 in the second stage shift register; and control the frequency of the conduction pulse appearing in the first scan signal OUT1 output by the first scan output module 131 in the second stage shift register to be the same as the frequency of the conduction pulse appearing in the second scan signal OUT2 output by the second scan output module 132 in the third stage shift register, so as to ensure that the first row of pixel circuits 20 works at a high data refresh frequency and the second row of pixel circuits 20 works at a low data refresh frequency.

[0206] In the scanning driving circuit provided by the embodiment of the present utility model, a plurality of cascaded shift registers 10 are included. Each stage of the shift register 10 includes: a driving control module 11 and at least two scanning output modules 13. Each frequency cutting control signal SW can independently control whether the corresponding scanning output module 13 outputs a scanning signal with a conducting potential, so as to realize the separate control of the working modes of different scanning output modules 13 in the same shift register 10. By controlling the potential jump times of at least two frequency cutting control signals SW to be different, the combination modes of the working modes of at least two scanning output modules 13 in the same shift register 10 can be made different, so that the same shift register 10 outputs at least two scanning signals with different frequencies of the conducting pulses, thereby providing conditions for connecting different stages of shift registers 10 to the same row of pixel circuits 20 and connecting the same stage of shift register 10 to different rows of pixel circuits 20, ensuring that each row of pixel circuits can work normally when the display device performs partitioned frequency division display, thereby effectively reducing the number of groups of the scanning driving circuit 100 in the display panel, being beneficial to simplifying the overall structure of the driving circuit in the border area of the display panel, and being beneficial to the realization of the narrow border of the display panel.

[0207] On the basis of the above embodiments, when a stage transmission output module 12 is provided in the shift register 10, based on the potential control of the driving control module 11 on the first output terminal N1 and the second output terminal N2, each stage transmission output module 12 can realize the step-by-step shift output of the first-stage input signal, and provide a stage transmission signal Carry with the same frequency as the first-stage input signal, providing a basis for each scanning output module 13 in each stage of the shift register 10 to freely select to output a scanning signal with the same frequency as the first-stage input signal or a frequency of the conducting pulse lower than that of the first-stage input signal based on the control of the frequency cutting control signal SW.

[0208] On the basis of the above embodiments, optionally, one scanning output module 13 is selected from each stage of the shift register 10 to jointly form a scanning output group, and different scanning output modules 13 in the same stage of the shift register 10 belong to different scanning output groups. For example, the first scanning output modules 131 in each shift register 10 form a scanning output group, and the second scanning output modules 132 in each shift register 10 form another scanning output group. It can be set that each scanning output module 13 in the same scanning output group is connected to the same frequency cutting control signal SW, so as to simplify the structure of the scanning driving circuit 100, simplify the wiring of the display panel, and at the same time reduce the output ports of the driving chip, making the scanning driving circuit 100 easy to implement and popularize. On this basis, for any scanning output group, the frequency cutting control signal SW performs a potential jump in at least part of the display frames, so that in this display frame, the frequencies of the conducting pulses appearing in the scanning signals output by at least two scanning output modules 13 in the scanning output group are different, so as to realize the display of different frequencies in the column direction of the display panel.

[0209] Based on the above embodiments, optionally, each of the scanning output modules 13 in the same scanning output group is respectively connected to the same functional module of each row of pixel circuits 20. For example, each first scanning output module 131 is connected to the access terminal corresponding to the first control signal S1 in the pixel circuit 20; each second scanning output module 132 is connected to the access terminal corresponding to the second control signal S2 in the pixel circuit 20. And, multiple scanning output modules 13 connected to different functional modules in the same pixel circuit 20 belong to different scanning output groups and are located in different-stage shift registers 10. For example, the first row of pixel circuits 20 is respectively connected to the first scanning output module 131 in the first-stage shift register 10 and the second scanning output module 132 in the second-stage shift register 10, and the first scanning output module 131 and the second scanning output module 132 belong to different scanning output groups. Such an arrangement can enable each frequency-cutting control signal SW to control the frequency at which a conduction pulse appears in the scanning signal OUT output by each scanning output module 13 in units of scanning output groups, which is beneficial to simplifying the control logic.

[0210] Based on the above embodiments, optionally, any one of the scanning output modules 13 may include a transmission control unit and a scanning output unit. The scanning output unit may have the same functional circuit structure as the stage transmission output module 12. For example, it includes two control terminals, a conduction potential input terminal, a cut-off potential input terminal, and an output terminal. The potential of one of the control terminals is used to control whether the cut-off potential input terminal is connected to the output terminal, and the potential of the other control terminal is used to control whether the conduction potential input terminal is connected to the output terminal, so that this functional circuit can control the output signal of its output terminal to be a conduction potential or a cut-off potential based on the potentials of its two control terminals. The transmission control unit can control the on / off of its internal circuit based on the frequency-cutting control signal SW, so as to control whether at least one control terminal of the scanning driving unit can be connected to the driving control module 11 through the transmission control unit, to control whether the scanning output unit can output a conduction potential, and thus control the frequency at which a conduction pulse appears in the scanning signal. Exemplarily, the first connection terminal of the transmission control unit is connected to one of the first output terminal N1 and the second output terminal N2, and the second connection terminal of the transmission control unit accesses the frequency-cutting control signal SW; the first control terminal of the scanning output unit is connected to the third connection terminal of the transmission control unit, and the second control terminal of the scanning output unit is connected to the other of the first output terminal N1 and the second output terminal N2; then the transmission control unit can control the frequency at which a conduction pulse appears in the scanning signal output by the scanning output unit by controlling the potential of its third connection terminal.

[0211] In the above embodiments, the working principles of the functional modules in the scan driving circuit 100 are exemplarily given. Next, in combination with the specific structure of the pixel circuit 20, the specific connection manner between the scan driving circuit 100 and the pixel circuit 20, and the specific structures that the shift registers 10 at all levels may have will be described.

[0212] Figure 9 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Refer to Figure 9 In one embodiment, optionally, the pixel circuit 20 includes: a driving module 21 including a driving transistor DTFT; a data writing module 22 including a data writing transistor M24; a threshold compensation module 23 including a threshold compensation transistor M25; a gate reset module 24 including a gate initialization transistor M22; an anode reset module including an anode initialization transistor M23; a light emission control module 26 including a first light emission control transistor M26 and a second light emission control transistor M27; and a storage module 27 including a storage capacitor Cst, constituting a pixel circuit 20 of a 7T1C architecture.

[0213] Specifically, the first light emission control transistor M26, the driving transistor DTFT, the second light emission control transistor M27, and the light emitting device OLED are connected in series in sequence; the data writing transistor M24 is connected to a data voltage Vdata and is electrically connected to the first pole of the driving transistor DTFT; the threshold compensation transistor M25 is connected between the gate and the second pole of the driving transistor DTFT; the gate initialization transistor M22 is connected to a first initialization signal Vref1 and is electrically connected to the gate of the driving transistor DTFT; the anode initialization transistor M23 is connected to a second initialization signal Vref2 and is electrically connected to the anode of the light emitting device OLED; the cathode of the light emitting device OLED is connected to a second power supply signal VSS; one end of the storage capacitor Cst is connected to the gate of the driving transistor DTFT, and the other end is connected to a first power supply signal VDD. Among them, the gate of the gate initialization transistor M22 is connected to a first control signal S1, the gate of the threshold compensation transistor M25 is connected to a second control signal S2, the gate of the data writing transistor M24 is connected to a third control signal S3, the gate of the anode initialization transistor M23 is connected to a fourth control signal S4, and the gates of the first light emission control transistor M26 and the second light emission control transistor M27 are both connected to a light emission control signal EM. Exemplarily, the threshold compensation transistor M25 and the gate initialization transistor M22 may be N-type transistors, and the other transistors may be P-type transistors, constituting an LTPO pixel circuit.

[0214] Figure 10 It is a schematic driving timing diagram of a pixel circuit provided by an embodiment of the present invention. In combination with Figure 9 and Figure 10, Exemplarily, when the pixel circuit 20 is in low-frequency display, one display cycle may include one refresh frame FA and at least one hold frame FI. When in high-frequency display, one display cycle may only include the refresh frame FA. Among them, the refresh frame FA includes a reset stage T21, a data writing stage T22, and a first light-emitting stage T23. The hold frame FI includes a blanking stage T24 and a second light-emitting stage T25, and data writing is no longer performed during the blanking stage T24.

[0215] Specifically, based on the low-frequency refresh scenario, and taking the same timing of the third control signal S3 and the fourth control signal S4 as an example, the driving process of the pixel circuit 20 includes:

[0216] Reset stage T21, the first control signal S1, the third control signal S3, the fourth control signal S4, and the light-emitting control signal EM are all at high potential. The gate initialization transistor M22 is turned on, and the first initialization signal Vref1 passes through the gate initialization transistor M22 to reset the gate of the driving transistor DTFT.

[0217] Data writing stage T22, the first control signal S1, the third control signal S3, and the fourth control signal S4 are all at low potential, the second control signal S2 and the light-emitting control signal EM are both at high potential. The gate initialization transistor M22 is turned off, the anode initialization transistor M23, the data writing transistor M24, and the threshold compensation transistor M25 are all turned on. The data signal Vdata passes through the data writing transistor M24, the first and second poles of the driving transistor DTFT, and the threshold compensation transistor M25 to be transmitted to the gate of the driving transistor DTFT. At the same time, the second initialization signal Vref2 passes through the anode initialization transistor M23 to reset the anode of the light-emitting device OLED.

[0218] First light-emitting stage T23, the first control signal S1, the second control signal S2, and the light-emitting control signal EM are all at low potential, the third control signal S3 and the fourth control signal S4 are at high potential. The threshold compensation transistor M25 is turned off, the first light-emitting control transistor M26 and the second light-emitting control transistor M27 are both turned on, and the driving transistor DTFT generates a driving current to drive the light-emitting device OLED to emit light.

[0219] During the black insertion stage T24, the first control signal S1 and the second control signal S2 are maintained at a low potential, the third control signal S3 is maintained at a high potential, and the emission control signal EM becomes a high potential. The first emission control transistor M26 and the second emission control transistor M27 are both turned off, and the light-emitting device OLED stops emitting light. In this stage, the fourth control signal S4 can have a conduction pulse (i.e., a low potential pulse) to control the anode initialization transistor M23 to conduct, and reset the anode of the light-emitting device OLED again, so that the emission brightness of the light-emitting device OLED in the second emission stage T25 is closer to the brightness in the first emission stage T23.

[0220] During the second emission stage T25, the first control signal S1 and the second control signal S2 are maintained at a low potential, the third control signal S3 and the fourth control signal S4 are maintained at a high potential, and the emission control signal EM becomes a low potential again. The first emission control transistor M26 and the second emission control transistor M27 conduct again, and the driving transistor DTFT generates a driving current again to drive the light-emitting device OLED to emit light.

[0221] The driving process of the subsequent stages repeats to maintain the driving of the frame FI until the next refresh frame FA arrives.

[0222] As can be seen from the above analysis, Figure 9 In the driving process of the pixel circuit 20, the first control signal S1 and the second control signal S2 with misaligned conduction pulses are required. Therefore, a scan driving circuit 100 capable of outputting a low potential scan signal for a long time can be correspondingly set to provide the first control signal S1 and the second control signal S2, and a specific connection method similar to that Figure 8 between the scan driving circuit 100 and the pixel circuit 20 in is used to drive each row of pixel circuits 20. It should be noted that for the LTPO pixel circuit, the two scan output modules 13 of the same shift register 10 in the scan driving circuit 100 can be connected to two adjacent rows of pixel circuits 20, or can be connected to two non-adjacent rows of pixel circuits 20, which can be specifically set according to actual requirements. For example, when the conduction pulses of the first control signal S1 and the second control signal S2 need to be completely non-overlapping, the two scan output modules 13 of the same shift register 10 can be set to be connected to two non-adjacent rows of pixel circuits 20 respectively.

[0223] Next, the structure of the scan driving circuit 100 capable of outputting a low potential scan signal for a long time (i.e., the conduction pulse output by the scan output module 13 is at a high potential) will be described. Figure 11 is a schematic structural diagram of a shift register provided by an embodiment of the present invention. Refer to Figure 11, in one embodiment, optionally, the drive control module 11 controls the potentials of the first output terminal N1 and the second output terminal N2 in response to the first clock signal ECK1, the second clock signal ECK2, the input signal IN, the first potential signal VGL, and the second potential signal VGH. The stage transmission output module 12 outputs the first potential signal VGL or the second potential signal VGH as the stage transmission signal Carry according to the potentials of the first output terminal N1 and the second output terminal N2. For any one of the scan output modules 13, the transmission control unit 1301 is used to control whether the potential of the second output terminal N2 is transmitted to the third connection terminal N3 of the transmission control unit 1301 according to the frequency cutting control signal and the stage transmission signal Carry. The scan output unit 1302 is used to output the first potential signal VGL or the second potential signal VGH as the scan signal in response to the potentials of the first output terminal N1 and the third connection terminal N3.

[0224] Exemplarily, the first potential signal VGL and the second potential signal VGH may be DC voltage signals with different potential levels. For example, the first potential signal VGL is a low potential and the second potential signal VGH is a high potential. Both the first clock signal ECK1 and the second clock signal ECK2 are clock signals with alternating high and low potentials.

[0225] Specifically, referring to Figure 12 , the drive control module 11 includes: a first input unit 111, a first control unit 112, a second control unit 113, a first node control unit 114, a second node control unit 115, and a third node control unit 116.

[0226] Among them, the first input unit 111 includes a transistor M21. The gate of the transistor M21 is connected to the first clock signal ECK1, the first pole is connected to the input signal IN, and the second pole is connected to the first output terminal N1. The first input unit 111 is used to transmit the input signal IN to the first output terminal N1 in response to the first clock signal ECK1.

[0227] The first control unit 112 includes a transistor M12. The gate of the transistor M12 is connected to the first clock signal ECK1, the first pole is connected to the first potential signal VGL, and the second pole is connected to the output terminal of the first control unit 112. The first control unit 112 is used to transmit the first potential signal VGL to the output terminal of the first control unit 112 in response to the first clock signal ECK1.

[0228] The second control unit 113 includes transistors M17 and M18, and a capacitor C13. The gate of transistor M17 is connected to the output terminal of the first control unit 112, its first pole is connected to the second clock signal ECK2, and its second pole is connected to the first pole of transistor M18. The gate of transistor M18 is connected to the second clock signal ECK2, and its second pole is connected to the second output terminal N2. The capacitor C13 is connected between the gate and the second pole of transistor M17. The second control unit 113 is configured to control the potential of the second output terminal N2 according to the second clock signal ECK2 and the potential of the output terminal of the first control unit 112.

[0229] The first node control unit 114 includes a transistor M13. The gate of transistor M13 is connected to the first output terminal N1, its first pole is connected to the first clock signal ECK1, and its second pole is connected to the output terminal of the first control unit 112. The first node control unit 114 is configured to control the potential of the output terminal of the first control unit 112 according to the potential of the first output terminal N1.

[0230] The second node control unit 115 includes transistors M14 and M15. The gate of transistor M14 is connected to the output terminal of the first control unit 112, its first pole is connected to the second potential signal VGH, and its second pole is connected to the first pole of transistor M15. The gate of transistor M15 is connected to the second clock signal ECK2, and its second pole is connected to the first output terminal N1. The second node control unit 115 is configured to control the potential of the first output terminal N1 according to the potential of the output terminal of the first control unit 112.

[0231] The third node control unit 116 includes a transistor M19. The gate of transistor M19 is connected to the first output terminal N1, its first pole is connected to the second potential signal VGH, and its second stage is connected to the second output terminal N2. The third node control unit 116 is configured to control the potential of the second output terminal N2 according to the potential of the first output terminal N1.

[0232] The stage transfer output module 12 includes: a first output unit 121 and a second output unit 122.

[0233] Among them, the first output unit 121 may include a transistor M31. The gate of transistor M31 is connected to the first output terminal N1, its first pole is connected to the first potential signal VGL, and its second pole is connected to the output terminal of the stage transfer output module 12. The first output unit 121 is configured to output the first potential signal VGL as a carry signal Carry in response to the potential of the first output terminal N1. Further, the first output unit 121 may further include a capacitor C14. The first end of the capacitor C14 is connected to the second clock signal ECK2, and the second end is connected to the first output terminal N1. The capacitor C14 is configured to reduce the potential of the first output terminal N1 based on the coupling effect at the falling edge of the second clock signal ECK2, so that the transistor M31 can be fully turned on.

[0234] The second output unit 122 may include a transistor M32 and a capacitor C12. The gate of the transistor M32 is connected to the second output terminal N2, the first pole accesses the second potential signal VGH, and the second pole is connected to the output terminal of the stage transmission output module 12. The capacitor C12 is connected between the gate and the first pole of the transistor M32. The second output unit 122 is configured to output the second potential signal VGH as the stage transmission signal Carry in response to the potential of the second output terminal N2.

[0235] Based on the above embodiments, optionally, for any scan output module:

[0236] The transmission control unit 1301 includes: a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is connected to the output terminal of the stage transmission output module 12, the first pole of the first transistor M1 accesses the frequency-cutting control signal, and the second pole of the first transistor M1 is connected to the gate of the second transistor M2; the first pole of the second transistor M2 is connected to the first connection terminal of the transmission control unit 1301, this first connection terminal is connected to the second output terminal N2, and the second pole of the second transistor M2 is connected to the third connection terminal N3.

[0237] The scan output unit 1302 includes: a third transistor M3, a fourth transistor M4, and a first capacitor C1; the gate of the third transistor M3 is connected to the first output terminal N1, the first pole of the third transistor M3 accesses the first potential signal VGL, and the second pole of the third transistor M3 is connected to the output terminal of the scan output unit 1302; the gate of the fourth transistor M4 is connected to the third connection terminal N3, the first pole of the fourth transistor M4 accesses the second potential signal CGH, and the second pole of the fourth transistor M4 is connected to the output terminal of the scan output unit 1302; the first capacitor C1 is connected between the gate and the first pole of the fourth transistor M4.

[0238] Next, based on Figure 12 the structure of the shift register 10, taking the case where each transistor in the shift register 10 is a P-type transistor as an example, combined with Figure 13 the driving process of the shift register 10 will be described. Among them, to fully illustrate the working process of the circuit, Figure 13 in the example, it is shown that the first scan output module 131 operates in the first working mode and the second scan output module 132 operates in the second working mode, but this is not a limitation to the present invention. Substantially, the first scan output module 131 and the second scan output module 132 have the same control logic. In practical applications, any scan output module can be controlled to operate in any mode as needed. Next, combined with Figure 12 and Figure 13 , first, taking the working process of the first scan output module 131 as an example, the control method in the first working mode will be described.

[0239] Exemplarily, the operation process of the shift register 10 includes:

[0240] In the first stage T11, the first clock signal ECK1 and the first frequency switching control signal SW1 are at low potential, and the second clock signal ECK2 and the input signal IN are at high potential. The transistors M21 and M12 are turned on, and the transistors M15 and M18 are turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 through the transistor M21, making the potential VN1 of the first output terminal N1 at high potential, and controlling the transistors M13, M19, M31, and the third transistor M3 to be turned off. The low potential of the first potential signal VGL is transmitted to the output terminal of the first control unit 112 through the transistor M12, making the transistors M14 and M17 turned on. Due to the storage effect of the capacitor C12, the potential VN2 of the second output terminal N2 remains at the high potential of the previous stage, making the transistor M32 turned off. Therefore, the carry signal Carry remains at the low potential of the previous stage. The carry signal Carry controls the first transistor M1 to be turned on, and the low potential of the first frequency switching control signal SW1 is transmitted to the gate of the second transistor M2, controlling the second transistor M2 to be turned on. The high potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to be turned off. Therefore, the first scan signal OUT1 also remains at the low potential of the previous stage.

[0241] In the second stage T12, the second clock signal ECK2 and the first frequency switching control signal SW1 are at low potential, and the first clock signal ECK1 and the input signal IN are at high potential. The transistors M15 and M18 are turned on, and the transistors M21 and M12 are turned off. Due to the storage effect of the capacitor C13, the output terminal of the first control unit 112 remains at the low potential of the previous stage, making the transistors M14 and M17 turned on. The high potential of the second potential signal VGH is transmitted to the first output terminal N1 through the transistors M14 and M15, maintaining the off state of the transistors M13, M19, M31, and the third transistor M3. The low potential of the second clock signal ECK2 is transmitted to the second output terminal N2 through the transistors M17 and M18, changing the potential VN2 of the second output terminal N2 to low potential, making the transistor M32 turned on, and the second potential signal VGH is output through the transistor M32, making the carry signal Carry become high potential. The carry signal Carry controls the first transistor M1 to be turned off, and the low potential of the first frequency switching control signal SW1 cannot be transmitted to the gate of the second transistor M2. The gate of the second transistor M2 remains at the low potential of the previous stage, controlling the second transistor M2 to be turned on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to be turned on, and the second potential signal VGH is output through the fourth transistor M4, making the first scan signal OUT1 also become high potential.

[0242] In the third stage T13, the first clock signal ECK1 and the first frequency switching control signal SW1 are at low potential, while the second clock signal ECK2 and the input signal IN are at high potential. The transistors M21 and M12 are turned on, and the transistors M15 and M18 are turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 through the transistor M21, turning off the transistors M13, M19, M31, and the third transistor M3. The low potential of the first potential signal VGL is transmitted to the output terminal of the first control unit 112 through the transistor M12, turning on the transistors M14 and M17. The high potential of the second clock signal ECK2 is output through the transistor M17, but since the transistor M18 is turned off, this high potential cannot be transmitted to the second output terminal N2. Due to the storage effect of the capacitor C12, the second output terminal N2 maintains the low potential of the previous stage, keeping the transistor M32 turned on and the carry signal Carry at high potential. The carry signal Carry controls the first transistor M1 to turn off, and the low potential of the first frequency switching control signal SW1 cannot be transmitted to the gate of the second transistor M2, and the gate of the second transistor M2 continues to maintain a low potential, controlling the second transistor M2 to turn on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to turn on, and the second potential signal VGH is output through the fourth transistor M4, keeping the first scan signal OUT1 at high potential as well.

[0243] In the fourth stage T14, the first clock signal ECK1 is at high potential, while the second clock signal ECK2, the first frequency switching control signal SW1, and the input signal IN are at low potential. The transistors M21 and M12 are turned off, and the transistors M15 and M18 are turned on. Due to the storage effect of the capacitor C13, the output terminal of the first control unit 112 maintains the low potential of the previous stage, turning on the transistors M14 and M17. The high potential of the second potential signal VGH is transmitted to the first output terminal N1 through the transistors M14 and M15, keeping the transistors M13, M19, M31, and the third transistor M3 in the off state. The low potential of the second clock signal ECK2 is transmitted to the second output terminal N2 through the transistors M17 and M18, turning on the transistor M32. The high potential of the second potential signal VGH is transmitted through the transistor M32, and the carry signal Carry remains at high potential. The carry signal Carry still controls the first transistor M1 to turn off, and the gate of the second transistor M2 continues to maintain a low potential, controlling the second transistor M2 to turn on. The low potential of the second output terminal N2 is transmitted to the third connection terminal N3 through the second transistor M2, controlling the fourth transistor M4 to turn on, and the second potential signal VGH is output through the fourth transistor M4, keeping the first scan signal OUT1 at high potential as well.

[0244] In the fifth stage T15, the second clock signal ECK2 is at a high potential, while the first clock signal ECK1, the first frequency switching control signal SW1, and the input signal IN are at low potentials. The transistors M21 and M12 are turned on, and the transistors M15 and M18 are turned off. The low potential of the input signal IN is transmitted through the transistor M21 to the first output terminal N1, causing the potential VN1 of the first output terminal N1 to change to a low potential, which controls the transistors M13, M19, M31, and the third transistor M3 to be turned on. The low potential of the first clock signal ECK1 is transmitted through the transistor M13 to the output terminal of the first control unit 112, causing the transistors M14 and M17 to be turned on. The high potential of the second clock signal ECK2 is output through the transistor M17, but since the transistor M18 is turned off, this high potential cannot be transmitted to the second output terminal N2. The high potential of the second potential signal VGH is transmitted through the transistor M19 to the second output terminal N2, causing the potential VN2 of the second output terminal N2 to change to a high potential, which controls the transistor M32 to be turned off. The low potential of the first potential signal VGL is output through the transistor M31, and the carry signal Carry changes to a low potential. The carry signal Carry controls the first transistor M1 to be turned on, and the low potential of the first frequency switching control signal SW1 is transmitted to the gate of the second transistor M2, controlling the second transistor M2 to be turned on. The high potential of the second output terminal N2 is transmitted through the second transistor M2 to the third connection terminal N3, controlling the fourth transistor M4 to be turned off. The low potential of the first potential signal VGL is transmitted through the third transistor M3, so the first scan signal OUT1 also changes to a low potential.

[0245] In the sixth stage T16, the first clock signal ECK1 is at a high potential, while the second clock signal ECK2, the first frequency switching control signal SW1, and the input signal IN are at low potentials. The transistors M15 and M18 are turned on. Due to the coupling effect of the capacitor C14, as the second clock signal ECK2 changes to a low potential, the potential of the first output terminal N1 becomes an even lower low potential than in the fifth stage T15, causing the transistors M31 and the third transistor M3 to conduct more fully. The high potential of the first clock signal ECK1 is transmitted through the transistor M13 to the output terminal of the first control unit 112, causing the transistors M17 and M14 to be turned off. The high potential of the second potential signal VGH is transmitted through the transistor M19 to the second output terminal N2, causing the transistor M32 to remain turned off. The low potential of the first potential signal VGL is output through the transistor M31, and the carry signal Carry remains at a low potential. At the same time, the low potential of the first potential signal VGL is output through the third transistor M3, and the first scan signal OUT1 also remains at a low potential.

[0246] Subsequently, the fifth stage T15 and the sixth stage T16 are repeated, and both the carry signal Carry and the first scan signal OUT1 remain at low potentials until the input signal IN changes to a high potential again.

[0247] In the above embodiments, when the first scanning output module 131 operates in the first operating mode, the first frequency switching control signal SW1 remains at the low potential VL throughout the display frame as an example, but it is not a limitation to the present invention. In other embodiments, when the first scanning output module 131 operates in the first operating mode, the first frequency switching control signal SW1 may also have a potential jump, and may include at least one high potential holding stage, as long as it can control the gate potential of the second transistor M2 to remain at the low potential before and after each potential jump edge of the second output terminal N2, so that the third connection terminal N3 can follow the potential VN2 of the second output terminal N2 to change, and the driving process of the first operating mode can be realized.

[0248] Taking the working process of the second scanning output module 132 as an example, the control method in the second operating mode will be described below. The following mainly describes the differences between the driving processes in the second operating mode and the first operating mode, and the same parts will not be repeated.

[0249] Specifically, in the second operating mode, the rising edge of the second frequency switching control signal SW2 occurs before the rising edge of the stage transfer signal Carry (that is, before the falling edge of the potential VN2 of the second output terminal N2, for example, set at any position in the first stage T11), and the high potential holding stage of the second frequency switching control signal SW2 covers the falling edge of the potential VN2 of the second output terminal N2. In this way, before the rising edge of the stage transfer signal Carry, during the period when the first transistor M1 remains conducting, the high potential of the second frequency switching control signal SW2 can be transmitted to the gate of the second transistor M2 in advance, and this signal transmission process continues until the rising edge of the stage transfer signal Carry arrives; during the high potential holding stage of the stage transfer signal Carry, the first transistor M1 is cut off, and the gate of the second transistor M2 maintains the high potential. Therefore, the gate potential of the second transistor M2 changes to the high potential before the rising edge of the stage transfer signal Carry. Before the gate potential of the second transistor M2 changes to the high potential, the second output terminal N2 remains at the high potential. Therefore, until the second transistor M2 is turned off due to the increase in the gate potential, the third connection terminal N3 remains at the same high potential as the second output terminal N2. During the stage when the second transistor M2 is turned off due to the increase in the gate potential, the potential jump of the second output terminal N2 cannot be transmitted to the third connection terminal N3. Therefore, the third connection terminal N3 remains at the high potential in this display frame, always controlling the fourth transistor M4 to remain cut off, so that the scanning output unit in the second scanning output module 132 cannot output the high potential of the second potential signal VGH. Therefore, in this display frame, the second scanning signal OUT2 always remains at the low potential.

[0250] In the above-described embodiment, it is exemplarily shown that in the second operating mode, the falling edge of the second frequency switching control signal SW2 occurs before the falling edge of the carry signal Carry, but this is not a limitation on the present invention. In other embodiments, exemplarily, the falling edge of the second frequency switching control signal SW2 may also occur after the falling edge of the carry signal Carry, or even the second frequency switching control signal SW2 may not include a falling edge in the display frame. Then, after the falling edge of the carry signal Carry, the first transistor M1 is turned on again, and the second frequency switching control signal SW2 can be transmitted to the gate of the second transistor M2. At this time, if the second frequency switching control signal SW2 is at a high potential, the second transistor M2 remains in the off state, and the third connection terminal N3 remains at a high potential; if the second frequency switching control signal SW2 is at a low potential, the second transistor M2 is turned on, and the high potential of the second output terminal N2 is transmitted to the third connection terminal N3. Therefore, after the falling edge of the carry signal Carry, regardless of the potential of the second frequency switching control signal SW2, it does not affect the high potential of the third connection terminal N3 to be maintained, and the control process in the second operating mode can be achieved.

[0251] Continue to refer to Figure 12 , based on the above-described embodiments, optionally, the drive control module 11 may further include a transistor M20. The second pole of the transistor M21 may be connected to the first output terminal N1 through the transistor M20, and the gate of the transistor M20 is connected to the first potential signal VGL. The transistor M20 is used to prevent the too low potential of the first output terminal N1 from being transmitted to the first pole N11 of the transistor M20, and to avoid damage to the transistors connected to the first pole N11 of the transistor M20 due to excessive voltage stress. Exemplarily, both the first node control unit 114 and the second node control unit 115 are connected to the first output terminal N1 through the transistor M20.

[0252] Based on the same principle, a transistor M16 may also be provided in the second control unit 113 to avoid the too low potential of the gate of the transistor M17 from being transmitted forward. The transistor M16 is connected between the output terminal of the first control unit 112 and the gate of the transistor M17, and the gate of the transistor M16 is connected to the first potential signal VGL.

[0253] Continue to refer to Figure 12, based on the above embodiments, optionally, the transmission control unit 1301 may further include a fifth transistor M5; the gate of the fifth transistor M5 is connected to the first output terminal N1, the first pole of the fifth transistor M5 accesses the second potential signal VGH, and the second pole of the fifth transistor M5 is connected to the third connection terminal N3. The fifth transistor M5 provided in this embodiment can play a role similar to that of the third node control unit 116. Specifically, the fifth transistor M5 is used to conduct when the first output terminal N1 is at a low potential, stably transmit the high potential of the second potential signal VGH to the third connection terminal N3, keep the fourth transistor M4 cut off, and ensure the accuracy of the potential of the scan signal OUT. On this basis, when the scan output module 13 needs to operate in the first operating mode, the high potential holding stage of the corresponding frequency switching signal SW can cover the falling edge of the stage transmission signal Carry. After the falling edge of the stage transmission signal Carry, the fifth transistor M5 can stably provide the high potential of the second potential signal VGH to the third connection terminal N3.

[0254] Figure 14 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 8 , based on the above embodiments, optionally, for at least one of the at least two scan output modules, it may further include: a third capacitor C93 to reliably hold the gate potential of the second transistor M2 when the first transistor M1 is turned off, and prevent other potential signals from being coupled into the gate of the second transistor M2 due to potential floating, affecting the conduction state of the second transistor M2. Specifically, the first end of the third capacitor C93 accesses a fixed potential signal, and the second end is connected to the second pole of the first transistor M1 (i.e., connected to the gate of the second transistor M2). Exemplarily, any DC voltage signal required by the shift register 10 can be reused as the fixed potential signal to simplify the wiring of the display panel. For example, the first potential signal VGL or the second potential signal VGH can be used as the above fixed potential signal.

[0255] Further, at least one of the at least two scan output modules may further include: a twelfth transistor M92 to ensure that the output terminal of the scan output unit 1302 stably outputs a cut-off potential (i.e., a low potential) when the second transistor M2 is turned off. Specifically, the gate of the twelfth transistor M92 is connected to the second pole of the first transistor M1, the first pole of the twelfth transistor M92 accesses the first potential signal VGL, and the second pole of the twelfth transistor M92 is connected to the output terminal of the scan output unit 1302. Among them, the channel types of the twelfth transistor M92 and the second transistor M2 are different, so that the potential of the second pole of the first transistor M1 can control the twelfth transistor M92 to conduct while controlling the second transistor M2 to turn off. Exemplarily, the second transistor M2 is a P-type transistor, and the twelfth transistor M92 is an N-type transistor. In this embodiment, it is exemplarily shown that each scan output module includes a third capacitor C93 and a twelfth transistor M92.

[0256] When using Figure 12 or Figure 14 the shift register 10 structure shown, in cooperation with Figure 8 the display panel structure shown, the driving timing of the display panel can be referred to Figure 15 . Figure 15 Exemplarily, in [reference document], the refresh frequencies of the pixel circuits 20 in the first row and the third row are both higher than the refresh frequency of the pixel circuit 20 in the second row. Figure 15 In [reference document], the shaded areas filled with dots represent the stages when the corresponding row pixel circuits 20 perform data refreshing.

[0257] Referring to Figure 15 it can be seen that in the display frame F1, the pixel circuits 20 in all three rows perform data refreshing, and the corresponding scan signals all include conduction pulses. Specifically, for example, the data writing stage of the pixel circuit 20 in the first row occurs after the conduction pulse of the first scan signal OUT11 in the first stage ends and before the conduction pulse of the second scan signal OUT22 in the second stage ends. The data writing stage of the pixel circuit 20 in the second row occurs after the conduction pulse of the first scan signal OUT12 in the second stage ends and before the conduction pulse of the second scan signal OUT23 in the third stage ends, and so on.

[0258] In the display frame F2, the pixel circuits 20 in the first row and the third row perform data refreshing, and the corresponding scanning signals all include turn-on pulses; the pixel circuits 20 in the second row do not perform data refreshing, and the corresponding scanning signals do not include turn-on pulses. Specifically, the first-stage first scanning signal OUT11 and the second-stage second scanning signal OUT22 both have turn-on pulses, so that the pixel circuits 20 in the first row can perform data refreshing; the second-stage first scanning signal OUT12 and the third-stage second scanning signal OUT23 do not include turn-on pulses, so that the pixel circuits 20 in the second row can perform data holding; the third-stage first scanning signal OUT13 and the fourth-stage second scanning signal OUT24 both have turn-on pulses, so that the pixel circuits 20 in the third row can perform data refreshing. Then, the rising edge of the first frequency-cutting control signal SW1 occurs between the rising edge of the first-stage carry signal Carry1 and the rising edge of the second-stage carry signal Carry2, so that the second-stage first scanning signal OUT12 has no turn-on pulse, and the falling edge of the first frequency-cutting control signal SW1 occurs between the rising edge of the second-stage carry signal Carry2 and the rising edge of the third-stage carry signal Carry3, so that the third-stage first scanning signal OUT13 resumes outputting turn-on pulses. The rising edge of the second frequency-cutting control signal SW2 occurs between the rising edge of the second-stage carry signal Carry2 and the rising edge of the third-stage carry signal Carry3, so that the third-stage second scanning signal OUT23 has no turn-on pulse, and the falling edge of the second frequency-cutting control signal SW2 occurs between the rising edge of the third-stage carry signal Carry3 and the rising edge of the fourth-stage carry signal Carry4, so that the fourth-stage second scanning signal OUT24 resumes outputting turn-on pulses.

[0259] In summary, by controlling the potential jump time of different frequency-cutting control signals SW, the frequency of the turn-on pulses appearing in the scanning signals OUT output by each scanning output module 13 in each stage of the shift register 10 can be controlled, so as to realize the display of different frequencies in the column direction of the display panel.

[0260] In the above embodiments, the structures of the LTPO pixel circuit and its corresponding scanning driving circuit are exemplarily given, but they are not used as limitations on the present invention. In other embodiments, as Figure 16 shown, after replacing both the threshold compensation transistor M25 and the gate initialization transistor M22 with P-type transistors, all the transistors in the pixel circuit 20 are P-type transistors, forming an LTPS pixel circuit. The corresponding driving timing can be referred to Figure 17 , and the turn-on potentials of the first control signal S1 and the second control signal S2 both become low potentials. The specific driving process can still refer to the driving process of the LTPO pixel circuit and will not be repeated here. Figure 17 And Figure 10Another difference lies in that: the third control signal S3 can also be a high-frequency signal. Then, in each black insertion stage T24, when the third control signal S3 is at a low potential, the data writing transistor M24 can be controlled to conduct, and the data voltage Vdata is transmitted to the first pole of the driving transistor DTFT, so as to reset the first pole of the driving transistor DTFT, and try to make the driving transistor DTFT restore the same characteristics as those in the refresh frame FA.

[0261] According to Figure 17 it can be known that Figure 16 in the driving process of the pixel circuit 20 in, the first control signal S1 and the second control signal S2 where the conduction pulses are misaligned need to be conducted. Therefore, a scan driving circuit 100 capable of outputting a high-potential scan signal for a long time can be correspondingly set to provide the first control signal S1 and the second control signal S2, and still adopt the specific connection method of the scan driving circuit 100 and the pixel circuit 20 in Figure 8 to drive each row of pixel circuits 20. In addition, when the third control signal S3 is a low-frequency signal, the second control signal S2 can also be multiplexed as the third control signal S3; when the fourth control signal S4 is a low-frequency signal, the first control signal S1 or the second control signal S2 can also be multiplexed as the fourth control signal S4. Then, only a circuit for providing the light emission control signal EM needs to be further set at the position of the display panel border, which can further simplify the panel structure and reduce the panel border.

[0262] Next, the structure of the scan driving circuit 100 capable of outputting a high-potential scan signal for a long time (that is, the conduction pulse output by the scan output module 13 is at a low potential) will be described. Figure 18 is a schematic structural diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 18 , in one embodiment, optionally, the driving control module 11 controls the potentials of the first output terminal N1 and the second output terminal N2 in response to the fourth clock signal SCK1, the third clock signal SCK2, the input signal IN, the first potential signal VGL, and the second potential signal VGH. The stage transmission output module 12 outputs the second potential signal VGH or the third clock signal SCK2 as the stage transmission signal Carry according to the potentials of the first output terminal N1 and the second output terminal N2. For any scan output module, the transmission control unit 1301 is used to control whether the potential of the first output terminal N1 is transmitted to the third connection terminal N3 according to the frequency conversion control signal; the scan output unit 1302 is used to output the second potential signal VGH or the third clock signal SCK2 as the scan signal OUT in response to the potentials of the third connection terminal N3 and the second output terminal N2. Exemplarily, both the fourth clock signal SCK1 and the third clock signal SCK2 are clock signals with alternating high and low potentials.

[0263] Specifically, refer to Figure 19, the drive control module 11 includes: a second input unit 1121, a third control unit 1122, a fourth node control unit 1123, and a fifth node control unit 1124.

[0264] Among them, the second input unit 1121 includes a transistor M41. The gate of the transistor M41 is connected to the fourth clock signal SCK1, the first pole is connected to the input signal IN, and the second pole is connected to the first output terminal N1. The second input unit 1121 is configured to transmit the input signal IN to the first output terminal N1 in response to the fourth clock signal SCK1.

[0265] The third control unit 1122 includes a transistor M42. The gate of the transistor M42 is connected to the fourth clock signal SCK1, the first pole is connected to the first potential signal VGL, and the second pole is connected to the second output terminal N2. The third control unit 1122 is configured to transmit the first potential signal VGL to the second output terminal N2 in response to the fourth clock signal SCK1.

[0266] The fourth node control unit 1123 includes a transistor M43. The gate of the transistor M43 is connected to the first output terminal N1, the first pole is connected to the four clock signal SCK1, and the second pole is connected to the second output terminal N2. The fourth node control unit 1123 is configured to transmit the fourth clock signal SCK1 to the second output terminal N2 in response to the potential of the first output terminal N1.

[0267] The fifth node control unit 1124 includes transistors M44 and M45; the gate of the transistor M44 is connected to the second output terminal N2, the first pole is connected to the second potential signal VGH, and the second pole is connected to the first pole of the transistor M45; the gate of the transistor M45 is connected to the third clock signal SCK2, and the second pole is connected to the first output terminal N1. The fifth node control unit 1124 is configured to transmit the second potential signal VGH to the first output terminal N1 in response to the third clock signal SCK2 and the potential of the second output terminal N2.

[0268] The stage transmission output module 12 includes: a third output unit 123 and a fourth output unit 124. Among them, the third output unit 123 includes a transistor M47 and a capacitor C22. The gate of the transistor M47 is connected to the first output terminal N1, the first pole is connected to the third clock signal SCK2, and the second pole is connected to the output terminal of the stage transmission output module 12; the capacitor C22 is connected between the gate and the second pole of the transistor M47. The third output unit 123 is used to transmit the third clock signal SCK2 to the output terminal of the stage transmission output module 12 in response to the potential of the first output terminal N1. The fourth output unit 124 includes a transistor M48 and a capacitor C23. The gate of the transistor M48 is connected to the second output terminal N2, the first pole is connected to the second potential signal VGH, and the second pole is connected to the output terminal of the stage transmission output module 12; the capacitor C23 is connected between the gate and the first pole of the transistor M48. The fourth output unit 124 is used to transmit the second potential signal VGH to the output terminal of the stage transmission output module 12 in response to the potential of the second output terminal N2.

[0269] Based on the above embodiments, optionally, for any scanning output module:

[0270] The transmission control unit 1301 includes: a sixth transistor M6; the gate of the sixth transistor M6 is connected to the frequency switching control signal SW, the first pole of the sixth transistor M6 is connected to the first connection terminal, the first connection terminal is connected to the first output terminal N1, and the second pole of the sixth transistor M6 is connected to the third connection terminal N3.

[0271] The scanning output unit 1302 includes: a seventh transistor M7, an eighth transistor M8, and a second capacitor C2; the gate of the seventh transistor M7 is connected to the third connection terminal N3, the first pole of the seventh transistor M7 is connected to the third clock signal SCK2, the second pole of the seventh transistor M7 is connected to the output terminal of the scanning output unit 1302; the second capacitor C2 is connected between the gate and the second pole of the seventh transistor M7; the gate of the eighth transistor M8 is connected to the second output terminal N2, the first pole of the eighth transistor is connected to the second potential signal VGH, and the second pole of the eighth transistor M8 is connected to the output terminal of the scanning output unit 1302.

[0272] Next, based on Figure 19 the structure of the shift register 10 in Figure 20 take the transistors in the shift register 10 as P-type transistors as an example, and combine Figure 20 to illustrate the driving process of the shift register 10. Among them, to fully illustrate the working process of the circuit, Figure 19 and Figure 20, first, taking the working process of the first scanning output module 131 as an example, the control method in the first working mode will be described.

[0273] Exemplarily, in the first working mode, the first frequency-switching control signal SW1 remains at a low potential, causing the sixth transistor M6 to remain conducting in this display frame, such that the potential of the third connection terminal N3 changes synchronously with the potential VN1 of the first output terminal N1, thereby enabling the scanning output unit 1302 in the first scanning output module 131 to have the same output state as the stage transmission output module 12 and output signals with the same waveform. Exemplarily, the driving process of the shift register 10 includes:

[0274] In the first stage T31, the fourth clock signal SCK1, the input signal IN, and the first frequency-switching control signal SW1 are all at low potentials, and the third clock signal SCK2 is at a high potential. The transistors M41 and M42 are conducting, and the transistor M45 is off. The low potential of the input signal IN is transmitted to the first output terminal N1 through the transistor M41, controlling the transistors M43 and M47 to conduct, and the transistor M47 outputs the high potential of the third clock signal SCK2. The low potential of the fourth clock signal SCK1 is transmitted to the second output terminal N2 through the transistor M43, and the low potential of the first potential signal VGL is transmitted to the second output terminal N2 through the transistor M42, causing the transistor M48 to conduct and output the high potential of the second potential signal VGH. Therefore, the stage transmission signal Carry is at a high potential. Correspondingly, the seventh transistor M7 and the eighth transistor M8 are also both conducting, making the first scanning signal OUT1 also at a high potential.

[0275] In the second stage T32, the third clock signal SCK2 is at a low potential, and the fourth clock signal SCK1 and the input signal IN are both at high potentials. The transistors M41 and M42 are off, and the transistor M45 is conducting. Due to the storage effect of the capacitor C22, the first output terminal N1 maintains the low potential of the previous stage, causing the transistor M43 to conduct and transmit the high potential of the fourth clock signal SCK1 to the second output terminal N2, further causing the transistors M48 and the eighth transistor M8 to both be off. At the same time, the low potential of the first output terminal N1 causes the transistor M47 to conduct and output the low potential of the third clock signal SCK2. Since the stage transmission signal Carry changes from a high potential to a low potential, based on the coupling effect of the capacitor C22, the potential of the first output terminal N1 further decreases, enabling the stable output of the low potential of the stage transmission signal Carry. Correspondingly, the seventh transistor M7 is conducting and outputs the low potential of the third clock signal SCK2 as the scanning signal, and the second capacitor C2 plays a role similar to that of the second capacitor C22, controlling the stable output of the low potential of the first scanning signal OUT1.

[0276] In the third stage T33, the fourth clock signal SCK1 is at a low potential, and the third clock signal SCK2 and the input signal IN are both at high potentials. The transistors M41 and M42 are turned on, and the transistor M45 is turned off. The high potential of the input signal IN is transmitted to the first output terminal N1 through the transistor M41. The high potential of the first output terminal N1 controls the transistors M43, M47, and the seventh transistor M7 to be turned off. The low potential of the first potential signal VGL is transmitted to the second output terminal N2 through the transistor M42, causing the transistors M48 and the eighth transistor M8 to be turned on, and both output the high potential of the second potential signal VGH. Therefore, in this stage, both the carry signal Carry and the first scan signal OUT1 are at high potentials.

[0277] In the fourth stage T34, the third clock signal SCK2 is at a low potential, and the fourth clock signal SCK1 and the input signal IN are both at high potentials. The transistors M41 and M42 are turned off, and the transistor M45 is turned on. Due to the storage effect of the capacitor C23, the second output terminal N2 maintains the low potential of the previous stage, causing the transistor M44 to be turned on. The high potential of the second potential signal VGH is transmitted to the first output terminal N1 along the transistors M44 and M45, controlling the transistors M43, M47, and the seventh transistor M7 to be turned off. At the same time, the low potential of the second output terminal N2 controls the eighth transistor M8 and the transistor M48 to be turned on, and both output the high potential of the second potential signal VGH. Therefore, in this stage, both the carry signal Carry and the first scan signal OUT1 remain at high potentials.

[0278] The driving processes of the third stage T33 and the fourth stage T34 are repeated in subsequent stages until the input signal IN jumps to a low potential again.

[0279] The above embodiments exemplarily show that when the first scan output module 131 operates in the first operating mode, the first frequency switching control signal SW1 remains at the low potential VL throughout the display frame, but this is not a limitation on the present invention. In other embodiments, as long as it is ensured that the first frequency switching control signal SW1 is at a low potential in the second stage T32, so that the seventh transistor M7 can normally output the low potential of the third clock signal SCK2.

[0280] Taking the working process of the second scan output module 132 as an example below, the control method in the second operating mode will be described. The following mainly describes the differences in the driving processes between the second operating mode and the first operating mode, and the same parts will not be repeated.

[0281] Specifically, in the second operating mode, the rising edge of the second frequency switching control signal SW2 is set before the potential VN1 at the first output terminal N1 jumps to a low potential, and the falling edge of the second frequency switching control signal SW2 is set after the potential VN1 at the first output terminal N1 jumps to a high potential, so that the low potential at the first output terminal N1 cannot be transmitted to the third connection terminal N3. Then, the third connection terminal N3 always maintains a high potential in this display frame, causing the seventh transistor M7 to always remain off. Therefore, in the second operating mode, the second scan signal OUT2 always maintains a high potential.

[0282] Continue to refer to Figure 19 , based on the above embodiments, optionally, the shift register 10 may further include: a transistor M46 connected between the first output terminal N1 and the gate of the transistor M47, and the gate of the transistor M46 is connected to the first potential signal VGL. The transistor M46 is used to prevent the excessively low potential at the gate of the transistor M47 from being transmitted to the first output terminal N1, avoiding damage to the transistors connected to the first output terminal N1 due to excessive voltage stress. Exemplarily, after adding the transistor M46, the first connection terminal of each transmission control unit 1301 can still be directly connected to the first output terminal N1, or can be connected to the first output terminal N1 through the transistor M46.

[0283] Based on the same principle, optionally, the transmission control unit 1301 may further be provided with: an eleventh transistor M11; the eleventh transistor M11 is connected between the second pole of the sixth transistor M6 and the third connection terminal N3, and the gate of the eleventh transistor M11 is connected to the first potential signal VGL. The eleventh transistor M11 is used to prevent the excessively low potential at the third connection terminal N3 from being transmitted forward.

[0284] Based on the above embodiments, optionally, the transmission control unit 1301 further includes: a ninth transistor M9; the gate of the ninth transistor M9 is connected to a first switching signal (marked as SK11 in the first scan output module 131 and marked as SK12 in the second scan output module 132), the first pole of the ninth transistor M9 is connected to a second potential signal VGH, and the second pole of the ninth transistor M9 is connected to a third connection terminal N3. The ninth transistor M9 is configured to transmit the second potential signal VGH to the third connection terminal N3 in response to the first switching signal, specifically, when the scan output module where it is located operates in the second operating mode, when the sixth transistor M6 is turned off, it timely provides the cut-off potential for the gate of the seventh transistor M7 to ensure that the seventh transistor M7 remains in the off state when the sixth transistor M6 is turned off. Exemplarily, the gates of the ninth transistors M9 in each scan output module in the same scan output group can be connected to the same first switching signal. Wherein, when the channel types of the sixth transistor M6 and the ninth transistor M9 are the same, the frequency switching control signal and the first switching signal can be set as inverted signals with opposite high and low potentials; or, when the channel types of the sixth transistor M6 and the ninth transistor M9 are different, the frequency switching control signal can be multiplexed as the first switching signal to reduce the signal lines required by the scan driving circuit and simplify the wiring of the display panel.

[0285] Based on the above embodiments, optionally, the transmission control unit 1301 further includes: a tenth transistor M10; the gate of the tenth transistor M10 is connected to a second switching signal (marked as SK21 in the first scan output module 131 and marked as SK22 in the second scan output module 132), the first pole of the tenth transistor M10 is connected to a first potential signal VGL, and the second pole of the tenth transistor M10 is connected to a third connection terminal N3. The tenth transistor M10 is configured to transmit the first potential signal VGL to the third connection terminal N3 in response to the second switching signal, specifically, when the scan output module where it is located operates in the first operating mode, after the start of the first stage T31 and before the start of the second stage T32, it timely provides the conduction potential of the seventh transistor M7 for the gate of the seventh transistor M7. Exemplarily, the input signal IN can be multiplexed as the second switching signal SK21 required by the first scan output module 131 and / or the second switching signal SK22 required by the second scan output module 132 to simplify the wiring of the display panel.

[0286] When using Figure 19 the shown shift register 10 structure and cooperating with Figure 8 the shown display panel structure, the driving timing of the display panel can be referred to Figure 21 . Figure 21 Similarly, the case where the refresh frequencies of the pixel circuits 20 in the first row and the third row are both higher than the refresh frequency of the pixel circuit 20 in the second row is also given.

[0287] See Figure 21 It can be seen that in display frame F1, data refreshing is performed on all three rows of pixel circuits 20, and corresponding scan signals all include conduction pulses. Specifically, the first-stage first scan signal OUT11 to the third-stage first scan signal OUT13 all include conduction pulses, and the second-stage second scan signal OUT22 to the fourth-stage second scan signal OUT24 all include conduction pulses.

[0288] In display frame F2, data refreshing is performed on the first row and the third row of pixel circuits 20, and corresponding scan signals all include conduction pulses; data refreshing is not performed on the second row of pixel circuits 20, and corresponding scan signals do not include conduction pulses. Specifically, the first-stage first scan signal OUT11 and the second-stage second scan signal OUT22 both have conduction pulses; the second-stage first scan signal OUT12 and the third-stage second scan signal OUT23 do not include conduction pulses; the third-stage first scan signal OUT13 and the fourth-stage second scan signal OUT24 both have conduction pulses. Then, the high-potential holding stage of the first frequency-cutting control signal SW1 covers the conduction pulse of the second-stage carry signal Carry2, so that the second-stage first scan signal OUT12 has no conduction pulse. The high-potential holding stage of the second frequency-cutting control signal SW2 covers the conduction pulse of the third-stage carry signal Carry3, so that the third-stage second scan signal OUT23 has no conduction pulse.

[0289] In summary, by controlling the potential jump time of different frequency-cutting control signals SW, the frequency of the conduction pulses appearing in the scan signals OUT output by each scan output module 13 in each stage of the shift register 10 can be controlled, so as to realize the display of different frequencies in the column direction of the display panel.

[0290] In the above embodiments, the specific connection manners of the scan driving circuit 100 for providing the first control signal S1 and the second control signal S2 and the pixel circuit 20 are exemplarily given. In addition, driving circuits for providing the third control signal S3, the fourth control signal S4, and the light-emitting control signal EM need to be respectively arranged at corresponding positions on the border of the display panel. Among them, the driving circuit for providing the light-emitting control signal EM can adopt any existing structure of the light-emitting control driving circuit, which will not be elaborated here. Below, the setting manners of the driving circuits for providing the third control signal S3 and the fourth control signal S4 will be mainly described in combination with different structures of the pixel circuit 20.

[0291] For the LTPO pixel circuit as Figure 9 shown:

[0292] When it is necessary to provide the third control signal S3 and the fourth control signal S4 as Figure 10 shown:

[0293] In one embodiment, optionally, two sets of driving circuits may be provided to respectively provide a third control signal S3 and a fourth control signal S4. Specifically, the shift register unit in the driving circuit for providing the third control signal S3 may adopt a structure similar to that of the shift register in Figure 13 , but only one scan output module is retained to provide the third control signal S3. The shift register unit in the driving circuit for providing the fourth control signal S4 may adopt a shift register circuit with a long-time output high potential of any existing structure, such as a shift register circuit with an 8T2C structure.

[0294] In another embodiment, optionally, one set of driving circuits may be adopted to simultaneously provide the third control signal S3 and the fourth control signal S4. Specifically, the shift register unit in this driving circuit may adopt a structure similar to that of the shift register in Figure 19 , but only one scan output module is retained. In each shift register unit, the scan signal output by the scan output module serves as the third control signal S3, and the stage transmission signal output by the stage transmission output module serves as the fourth control signal S4.

[0295] When it is necessary to provide the third control signal S3 and the fourth control signal S4 that are both high-frequency, one set of driving circuits may be adopted to simultaneously provide the third control signal S3 and the fourth control signal S4. Specifically, the shift register unit in this driving circuit may adopt a shift register circuit with a long-time output high potential of any existing structure, such as a shift register circuit with an 8T2C structure. Among them, the scan signal output by the first-level shift register unit may serve as the third control signal S3 and the fourth control signal S4 required by the same row of pixel circuits 20, or respectively serve as the third control signal S3 required by one row of pixel circuits 20 and the fourth control signal S4 required by another row of pixel circuits 20. The specific setting method may be determined according to actual requirements.

[0296] For the LTPS pixel circuit as shown in Figure 16 :

[0297] When it is necessary to provide the third control signal S3 and the fourth control signal S4 as shown in Figure 17 :

[0298] In one embodiment, optionally, one set of additional driving circuits may be adopted to simultaneously provide the third control signal S3 and the fourth control signal S4. Specifically, the shift register unit in this driving circuit may adopt a shift register circuit with a long-time output high potential of any existing structure, such as a shift register circuit with an 8T2C structure.

[0299] In another embodiment, optionally, the carry signals Carry at all levels in the scan driving circuit 100 may be utilized to provide the third control signal S3 and / or the fourth control signal S4 that always maintain a high frequency for the pixel circuit 20, so as to simplify the structure of the display panel. Figure 22 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 22 , in one embodiment, optionally, on the basis of the Figure 8 connection method, the (j + 1)-th level carry signal may also be used as the third control signal S3 required by the j-th row of pixel circuits 20, so as to provide the high-frequency third control signal S3, and ensure that in the refresh frame FA, the conduction pulse of the third control signal S3 overlaps with the conduction pulse of the second control signal S2, ensuring the normal progress of the data writing process. Moreover, the third control signal S3 in the same pixel circuit 20 can be multiplexed as the fourth control signal S4, that is, the (j + 1)-th level carry signal can simultaneously serve as the fourth control signal S4 required by the j-th row of pixel circuits 20, so as to provide the high-frequency fourth control signal S4. Alternatively, in other embodiments, the j-th level carry signal may also be set as the fourth control signal S4 required by the j-th row of pixel circuits 20, and similarly, the normal execution of each driving stage of the pixel circuit 20 can be controlled.

[0300] When a low-frequency third control signal S3 needs to be provided, the second control signal S2 required by the pixel circuit 20 can be multiplexed as the third control signal S3; when a low-frequency fourth control signal S4 needs to be provided, the first control signal S1 or the second control signal S2 required by the pixel circuit 20 can be multiplexed as the fourth control signal S4.

[0301] An embodiment of the present invention also provides a display device, including the scan driving circuit provided by any embodiment of the present invention, and having corresponding beneficial effects. Figure 23 is a schematic structural diagram of a display device provided by an embodiment of the present invention. Refer to Figure 23 , exemplarily, the display device may include a display panel and a driving chip 50. The scan driving circuit 100 and the pixel circuit 20 are both disposed in the display panel. Taking each shift register 10 including two scan output modules as an example, the scan driving circuit 100 can respectively provide the first control signal and the second control signal to each row of pixel circuits 20 through each first scan line LS1 and second scan line LS2. The driving chip 50 can respectively provide the first frequency-cutting control signal and the second frequency-cutting control signal to different scan output modules in each shift register 10 through the first frequency-cutting signal line LSW1 and the second frequency-cutting signal line LSW2. In addition, the driving chip 50 can also provide an input signal to the first-stage shift register 10 in the scan driving circuit 100 through the input signal line LIN, and provide a data voltage to each column of pixel circuits 20 through each data line LD.

[0302] Based on the above embodiments, optionally, the pixel circuit 20 includes: a driving module, a threshold compensation module, and a gate reset module; the gate reset module is connected to the control end of the driving module, and the threshold compensation module is connected between the control end and the output end of the driving module. The specific connection relationship between each stage shift register 10 in the scan driving circuit 100 and each row of pixel circuits 20 can be: one scan output module of the shift register 10 is connected to the control end of the gate reset module in one row of pixel circuits, and another scan output module of the shift register is connected to the control end of the threshold compensation module in another row of pixel circuits. Wherein, the other row of pixel circuits is the first row or the i-th row of pixel circuits before the above-mentioned one row of pixel circuits, and i>1.

[0303] Furthermore, the pixel circuit further includes a data writing module and an anode reset module. The data writing module is connected to the input end of the driving module; the anode reset module is connected to the anode of the light-emitting device. When the data writing module, the anode reset module, the gate reset module, and the threshold compensation module include transistors of the same channel type, and the shift register 10 includes a stage transfer output module, the stage transfer output module in the shift register 10 is further connected to the control end of the data writing module and / or the control end of the anode reset module.

[0304] It should be noted that in each embodiment of the scan driving circuit, specific descriptions are made for the structures of different display panels, and these can all be regarded as the specific structures of the display panel in the display device provided by the embodiments of the present invention. The repeated content will not be elaborated here.

[0305] The embodiments of the present invention further provide a driving method for a display device, which is used to drive the display device provided by any embodiment of the present invention to perform sub-region frequency division display in the column direction; the driving method includes:

[0306] According to the target display partition position of the display device in the column direction, control the potential jump time of each frequency division control signal in one frame of display, so that the frequency of the conduction pulses appearing in the scan signal output by the scan output module connected to the pixel circuit above the target display partition position is different from the frequency of the conduction pulses appearing in the scan signal output by the scan output module connected to the pixel circuit below the target display partition position; and make the frequency of the conduction pulses appearing in the scan signals output by all the scan output modules connected to the same pixel circuit the same.

[0307] It should be noted that in each embodiment of the scan driving circuit, specific descriptions are made for the driving methods of different display devices, and these can all be regarded as the driving methods of the display device provided by the embodiments of the present invention. The repeated content will not be elaborated here.

[0308] It should be understood that the various forms of processes shown above can be used, with steps reordered, added or deleted. For example, the steps described in the present utility model can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present utility model can be achieved, and no limitation is imposed herein.

[0309] The above specific embodiments do not constitute a limitation on the protection scope of the present utility model. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A scanning driving circuit, characterized in that, Comprising: A plurality of cascaded shift registers; The n-th stage shift register among the plurality of shift registers includes: A drive control module for controlling the potentials of the first output terminal and the second output terminal of the drive control module according to the input signal accessed by the shift register; A scan output module, and the scan output module includes: A transmission control unit including an internal node and a third connection terminal, and the internal node is used to control whether the second output terminal is conducted with the third connection terminal; A scan output unit, the first control terminal of the scan output unit is connected to the third connection terminal, and the second control terminal of the scan output unit is connected to the first output terminal; the scan output unit is used to output a scan signal according to the potentials of the first control terminal and the second control terminal; wherein, n is an integer greater than 0; A voltage stabilizing unit, the first end of the voltage stabilizing unit is connected to the internal node of the transmission control unit, and the voltage stabilizing unit is used to store the potential of the internal node of the transmission control unit.

2. The scanning drive circuit according to claim 1, wherein The transmission control unit further includes a first connection terminal and a second connection terminal, the first connection terminal of the transmission control unit is connected to the second output terminal, and the second connection terminal of the transmission control unit accesses a frequency-cutting control signal; the transmission control unit is used to control the potential of the third connection terminal of the transmission control unit according to the potentials of the first connection terminal and the second connection terminal; The frequency-cutting control signal is used to control the frequency at which a conduction pulse appears in the scan signal output by the scan output module.

3. The scanning drive circuit according to claim 2, wherein The second end of the voltage stabilizing unit is connected to the output terminal of the scan output unit, and the voltage stabilizing unit is used to transmit a first potential signal to the output terminal of the scan output unit when the scan signal outputs a non-conduction pulse; wherein, the potential corresponding to the conduction pulse of the scan signal is a second potential signal, and the first potential signal and the second potential signal are high and low level signals with respect to each other.

4. The scanning driving circuit according to claim 3, wherein The n-th stage shift register among the plurality of shift registers further includes: a stage transmission output module respectively connected to the first output terminal and the second output terminal, and is used to output a stage transmission signal in response to the potentials of the first output terminal and the second output terminal; the stage transmission signal serves as an input signal for the (n + s)-th stage shift register; Wherein, s is an integer greater than 0.

5. The scanning drive circuit according to claim 4, wherein, s＝1。 6. The scanning drive circuit according to claim 4, wherein The conduction pulse output by the scan output unit is at a high potential; The transmission control unit includes: a first transistor and a second transistor; the gate of the first transistor is connected to the output terminal of the stage transmission output module, the first pole of the first transistor accesses the frequency-cutting control signal, and the second pole of the first transistor is connected to the gate of the second transistor; the first pole of the second transistor is connected to the first connection terminal, the first connection terminal is connected to the second output terminal, and the second pole of the second transistor is connected to the third connection terminal; The scanning output unit includes: a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is connected to the first output terminal, a first pole of the third transistor receives a first potential signal, and a second pole of the third transistor is connected to an output terminal of the scanning output unit; a gate of the fourth transistor is connected to the third connection terminal, a first pole of the fourth transistor receives a second potential signal, and a second pole of the fourth transistor is connected to the output terminal of the scanning output unit; the first capacitor is connected between the gate and the first pole of the fourth transistor; The voltage stabilizing unit includes: a third capacitor and a twelfth transistor, a first end of the third capacitor receives a fixed potential signal, and a second end of the third capacitor is connected to the second pole of the first transistor; A gate of the twelfth transistor is connected to the second pole of the first transistor, a first pole of the twelfth transistor receives the first potential signal, and a second pole of the twelfth transistor is connected to the output terminal of the scanning output unit; the twelfth transistor has a channel type different from that of the second transistor.

7. The scanning drive circuit according to claim 6, wherein The transmission control unit further includes a fifth transistor; a gate of the fifth transistor is connected to the first output terminal, a first pole of the fifth transistor receives the second potential signal, and a second pole of the fifth transistor is connected to the third connection terminal.

8. The scanning drive circuit according to claim 4, wherein The drive control module includes: a first input unit, connected to the first output terminal, for responding to a first clock signal and transmitting the input signal to the first output terminal; a first control unit, for responding to the first clock signal and transmitting the first potential signal to an output terminal of the first control unit; a second control unit, connected between the output terminal of the first control unit and the second output terminal, for controlling the potential of the second output terminal according to a second clock signal and the potential of the output terminal of the first control unit; a first node control unit, respectively connected to the first output terminal and the output terminal of the first control unit, for controlling the potential of the output terminal of the first control unit according to the potential of the first output terminal; a second node control unit, respectively connected to the first output terminal and the output terminal of the first control unit, for controlling the potential of the first output terminal according to the potential of the output terminal of the first control unit; a third node control unit, respectively connected to the first output terminal and the second output terminal, for controlling the potential of the second output terminal according to the potential of the first output terminal; The stage transmission output module includes: a first output unit, connected to the first output terminal, for responding to the potential of the first output terminal and transmitting the first potential signal to an output terminal of the stage transmission output module; a second output unit, connected to the second output terminal, for responding to the potential of the second output terminal and transmitting the second potential signal to the output terminal of the stage transmission output module.

9. The scanning drive circuit according to claim 2, wherein, Each of the shift registers is connected to a row of pixel circuits; Each of the frequency-cutting control signals controls the frequency at which the conduction pulse appears in the scan signal output by the scan output unit connected to the pixel circuit above the display partition position according to the display partition position of the display panel in the column direction, which is different from the frequency at which the conduction pulse appears in the scan signal output by the scan output unit connected to the pixel circuit below the display partition position.

10. The scanning driving circuit according to any one of claims 2-9, characterized in that, Each transmission control unit accesses the same frequency-cutting control signal; The frequency-cutting control signal undergoes a potential jump in at least some display frames, so that the frequencies at which the conduction pulse appears in the scan signals output by at least two of the scan output units are different.

11. The scanning drive circuit according to claim 10, characterized in that, Each of the scan output units is respectively connected to the same functional module of each row of pixel circuits.

12. A scanning driving circuit, characterized in that, It includes: A plurality of cascaded shift registers; The nth-stage shift register among the plurality of shift registers includes: A drive control module for controlling the potentials of the first output terminal and the second output terminal of the drive control module according to the input signal accessed by the shift register; At least two scan output modules, the scan output modules are connected to the first output terminal and the second output terminal and access the frequency-cutting control signal, and the scan output modules are used for outputting scan signals; wherein, different scan output modules access different frequency-cutting control signals, and different frequency-cutting control signals are respectively used for controlling the frequency at which the conduction pulse appears in the scan signals output by the corresponding scan output modules, where n is an integer greater than 0.

13. The scanning driving circuit according to claim 12, wherein The nth-stage shift register among the plurality of shift registers further includes: a stage transmission output module, which is respectively connected to the first output terminal and the second output terminal, and is used for outputting a stage transmission signal in response to the potentials of the first output terminal and the second output terminal; the stage transmission signal serves as the input signal of the (n + s)th-stage shift register; Wherein, s is an integer greater than 0.

14. The scanning driving circuit according to claim 13, wherein s＝1。 15. The scanning driving circuit according to claim 12, wherein At least two of the scan output modules in the same stage of the shift register are respectively connected to at least two rows of pixel circuits, and some of the scan output modules in at least two stages of the shift register are connected to the same row of pixel circuits; Each of the frequency-cutting control signals controls the frequency at which the conduction pulse appears in the scan signal output by the scan output module connected to the pixel circuit above the display partition position according to the display partition position of the display panel in the column direction, which is different from the frequency at which the conduction pulse appears in the scan signal output by the scan output module connected to the pixel circuit below the display partition position.

16. The scanning driving circuit according to any one of claims 12-15, wherein One scan output group in the scan driving circuit includes one scan output module in each stage of the shift register, and different scan output modules in the same stage of the shift register belong to different scan output groups; each of the scan output modules in the same scan output group accesses the same frequency-cutting control signal; Wherein, for any one of the scan output groups, the frequency-cutting control signal undergoes a potential jump in at least some display frames, so that the frequencies at which the conduction pulse appears in the scan signals output by at least two scan output modules in the scan output group are different.

17. The scanning driving circuit according to claim 16, wherein Each of the scanning output modules in the same scanning output group is respectively connected to the same functional module of each row of pixel circuits; the multiple scanning output modules connected to different functional modules in the same pixel circuit belong to different scanning output groups.

18. The scanning drive circuit according to claim 16, wherein The first-stage shift register includes two scanning output modules, namely a first scanning output module and a second scanning output module; The output end of the nth-stage first scanning output module is connected to the nth row of pixel circuits, and the conduction pulse output by the nth-stage first scanning output module acts on the first stage of the nth row of pixel circuits; the output end of the (n + m)th-stage second scanning output module is connected to the nth row of pixel circuits, and the conduction pulse output by the (n + m)th-stage second scanning output module acts on the second stage of the nth row of pixel circuits; where, for the same pixel circuit, in the same display frame, the first stage occurs before the second stage, and m is an integer greater than 0.

19. The scanning drive circuit according to claim 18, wherein, The first stage is a reset stage, and the second stage is a data writing stage.

20. The scanning driving circuit according to claim 18, wherein m＝1。 21. The scanning drive circuit according to claim 18, characterized in that, In one-frame display, when the scanning signals output by the first scanning output modules from the ith stage to the (i + k)th stage have the conduction pulse, the scanning signals output by the second scanning output modules from the (i + m)th stage to the (i + m + k)th stage have the conduction pulse; where, both i and k are integers greater than 0.

22. The scanning drive circuit according to claim 18, wherein Define the frequency-cutting control signal accessed by the first scanning output module as the first frequency-cutting control signal, and define the frequency-cutting control signal accessed by the second scanning output module as the second frequency-cutting control signal; When the display partition position is between the ith row of pixel circuits and the (i + 1)th row of pixel circuits, in some display frames, the first frequency-cutting control signal undergoes a potential jump before the ith-stage first scanning output module outputs a conduction pulse, so that the frequency of the conduction pulse appearing in the scanning signal output by the ith-stage first scanning output module is different from the frequency of the conduction pulse appearing in the scanning signal output by the (i + 1)th-stage first scanning output module, realizing sub-region frequency division display of the display panel in the column direction; i is an integer greater than 0; And, corresponding to the display frame in which the first frequency-cutting control signal undergoes the potential jump, the second frequency-cutting control signal undergoes a potential jump before the (i + m)th-stage second scanning output module outputs a conduction pulse, so that the frequency of the conduction pulse appearing in the scanning signal output by the second scanning output module connected to each row of pixel circuits is the same as the frequency of the conduction pulse appearing in the scanning signal output by the first scanning output module connected to the corresponding row of pixel circuits.

23. The scanning driving circuit according to claim 13, wherein, The scanning output module includes: A transmission control unit, the first connection end of the transmission control unit is connected to one of the first output end and the second output end, and the second connection end of the transmission control unit accesses the frequency-cutting control signal; the transmission control unit is used to control the potential of the third connection end of the transmission control unit according to the potentials of the first connection end and the second connection end; A scan output unit, wherein a first control terminal of the scan output unit is connected to the third connection terminal, and a second control terminal of the scan output unit is connected to the other one of the first output terminal and the second output terminal; the scan output unit is configured to output the scan signal according to potentials of the first control terminal and the second control terminal.

24. The scanning drive circuit according to claim 23, wherein The conduction pulse output by the scan output module is at a high potential; The transmission control unit includes: a first transistor and a second transistor; a gate of the first transistor is connected to an output terminal of the stage transmission output module, a first pole of the first transistor accesses the frequency cutting control signal, and a second pole of the first transistor is connected to a gate of the second transistor; a first pole of the second transistor is connected to the first connection terminal, the first connection terminal is connected to the second output terminal, and a second pole of the second transistor is connected to the third connection terminal; The scan output unit includes: a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is connected to the first output terminal, a first pole of the third transistor accesses a first potential signal, and a second pole of the third transistor is connected to an output terminal of the scan output unit; a gate of the fourth transistor is connected to the third connection terminal, a first pole of the fourth transistor accesses a second potential signal, and a second pole of the fourth transistor is connected to the output terminal of the scan output unit; the first capacitor is connected between the gate and the first pole of the fourth transistor.

25. The scanning drive circuit according to claim 24, wherein The transmission control unit further includes a fifth transistor; a gate of the fifth transistor is connected to the first output terminal, a first pole of the fifth transistor accesses the second potential signal, and a second pole of the fifth transistor is connected to the third connection terminal.

26. The scanning drive circuit according to claim 24, wherein, At least one of the at least two scan output modules further includes: a third capacitor; a first end of the third capacitor accesses a fixed potential signal, and a second end of the third capacitor is connected to a second pole of the first transistor.

27. The scanning driving circuit according to claim 24, wherein At least one of the at least two scan output modules further includes: a twelfth transistor; a gate of the twelfth transistor is connected to a second pole of the first transistor, a first pole of the twelfth transistor accesses the first potential signal, and a second pole of the twelfth transistor is connected to an output terminal of the scan output unit; the twelfth transistor has a channel type different from that of the second transistor.

28. The scanning driving circuit according to claim 24, wherein The drive control module includes: A first input unit, connected to the first output terminal, configured to transmit the input signal to the first output terminal in response to a first clock signal; A first control unit, configured to transmit the first potential signal to an output terminal of the first control unit in response to the first clock signal; A second control unit, connected between the output terminal of the first control unit and the second output terminal, configured to control a potential of the second output terminal according to a second clock signal and a potential of the output terminal of the first control unit; A first node control unit, respectively connected to the first output terminal and the output terminal of the first control unit, configured to control the potential of the output terminal of the first control unit according to the potential of the first output terminal; A second node control unit, respectively connected to the first output terminal and the output terminal of the first control unit, for controlling the potential of the first output terminal according to the potential of the output terminal of the first control unit; A third node control unit, respectively connected to the first output terminal and the second output terminal, for controlling the potential of the second output terminal according to the potential of the first output terminal; The stage transmission output module includes: A first output unit, connected to the first output terminal, for responding to the potential of the first output terminal and transmitting the first potential signal to the output terminal of the stage transmission output module; A second output unit, connected to the second output terminal, for responding to the potential of the second output terminal and transmitting the second potential signal to the output terminal of the stage transmission output module.

29. The scanning driving circuit according to claim 23, wherein The conduction pulse output by the scan output module is at a low potential; The transmission control unit includes: a sixth transistor; the gate of the sixth transistor is connected to the frequency cutting control signal, the first pole of the sixth transistor is connected to the first connection terminal, the first connection terminal is connected to the first output terminal, and the second pole of the sixth transistor is connected to the third connection terminal; The scan output unit includes: a seventh transistor, an eighth transistor and a second capacitor; the gate of the seventh transistor is connected to the third connection terminal, the first pole of the seventh transistor is connected to the third clock signal, and the second pole of the seventh transistor is connected to the output terminal of the scan output unit; the second capacitor is connected between the gate and the second pole of the seventh transistor; the gate of the eighth transistor is connected to the second output terminal, the first pole of the eighth transistor is connected to the second potential signal, and the second pole of the eighth transistor is connected to the output terminal of the scan output unit.

30. The scanning drive circuit according to claim 29, wherein, The transmission control unit further includes: a ninth transistor; the gate of the ninth transistor is connected to the first switch signal, the first pole of the ninth transistor is connected to the second potential signal, and the second pole of the ninth transistor is connected to the third connection terminal.

31. The scanning drive circuit according to claim 29, wherein The transmission control unit further includes: a tenth transistor; the gate of the tenth transistor is connected to the second switch signal, the first pole of the tenth transistor is connected to the first potential signal, and the second pole of the tenth transistor is connected to the third connection terminal.

32. The scanning drive circuit according to claim 31, wherein, The transmission control unit further includes: an eleventh transistor; the eleventh transistor is connected between the second pole of the sixth transistor and the third connection terminal, and the gate of the eleventh transistor is connected to the first potential signal.

33. The scanning driving circuit according to claim 29, wherein The drive control module includes: A second input unit, connected to the first output terminal, for responding to the fourth clock signal and transmitting the input signal to the first output terminal; A third control unit, connected to the second output terminal, for responding to the fourth clock signal and transmitting the first potential signal to the second output terminal; A fourth node control unit, respectively connected to the first output terminal and the second output terminal, for responding to the potential of the first output terminal and transmitting the fourth clock signal to the second output terminal; The fifth node control unit is respectively connected to the first output end and the second output end, and is configured to respond to the third clock signal and the potential of the second output end, and transmit the second potential signal to the first output end; The stage transmission output module includes: A third output unit, connected to the first output end, and configured to respond to the potential of the first output end and transmit the third clock signal to the output end of the stage transmission output module; A fourth output unit, connected to the second output end, and configured to respond to the potential of the second output end and transmit the second potential signal to the output end of the stage transmission output module.

34. A display device, characterized in that, It includes: A pixel circuit and the scan driving circuit according to any one of claims 12-33.

35. The display device according to claim 34, wherein Each stage of the shift register includes two of the scan output modules; The pixel circuit includes: a driving module, a threshold compensation module, and a gate reset module; the gate reset module is connected to the control end of the driving module, and the threshold compensation module is connected between the control end and the output end of the driving module; One of the scan output modules of the shift register is connected to the control end of the gate reset module in one row of the pixel circuit, and the other scan output module of the shift register is connected to the control end of the threshold compensation module in another row of the pixel circuit.

36. The display device according to claim 35, wherein The pixel circuit further includes a data writing module and an anode reset module, the data writing module is connected to the input end of the driving module; the anode reset module is connected to the anode of the light emitting device; the data writing module, the anode reset module, the gate reset module, and the threshold compensation module include transistors of the same channel type; the shift register further includes a stage transmission output module, and the stage transmission output module is further connected to the control end of the data writing module and / or the control end of the anode reset module.

37. The display device according to claim 35, characterized in that, The two scan output modules include a first scan output module and a second scan output module; the output end of the first scan output module of the nth stage is connected to the control end of the gate reset module in the pixel circuit of the nth row, and the output end of the second scan output module of the (n + m)th stage is connected to the control end of the threshold compensation module in the pixel circuit of the nth row; both n and m are integers greater than 0.

38. The display device according to claim 37, wherein m＝1。

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