Lock feedback circuit supporting simultaneous detection of multi-path states

Abstract

The utility model discloses a lock feedback circuit supporting simultaneous detection of multipath states in the technical field of electromagnetic locks, which comprises a lock interface and a CPU (central processing unit) master control circuit, and further comprises an ADC (analog to digital converter) acquisition circuit electrically connected between the lock interface and the CPU master control circuit, the ADC acquisition circuit comprises a TVS (transient voltage suppressor) electrostatic protection D13 and a plurality of resistors, and the TVS electrostatic protection D13 is electrically connected with the CPU master control circuit. The plurality of resistors are divided into a plurality of feedback lines which are connected in parallel, each feedback line is correspondingly connected with a lock interface, the plurality of feedback lines output different voltage values according to the on-off of the lock interface, and the CPU main control circuit judges the on-off of the lock interface according to the different voltage values; the ADC acquisition circuit is used for detecting voltage values of different lock interfaces, one ADC acquisition circuit can detect the on-off states of four electromagnetic locks at the same time, the electromagnetic locks can be detected in batches, the voltage stabilizing circuit is matched, the capacity of detecting the number of the electromagnetic locks and improving the detection precision is considered, a large number of IO ports are reduced, the wiring difficulty is reduced, and the cost is reduced. And the anti-interference capability of electromagnetic lock detection is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of electromagnetic locks, in particular to a lock feedback circuit supporting simultaneous detection of multiple states. Background Art

[0002] An electromagnetic lock is a lock used for the cabinet door of an intelligent storage locker, and can control unlocking by controlling a switch circuit. The electromagnetic lock is generally an inductive load, and the opening control of the electromagnetic lock is realized by controlling the short-time energization of the coil.

[0003] Regarding the lock switch state of the electromagnetic lock, the prior art mainly detects the level state of the lock feedback interface by using an IO port. One IO port detects one lock. If you want to detect the switch states of multiple electromagnetic locks at one time, it will require too many IO ports, making the wiring difficult and the detection efficiency to be improved. Summary of the Utility Model

[0004] The purpose of this part is to outline some aspects of the embodiments of the utility model and briefly introduce some preferred embodiments. Simplifications or omissions may be made in this part, as well as in the abstract and the title of the utility model of the present application, to avoid obscuring the purpose of this part, the abstract and the title. Such simplifications or omissions shall not be used to limit the scope of the utility model.

[0005] Therefore, the purpose of the utility model is to provide a lock feedback circuit supporting simultaneous detection of multiple states, which uses an ADC acquisition circuit to detect the voltage values of different lock interfaces, so that one ADC acquisition circuit can simultaneously detect the switch states of 4 electromagnetic locks, enabling batch detection of electromagnetic locks. Cooperating with a voltage stabilization circuit, it takes into account the ability to detect the number of electromagnetic locks and improve the detection accuracy, reduces the occupation of a large number of IO ports, reduces the wiring difficulty, and improves the anti-interference ability of electromagnetic lock detection.

[0006] To solve the above technical problems, the utility model provides a lock feedback circuit supporting simultaneous detection of multiple states, adopting the following technical solutions: including a lock interface and a CPU main control circuit, and further including an ADC acquisition circuit electrically connected between the lock interface and the CPU main control circuit. The ADC acquisition circuit includes a TVS electrostatic protection D13 and several resistors. The several resistors are divided into multiple parallel feedback lines, each feedback line is correspondingly connected to a lock interface, and the multiple feedback lines output different voltage values according to the on-off of the lock interface. The CPU main control circuit judges the on-off of the lock interface according to the different voltage values.

[0007] Optionally, the ADC acquisition circuit consists of a TVS electrostatic protection D13 and nine resistors. Two of the nine resistors are combined pairwise to form four parallel feedback lines. The first end of the remaining one resistor is connected to the power input terminal, and the second end of the remaining one resistor is connected to the first ends of the four feedback lines, the first end of the TVS electrostatic protection D13, and the P1.3 interface of the CPU main control circuit. The second ends of the four feedback lines are respectively connected to CK1, CK2, CK3, and CK4 of four lock interfaces, and the second end of the TVS electrostatic protection D13 is grounded.

[0008] Optionally, the nine resistors consist of resistor R57, R58, R62, R59, R63, R60, R64, R61, and R65. Resistor R58 and R62; R59 and R63; R60 and R64; and R61 and R65 are divided into four parallel feedback lines. The first end of resistor R57 is connected to the power input terminal of the ADC acquisition circuit, and the second end of resistor R57 is connected to the first ends of the four feedback lines, the first end of the TVS electrostatic protection D13, and the P1.3 interface of the CPU main control circuit.

[0009] Optionally, multiple feedback lines output 15 different voltage values of V CK1 、V CK2 、V CK3 、V CK4 、V CK1+CK2 、V CK1+CK3 、V CK1+CK4 、V CK2+CK3 、V CK2+CK4 、V CK3+CK4 、V CK1+CK2+CK3 、V CK1+CK2+CK4 、V CK1+CK3+CK4 、V CK2+CK3+CK4 and V CK1+CK2+CK3+CK4 .

[0010] Optionally, the voltage difference between any two of the 15 different voltage values output by multiple feedback lines according to the on / off of the lock interface is ≥0.1V.

[0011] Optionally, the sampling progress of the nine resistors is all 1%.

[0012] Optionally, it further includes a voltage stabilizing circuit. The first end of the voltage stabilizing circuit is connected to the power interface through a power conversion chip, and the second end of the voltage stabilizing circuit is connected to the power input terminal of the ADC acquisition circuit.

[0013] Optionally, the voltage stabilizing circuit includes a chip TL431, a resistor R46, a resistor R47, a resistor R48, and a filtering capacitor C20. The first end of the resistor R48 is connected to the power conversion chip. The second end of the resistor R48 is connected to the first end of the resistor R46, pin 2 of the chip TL431, the first end of the filtering capacitor C20, and the power input terminal of the ADC acquisition circuit. The second end of the resistor R46 is connected to the first end of the resistor R47 and pin 1 of the chip TL431. The second end of the resistor R47, pin 3 of the chip TL431, and the second end of the filtering capacitor C20 are grounded.

[0014] In summary, the present utility model includes at least one of the following beneficial effects:

[0015] The present utility model uses an ADC acquisition circuit to detect the voltage values of different lock interfaces, enabling one ADC acquisition circuit to simultaneously detect the switch states of 4 electromagnetic locks, allowing for batch detection of electromagnetic locks. In combination with the voltage stabilizing circuit, it takes into account the ability to detect the number of electromagnetic locks and improve the detection accuracy, reduces the occupation of a large number of IO ports, simplifies the wiring difficulty, and enhances the anti-interference ability of the electromagnetic lock detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 is a schematic diagram of the present utility model;

[0018] Figure 2 is a schematic diagram of the ADC acquisition circuit of the present utility model;

[0019] Figure 3 is a schematic diagram of the voltage stabilizing circuit of the present utility model;

[0020] Figure 4 is a schematic diagram of the circuit of four lock interfaces of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only some, rather than all, of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0022] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "top / bottom end", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0023] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "provided with", "sheathed / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0024] Embodiment 1

[0025] Referring to Figure 1 , the present utility model discloses a lock feedback circuit supporting simultaneous detection of multiple states, including a lock interface and a CPU main control circuit, and further including an ADC acquisition circuit electrically connected between the lock interface and the CPU main control circuit. Referring to Figure 2 , the ADC acquisition circuit includes a TVS electrostatic protection D13 and nine resistors R57, R58, R62, R59, R63, R60, R64, R61 and R65. Resistors R58 and R62; R59 and R63; R60 and R64; and R61 and R65 are divided into four parallel feedback lines. The first end of resistor R57 is connected to the power input terminal of the ADC acquisition circuit. The second end of resistor R57 is connected to the first ends of the four feedback lines, the first end of the TVS electrostatic protection D13, and the P1.3 interface of the CPU main control circuit. The second end of the TVS electrostatic protection D13 is grounded. The second ends of the four feedback lines are respectively connected to CK1, CK2, CK3 and CK4 of four lock interfaces. Referring to Figure 4 , which is a schematic diagram of the four lock interface circuits respectively connected by the four feedback lines.

[0026] Among them, the selection of the nine resistors R57, R58, R62, R59, R63, R60, R64, R61 and R65 follows the principle of maximizing the voltage difference between pairwise combinations. There are a total of 15 combinations. According to the resistor voltage division formula Uout = R1 / (R1 + R2)*Uin, 15 combined voltages can be obtained, that is, multiple feedback lines output 15 different voltage values V according to the on / off states of the lock interfacesCK1 , V CK2 , V CK3 , V CK4 , V CK1+CK2 , V CK1+CK3 , V CK1+CK4 , V CK2+CK3 , V CK2+CK4 , V CK3+CK4 , V CK1+CK2+CK3 , V CK1+CK2+CK4 , V CK1+CK3+CK4 , V CK2+CK3+CK4 and V CK1+CK2+CK3+CK4 .

[0027] This utility model uses the C language computer program to write the query resistance code; findAdcRes(3dp - 15).c calculates a truth table formed by the resistance values with the pressure difference between two pairs >= 0.1V. Considering factors such as power consumption, stability, and whether the resistance value is a common resistance value, the following numerical groups are selected.

[0028] Multiple feedback lines output 15 different voltage values V according to the on - off of the lock interface CK1 , V CK2 , V CK3 , V CK4 , V CK1+CK2 , V CK1+CK3 , V CK1+CK4 , V CK2+CK3 , V CK2+CK4 , V CK3+CK4 , V CK1+CK2+CK3 , V CK1+CK2+CK4 , V CK1+CK3+CK4 , V CK2+CK3+CK4 and V CK1+CK2+CK3+CK4 are 3.729V, 4.242V, 3.077V, 2.917V, 3.290V, 2.543V, 2.432V, 2.772V, 2.642V, 2.137V, 2.331V, 2.238V, 1.865V, 1.986V, and 1.749V respectively.

[0029] Since the sampling progress of the 9 resistors is all 1%. Therefore, the error of the actual test value will not exceed 0.03V, which greatly guarantees the voltage stability. The CPU main control circuit judges which feedback lines are open and closed by reading different voltage values.

[0030] Embodiment 2

[0031] Refer to Figure 1, based on the same concept as in the above-mentioned First Embodiment, the lock feedback circuit supporting simultaneous detection of multiple states further includes a voltage stabilization circuit. The first end of the voltage stabilization circuit is connected to a power interface through a power conversion chip, and the second end of the voltage stabilization circuit is connected to the power input terminal of the ADC acquisition circuit.

[0032] Among them, the power conversion chip 5V is an existing product, which can convert the power input of 9V - 24V from the power interface into 5.2V. Through the voltage stabilization circuit, the input voltage of 5.2V can be accurately stabilized to the range of 4.998 - 5.002V, with the voltage accurate to two decimal places, thereby providing an accurate reference power supply for the ADC acquisition circuit.

[0033] Referring to Figure 3 , specifically, in this embodiment, the voltage stabilization circuit includes a chip TL431, a resistor R46, a resistor R47, a resistor R48, and a filter capacitor C20. The first end of the resistor R48 is connected to the power conversion chip, and the second end of the resistor R48 is connected to the first end of the resistor R46, pin 2 of the chip TL431, the first end of the filter capacitor C20, and the power input terminal of the ADC acquisition circuit. The second end of the resistor R46 is connected to the first end of the resistor R47 and pin 1 of the chip TL431. The second end of the resistor R47, pin 3 of the chip TL431, and the second end of the filter capacitor C20 are grounded.

[0034] The resistor R48 is used to limit the current in the circuit, ensuring that the feedback of the ADC acquisition circuit is normal while also ensuring that the current in the main circuit is not affected. The settings of R46 and R47 make the voltage adjustable, and the chip TL431 and the 0.1uF filter capacitor C20 provide a stable 4.998 - 5.002V to ensure that the voltage sampled by the ADC acquisition circuit is stable and not affected by the power conversion chip.

[0035] The above are all the preferred embodiments of the present invention. The protection scope of the present invention is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of the present invention should be covered within the protection scope of the present invention.

Claims

1. A lock feedback circuit supporting simultaneous detection of multiple states, comprising a lock interface and a CPU main control circuit, characterized in that: It also includes an ADC acquisition circuit electrically connected between the lock interface and the CPU main control circuit. The ADC acquisition circuit includes a TVS electrostatic protection D13 and several resistors. The several resistors are divided into multiple parallel feedback lines, and each feedback line is correspondingly connected to a lock interface. The multiple feedback lines output different voltage values according to the on / off state of the lock interface, and the CPU main control circuit judges the on / off state of the lock interface according to the different voltage values.

2. The lock feedback circuit supporting simultaneous detection of multiple states according to claim 1, wherein: The ADC acquisition circuit is composed of a TVS electrostatic protection D13 and nine resistors. Two of the nine resistors are combined into four parallel feedback lines. The first end of the remaining one resistor is connected to the power input terminal, and the second end of the remaining one resistor is connected to the first ends of the four feedback lines, the first end of the TVS electrostatic protection D13, and the P1.3 interface of the CPU main control circuit. The second ends of the four feedback lines are respectively connected to CK1, CK2, CK3, and CK4 of four lock interfaces, and the second end of the TVS electrostatic protection D13 is grounded.

3. The lock feedback circuit supporting simultaneous detection of multiple states according to claim 2, characterized in that: The nine resistors are composed of resistor R57, R58, R62, R59, R63, R60, R64, R61, and R65. Resistor R58 and R62; R59 and R63; R60 and R64, and R61 and R65 are divided into four parallel feedback lines. The first end of resistor R57 is connected to the power input terminal of the ADC acquisition circuit, and the second end of resistor R57 is connected to the first ends of the four feedback lines, the first end of the TVS electrostatic protection D13, and the P1.3 interface of the CPU main control circuit.

4. A lock feedback circuit supporting simultaneous detection of multiple states according to claim 2, characterized in that: Multiple feedback lines output 15 different voltage values of V according to the on / off state of the lock interface CK1 、V CK2 、V CK3 、V CK4 、V CK1+CK2 、V CK1+CK3 、V CK1+CK4 、V CK2+CK3 、V CK2+CK4 、V CK3+CK4 、V CK1+CK2+CK3 、V CK1+CK2+CK4 、V CK1+CK3+CK4 、V CK2+CK3+CK4 and V CK1+CK2+CK3+CK4 。 5. The lock feedback circuit supporting simultaneous detection of multiple states according to claim 4, characterized in that: The multiple feedback lines output 15 different voltage values according to the on / off state of the lock interface, and the voltage difference between any two of them is ≥0.1V.

6. The lock feedback circuit supporting simultaneous detection of multiple channels of states according to claim 2, wherein: The sampling progress of the nine resistors is all 1%.

7. A lock feedback circuit supporting simultaneous detection of multiple states according to any one of claims 2-6, characterized in that: It also includes a voltage stabilizing circuit. The first end of the voltage stabilizing circuit is connected to the power interface through a power conversion chip, and the second end of the voltage stabilizing circuit is connected to the power input terminal of the ADC acquisition circuit.

8. The lock feedback circuit supporting simultaneous detection of multiple states according to claim 7, characterized in that: The voltage stabilizing circuit includes chip TL431, resistor R46, resistor R47, resistor R48, and filter capacitor C20. The first end of resistor R48 is connected to the power conversion chip. The second end of resistor R48 is connected to the first end of resistor R46, pin 2 of chip TL431, the first end of filter capacitor C20, and the power input terminal of the ADC acquisition circuit. The second end of resistor R46 is connected to the first end of resistor R47 and pin 1 of chip TL431. The second end of resistor R47, pin 3 of chip TL431, and the second end of filter capacitor C20 are grounded.

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