Spatial spectrum interference duration detection circuit

Abstract

The utility model provides a space frequency spectrum interference duration detection circuit, which comprises a frequency sweeping module, a signal source module, a main control module, a micro-control module and a trigger module, and is characterized in that the output end of the frequency sweeping module is electrically connected with the input end of the main control module, and the frequency sweeping module is used for detecting radio signals of a preset frequency band in a space; the input end of the signal source module is electrically connected with the output end of the main control module, and the signal source module is used for generating an interference signal and sending the interference signal to a space; the output end of the signal source module is electrically connected with the input end of the micro-control module and is used for triggering timing starting; the trigger module is electrically connected with the external signal receiver and the micro-control module and used for triggering timing to stop. Through cooperation of the frequency sweeping module, the signal source module, the main control module, the micro-control module and the trigger module, comprehensive monitoring and interference testing of radio signals in a specific frequency band are realized, the noise interference duration is detected, and powerful support is provided for evaluating the anti-interference capability of the wireless signals.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless device detection, in particular to a spatial spectrum interference duration detection circuit. Background Technique

[0002] A spectrum interference tester, also known as a spectrum analyzer, is an electronic measuring instrument used to measure and analyze the spectral characteristics of signals; it can monitor the spectral distribution of signals in real time, helping engineers quickly locate and solve problems such as signal interference and spectrum congestion; with the rapid development of wireless communication technology, the effective utilization and management of spectrum resources have become particularly important, and spectrum analyzers have thus been widely used.

[0003] The publication number CN218243532U discloses an anti-interference test radio frequency device for testing the anti-interference ability of a receiving-end device during wireless signal transmission, including a radio frequency signal generating device, a radio frequency signal monitoring device, and a main control device. The radio frequency signal generating device and the radio frequency signal monitoring device are respectively connected to the main control device. The radio frequency signal generating device is used to generate adjustable and controllable interference signals, and the radio frequency signal monitoring device is used to receive the interference signals transmitted by the radio frequency signal generating device with full-band coverage. The main control device monitors and adjusts the interference signals through the radio frequency signals received by the radio frequency signal monitoring device.

[0004] Currently, during the process of detecting the anti-interference ability of wireless signals during transmission, it is impossible to detect the interference duration of wireless signals, which cannot provide strong support for the evaluation of the anti-interference ability of wireless signals, thereby reducing the effectiveness of detection. Content of the Utility Model

[0005] In view of this, the utility model proposes a spatial spectrum interference duration detection circuit, which can detect the interference duration of wireless signals, provide strong support for the evaluation of the anti-interference ability of wireless signals, and thus improve the effectiveness of detection.

[0006] The technical solution of the utility model is realized as follows: The utility model provides a spatial spectrum interference duration detection circuit, including a frequency sweeping module, a signal source module, a main control module, a micro-control module, and a trigger module. Among them,

[0007] The output end of the frequency sweeping module is electrically connected to the input end of the main control module. The frequency sweeping module is used to detect radio signals in a preset frequency band in space;

[0008] The input end of the signal source module is electrically connected to the output end of the main control module. The signal source module is used to generate interference signals and send them into space; the output end of the signal source module is electrically connected to the input end of the micro-control module, and is used to trigger the start of timing;

[0009] The trigger module is electrically connected to the external signal receiver and the micro-control module respectively, and is used to trigger the stop of timing; the micro-control module is communicatively connected to the main control module, and is used to send the interference duration to the main control module.

[0010] On the basis of the above technical solutions, preferably, a connection module is provided between the signal source module and the micro-control module. The output end of the signal source module is electrically connected to the input end of the connection module, and the output end of the connection module is electrically connected to the input end of the micro-control module, and is used to receive the transmission signal of the signal source module and feedback it to the micro-control module to trigger the internal timer to start.

[0011] On the basis of the above technical solutions, preferably, the connection module includes a resistor R45, a resistor R46, a bidirectional breakdown diode D6, a bidirectional breakdown diode D7, and a communication interface CN2. Among them, pin 3 of the communication interface CN2 is electrically connected to one end of the resistor R45 and the bidirectional breakdown diode D7 respectively. The other end of the resistor R45 is electrically connected to the micro-control module. Pin 2 of the communication interface CN2 is electrically connected to one end of the resistor R46 and the bidirectional breakdown diode D6 respectively. The other end of the resistor R46 is electrically connected to the micro-control module. The other ends of the bidirectional breakdown diode D6 and the bidirectional breakdown diode D7 are grounded respectively, and the communication interface CN2 is electrically connected to the signal source module.

[0012] On the basis of the above technical solutions, preferably, the trigger module includes a connection terminal block J4, a resistor R28, a resistor R29, a comparator U8, a capacitor C35, and a MOS transistor M1. The connection terminal block J4 is electrically connected to the external signal receiver. One end of the connection terminal block J4 is electrically connected to the resistor R28. The other end of the resistor R28 is electrically connected to the positive input terminal of the resistor R29 and the comparator U8 respectively. The other end of the resistor R29 is electrically connected to the negative input terminal of the comparator U8 and grounded. The output end of the comparator U8 is electrically connected to the gate of the MOS transistor M1. The source of the MOS transistor M1 is electrically connected to the external power supply. The drain of the MOS transistor M1 is electrically connected to the micro-control module. The power supply terminal of the comparator U8 is electrically connected to the external power supply and the capacitor C35 respectively. The other end of the capacitor C35 is grounded.

[0013] On the basis of the above technical solutions, preferably, a communication module is provided between the micro-control module and the main control module. Among them, the output end of the micro-control module is electrically connected to the input end of the communication module, and the output end of the communication module is communicatively connected to the main control module, and is used to send the interference duration to the built-in screen of the main control module for display.

[0014] On the basis of the above technical solutions, preferably, the communication module includes a transmitting unit and a receiving unit. The input end of the transmitting unit is electrically connected to the output end of the micro-control module. The output end of the receiving unit is electrically connected to the input end of the main control module. The transmitting unit is wirelessly communicatively connected to the receiving unit.

[0015] Based on the above technical solutions, preferably, both the transmitting unit and the receiving unit include a communication chip U10, an antenna JP1, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a capacitor C41, a capacitor EC7, and a filter L5. The pin 19 of the communication chip U10 is electrically connected to the antenna JP1. The pins 17, 16, and 15 of the communication chip U10 are respectively electrically connected to the resistors R30, R31, and R32. The other ends of the resistors R31, R31, and R32 are commonly grounded. The pin 14 of the communication chip U10 is electrically connected to one end of the resistor R33. The pin 13 of the communication chip U10 is electrically connected to one end of the resistor R34. The other ends of the resistors R33 and R34 are both electrically connected to the output end of the micro-control module 4. The pin 11 of the communication chip U10 is respectively electrically connected to the positive electrodes of the capacitor C41, the capacitor EC7, and one end of the filter L5. The other end of the capacitor C41 is commonly grounded with the pin 10 of the communication chip U10. The negative electrode of the capacitor EC7 is grounded. The other end of the filter L5 is connected to the +5V power supply.

[0016] Based on the above technical solutions, preferably, it further includes a plurality of buck modules. The input end of the buck module is electrically connected to an external direct power supply. The output ends of the buck module are respectively electrically connected to the power supply terminals of the micro-control module and the main control module for power supply.

[0017] Based on the above technical solutions, preferably, the step-down module includes a step-down chip U4, capacitors C19, C20, C21, resistors R11, R14, a triode Q2, a capacitor C15, a zener diode D2, a filter L2, capacitors EC1, EC2, a capacitor C17, a resistor R9, a resistor R13, and a connection terminal block J3. Pin 7 of the step-down chip U4 is electrically connected to capacitors C19, C20, C21, and an external DC power supply respectively. The other ends of capacitors C19, C20, and C21 are grounded respectively. Pin 1 of the step-down chip U4 is electrically connected to the capacitor C15. The other end of the capacitor C15 is electrically connected to pin 1 of the step-down chip U4, the negative electrode of the zener diode D2, and the filter L2 respectively. The other end of the filter L2 is electrically connected to capacitors EC1, EC2, a capacitor C17, a resistor R17, one end of the connection terminal block J3, and the output voltage respectively. The other end of the resistor R17 is electrically connected to pin 4 of the step-down chip U4 and the resistor R19 respectively. The positive electrode of the zener diode D2, capacitors EC5, EC6, a capacitor C26, the resistor R19, and the other end of the connection terminal block 13 are grounded respectively. Pin 5 of the step-down chip U4 is electrically connected to the collector of the triode Q2. The base of the triode Q2 is electrically connected to resistors R11, R14, and the micro-control module respectively. The other end of the resistor R14 is commonly grounded with the emitter of the triode Q2. The other end of the resistor R11 is electrically connected to the second power supply output voltage terminal.

[0018] Based on the above technical solutions, preferably, the model of the micro-control module is STM32F103C8T6.

[0019] The spatial spectrum interference duration detection circuit of the present utility model has the following beneficial effects compared with the prior art:

[0020] (1) Through the cooperation of the frequency sweeping module, the signal source module, the main control module, the micro-control module, and the trigger module, the comprehensive monitoring and interference testing of radio signals in a specific frequency band are realized, and the noise interference duration is detected, providing strong support for evaluating the anti-interference ability of wireless signals;

[0021] (2) By real-time monitoring the connection status of the communication signal and timely stopping the internal timer when the signal is disconnected, the high precision and accuracy of the interference duration measurement are ensured;

[0022] (3) By setting a communication module between the micro-control module and the main control module to adopt a wireless communication mode, and setting the transmitting unit and the receiving unit on the micro-control module and the main control module respectively, the long-distance and convenient data transmission is realized. Description of the Drawings

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0024] Figure 1 It is the circuit principle block diagram of the spatial spectrum interference duration detection circuit of the present invention;

[0025] Figure 2 It is the microcontrol module circuit diagram of the spatial spectrum interference duration detection circuit of the present invention;

[0026] Figure 3 It is the circuit diagram of the connection module of the spatial spectrum interference duration detection circuit of the present invention;

[0027] Figure 4 It is the circuit diagram of the trigger module of the spatial spectrum interference duration detection circuit of the present invention;

[0028] Figure 5 It is the circuit diagram of the communication module of the spatial spectrum interference duration detection circuit of the present invention;

[0029] Figure 6 It is the circuit diagram of the buck module of the spatial spectrum interference duration detection circuit of the present invention. Specific embodiments

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in combination with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0031] Such as Figure 1-2As shown in the figure, a spatial spectrum interference duration detection circuit of the present utility model includes a frequency sweeping module 1, a signal source module 2, a main control module 3, a micro-control module 4, and a trigger module 5. Among them, the output end of the frequency sweeping module 1 is electrically connected to the input end of the main control module 3, and the frequency sweeping module 1 is used to detect radio signals in a preset frequency band in space; the input end of the signal source module 2 is electrically connected to the output end of the main control module 3, and the signal source module 2 is used to generate interference signals and send them into space; the output end of the signal source module 2 is electrically connected to the input end of the micro-control module 4, which is used to trigger the start of timing; the trigger module 5 is electrically connected to an external signal receiver and the micro-control module 4 respectively, and is used to trigger the stop of timing; the micro-control module 4 is communicatively connected to the main control module 3, and is used to send the interference duration to the main control module 3.

[0032] It should be noted that a wireless signal is sent from the remote control to the external signal receiver. First, the frequency sweeping module 1 is responsible for detecting radio signals within a preset frequency band in space; this module scans the specified frequency band, collects and analyzes key information such as signal strength and frequency distribution within this frequency band. Specifically, the frequency sweeping module 1 can be one of a frequency sweeper, a field strength meter, or a spectrum analyzer. According to the instruction of the main control module 3, the signal source module 2 generates interference signals with specific frequencies and characteristics, and sends these signals into space to simulate actual possible interference situations. When the micro-control module 4 receives the interference signal sent by the signal source module 2, it triggers the timer to start timing. When the trigger module 5 receives the stop signal from the external signal receiver, the micro-control module 4 stops timing and calculates the interference duration. The micro-control module 4 transmits the interference duration to the built-in display on the main control module 3 for display. Through the cooperation of each module, this spatial spectrum interference duration detection circuit can achieve comprehensive monitoring and interference testing of radio signals within a specific frequency band, and detect the noise interference duration, providing strong support for evaluating the anti-interference ability of wireless signals.

[0033] Specifically, the model of the micro-control module 4 in this embodiment is STM32F103C8T6.

[0034] In this embodiment, a connection module 6 is provided between the signal source module 2 and the micro-control module 4. The output end of the signal source module 2 is electrically connected to the input end of the connection module 6, and the output end of the connection module 6 is electrically connected to the input end of the micro-control module 4, which is used to receive the emission signal of the signal source module 2 and feedback it to the micro-control module 4 to trigger the start of the internal timer.

[0035] Specifically, the signal source module 2 in this embodiment can be one of a radio frequency power amplifier, a broadband frequency source, or a spectrum analyzer.

[0036] Such as Figure 3As shown, as a preferred embodiment, the connection module 6 in this embodiment includes a resistor R45, a resistor R46, a bidirectional breakdown diode D6, a bidirectional breakdown diode D7, and a communication interface CN2. Among them, pin 3 of the communication interface CN2 is electrically connected to one end of the resistor R45 and the bidirectional breakdown diode D7 respectively. The other end of the resistor R45 is electrically connected to the micro-control module 4. Pin 2 of the communication interface CN2 is electrically connected to one end of the resistor R46 and the bidirectional breakdown diode D6 respectively. The other end of the resistor R46 is electrically connected to the micro-control module 4. The other ends of the bidirectional breakdown diode D6 and the bidirectional breakdown diode D7 are grounded respectively. The communication interface CN2 is electrically connected to the signal source module 2.

[0037] It should be noted that when the signal source module 2 sends a signal through the communication interface CN2, the resistors R45 and R46 respectively limit the magnitude of the current flowing to the micro-control module 4 to prevent damage to the micro-control module due to excessive current. At the same time, they also help to perform a certain degree of voltage division during signal transmission to ensure that the signal received by the micro-control module is within its tolerable range. The bidirectional breakdown diodes D6 and D7 are respectively connected in parallel between the two signal pins of the communication interface CN2 and the ground to prevent voltage overshoot or reverse voltage from the signal source module 2 from damaging the micro-control module 4.

[0038] As Figure 4 As shown, as a preferred embodiment, the trigger module 5 in this embodiment includes a connection terminal block J4, a resistor R28, a resistor R29, a comparator U8, a capacitor C35, and a PMOS transistor M1. The connection terminal block J4 is electrically connected to an external signal receiver. One end of the connection terminal block J4 is electrically connected to the resistor R28. The other end of the resistor R28 is electrically connected to the positive input terminal of the resistor R29 and the comparator U8 respectively. The other end of the resistor R29 is electrically connected to the negative input terminal of the comparator U8 and grounded. The output terminal of the comparator U8 is electrically connected to the gate of the PMOS transistor M1. The source of the PMOS transistor M1 is electrically connected to an external power supply. The drain of the PMOS transistor M1 is electrically connected to the micro-control module 4. The power supply terminal of the comparator U8 is electrically connected to the external power supply and the capacitor C35 respectively. The other end of the capacitor C35 is grounded.

[0039] Specifically, the model of the comparator U8 is LM393. In the communication between the existing remote controller and the receiver, there is usually an indication signal of "receiving successfully" or "signal valid". If the receiver does not receive a valid signal from the remote controller, it will set the output to a low level. This technology is the prior art and will not be elaborated here. The voltage of the communication signal is reduced to the processing range of the comparator U8 through the resistor R28 and the resistor R29. The comparator U8 compares the detected voltage with a preset threshold voltage. When the communication signal is disconnected, the detected voltage is lower than the threshold, and the comparator U8 outputs a low level. When the communication signal is connected, the detected voltage is higher than the threshold, and the comparator U8 outputs a high level. When the comparator U8 outputs a high level, the PMOS transistor M1 is cut off. When the output is at a low level, the PMOS transistor M1 is turned on, and then the low-level signal is sent to the micro-control module 4, and the micro-control module 4 stops the internal timer from timing. The time difference calculated by the timer is the interference time of the crane.

[0040] A communication module 7 is arranged between the micro-control module 4 and the main control module 3 in this embodiment. Specifically, the output end of the micro-control module 4 is electrically connected to the input end of the communication module 7, and the output end of the communication module 7 is communicatively connected to the main control module 3, and is used to send the interference duration to the built-in screen of the main control module 3 for display.

[0041] Specifically, the model of the main control module 3 in this embodiment is LattePanda-3-Delta-864.

[0042] The communication module 7 in this embodiment includes a transmitting unit 71 and a receiving unit 72. The input end of the transmitting unit 71 is electrically connected to the output end of the micro-control module 4, the output end of the receiving unit 72 is electrically connected to the input end of the main control module 3, and the transmitting unit 71 is wirelessly communicatively connected to the receiving unit 72.

[0043] Such as Figure 5As shown, as a preferred embodiment, the transmitting unit 71 and the receiving unit 72 in this embodiment both include a communication chip U10, an antenna JP1, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a capacitor C41, a capacitor EC7, and a filter L5. The pin 19 of the communication chip U10 is electrically connected to the antenna JP1. The pins 17, 16, and 15 of the communication chip U10 are respectively electrically connected to the resistors R30, R31, and R32. The other ends of the resistors R31, R31, and R32 are commonly grounded. The pin 14 of the communication chip U10 is electrically connected to one end of the resistor R33. The pin 13 of the communication chip U10 is electrically connected to one end of the resistor R34. The other ends of the resistors R33 and R34 are both electrically connected to the output end of the micro-control module 4. The pin 11 of the communication chip U10 is respectively electrically connected to the positive electrodes of the capacitor C41, the capacitor EC7, and one end of the filter L5. The other end of the capacitor C41 is commonly grounded with the pin 10 of the communication chip U10. The negative electrode of the capacitor EC7 is grounded. The other end of the filter L5 is connected to the +5V power supply.

[0044] Among them, the model of the communication chip U10 is E28-2G4T27SX. The antenna JP1 radiates RF signals into the air or receives RF signals from the air. The filter L5, together with the capacitors C41 and EC7, constitutes an LC filter circuit to filter out high-frequency noise on the power line, ensuring stable power supply for the communication chip U10, and realizing the communication and data exchange between the micro-control module 4 and the main control module 3.

[0045] This embodiment also includes a plurality of buck modules 8. The input end of the buck module 8 is electrically connected to an external direct power supply. The output ends of the buck module 8 are respectively electrically connected to the power supply terminals of the micro-control module 4 and the main control module 3 for power supply.

[0046] Such as Figure 6As shown, as a preferred embodiment, the buck module 8 in this embodiment includes a buck chip U4, capacitors C19, C20, C21, resistors R11, R14, a triode Q2, a capacitor C15, a zener diode D2, a filter L2, capacitors EC1, EC2, a capacitor C17, a resistor R9, a resistor R13, and a connection terminal block J3. The pin 7 of the buck chip U4 is electrically connected to the capacitors C19, C20, C21, and an external DC power supply respectively. The other ends of the capacitors C19, C20, and C21 are grounded respectively. The pin 1 of the buck chip U4 is electrically connected to the capacitor C15. The other end of the capacitor C15 is electrically connected to the pin 1 of the buck chip U4, the negative electrode of the zener diode D2, and the filter L2 respectively. The other end of the filter L2 is electrically connected to the capacitors EC1, EC2, the capacitor C17, the resistor R17, one end of the connection terminal block J3, and the output voltage respectively. The other end of the resistor R17 is electrically connected to the pin 4 of the buck chip U4 and the resistor R19 respectively. The positive electrode of the zener diode D2 is grounded together with the capacitors EC5, EC6, the capacitor C26, the resistor R19, and the other end of the connection terminal block 13. The pin 5 of the buck chip U4 is electrically connected to the collector of the triode Q2. The base of the triode Q2 is electrically connected to the resistors R11, R14, and the microcontrol module 4 respectively. The other end of the resistor R14 is commonly grounded with the emitter of the triode Q2. The other end of the resistor R11 is electrically connected to the second power supply output voltage terminal.

[0047] The model of the buck chip U4 in this embodiment is TPS5450DDAR. The buck module 8 realizes the stable bucking and output of the input DC voltage, providing a reliable power supply guarantee for the circuit.

[0048] Working principle:

[0049] The spectrum analyzer detects radio signals in the nearby frequency bands by setting a certain frequency band of interest. The detected wireless signals are transmitted to the main control module 3 for reading and display. Then, the main control module 3 controls the signal source module 2 to generate an interference sequence signal and sends it into the space through the built-in power amplifier. At the same time, when the interference signal is sent, the signal source module 2 sends a signal to the microcontrol module 4 to start the internal timer. When the interference signal disconnects the external signal receiver, the voltage detected by the comparator U8 is lower than the threshold, and the comparator U8 outputs a low level. When the comparator U8 outputs a low level, the PMOS transistor M1 conducts, and the low-level signal is transmitted to the microcontrol module 4. Then, the microcontrol module 4 stops the internal timer from timing, and the time difference calculated by the timer is the interference duration of the crane.

[0050] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A spatial spectrum interference duration detection circuit, characterized in that It includes a frequency sweeping module (1), a signal source module (2), a main control module (3), a micro control module (4) and a trigger module (5). Among them, the output end of the frequency sweeping module (1) is electrically connected to the input end of the main control module (3). The frequency sweeping module (1) is used to detect radio signals in a preset frequency band in space; the input end of the signal source module (2) is electrically connected to the output end of the main control module (3). The signal source module (2) is used to generate interference signals and send them into space. The output end of the signal source module (2) is electrically connected to the input end of the micro control module (4) and is used to trigger the start of timing; the trigger module (5) is electrically connected to an external signal receiver and the micro control module (4) respectively and is used to trigger the stop of timing. The micro control module (4) is communicatively connected to the main control module (3) and is used to send the interference duration to the main control module (3).

2. The spatial spectrum interference duration detection circuit according to claim 1, wherein: A connection module (6) is arranged between the signal source module (2) and the micro control module (4). The output end of the signal source module (2) is electrically connected to the input end of the connection module (6). The output end of the connection module (6) is electrically connected to the input end of the micro control module (4) and is used to receive the transmission signal of the signal source module (2) and feedback it to the micro control module (4) to trigger the start of the internal timer.

3. The spatial spectrum interference duration detection circuit according to claim 2, wherein: The connection module (6) includes a resistor R45, a resistor R46, a bidirectional breakdown diode D6, a bidirectional breakdown diode D7 and a communication interface CN2. Among them, pin 3 of the communication interface CN2 is electrically connected to one end of the resistor R45 and the bidirectional breakdown diode D7 respectively. The other end of the resistor R45 is electrically connected to the micro control module (4). Pin 2 of the communication interface CN2 is electrically connected to one end of the resistor R46 and the bidirectional breakdown diode D6 respectively. The other end of the resistor R46 is electrically connected to the micro control module (4). The other ends of the bidirectional breakdown diode D6 and the bidirectional breakdown diode D7 are grounded respectively. The communication interface CN2 is electrically connected to the signal source module (2).

4. The spatial spectrum interference duration detection circuit according to claim 1, wherein: The trigger module (5) includes a connection terminal block J4, a resistor R28, a resistor R29, a comparator U8, a capacitor C35 and a MOS transistor M1. The connection terminal block J4 is electrically connected to an external signal receiver. One end of the connection terminal block J4 is electrically connected to the resistor R28. The other end of the resistor R28 is electrically connected to the positive input end of the resistor R29 and the comparator U8 respectively. The other end of the resistor R29 is electrically connected to the negative input end of the comparator U8 and is grounded. The output end of the comparator U8 is electrically connected to the gate of the MOS transistor M1. The source of the MOS transistor M1 is electrically connected to an external power supply. The drain of the MOS transistor M1 is electrically connected to the micro control module (4). The power supply end of the comparator U8 is electrically connected to an external power supply and the capacitor C35 respectively. The other end of the capacitor C35 is grounded.

5. The spatial spectrum interference duration detection circuit according to claim 1, characterized in that: A communication module (7) is arranged between the micro control module (4) and the main control module (3). Among them, the output end of the micro control module (4) is electrically connected to the input end of the communication module (7). The output end of the communication module (7) is communicatively connected to the main control module (3) and is used to send the interference duration to the built-in screen of the main control module (3) for display.

6. The spatial spectrum interference duration detection circuit according to claim 5, wherein: The communication module (7) includes a transmitting unit (71) and a receiving unit (72). The input end of the transmitting unit (71) is electrically connected to the output end of the micro-control module (4), and the output end of the receiving unit (72) is electrically connected to the input end of the main control module (3). The transmitting unit (71) is wirelessly communicatively connected to the receiving unit (72).

7. The spatial spectrum interference duration detection circuit according to claim 6, characterized in that: Both the transmitting unit (71) and the receiving unit (72) include a communication chip U10, an antenna JP1, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a capacitor C41, a capacitor EC7, and a filter L5. The pin 19 of the communication chip U10 is electrically connected to the antenna JP1. The pins 17, 16, and 15 of the communication chip U10 are respectively electrically connected to the resistors R30, R31, and R32. The other ends of the resistors R31, R31, and R32 are commonly grounded. The pin 14 of the communication chip U10 is electrically connected to one end of the resistor R33. The pin 13 of the communication chip U10 is electrically connected to one end of the resistor R34. The other ends of the resistors R33 and R34 are both electrically connected to the output end of the micro-control module (4). The pin 11 of the communication chip U10 is respectively electrically connected to the positive electrodes of the capacitor C41, the capacitor EC7, and one end of the filter L5. The other end of the capacitor C41 is commonly grounded with the pin 10 of the communication chip U10. The negative electrode of the capacitor EC7 is grounded. The other end of the filter L5 is connected to the +5V power supply.

8. The spatial spectrum interference duration detection circuit according to claim 1, wherein: It further includes a plurality of step-down modules (8). The input end of the step-down module (8) is electrically connected to an external direct power supply, and the output end of the step-down module (8) is respectively electrically connected to the power supply terminals of the micro-control module (4) and the main control module (3) for power supply.

9. The spatial spectrum interference duration detection circuit according to claim 8, wherein: The step-down module (8) includes a step-down chip U4, capacitors C19, C20, C21, resistors R11, R14, a triode Q2, a capacitor C15, a zener diode D2, a filter L2, capacitors EC1, EC2, a capacitor C17, resistors R9, R13, and a connection terminal block J3. The pin 7 of the step-down chip U4 is electrically connected to the capacitors C19, C20, C21, and an external DC power supply respectively. The other ends of the capacitors C19, C20, and C21 are grounded respectively. The pin 1 of the step-down chip U4 is electrically connected to the capacitor C15. The other end of the capacitor C15 is electrically connected to the pin 1 of the step-down chip U4, the negative electrode of the zener diode D2, and the filter L2 respectively. The other end of the filter L2 is electrically connected to the capacitors EC1, EC2, the capacitor C17, the resistor R17, one end of the connection terminal block J3, and the output voltage respectively. The other end of the resistor R17 is electrically connected to the pin 4 of the step-down chip U4 and the resistor R19 respectively. The positive electrode of the zener diode D2, the capacitors EC5, EC6, the capacitor C26, the resistor R19, and the other end of the connection terminal block 13 are grounded respectively. The pin 5 of the step-down chip U4 is electrically connected to the collector of the triode Q2. The base of the triode Q2 is electrically connected to the resistors R11, R14, and the micro-control module (4) respectively. The other end of the resistor R14 and the emitter of the triode Q2 are commonly grounded. The other end of the resistor R11 is electrically connected to the second power supply output voltage terminal.

10. The spatial spectrum interference duration detection circuit according to claim 1, wherein: The model of the micro-control module (4) is STM32F103C8T6.

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