Display device

Abstract

A display device includes: a substrate; a transistor on the substrate; an interlayer insulating layer on the transistor; a first electrode disposed on the interlayer insulating layer and connected to the transistor via a contact hole in the interlayer insulating layer; a pixel defining layer disposed on the interlayer insulating layer and the first electrode; the sacrificial layer is arranged in the groove of the interlayer insulating layer; a gap filling layer disposed on the sacrificial layer and between a first sub-pixel defining layer and a second sub-pixel defining layer included in the pixel defining layer; a light emitting stack on the first electrode and the pixel defining layer; and a first trench formed between the first sub-pixel defining layer and the gap filling layer, between an inner wall of the groove and the gap filling layer, and between the inner wall of the groove and the sacrificial layer.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0108896, filed on August 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] A head-mounted display (HMD) is an image display device that can be worn on a user's head, and the head-mounted display can be in the form of glasses or a helmet to focus an image at a short distance in front of the user's eyes. The head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0004] The head-mounted display can magnify an image displayed on a small display device by using a plurality of lenses, and the head-mounted display can display the magnified image. Therefore, the display device applied to the head-mounted display can provide a high-resolution image, for example, an image having a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, for some head-mounted displays, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution small organic light-emitting display device, is used as the display device. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is disposed on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device having microgrooves and a method of manufacturing the display device.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate; a transistor on the substrate; an interlayer insulating layer on the transistor; a first electrode disposed on the interlayer insulating layer and connected to the transistor via a contact hole in the interlayer insulating layer; a pixel defining layer disposed on the interlayer insulating layer and the first electrode, wherein the pixel defining layer includes a first sub-pixel defining layer and a second sub-pixel defining layer spaced apart from each other; a sacrificial layer disposed in a groove of the interlayer insulating layer; a gap filling layer disposed on the sacrificial layer and between the first sub-pixel defining layer and the second sub-pixel defining layer; a light-emitting stack on the first electrode and the pixel defining layer; and a first trench formed between the first sub-pixel defining layer and the gap filling layer, between an inner wall of the groove of the interlayer insulating layer and the gap filling layer, and between the inner wall of the groove and the sacrificial layer.

[0007] In one embodiment, the first trench has a groove shape continuously formed between the first sub-pixel defining layer and the gap filling layer, between the inner wall of the groove and the gap filling layer, and between the inner wall of the groove and the sacrificial layer.

[0008] In one embodiment, the light-emitting stack is at least partially disconnected in a region corresponding to the first trench.

[0009] In one embodiment, the width of the first trench is 0.1 μm, and the depth of the first trench is

[0010] In one embodiment, a second trench is further included, which is formed between the second sub-pixel defining layer and the gap filling layer, between the other inner wall of the groove and the gap filling layer, and between the other inner wall of the groove and the sacrificial layer.

[0011] In one embodiment, the second trench has a groove shape continuously formed between the second sub-pixel defining layer and the gap filling layer, between the other inner wall of the groove and the gap filling layer, and between the other inner wall of the groove and the sacrificial layer.

[0012] In one embodiment, the light-emitting stack is at least partially disconnected in a region corresponding to the second trench.

[0013] In one embodiment, the width of the second trench is 0.1 μm, and the depth of the second trench is

[0014] In one embodiment, the top surface of the pixel defining layer is disposed at a height equal to the height of the top surface of the gap filling layer.

[0015] In one embodiment, the sacrificial layer includes indium gallium zinc oxide (IGZO) or molybdenum (Mo).

[0016] In one embodiment, the gap filling layer includes silicon oxide (SiO x )

[0017] In one embodiment, a second electrode on the light-emitting stack is further included.

[0018] According to an embodiment of the present disclosure, a method for manufacturing a display device includes: disposing an interlayer insulating layer on a substrate; disposing a first electrode on the interlayer insulating layer; disposing a pixel defining layer on the interlayer insulating layer and the first electrode; forming a preliminary trench having a groove in the interlayer insulating layer and forming a through hole in the pixel defining layer; disposing a sacrificial layer on the first electrode, the pixel defining layer, and the inner wall of the preliminary trench; disposing a gap filling layer on the sacrificial layer; removing the gap filling layer on the pixel defining layer and removing the sacrificial layer on the pixel defining layer such that the sacrificial layer remains on the first electrode, such that the gap filling layer remains on the first electrode, such that the gap filling layer remains in the preliminary trench, and such that the sacrificial layer remains in the preliminary trench; disposing a photoresist pattern that covers the sacrificial layer in the preliminary trench, the gap filling layer in the preliminary trench, and one or more portions of the sacrificial layer adjacent to the pixel defining layer; using the photoresist pattern as a mask to remove the gap filling layer on the first electrode; removing the photoresist pattern; and forming a first trench and a second trench by removing a remaining portion of the sacrificial layer except for a portion of the sacrificial layer covered by the gap filling layer in the preliminary trench using the gap filling layer in the preliminary trench as a mask.

[0019] In an embodiment, it further includes disposing a light emitting stack on the first electrode and the pixel defining layer.

[0020] In an embodiment, forming the first trench and the second trench disconnects the light emitting stack in regions corresponding to the first trench and the second trench.

[0021] In an embodiment, forming the preliminary trench divides the pixel defining layer into a first sub-pixel defining layer and a second sub-pixel defining layer spaced apart from each other by the preliminary trench.

[0022] In an embodiment, a top surface of the pixel defining layer is disposed at a height equal to a height of a top surface of the gap filling layer in the trench.

[0023] In an embodiment, the sacrificial layer includes indium gallium zinc oxide (IGZO) or molybdenum (Mo).

[0024] In an embodiment, the gap filling layer includes silicon oxide (SiO x )

[0025] In an embodiment, it further includes disposing a second electrode on the light emitting stack.

[0026] In one embodiment, the width of the first trench is 0.1 μm and the depth of the first trench is and the width of the second trench is 0.1 μm and the depth of the second trench is

[0027] Examples of the display device and the method for manufacturing the display device described herein support the implementation of micro trenches. For example, according to one embodiment, the chemical mechanical polishing method and the thickness control of the sacrificial layer described herein support the formation of micro trenches having a width of 100 nm, which cannot be achieved using conventional photolithography processes.

[0028] The effects of the present disclosure are not limited to the above effects, and other effects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by referring to the exemplary embodiments of the present disclosure described in detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is an exploded perspective view of a display device according to an embodiment;

[0031] Figure 2 is for illustration Figure 1 a layout diagram of an example of the display panel shown in;

[0032] Figure 3 is a block diagram of a display device according to an embodiment;

[0033] Figure 4 is an equivalent circuit diagram of a first sub-pixel according to an example embodiment;

[0034] Figure 5 and Figure 6 is a plan view of pixels in a display area according to an embodiment;

[0035] Figure 7 is for illustration along Figure 5 a cross-sectional view of an example of a display device taken along line A-A';

[0036] Figure 8 is a cross-sectional view of a display device according to an embodiment;

[0037] Figures 9 to 19 is a cross-sectional process diagram of a display device according to an embodiment;

[0038] Figure 20 is a diagram for describing the degree of disconnection of a light-emitting stack according to the width of a micro trench;

[0039] Figure 21 A perspective view illustrating a head-mounted display device according to an embodiment;

[0040] Figure 22 For illustration Figure 21 An exploded perspective view of an example of the head-mounted display device; and

[0041] Figure 23 A perspective view illustrating a head-mounted display device according to an embodiment. DETAILED DESCRIPTION

[0042] Embodiments supported by the present disclosure will now be more fully described hereinafter with reference to the drawings showing one or more example embodiments. However, aspects supported by the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the present utility model to those skilled in the art.

[0043] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, like reference numerals indicate like components. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0044] Although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, without departing from the teachings of one or more embodiments, the first element discussed below may be referred to as the second element. The description of an element as a "first" element does not require and does not necessarily imply the existence of a second element or other elements. Terms such as "first", "second", etc. may also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, terms such as "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0045] As used herein, the term "about" or "approximately" includes the stated value and includes an appropriate range of deviation from the particular value determined by a person of ordinary skill in the art considering the measurements discussed and the errors associated with the measurement of a particular quantity. The term "about" may mean within one or more standard deviations, or for example within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0046] As used herein, the term "substantially equal" means approximately equal or actually equal (e.g., within a threshold percentage of an equal amount).

[0047] As used herein, the term "substantially the same" means approximately the same or actually the same (e.g., within a threshold difference).

[0048] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are possible technically. The various embodiments may be practiced individually or in combination.

[0049] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 To show an exploded perspective view of a display device according to an embodiment. Figure 2 For illustration Figure 1 A layout diagram of an example of the display panel shown in Figure 3 For illustration, a block diagram of a display device according to an embodiment.

[0051] Referring to Figure 1 and Figure 2 According to an embodiment, the display device 10 is a device for displaying moving images or still images. The display device 10 according to an embodiment may be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile personal computers (UMPCs), etc. For example, the display device 10 according to an embodiment may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. Alternatively or additionally, the display device 10 according to an embodiment may be applied to smart watches, watch phones, head-mounted displays (HMDs) for implementing virtual reality and augmented reality, etc.

[0052] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a driving circuit (also referred to as a "timing control circuit" or "timing controller") 400, and a power circuit (also referred to as a "power supply unit") 500.

[0053] The display panel 100 may have a planar shape such as a quadrilateral shape or a shape similar to a quadrilateral shape in a plan view. For example, the display panel 100 may have a planar shape such as a quadrilateral shape having a shorter side in the first direction DR1 and a longer side in the second direction DR2 intersecting the first direction DR1 in a plan view. In the display panel 100, the corner where the shorter side in the first direction DR1 and the longer side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be another polygon shape, a circular shape, or an elliptical shape. In some aspects, the planar shape may be, for example, a shape similar to another polygon shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but embodiments of the present disclosure are not limited thereto.

[0054] The display panel 100 includes a display area DAA for displaying an image and a non-display area NDA for not displaying an image as Figure 2 shown.

[0055] The display area DAA includes a plurality of sub-pixels SP, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0056] Each of the plurality of sub-pixels SP includes a light-emitting element that emits light. The plurality of sub-pixels SP may be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0057] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL includes a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0058] The plurality of sub-pixels SP includes a plurality of sub-pixels SP1, SP2, and SP3 (see Figure 7 ). The plurality of sub-pixels SP1, SP2, and SP3 (see Figure 7 ) may include a plurality of pixel transistors PTR as Figure 7 shown, and the plurality of pixel transistors PTR may be formed by a semiconductor process and may be provided on a semiconductor substrate SSUB (see Figure 7 ). For example, the plurality of pixel transistors PTR may be formed of complementary metal oxide semiconductor (CMOS).

[0059] The plurality of sub-pixels SP1, SP2, and SP3 (see Figure 7Each of them can be connected to any one of a plurality of write scan lines GWL, any one of a plurality of control scan lines GCL, any one of a plurality of bias scan lines EBL, any one of a plurality of first emission control lines EL1, any one of a plurality of second emission control lines EL2, and any one of a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 (see Figure 7 ) can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0060] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0061] The scan driving area SDA can be an area where a scan driver 610 and an emission driver 620 are provided. Although Figure 2 the example in shows that the scan driver 610 is provided on the left side of the display area DAA and the emission driver 620 is provided on the right side of the display area DAA, embodiments of the present disclosure are not limited thereto. For example, the scan driver 610 and the emission driver 620 can be provided on both the left and right sides of the display area DAA.

[0062] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors can be formed on a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed by CMOS.

[0063] The scan driver 610 can include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive the scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 can generate write scan signals according to the scan timing control signal SCS of the timing control circuit 400, and output them to the write scan lines GWL in sequence. The control scan signal output unit 612 can generate control scan signals in response to the scan timing control signal SCS, and output them to the control scan lines GCL in sequence. The bias scan signal output unit 613 can generate bias scan signals according to the scan timing control signal SCS, and output them to the bias scan lines EBL in sequence.

[0064] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate first emission control signals according to the emission timing control signal ECS, and output them sequentially to the first emission control line EL1. The second emission control driver 622 may generate second emission control signals according to the emission timing control signal ECS, and output them sequentially to the second emission control line EL2.

[0065] The data driving area DDA may be an area where the data driver 700 is provided. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the plurality of data transistors may be formed of CMOS.

[0066] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610 (see Figure 7 ), and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3 (see Figure 7 ).

[0067] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed because each of the plurality of pads PD is not covered by a cover layer CVL (see Figure 7 ) and a polarizing plate POL (see Figure 7 ).

[0068] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100. For example, it may be provided on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate the heat generated from the display panel 100. The heat dissipation layer 200 may include graphite having a high thermal conductivity or a metal such as silver (Ag), copper (Cu), or aluminum (Al).

[0069] The circuit board 300 can be electrically connected to a plurality of pads PD in the pad region PDA of the display panel 100 by using a conductive bonding member such as an anisotropic conductive film. The circuit board 300 can be a flexible printed circuit board or a flexible film having a flexible material. Although the circuit board 300 is illustrated as unfolded in Figure 1 , the circuit board 300 can be bent. For an example case where the circuit board 300 is in a bent state, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100. One end of the circuit board 300 can be an end opposite to the other end of the circuit board 300, and the other end of the circuit board 300 is connected to the plurality of pads PD in the pad region PDA of the display panel 100 by using a conductive bonding member.

[0070] The timing control circuit 400 can receive digital video data and timing signals input from the outside. The timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0071] The power supply circuit 500 can generate a plurality of panel driving voltages based on a power supply voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. The description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be provided later with reference to Figure 4 .

[0072] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to one side of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0073] In one or more alternative and / or additional embodiments, similar to the scan driver 610, the emission driver 620, and the data driver 700, the timing control circuit 400 may be disposed in the timing circuit region of the non-display area NDA of the display panel 100. In this case, for example, the timing circuit region may be disposed between the data driving region DDA and the pad region PDA.

[0074] Figure 4 It is an equivalent circuit diagram of a first sub-pixel according to an exemplary embodiment.

[0075] Reference Figure 4 , the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Further, the first sub-pixel SP1 may be connected to the first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, the second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and the third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0076] The first sub-pixel SP1 may include a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor C1, and a second capacitor C2.

[0077] The light-emitting element LE emits light in response to a driving current flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE may be proportional to the driving current. The light-emitting element LE may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of the present disclosure are not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0078] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current") flowing between the source and drain electrodes of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0079] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Accordingly, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0080] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal of the write control line GCL to connect the first node N1 to the second node N2. For this purpose, since the gate electrode and the source electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the write control line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0081] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the driving current of the first transistor T1 may be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0082] The fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0083] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0084] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0085] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0086] The first node N1 is a node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0087] Each of the first through sixth transistors T1 through T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first through sixth transistors T1 through T6 may be a P-type MOSFET, but embodiments of the present disclosure are not limited thereto. Each of the first through sixth transistors T1 through T6 may be an N-type MOSFET. In one or more alternative and / or additional embodiments, some of the first through sixth transistors T1 through T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0088] Although Figure 4 the example in Figure 4 illustrates that the first sub-pixel SP1 includes six transistors T1 through T6 and two capacitors C1 and C2, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the example shown in Figure 4 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to those shown in

[0089] Further, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with Figure 4 the equivalent circuit diagram of the first sub-pixel SP1 described above and are substantially the same. Therefore, in the present disclosure, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 is omitted.

[0090] Figure 5 and Figure 6 is an example of a plan view of a pixel in a display area according to an embodiment.

[0091] Referring to Figure 5 and Figure 6 , each of the sub-pixels SP includes a first emission area EA1 as the emission area of the first sub-pixel SP1 (see Figure 7 ), a second emission area EA2 as the emission area of the second sub-pixel SP2 (see Figure 7 ), and a third emission area EA3 as the emission area of the third sub-pixel SP3 (see Figure 7 ).

[0092] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, or a rhombus in the plan view. For example, as shown in Figure 5 , the first emission area EA1 may have a rectangular shape in the plan view, having a shorter side in the first direction DR1 and a longer side in the second direction DR2. In some aspects, as shown in Figure 5 , each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape in the plan view, having a longer side in the first direction DR1 and a shorter side in the second direction DR2.

[0093] In one example, the length of the first emission area EA1 in the first direction DR1 may be less than the length of the second emission area EA2 in the first direction DR1, and the length of the first emission area EA1 in the first direction DR1 may be less than the length of the third emission area EA3 in the first direction DR1. In some aspects, the length of the second emission area EA2 in the first direction DR1 and the length of the third emission area EA3 in the first direction DR1 may be substantially the same.

[0094] The length of the first emission area EA1 in the second direction DR2 may be greater than the sum of the lengths of the second emission area EA2 in the second direction DR2 and the third emission area EA3 in the second direction DR2. The length of the second emission area EA2 in the second direction DR2 may be less than the length of the third emission area EA3 in the second direction DR2. In some embodiments, as shown in Figure 5As illustrated, the length of the second emission region EA2 in the second direction DR2 may be greater than the length of the third emission region EA3 in the second direction DR2.

[0095] Although Figure 5 the examples in illustrate that each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 has a rectangular shape in a plan view, embodiments of the present disclosure are not limited thereto. For example, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have other polygonal shapes, circular shapes, or elliptical shapes other than a quadrilateral shape in a plan view.

[0096] In each of the plurality of sub-pixels SP, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Further, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In some aspects, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of the first emission region EA1, the area of the second emission region EA2, and the area of the third emission region EA3 may be different.

[0097] In one or more alternative and / or additional embodiments, as Figure 6 shown in, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape in a plan view. In this case, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. However, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 may refer to a direction inclined 45 degrees with respect to the first direction DR1 and the second direction DR2 between the first direction DR1 and the second direction DR2. The second diagonal direction DD2 may be a direction perpendicular to the first diagonal direction DD1.

[0098] The first emission region EA1 may emit light of a first color, the second emission region EA2 may emit light of a second color, and the third emission region EA3 may emit light of a third color. In one example, the light of the first color may be light in a blue wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 600 nm to about 750 nm.

[0099] In Figure 5 the illustrated example, each of the plurality of sub-pixels SP includes three emission regions EA1, EA2, and EA3, but embodiments of the present disclosure are not limited to this. That is, for example, each of the plurality of sub-pixels SP may include four emission regions.

[0100] The layout of the emission regions of the plurality of sub-pixels SP is not limited to Figure 5 the example illustrated in. For example, the emission regions of the plurality of sub-pixels SP may be arranged in a stripe structure in which the emission regions are arranged in a first direction DR1, a structure in which the emission regions are arranged in a diamond shape, or a Figure 6 hexagonal structure in which the emission regions have a hexagonal shape in a plan view and are arranged side by side as shown in.

[0101] Figure 7 For example, a cross-sectional view of an example of the display device 10 taken along line A-A' Figure 5 is shown.

[0102] Referring to Figure 7 , the display panel 100 includes a semiconductor base plate SBP, a light-emitting element base plate EBP, a light-emitting element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0103] The semiconductor base plate SBP includes a semiconductor substrate SSUB. The semiconductor substrate SSUB includes a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR respectively. The plurality of pixel transistors PTR may be the first transistor to the sixth transistor T1 to T6 described in reference to Figure 4 .

[0104] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity (also referred to herein as an impurity of the first type). A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity (also referred to herein as an impurity of the second type). The second type of impurity may be different from the aforementioned first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. In one or more alternative and / or additional embodiments, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0105] Each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH provided between the source region SA and the drain region DA.

[0106] The lower insulating layer BINS may be disposed between the gate electrode GE and the well region WA. The side insulating layer SINS may be disposed on the side of the gate electrode GE. The side insulating layer SINS may be disposed on the lower insulating layer BINS.

[0107] Each of the source region SA and the drain region DA may be a region doped with a first type of impurity. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction DR3. The channel region CH may overlap with the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the other side of the gate electrode GE.

[0108] Each of the plurality of well regions WA further includes a first lightly doped drain region LDD1 disposed between the channel region CH and the source region SA. Each of the plurality of well regions WA further includes a second lightly doped drain region LDD2 disposed between the channel region CH and the drain region DA. The first lightly doped drain region LDD1 may have an impurity concentration lower than that of the source region SA through (e.g., close to or adjacent to) the lower insulating layer BINS. The second lightly doped drain region LDD2 may have an impurity concentration lower than that of the drain region DA through (e.g., close to or adjacent to) the lower insulating layer BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first lightly doped drain region LDD1 and the second lightly doped drain region LDD2. Accordingly, the length of the channel region CH of each of the pixel transistors PTR may be increased, which may prevent punch-through and hot carrier phenomena that may otherwise be caused by a short channel.

[0109] The first semiconductor insulating layer SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be formed of an inorganic layer such as silicon carbonitride (SiC x N y ) or silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0110] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be formed of an inorganic layer such as silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0111] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, source region SA, and drain region DA of each pixel transistor PTR via a hole passing through the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0112] A third semiconductor insulating layer SINS3 may be disposed on a side surface (or side surfaces) of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed because the top surface of each of the plurality of contact terminals CTE is not covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be formed of an inorganic layer such as silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0113] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a non-bendable rigid substrate, and the polymer resin substrate may be a bendable or flexible substrate.

[0114] The light emitting element bottom plate EBP includes a first metal layer to an eighth metal layer ML1 to ML8, a reflective electrode layer RL, a plurality of vias (also referred to as "contact holes") VA1 to VA10, and a step layer. In some aspects, the light emitting element bottom plate EBP includes a plurality of interlayer insulating layers INS1 to INS8 disposed between the first metal layer to the eighth metal layer ML1 to ML8.

[0115] The first metal layer to the eighth metal layer ML1 to ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor bottom plate SBP, thereby implementing the circuit of the first sub-pixel SP1 shown in Figure 4 . That is, the first transistor to the sixth transistor T1 to T6 are formed on the semiconductor bottom plate SBP, and the connection of the first transistor to the sixth transistor T1 to T6 with the first capacitor C1 and the second capacitor C2 is implemented through the first metal layer to the eighth metal layer ML1 to ML8. In some aspects, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light emitting element LE is also implemented through the first metal layer to the eighth metal layer ML1 to ML8.

[0116] The first interlayer insulating layer INS1 can be disposed on the semiconductor base plate SBP. Each of the first vias VA1 can penetrate the first interlayer insulating layer INS1 and be connected to a contact terminal CTE exposed from the semiconductor base plate SBP. Each of the first metal layers ML1 can be disposed on the first interlayer insulating layer INS1 and be connected to the first via VA1.

[0117] The second interlayer insulating layer INS2 can be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the second vias VA2 can penetrate the second interlayer insulating layer INS2 and be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 can be disposed on the second interlayer insulating layer INS2 and be connected to the second via VA2.

[0118] The third interlayer insulating layer INS3 can be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the third vias VA3 can penetrate the third interlayer insulating layer INS3 and be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 can be disposed on the third interlayer insulating layer INS3 and be connected to the third via VA3.

[0119] The fourth interlayer insulating layer INS4 can be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the fourth vias VA4 can penetrate the fourth interlayer insulating layer INS4 and be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 can be disposed on the fourth interlayer insulating layer INS4 and be connected to the fourth via VA4.

[0120] The fifth interlayer insulating layer INS5 can be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 can penetrate the fifth interlayer insulating layer INS5 and be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 can be disposed on the fifth interlayer insulating layer INS5 and be connected to the fifth via VA5.

[0121] The sixth interlayer insulating layer INS6 can be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 can penetrate the sixth interlayer insulating layer INS6 and be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 can be disposed on the sixth interlayer insulating layer INS6 and be connected to the sixth via VA6.

[0122] The seventh interlayer insulating layer INS7 can be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 can pass through the seventh interlayer insulating layer INS7 and be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 can be disposed on the seventh interlayer insulating layer INS7 and be connected to the seventh vias VA7.

[0123] The eighth interlayer insulating layer INS8 can be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 can pass through the eighth interlayer insulating layer INS8 and be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 can be disposed on the eighth interlayer insulating layer INS8 and be connected to the eighth vias VA8.

[0124] The first through eighth metal layers ML1 to ML8 and the first through eighth vias VA1 to VA8 can be formed of substantially the same material. The first through eighth metal layers ML1 to ML8 and the first through eighth vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The first through eighth vias VA1 to VA8 can be formed of substantially the same material. The first through eighth interlayer insulating layers INS1 to INS8 can be formed of an inorganic layer such as silicon oxide (SiO x )), but the embodiments of the present disclosure are not limited thereto.

[0125] The thicknesses of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can be greater than the thickness of the first metal layer ML1. The thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can be substantially the same. For example, the thickness of the first metal layer ML1 can be about The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can be about And the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be about

[0126] The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of each of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, the thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be about The thickness of each of the seventh via VA7 and the eighth via VA8 may be about

[0127] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be formed of an inorganic layer such as silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0128] Each of the ninth vias VA9 may pass through the ninth interlayer insulating layer INS9 and be connected to the exposed eighth metal layer ML8. The ninth via VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the ninth via VA9 may be about

[0129] The reflective electrode layer RL may be disposed on the ninth interlayer insulating layer INS9. The reflective electrode layer RL may include one or more of the first reflective electrode to the fourth reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include the first reflective electrode to the fourth reflective electrode RL1, RL2, RL3, and RL4 as shown in Figure 7 In.

[0130] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrode RL1 may contain titanium nitride (TiN).

[0131] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the second reflective electrode RL2 may contain aluminum (Al).

[0132] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the third reflective electrode RL3 may contain titanium nitride (TiN).

[0133] The fourth reflective electrodes RL4 may be respectively disposed on the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the fourth reflective electrode RL4 may contain titanium (Ti).

[0134] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be about and the thickness of the second reflective electrode RL2 may be

[0135] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9. The tenth interlayer insulating layer INS10 may be formed of an inorganic layer such as silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0136] The eleventh interlayer insulating layer INS11 may be disposed on the tenth interlayer insulating layer INS10 and the reflective electrode layer RL. The eleventh interlayer insulating layer INS11 may be formed of an inorganic layer such as silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0137] The thickness of the eleventh interlayer insulating layer INS11 may vary among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The variation in the thickness of the eleventh interlayer insulating layer INS11 may adjust the resonance distance of light emitted from the light-emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating layer INS11 may be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 7 it is illustrated that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. In Figure 7 the illustrated example, the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1.

[0138] Each of the tenth vias VA10 may pass through the eleventh interlayer insulating layer INS11 and be connected to the exposed reflective electrode layer RL. The tenth vias VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the tenth vias VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth vias VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the tenth vias VA10 in the second sub-pixel SP2 may be less than the thickness of the tenth vias VA10 in the third sub-pixel SP3.

[0139] The light-emitting element layer EML may be disposed on the light-emitting element base plate EBP. The light-emitting element layer EML may include light-emitting elements LE each having a first electrode AND, a light-emitting stack ES, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0140] The first electrode AND of each of the light-emitting elements LE may be disposed on the eleventh interlayer insulating layer INS11 and connected to the tenth vias VA10. The first electrode AND of each of the light-emitting elements LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR via the tenth vias VA10, the first reflective electrode to the fourth reflective electrodes RL1 to RL4, the first via to the ninth vias VA1 to VA9, the first metal layer to the eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first electrode AND of each of the light-emitting elements LE may include titanium nitride (TiN).

[0141] The pixel defining layer PDL may be disposed on a part of the first electrode AND of each of the light-emitting elements LE. The pixel defining layer PDL may cover the edge of the first electrode AND of each of the light-emitting elements LE. The pixel defining layer PDL may be used to separate the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0142] The first emission area EA1 can be defined as the area where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are stacked in sequence in the first sub-pixel SP1 to emit light. The second emission area EA2 can be defined as the area where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are stacked in sequence in the second sub-pixel SP2 to emit light. The third emission area EA3 can be defined as the area where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are stacked in sequence in the third sub-pixel SP3 to emit light.

[0143] The pixel defining layer PDL can include a first pixel defining layer to a third pixel defining layer PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 can be disposed on the edge of the first electrode AND of each of the light-emitting elements LE, the second pixel defining layer PDL2 can be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 can be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can be formed of an inorganic layer such as silicon oxide (SiO x )), but embodiments of the present disclosure are not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can each have a thickness of about .

[0144] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as one pixel defining layer, the height of one pixel defining layer can increase, and thus the first encapsulation inorganic layer TFE1 may be separated due to the step coverage. The step coverage refers to the ratio of the degree of the thin film coated on the inclined portion to the degree of the thin film coated on the flat portion. In some cases, as the step coverage decreases, the possibility of the thin film separating at the inclined portion increases.

[0145] Therefore, in order to prevent the first encapsulation inorganic layer TFE1 from being separated due to the step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can have a cross-sectional structure with a stepped portion. For example, the width of the first pixel defining layer PDL1 can be greater than the widths of the second pixel defining layer PDL2 and the third pixel defining layer PDL3. The width of the second pixel defining layer PDL2 can be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined in the first direction DR1 and the second direction DR2.

[0146] Each of the plurality of trenches TRC may pass through the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. The eleventh interlayer insulating layer INS11 may be partially recessed at each of the plurality of trenches TRC.

[0147] At least one trench TRC may be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 two trenches TRC are illustrated as being disposed between adjacent sub-pixels SP1, SP2, and SP3, embodiments of the present disclosure are not limited thereto.

[0148] The light-emitting stack ES may include a plurality of intermediate layers. Figure 7 The light-emitting stack ES is illustrated as having a three-tandem structure including a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3, but embodiments of the present disclosure are not limited thereto. For example, the light-emitting stack ES may have a two-tandem structure including two intermediate layers (e.g., a first intermediate layer IL1 and a second intermediate layer IL2, etc.).

[0149] In the three-tandem structure, the light-emitting stack ES may have a tandem structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack ES may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a second color, and a third intermediate layer IL3 that emits light of a third color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0150] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are stacked in sequence. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a second color, and a second electron transport layer are stacked in sequence. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a third color, and a third electron transport layer are stacked in sequence.

[0151] A first charge generation layer for supplying charge to the second intermediate layer IL2 and supplying electrons to the first intermediate layer IL1 may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first intermediate layer IL1 and a P-type charge generation layer that supplies holes to the second intermediate layer IL2. The N-type charge generation layer may contain a dopant of a metal material.

[0152] A second charge generation layer for supplying charge to a third intermediate layer IL3 and electrons to a second intermediate layer IL2 may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second intermediate layer IL2 and a P-type charge generation layer for supplying holes to the third intermediate layer IL3.

[0153] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first intermediate layer IL1 may be separated between adjacent sub-pixels SP1, SP2, and SP3. For example, the trench TRC may provide separation between the sub-pixels SP1, SP2, and SP3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the trench TRC, the second intermediate layer IL2 may be separated between adjacent sub-pixels SP1, SP2, and SP3. A void or blank space ESS may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. The third intermediate layer IL3 may be disposed such that the third intermediate layer IL3 covers the second intermediate layer IL2 in each of the trenches TRC without being separated by the trench TRC. That is, in the three-tandem structure, each of the trenches TRC may be a structure for cutting off the first charge generation layer, the second charge generation layer, and the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the double-tandem structure, each of the trenches TRC may be a structure for cutting off the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0154] To stably cut off the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between adjacent sub-pixels SP1, SP2, and SP3 through the trench TRC, the height of each trench TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In some embodiments, to cut off the first to third intermediate layers IL1, IL2, and IL3 of the light-emitting element layer EML between adjacent sub-pixels SP1, SP2, and SP3, aspects of the present disclosure include implementing another structure instead of the trench TRC. For example, instead of the trench TRC, an inverted conical isolation wall may be disposed on the pixel defining layer PDL.

[0155] The number of intermediate layers IL1, IL2, and IL3 emitting different lights is not limited to Figure 7The example shown in . For example, the light-emitting stack ES may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole-transporting layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron-transporting layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer may be disposed between the two intermediate layers.

[0156] In Figure 7 In the illustrated example, the first intermediate layer to the third intermediate layer IL1, IL2, and IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but embodiments of the present disclosure are not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first emission region EA1 and may not be disposed in the second emission region EA2 and the third emission region EA3. In another example, the second intermediate layer IL2 may be disposed in the second emission region EA2 and may not be disposed in the first emission region EA1 and the third emission region EA3. In another example, the third intermediate layer IL3 may be disposed in the third emission region EA3 and may not be disposed in the first emission region EA1 and the second emission region EA2. In the case of this example where the first intermediate layer to the third intermediate layer IL1, IL2, and IL3 are separately disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively, the first color filter to the third color filter CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0157] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmissive transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, due to the microcavity effect, the light emission efficiency of each of the first sub-pixel to the third sub-pixel SP1, SP2, and SP3 may be improved.

[0158] The encapsulation layer TFE may be disposed on the light-emitting element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE3 that support preventing oxygen or moisture from penetrating into the light-emitting element layer EML. In some aspects, the encapsulation layer TFE may include at least one organic layer that supports protecting the light-emitting element layer EML from foreign substances such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0159] The first encapsulation inorganic layer TFE1 may be disposed on the second electrode CAT, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed of multiple layers in which multiple inorganic layers such as a silicon nitride (SiN x ) layer, a silicon oxynitride (SiO x N y ) layer, a silicon oxide (SiO x ) layer, a titanium oxide (TiO x ) layer, and an aluminum oxide (AlO x ) layer are alternately stacked. The encapsulation organic layer TFE2 may be a monomer. In one or more alternative and / or additional embodiments, the encapsulation organic layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0160] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In some aspects, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0161] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filling layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter to a third color filter CF1, CF2, and CF3. The first color filter to the third color filter CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0162] The first color filter CF1 may overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 may transmit light of a first color, for example, light in a blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. Thus, the first color filter CF1 may transmit light of the first color in the light emitted from the first emission region EA1.

[0163] The second color filter CF2 may overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color, for example, light in a green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. Thus, the second color filter CF2 may transmit light of the second color in the light emitted from the second emission region EA2.

[0164] The third color filter CF3 may overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, such as light in a red wavelength band. The red wavelength band may be from approximately 600 nm to 750 nm. Thus, the third color filter CF3 may transmit the light of the third color in the light emitted from the third emission region EA3.

[0165] Multiple lenses LNS may be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS may be configured to increase the proportion of light guided to the front of the display device 10. Each of the multiple lenses LNS may have a cross-sectional shape that bulges in the upward direction.

[0166] The filling layer FIL may be disposed on the multiple lenses LNS. The filling layer FIL may have a predetermined refractive index such that light travels in the third direction DR3 at the interface between the filling layer FIL and the multiple lenses LNS. In some aspects, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0167] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. In one example, the cover layer CVL is a glass substrate, and the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer CVL. In another example, the cover layer CVL is a glass substrate, and the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a polymer resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0168] The polarizing plate POL may be disposed on one surface of the cover layer CVL. The polarizing plate POL may be a structure for preventing visibility degradation caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but the embodiments of the present disclosure are not limited thereto. In some examples, when visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter to the third color filter CF1, CF2, and CF3, the polarizing plate POL may be omitted.

[0169] Figure 8 It is a cross-sectional view of a display device 10 according to an embodiment.

[0170] As Figure 8 shown, the first electrode AND may be disposed on the eleventh interlayer insulating layer INS11. In some embodiments, as described herein, the first electrode AND may be connected to the underlying metal layer via the tenth via VA10.

[0171] The pixel defining layer PDL may be disposed on the first electrode AND and the eleventh interlayer insulating layer INS11. In one embodiment, the pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3 stacked in sequence on the first electrode AND and the eleventh interlayer insulating layer INS11 in a third direction DR3, as described herein.

[0172] The pixel defining layer PDL may define an emission region. For example, the pixel defining layer PDL may have an opening region defining a first emission region EA1 and a second emission region EA2. In one embodiment, the pixel defining layer PDL may be at least partially disconnected. In this case, the left portion of the disconnected pixel defining layer PDL may be defined as a first sub-pixel defining layer SPDL1, and the separated right portion of the pixel defining layer PDL may be defined as a second sub-pixel defining layer SPDL2. The first sub-pixel defining layer SPDL1 may be spaced apart from the second sub-pixel defining layer SPDL2 by a predetermined distance.

[0173] The sacrificial layer SAL may be disposed in the groove 660 of the eleventh interlayer insulating layer INS11. The sacrificial layer SAL may comprise a metallic material. For example, the sacrificial layer SAL may comprise indium gallium zinc oxide (IGZO) or molybdenum (Mo). For example, the sacrificial layer SAL may be made of indium gallium zinc oxide (IGZO) or molybdenum (Mo).

[0174] The gap filling layer GFL may be disposed on the sacrificial layer SAL. For example, the gap filling layer GFL may be disposed on the sacrificial layer SAL and between the first sub-pixel defining layer SPDL1 and the second sub-pixel defining layer SPDL2. The gap filling layer GFL may comprise, for example, SiO x . For example, the gap filling layer GFL may be made of SiO x . In some embodiments, the height of the top surface of the gap filling layer GFL may be the same as the height of the top surface of the pixel defining layer PDL. In other words, the top surface of the gap filling layer GFL may be disposed at the same height as the top surface of the pixel defining layer PDL. In this case, for example, the height referred to herein Figure 8 may be a dimension in the third direction DR3.

[0175] The first trench TRC1 can be formed between the first sub-pixel defining layer SPDL1 and the gap filling layer GFL, between the gap filling layer GFL and the inner wall (e.g., the left inner wall) of the groove 660 of the eleventh interlayer insulating layer INS11, and between the sacrificial layer SAL and the inner wall (e.g., the left inner wall) of the groove 660 of the eleventh interlayer insulating layer INS11. In other words, the first trench TRC1 can have a groove shape continuously formed between the first sub-pixel defining layer SPDL1 and the gap filling layer GFL, between the gap filling layer GFL and the left inner wall of the groove 660 of the eleventh interlayer insulating layer INS11, and between the sacrificial layer SAL and the left inner wall of the groove 660 of the eleventh interlayer insulating layer INS11. The inner wall of the first trench TRC1 can be defined by the sacrificial layer SAL, the gap filling layer GFL, the first sub-pixel defining layer SPDL1, and the eleventh interlayer insulating layer INS11. The first trench TRC1 can have a fine size. For example, the width W of the first trench TRC1 can be 0.1 μm, and the depth D of the first trench TRC1 can be In one embodiment, the first trench TRC1 can have a closed curve shape surrounding the emission region in a plan view. For example, the first trench TRC1 can have a closed curve shape surrounding Figure 6 the first emission region EA1 shown in, and can have the same shape as the first emission region EA1. In other words, the first trench TRC1 can have a larger size such that the first trench TRC1 surrounds the first emission region EA1 while having the same shape as the first emission region EA1 (e.g., a hexagonal closed curve shape as shown in Figure 6 .

[0176] The second trench TRC2 can be formed between the second sub-pixel defining layer SPDL2 and the gap filling layer GFL, between the gap filling layer GFL and the inner wall (e.g., the right inner wall) of the groove 660 of the eleventh interlayer insulating layer INS11, and between the sacrificial layer SAL and the inner wall (e.g., the right inner wall) of the groove 660 of the eleventh interlayer insulating layer INS11. In other words, the second trench TRC2 can have a groove shape continuously formed between the second sub-pixel defining layer SPDL2 and the gap filling layer GFL, between the gap filling layer GFL and the right inner wall of the groove 660 of the eleventh interlayer insulating layer INS11, and between the sacrificial layer SAL and the right inner wall of the groove 660 of the eleventh interlayer insulating layer INS11. The inner wall of the second trench TRC2 can be defined by the sacrificial layer SAL, the gap filling layer GFL, the second sub-pixel defining layer SPDL2, and the eleventh interlayer insulating layer INS11. The second trench TRC2 can have a fine size. For example, the second trench TRC2 can have the same width and depth as the first trench TRC1. In other words, the width of the second trench TRC2 can be 0.1 μm, and the depth of the second trench TRC2 can be

[0177] In one embodiment, the second trench TRC2 may have a closed curve shape surrounding the emission region in a plan view. For example, the second trench TRC2 may have a closed curve shape surrounding Figure 6 the first emission region EA1 shown in and may have the same shape as the first emission region EA1. In other words, the second trench TRC2 may have a larger size such that the second trench TRC2 surrounds the first emission region EA1 while having the same shape as the first emission region EA1 (e.g., a hexagonal closed curve shape as shown in Figure 6 ). In some embodiments, when the first trench TRC1 and the second trench TRC2 surround the same emission region (e.g., the first emission region EA1), the second trench TRC2 may have a larger size than the first trench TRC1 such that the second trench TRC2 surrounds both the first emission region EA1 and the first trench TRC1.

[0178] In one embodiment, the second trench TRC2 may surround an emission region other than the emission region surrounded by the first trench TRC1. For example, when the first trench TRC1 has a closed curve shape surrounding the first emission region EA1, the second trench TRC2 may surround a second emission region EA2 adjacent to the first emission region EA1. In other words, the second trench TRC2 may have a larger size such that the second trench TRC2 surrounds the second emission region EA2 while having the same shape as the second emission region EA2 (e.g., a hexagonal closed curve shape as shown in Figure 6 ).

[0179] The light-emitting stack ES may be disposed on the first electrode AND and the pixel defining layer PDL. As described herein, the light-emitting stack ES may include a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3 that are sequentially disposed on the first electrode AND and the pixel defining layer PDL in a third direction DR3. In this case, the light-emitting stack ES may be at least partially disconnected by the first trench TRC1 and the second trench TRC2 in regions corresponding to the first trench TRC1 and the second trench TRC2. For example, each of the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be disconnected in a region corresponding to the first trench TRC1. Each of the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be disconnected in a region corresponding to the second trench TRC2. In some embodiments, when the light-emitting stack ES further includes a charge generation layer disposed between adjacent intermediate layers, the charge generation layer may also be disconnected. Accordingly, an exemplary aspect of the light-emitting stack ES may prevent leakage current (e.g., side leakage current) between adjacent sub-pixels SP1, SP2, and SP3. Therefore, color mixing between adjacent sub-pixels SP1, SP2, and SP3 may be prevented.

[0180] The second electrode CAT may be disposed on the light-emitting stack ES.

[0181] Figures 9 to 19 is a cross-sectional process diagram of a display device according to an embodiment. Refer to Figures 9 to 19 Exemplary aspects of methods and processes supported by aspects of the present disclosure are described. In the description of the methods and processes herein, operations may be performed in an order different from the order shown and / or described, or may be performed in a different order or at different times. Certain operations may also be omitted from the flowcharts, one or more operations may be repeated, or other operations may be added.

[0182] As Figure 9 shown, the method may include disposing an eleventh interlayer insulating layer INS11 having a tenth via VA10 on a substrate SSUB (see Figure 7 ). Thereafter, the method may include disposing a first electrode AND on the eleventh interlayer insulating layer INS11.

[0183] As Figure 10 shown, the method may include disposing a pixel defining layer PDL on the eleventh interlayer insulating layer INS11 and the first electrode AND.

[0184] As Figure 11As shown in [figures], the method may include forming a preliminary trench PTRC in the pixel definition layer PDL and the eleventh interlayer insulating layer INS11. The preliminary trench PTRC may penetrate the pixel definition layer PDL. In this case, the pixel definition layer PDL may be disconnected by the preliminary trench PTRC and divided into a first sub-pixel definition layer SPDL1 and a second sub-pixel definition layer SPDL2. For example, the formation of the preliminary trench PTRC may disconnect the pixel definition layer PDL. In some aspects, through the preliminary trench PTRC, a via hole 777 may be formed in the pixel definition layer PDL, and a groove 666 may be formed in the eleventh interlayer insulating layer INS11 below the pixel definition layer PDL. In other words, the preliminary trench PTRC may include a via hole 777 passing through the pixel definition layer PDL and a groove 666 in the eleventh interlayer insulating layer INS11, and the via hole 777 may be connected to the groove 666. The inner wall of the preliminary trench PTRC may be defined by the eleventh interlayer insulating layer INS11, the first sub-pixel definition layer SPDL1, and the second sub-pixel definition layer SPDL2. In some embodiments, the width Wp of the preliminary trench PTRC may be 10 μm, and the depth Dp of the preliminary trench PTRC may be

[0185] As Figure 12 shown in [figures], the method may include forming a sacrificial layer SAL in the preliminary trench PTRC. For example, the method may include disposing the sacrificial layer SAL along the inner wall of the preliminary trench PTRC. In this case, the sacrificial layer SAL formed on the inner wall of the preliminary trench PTRC parallel to the third direction DR3 may have a fine width. For example, the portion of the sacrificial layer SAL formed on the inner wall of the preliminary trench PTRC may have a width. Here, this width may correspond to the width of the aforementioned first trench. Additionally, or alternatively, the method may include forming the aforementioned sacrificial layer SAL on the first electrode AND and the pixel definition layer PDL.

[0186] As Figure 13 shown in [figures], the method may include disposing a gap filling layer GFL on the sacrificial layer SAL. In this case, a portion of the gap filling layer GFL may be disposed in the preliminary trench PTRC.

[0187] As Figure 14 shown in [figures], the method may include planarizing the gap filling layer GFL and the sacrificial layer SAL. In other words, the gap filling layer GFL and the sacrificial layer SAL may be planarized relative to the top surface of the pixel definition layer PDL. For example, the method may include removing the gap filling layer GFL and the sacrificial layer SAL on the pixel definition layer PDL by a chemical mechanical polishing apparatus 555.

[0188] As Figure 15As shown, the method may include removing the gap fill layer GFL and the sacrificial layer SAL on the pixel definition layer PDL. In some embodiments, the sacrificial layer SAL and the gap fill layer GFL on the first electrode AND and the sacrificial layer SAL and the gap fill layer GFL in the preliminary trench PTRC may be retained. In other words, through Figure 14 the chemical mechanical polishing process shown in, the gap fill layer GFL and the sacrificial layer SAL may be disposed on the first electrode AND and in the preliminary trench PTRC, as Figure 15 shown. In some embodiments, the method may include performing a chemical mechanical polishing process such that the height of the top surface of the pixel definition layer PDL becomes the same as the height of the gap fill layer GFL in the preliminary trench PTRC through the polishing process.

[0189] As Figure 16 shown, the method may include setting a photoresist pattern PR such that the photoresist pattern PR covers the sacrificial layer SAL and the gap fill layer GFL in the preliminary trench PTRC and one or more portions of the sacrificial layer SAL adjacent to the pixel definition layer PDL. In other words, the method may include setting a photoresist pattern PR on the sacrificial layer SAL and the gap fill layer GFL in the preliminary trench PTRC and on one or more portions of the sacrificial layer SAL adjacent to the pixel definition layer PDL.

[0190] In an example, when an etching process is performed using the photoresist pattern PR as a mask, as Figure 17 shown, the gap fill layer GFL not covered by the photoresist pattern PR may be removed. In other words, the gap fill layer GFL on the first electrode AND may be removed through the etching process described with reference to Figure 17 the description.

[0191] As Figure 18 shown, the method may include removing the photoresist pattern PR. For example, the photoresist pattern PR may be removed through an ashing process.

[0192] As Figure 19 shown, by performing an etching process using the gap fill layer GFL in the preliminary trench PTRC as a mask, the etching process may remove the remaining portion of the sacrificial layer SAL except for the portion covered by the gap fill layer GFL. Through the etching process, the first trench TRC1 and the second trench TRC2 may be formed to have a fine size. The inner wall of the first trench TRC1 may be defined by the sacrificial layer SAL, the gap fill layer GFL, the first sub-pixel definition layer SPDL1, and the eleventh interlayer insulating layer INS11. In addition, the inner wall of the second trench TRC2 may be defined by the sacrificial layer SAL, the gap fill layer GFL, the second sub-pixel definition layer SPDL2, and the eleventh interlayer insulating layer INS11.

[0193] In some aspects, although not shown, the method may include disposing a light-emitting stack ES on a first electrode AND and a pixel defining layer PDL. In this case, the light-emitting stack ES may be disconnected in regions corresponding to the first trench TRC1 and the second trench TRC2.

[0194] In some aspects, although not shown, the method may include disposing a second electrode CAT on the light-emitting stack ES.

[0195] According to one embodiment, the thickness control and chemical mechanical polishing method of the sacrificial layer SAL support the formation of micro trenches TRC1 and TRC2 having a width of 100 nm, which cannot be achieved by a conventional photoetching process.

[0196] Figure 20 It is a diagram for describing the disconnection degree of the light-emitting stack ES according to the width of the micro trench.

[0197] As in the example shown in Figure 20 , an increase in the width of the first trench TRC1 may cause more charge generation layers CGL1 and CGL2 of the light-emitting stack ES to be disconnected. For example, when the width of the first trench TRC1 is 90 nm, the first charge generation layer CGL1 may be disconnected. When the width of the first trench TRC1 is 110 nm, the first charge generation layer CGL1 and the second charge generation layer CGL2 disposed thereon may be disconnected. In some embodiments, when the width of the first trench TRC1 is 130 nm or 150 nm, the charge generation layers CGL1 and CGL2 may be disconnected, and in some cases, the second electrode CAT may be disconnected. According to some embodiments, the width of the first trench TRC1 may preferably be 110 nm.

[0198] In some embodiments, according to Figure 20 , the display device may further include a capping layer CPL disposed on the second electrode CAT. For example, the method may include disposing the capping layer CPL on the second electrode CAT.

[0199] Figure 21 It is a perspective view illustrating a head-mounted display device according to one embodiment. Figure 22 For illustrating Figure 21 An exploded perspective view of an example of the head-mounted display device of

[0200] Referring to Figure 21 and Figure 22, the head-mounted display device 1000 according to an embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0201] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. The first display device 10_1 and the second display device 10_2 include various aspects of the display device 10 described herein, and repeated descriptions of the same elements are omitted for the sake of brevity. For example, each of the first display device 10_1 and the second display device 10_2 may be substantially the same as the display device 10 described in conjunction with Figures 1 to 6 and repeated descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0202] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0203] The intermediate frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0204] The control circuit board 1600 may be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 3 ), and transmit the digital video data DATA (see Figure 3 ) to the first display device 10_1 and the second display device 10_2 through the connector.

[0205] The control circuit board 1600 may transmit the digital video data DATA (see Figure 3 ) corresponding to the left-eye image optimized for the left eye of the user to the first display device 10_1, and may transmit the digital video data DATA (see Figure 3)Transmitted to the second display device 10_2. Alternatively, or additionally, the control circuit board 1600 may transmit the same digital video data DATA (see Figure 3 ) to the first display device 10_1 and the second display device 10_2.

[0206] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is arranged such that the housing cover 1200 covers an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for setting the user's left eye and a second eyepiece 1220 for setting the user's right eye. Figure 21 and Figure 22 Illustrate that the first eyepiece 1210 and the second eyepiece 1220 are separately arranged, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be integrated into one body.

[0207] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0208] The head-mounted band 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively held on the user's left eye and right eye. When the display device housing 1200 is implemented to be lightweight and compact, as Figure 23 shown, the head-mounted display device 1000 may be provided with a spectacle frame instead of the head-mounted band 1300.

[0209] In some aspects, the head-mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0210] Figure 23 Illustrate a perspective view of a head-mounted display device according to an embodiment.

[0211] Reference Figure 23 According to one embodiment, the head-mounted display device 1000_1 may be a glasses-type display device, and the display device housing 1200_1 may be implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to one embodiment may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple arms 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0212] The display device housing 1200_1 may contain the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the user's right eye through the right-eye lens 1020 after the optical path of the right-eye lens 1020 is changed by the optical path changing member 1070. As a result, the user may view an augmented reality image through the right eye, in which the virtual image displayed on the display device 10_3 and the real image seen through the right-eye lens 1020 are combined.

[0213] Figure 23 Illustratively, the display device housing 1200_1 is provided at the right end of the support frame 1030, but the embodiments of the present disclosure are not limited thereto. For example, the display device housing 1200_1 may be provided at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the user's left eye. In one or more alternative and / or additional embodiments, the display device housing 1200_1 may be provided at the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both the left and right eyes.

[0214] Embodiments of the present disclosure support one or more processes (e.g., methods or flowcharts) that support the features and embodiments described herein. Descriptions of elements such as "may be provided", "may be formed", etc. include processes (e.g., methods or flowcharts) for providing, forming, positioning, or modifying the elements, etc. according to the example aspects described herein.

[0215] Those of ordinary skill in the art to which the present disclosure pertains will be able to understand that the present disclosure may be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it will be understood that the example embodiments described herein are illustrative and not restrictive in all respects. It will be understood that the scope of the present disclosure is defined by the claims rather than the detailed description described herein, and all modifications and variations derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, characterized in that, Comprising: A substrate; A transistor on the substrate; An interlayer insulating layer on the transistor; A first electrode disposed on the interlayer insulating layer and connected to the transistor via a contact hole in the interlayer insulating layer; A pixel defining layer disposed on the interlayer insulating layer and the first electrode, wherein the pixel defining layer includes a first sub-pixel defining layer and a second sub-pixel defining layer spaced apart from each other; A sacrificial layer disposed in a groove of the interlayer insulating layer; A gap filling layer disposed on the sacrificial layer and between the first sub-pixel defining layer and the second sub-pixel defining layer; A light emitting stack on the first electrode and the pixel defining layer; And A first trench formed between the first sub-pixel defining layer and the gap filling layer, between an inner wall of the groove of the interlayer insulating layer and the gap filling layer, and between the inner wall of the groove and the sacrificial layer.

2. The display device according to claim 1, characterized in that, The first trench has a groove shape continuously formed between the first sub-pixel defining layer and the gap filling layer, between the inner wall of the groove and the gap filling layer, and between the inner wall of the groove and the sacrificial layer.

3. The display device according to claim 1, characterized in that, The light emitting stack is at least partially disconnected in a region corresponding to the first trench.

4. The display device according to claim 1, wherein Further comprising a second trench formed between the second sub-pixel defining layer and the gap filling layer, between the other inner wall of the groove and the gap filling layer, and between the other inner wall of the groove and the sacrificial layer.

5. The display device according to claim 4, wherein, The second trench has a groove shape continuously formed between the second sub-pixel defining layer and the gap filling layer, between the other inner wall of the groove and the gap filling layer, and between the other inner wall of the groove and the sacrificial layer.

6. The display device according to claim 4, characterized in that, The light emitting stack is at least partially disconnected in a region corresponding to the second trench.

7. The display device according to claim 4, wherein The width of the first groove is 0.1 μm and the depth of the first groove is And wherein the width of the second groove is 0.1 μm and the depth of the second groove is 8. The display device according to claim 1, wherein A top surface of the pixel defining layer is disposed at a height equal to a height of a top surface of the gap filling layer.

9. The display device according to claim 1, wherein The sacrificial layer contains indium gallium zinc oxide or molybdenum.

10. The display device according to claim 1, wherein The gap filling layer contains silicon oxide.

Images