Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a substrate body, a light shielding layer arranged on the substrate body and a plurality of transistors arranged on the light shielding layer. The shading layer comprises a first shading electrode and a second shading electrode, and the plurality of transistors comprise a first transistor and a second transistor; the first transistor comprises a first source electrode and a first drain electrode, the first source electrode is connected with the first shading electrode through a first via hole, the second transistor comprises a second source electrode and a second drain electrode, and the second source electrode is connected with the second shading electrode through a second via hole; wherein at least one of the first source electrode and the first drain electrode is adjacent to at least one of the second source electrode and the second drain electrode, and in a plane parallel to the substrate, the minimum distance between two adjacent electrodes of the first transistor and the second transistor is a first distance; the minimum distance between the first shading electrode and the second shading electrode is a second distance, and the first distance is smaller than the second distance.

Description

Technical Field

[0001] The utility model relates to the technical field of display, and more specifically, to a display substrate and a display device. Background Art

[0002] An organic light-emitting diode (OLED, Organic Light Emitting Diode) is an active light-emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, etc. With the continuous development of display technology, a display device using an OLED as a light-emitting element and controlled by a thin-film transistor (TFT, Thin Film Transistor) has become the mainstream product in the current display field. Signals between adjacent TFTs are prone to short-circuit, resulting in abnormal display. Summary of the Utility Model

[0003] An embodiment of the utility model provides a display substrate, including: a substrate, a light-shielding layer disposed on the substrate, and a plurality of transistors disposed on the light-shielding layer; the light-shielding layer includes a first light-shielding electrode and a second light-shielding electrode, and the plurality of transistors include a first transistor and a second transistor; the first transistor includes a first source electrode and a first drain electrode, the first source electrode is connected to the first light-shielding electrode through a first via hole, the second transistor includes a second source electrode and a second drain electrode, and the second source electrode is connected to the second light-shielding electrode through a second via hole; wherein, at least one of the first source electrode and the first drain electrode is adjacent to at least one of the second source electrode and the second drain electrode, in a plane parallel to the substrate, a minimum distance between two adjacent electrodes of the first transistor and the second transistor is a first distance, and a minimum distance between the first light-shielding electrode and the second light-shielding electrode is a second distance, and the first distance is less than the second distance.

[0004] In an exemplary embodiment, the first light-shielding electrode includes a first main body portion and a first connecting portion connected to each other, the first main body portion is configured to shield light from the first transistor, and the first connecting portion is configured to be connected to the first source electrode through the first via hole; the second light-shielding electrode includes a second main body portion and a second connecting portion connected to each other, the second main body portion is configured to shield light from the second transistor, and the second connecting portion is configured to be connected to the second source electrode through the second via hole.

[0005] In an exemplary embodiment, the first via hole includes a first sub-hole and a second sub-hole that communicate with each other. The second sub-hole is located on a side of the first sub-hole close to the substrate, and a positive projection of the second sub-hole on the substrate is within a range of a positive projection of the first sub-hole on the substrate; and / or, the second via hole includes a third sub-hole and a fourth sub-hole that communicate with each other. The fourth sub-hole is located on a side of the third sub-hole close to the substrate, and a positive projection of the fourth sub-hole on the substrate is within a range of a positive projection of the third sub-hole on the substrate.

[0006] In an exemplary embodiment, a positive projection of the second sub-hole on the substrate is within a range of a positive projection of the first connecting portion on the substrate, and a positive projection of the first sub-hole on the substrate and a positive projection of the first connecting portion on the substrate at least partially overlap.

[0007] In an exemplary embodiment, a positive projection of the first connecting portion on the substrate is within a range of a positive projection of the first sub-hole on the substrate.

[0008] In an exemplary embodiment, in a plane parallel to the substrate, a minimum distance between a side edge of the first connecting portion close to the second connecting portion and a side edge of the second sub-hole close to the second connecting portion is less than or equal to 1.5 micrometers.

[0009] In an exemplary embodiment, a positive projection of the fourth sub-hole on the substrate is within a range of a positive projection of the second connecting portion on the substrate, and a positive projection of the third sub-hole on the substrate and a positive projection of the second connecting portion on the substrate at least partially overlap.

[0010] In an exemplary embodiment, a positive projection of the second connecting portion on the substrate is within a range of a positive projection of the first sub-hole on the substrate.

[0011] In an exemplary embodiment, in a plane parallel to the substrate, a distance between a side edge of the second connecting portion close to the first connecting portion and a side edge of the fourth sub-hole close to the first connecting portion is less than or equal to 1.5 micrometers.

[0012] In an exemplary embodiment, the display substrate includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially disposed on the light-shielding layer; a first active layer of the first transistor and a second active layer of the second transistor are located above the first insulating layer, a first gate electrode of the first transistor and a second gate electrode of the second transistor are located above the second insulating layer, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located above the fourth insulating layer; the first source electrode and the first drain electrode are respectively connected to the first active layer through vias, and the second source electrode and the second drain electrode are respectively connected to the second active layer through vias.

[0013] In an exemplary embodiment, the first sub-hole penetrates through the fourth insulating layer, and the second sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, and the third insulating layer; or, the first sub-hole is located within the fourth insulating layer, and the second sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, the third insulating layer, and the remaining portion of the fourth insulating layer; the third sub-hole penetrates through the fourth insulating layer, and the fourth sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, and the third insulating layer; or, the third sub-hole is located within the fourth insulating layer, and the fourth sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, the third insulating layer, and the remaining portion of the fourth insulating layer.

[0014] In an exemplary embodiment, only the fourth insulating layer is disposed between the first connection portion and the first active layer, the first sub-hole is located within the fourth insulating layer, and the second sub-hole penetrates through the remaining portion of the fourth insulating layer; the third sub-hole is located within the fourth insulating layer, and the fourth sub-hole penetrates through the remaining portion of the fourth insulating layer.

[0015] In an exemplary embodiment, a capacitor is further included, and the capacitor includes a first electrode plate and a second electrode plate sequentially disposed in a direction away from the substrate. The first electrode plate is located above the second insulating layer, and the second electrode plate is located above the third insulating layer; a positive projection of the first electrode plate on the substrate at least partially overlaps with a positive projection of the second electrode plate on the substrate.

[0016] In an exemplary embodiment, the material of the light-shielding layer includes molybdenum.

[0017] In an exemplary embodiment, in a plane parallel to the substrate, the first source electrode and the second source electrode are adjacent.

[0018] An embodiment of the present invention further provides a display device, including the display substrate as described above.

[0019] The display substrate provided by the embodiment of the present utility model increases the distance between the first light-shielding electrode and the second light-shielding electrode by setting the minimum distance between two adjacent electrodes of the first transistor and the second transistor to be less than the minimum distance between the first light-shielding electrode and the second light-shielding electrode. In the case of the same circuit layout, the electric field generated between the first light-shielding electrode and the second light-shielding electrode is smaller. Even if the first light-shielding electrode and the second light-shielding electrode undergo electrochemical corrosion, charged particles are not easily moved to adjacent transistors, which can avoid signal short-circuit of adjacent transistors, and further avoid display anomalies of the display substrate. Moreover, by reducing the sizes of the first light-shielding electrode and the second light-shielding electrode, it also helps with the structural arrangement of the display substrate, providing more possibilities for the design of the display substrate and the display device.

[0020] Other features and advantages of the present utility model will be described in the following specification. Moreover, some of them will become obvious from the specification or be understood by implementing the present utility model. The objectives and other advantages of the present utility model can be achieved and obtained through the structures specifically pointed out in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings are used to provide a further understanding of the technical solutions of the present utility model, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present utility model, and do not constitute a limitation to the technical solutions of the present utility model.

[0022] Figure 1 is a schematic structural diagram of a display substrate;

[0023] Figure 2 is a schematic plan view structure diagram of a display substrate;

[0024] Figure 3 is a schematic plan view structure diagram of a display area in a display substrate;

[0025] Figure 4 is Figure 3 a schematic cross-sectional structure diagram of the display substrate along the EE direction in

[0026] Figure 5 is a schematic equivalent circuit diagram of a gate driving circuit;

[0027] Figure 6 is a schematic cross-sectional structure diagram of a display substrate in an exemplary embodiment;

[0028] Figure 7 is a schematic cross-sectional structure diagram of a first source electrode and a first connection part in an exemplary embodiment;

[0029] Figure 8 is in an exemplary embodiment Figure 6Orthographic projection relationship diagram of the first source electrode and the second source electrode on the substrate;

[0030] Figure 9 Schematic cross-sectional structure diagram of the display substrate in yet another exemplary embodiment;

[0031] Figure 10 Schematic cross-sectional structure diagram of the first source electrode and the first connection portion in yet another exemplary embodiment;

[0032] Figure 11 In an exemplary embodiment Figure 8 Orthographic projection relationship diagram of the first source electrode and the second source electrode on the substrate. Detailed implementation mode

[0033] To make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, the embodiments of the present utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the present application can be combined with each other arbitrarily. Although many possible feature combinations are shown in the drawings and discussed in the detailed implementation mode, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.

[0034] In the drawings, sometimes for clarity, the sizes, thicknesses of layers or regions of one or more constituent elements are exaggerated. Therefore, one embodiment of the present utility model is not necessarily limited to this size, and the shapes and sizes of one or more components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one embodiment of the present utility model is not limited to the shapes or values shown in the drawings, etc.

[0035] The ordinal numbers such as "first", "second", "third", etc. in the present utility model are set to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present utility model means two or more quantities.

[0036] In the present utility model, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0037] In the description of the embodiments of the present utility model, unless otherwise clearly specified and limited, the terms "connection", "direct connection", "indirect connection", "fixed connection", "installation", "assembly" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; the terms "installation", "connection", "fixed connection" may be directly connected or indirectly connected through an intermediate medium, and may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0038] In the present utility model, "electrically connected" includes the case where constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0039] In the present utility model, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and therefore, it also includes the state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and therefore, it also includes the state where the angle is more than 85° and less than 95°.

[0040] The embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.

[0041] Figure 1 It is a schematic structural diagram of a display substrate. As Figure 1As shown, the display substrate may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line, the data signal line, and the light-emitting signal line. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in a manner of sequentially transmitting the scan start signal provided in the form of a conductive level pulse to the next-stage circuit under the control of a clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in a manner of sequentially transmitting the emission stop signal provided in the form of a cutoff level pulse to the next-stage circuit under the control of a clock signal, where o may be a natural number.

[0042] Figure 2 is a schematic plan view of a display substrate. As Figure 2As shown, the display substrate may include a display area AA and a non-display area BB surrounding the display area AA. A light-emitting element and a pixel driving circuit may be provided in the display area AA, and a gate driving circuit 301 may be provided in the non-display area BB.

[0043] Figure 3 It is a schematic plan view of the display area in a display substrate. As Figure 3 shown, the display area AA of the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, and a third sub-pixel P3 that emits third-color light. Each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting elements in each sub-pixel are respectively connected to the pixel driving circuit of the corresponding sub-pixel, and the light-emitting elements are configured to emit light with a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0044] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombic, pentagonal, or hexagonal. The three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular (e.g., "pin" shape) manner, etc. The present invention does not make a limitation here.

[0045] In an exemplary embodiment, the pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel (W) that emits white light. Another example is that the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, square, or diamond shape manner, etc. The present invention does not make a limitation here.

[0046] Figure 4 For Figure 3 a schematic cross-sectional structure diagram of the display substrate along the EE direction in, which schematically shows the cross-sectional structure of the gate driving circuit and briefly shows the film layer structure of the display substrate. As Figure 4As shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101. The driving circuit layer 102 may include a plurality of transistors and storage capacitors constituting a gate driving circuit 301. The driving circuit layer 102 may be connected to sub-pixels in a display area AA to drive the corresponding sub-pixels to emit light. The substrate 101 may be a flexible substrate or a rigid substrate, and the present invention does not limit this. In some possible implementation manners, the display substrate may include other film layers, and the present invention does not limit this here.

[0047] Figure 5 It is a schematic equivalent circuit diagram of a gate driving circuit. As Figure 5 shown, the gate driving circuit 301 may include: a first scanning transistor GT1 to an eighth scanning transistor GT8, a first scanning capacitor GC1, and a second scanning capacitor GC2. In other embodiments, the gate driving circuit 301 may adopt a circuit structure of other structures, and the present invention does not limit this.

[0048] In an exemplary embodiment, the gate electrode of the first scanning transistor GT1 is electrically connected to the first clock signal terminal GCK1, the first pole of the first scanning transistor GT1 is electrically connected to the input terminal GIN, and the second pole of the first scanning transistor GT1 is electrically connected to the first node G1; the gate electrode of the second scanning transistor GT2 is electrically connected to the first node G1, the first pole of the second scanning transistor GT2 is electrically connected to the first clock signal terminal GCK1, and the second pole of the second scanning transistor GT2 is electrically connected to the second node G2; the gate electrode of the third scanning transistor GT3 is electrically connected to the first clock signal terminal GCK1, the first pole of the third scanning transistor GT3 is electrically connected to the second power supply terminal VGL, and the second pole of the third scanning transistor GT3 is electrically connected to the second node G2; the gate electrode of the fourth scanning transistor GT4 is electrically connected to the second node G2, the first pole of the fourth scanning transistor GT4 is electrically connected to the first power supply terminal VGH, and the second pole of the fourth scanning transistor GT4 is electrically connected to the output terminal GOUT; the gate electrode of the fifth scanning transistor GT5 is electrically connected to the third node G3, the first pole of the fifth scanning transistor GT5 is electrically connected to the second clock signal terminal GCK2, and the second pole of the fifth scanning transistor GT5 is electrically connected to the output terminal GOUT; the gate electrode of the sixth scanning transistor GT6 is electrically connected to the second node G2, the first pole of the sixth scanning transistor GT6 is electrically connected to the first power supply terminal VGH, and the second pole of the sixth scanning transistor GT6 is electrically connected to the first pole of the seventh scanning transistor GT7; the gate electrode of the seventh scanning transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second pole of the seventh scanning transistor GT7 is electrically connected to the first node G1; the gate electrode of the eighth scanning transistor GT8 is electrically connected to the second power supply terminal VGL, the first pole of the eighth scanning transistor GT8 is electrically connected to the first node G1, and the second pole of the eighth scanning transistor GT8 is electrically connected to the third node G3; one end of the first scanning capacitor GC1 is electrically connected to the first power supply terminal VGH, and the other end of the first scanning capacitor GC1 is electrically connected to the second node G2; the first electrode plate GC21 of the second scanning capacitor GC2 is electrically connected to the output terminal GOUT, and the second electrode plate GC22 of the second scanning capacitor GC2 is electrically connected to the third node G3.

[0049] In an exemplary embodiment, the first scanning transistor GT1 to the eighth scanning transistor GT8 can be P-type transistors or can be N-type transistors.

[0050] In an exemplary embodiment, the first power supply terminal VGH can be connected to the first power line through a high-voltage transmission line to continuously provide a high-level signal, and the second power supply terminal VGL can be connected to the second power line through a low-voltage transmission line to continuously provide a low-level signal.

[0051] In an exemplary embodiment, four clock signal lines may be used to provide a clock signal to the gate driving circuit 301, or six, eight, or a greater number of clock signal lines may be used to provide a clock signal to the gate driving circuit 301. The present invention places no limitations on the circuit structure of the gate driving circuit 301 or the number of clock signal lines used.

[0052] Figure 6 FIG. 4 is a schematic cross-sectional structure diagram of a display substrate in an exemplary embodiment, showing two adjacent transistor structures, with other film layer structures omitted for illustration. As Figure 6 shown, the display substrate may include a substrate 101 and a driving circuit layer 102 disposed on the substrate 101. The driving circuit layer 102 includes a light-shielding layer, a plurality of transistors and capacitors disposed on the light-shielding layer. The light-shielding layer may include a plurality of light-shielding electrodes located on the side of the transistors closer to the substrate 101, which can block the light incident from the side of the substrate 101 away from the light-shielding layer from affecting the transistors in the display substrate, preventing the transistors from being irradiated by external light and causing changes in their electrical characteristics, thereby improving the stability of the transistors. For example, the semiconductor material used for the active layer of the transistors has a photoconductive effect, and its electrical characteristics such as the on-state current and off-state current change significantly between the light-on state and the light-off state, that is, problems such as drift are likely to occur in the light-on state, resulting in unstable electrical characteristics.

[0053] In an exemplary embodiment, as Figure 6As shown, a first transistor A1 is disposed on a side of the first light-shielding electrode 21 away from the substrate 101. The first transistor A1 includes a first active layer 22, a first gate electrode 23, a first source electrode 24, and a first drain electrode 25. The first source electrode 24 can be connected to the first light-shielding electrode 21 through a first via hole. A second transistor A2 is disposed on a side of the second light-shielding electrode 31 away from the substrate 101. The second transistor A2 includes a second active layer 32, a second gate electrode 33, a second source electrode 34, and a second drain electrode 35. The second source electrode 34 can be connected to the second light-shielding electrode 31 through a second via hole. In an exemplary embodiment, the light-shielding electrode has a certain voltage after being powered on, and can form an auxiliary electric field that enables the channel region of the transistor to conduct with the corresponding gate electrode. A first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 are further disposed between the light-shielding layer and the transistor. The first insulating layer 11 can be referred to as a buffer layer, the second insulating layer 12 can be referred to as a gate insulating (GI) layer, the third insulating layer 13 can be referred to as a first interlayer dielectric (ILD), and the fourth insulating layer 14 can be referred to as a second interlayer dielectric. The capacitor can include a first electrode plate 41 and a second electrode plate 42 disposed opposite to each other in a direction perpendicular to the substrate 101. The first electrode plate 41 can be disposed on the same layer as the gate electrode. The second electrode plate 42 can be disposed on a side of the first electrode plate 41 away from the substrate 101, and can be spaced from the first electrode plate 41 by the third insulating layer 13. Figure 5 Taking the example that the first source electrode 24 of the first transistor A1 and the second source electrode 34 of the second transistor A2 are adjacent as an illustration, the "adjacent" of the two transistors means that there is no other transistor structure between the two transistors. In other embodiments, the adjacent relationship between the first source electrode 24, the first drain electrode 25, the second source electrode 34, and the second drain electrode 35 can be set as needed, and the present invention does not limit this.

[0054] As Figure 6 shown, the first source electrode 24 and the second source electrode 34 are adjacent. The minimum distance between the first source electrode 24 and the second source electrode 34 is a first distance, and the minimum distance between the first light-shielding electrode 21 and the second light-shielding electrode 31 is a second distance. The first distance and the second distance are equal, both being D.

[0055] In an exemplary embodiment, the first light-shielding electrode 21 may include a first main body portion 221 and a first connecting portion 222 that are connected to each other. The first main body portion 221 is arranged to shield light from the first transistor A1, and the first connecting portion 222 is arranged to be connected to the first source electrode 24. The first connecting portion 222 can also shield light from the first transistor A1. The second light-shielding electrode 31 may include a second main body portion 321 and a second connecting portion 322 that are connected to each other. The second main body portion 321 is arranged to shield light from the second transistor A2, and the second connecting portion 322 is arranged to be connected to the second source electrode 34 and to shield light from the second transistor A2. When the first source electrode 24 and the second source electrode 34 are adjacent, the distance between the first light-shielding electrode 21 and the second light-shielding electrode 31 is the distance between the first connecting portion 222 and the second connecting portion 322.

[0056] Figure 7 FIG. is a schematic cross-sectional structure diagram of the first source electrode and the first connecting portion in an exemplary embodiment. As Figure 7 shown, in the direction perpendicular to the substrate 101, only the fourth insulating layer 14 may be provided between the first source electrode 24 and the first connecting portion 222 of the first light-shielding electrode 21. The film layer between the first source electrode 24 and the first connecting portion 222 can be set as needed, and the present invention does not limit this. A via K may be formed on the fourth insulating layer 14, and the first source electrode 24 is connected to the first connecting portion 222 through the via K. The orthographic projection of the first source electrode 24 on the substrate 101 coincides with the orthographic projection of the first connecting portion 222 on the substrate 101, and the orthographic projection of the via K on the substrate 101 is within the orthographic projection of the first connecting portion 222 on the substrate 101, which can ensure stable connection between the first source electrode 24 and the first connecting portion 222. As Figure 7 shown, in the same direction in the plane where the substrate 101 is located, the distance between the edge of the via K and the edge of the first source electrode 24 is equal to the distance between the edge of the via K and the edge of the first connecting portion 222, both being L. The size of L can be set as needed, and L in different directions can be set to different values. The present invention does not limit this. The cross-sectional structure of the second source electrode 34 and the second connecting portion 322 can be referred to Figure 7 shown, and will not be elaborated here.

[0057] Figure 8 FIG. is for an exemplary embodiment Figure 6 is a diagram showing the orthographic projection relationship of the first source electrode and the second source electrode on the substrate, showing the orthographic projection relationship of the first source electrode 24, the second source electrode 34, the first connecting portion 222, and the second connecting portion 322 on the substrate 101. Figure 8 Only part of the first main body portion 221 and the second main body portion 321 are shown in Figure 7The orthographic projection relationship between the first source electrode and the second source electrode on the substrate can be referred to Figure 8 as shown, which will not be elaborated here.

[0058] As Figure 8 shown, the orthographic projection of the first source electrode 24 on the substrate 101 coincides with the orthographic projection of the first connection portion 222 on the substrate 101, and the orthographic projection of the second source electrode 34 on the substrate 101 coincides with the orthographic projection of the second connection portion 322 on the substrate 101. The minimum distance between the first source electrode 24 and the second source electrode 34 is the first distance D1, and the minimum distance between the first connection portion 222 and the second connection portion 322 is the second distance D2. The first distance D1 is equal to the second distance D2. The inventor of the present utility model has found through research that during the reliability test, the light-shielding electrode is prone to electrochemical corrosion in a high-temperature and high-humidity environment. For example, the material of the light-shielding electrode includes metal molybdenum (Mo). After losing electrons, Mo atoms form Mo ions. When the second distance D2 is small, for example, the second distance D2 is about 3 micrometers, the electric field between the first connection portion 222 and the second connection portion 322 is large, and Mo ions are easily migrated to the adjacent light-shielding layer under the action of the electric field, resulting in signal short-circuit of the adjacent transistors, and further causing output abnormality of the circuit where these two transistors are located, resulting in display abnormality of the display substrate.

[0059] An embodiment of the present utility model provides a display substrate, including: a substrate, a light-shielding layer provided on the substrate, and a plurality of transistors provided on the light-shielding layer; the light-shielding layer includes a first light-shielding electrode and a second light-shielding electrode, and the plurality of transistors includes a first transistor and a second transistor; the first transistor includes a first source electrode and a first drain electrode, and the first source electrode is connected to the first light-shielding electrode through a first via hole. The second transistor includes a second source electrode and a second drain electrode, and the second source electrode is connected to the second light-shielding electrode through a second via hole; wherein, at least one of the first source electrode and the first drain electrode is adjacent to at least one of the second source electrode and the second drain electrode. In a plane parallel to the substrate, the minimum distance between two adjacent electrodes of the first transistor and the second transistor is the first distance, and the minimum distance between the first light-shielding electrode and the second light-shielding electrode is the second distance, and the first distance is less than the second distance.

[0060] The display substrate provided by the embodiment of the present utility model increases the distance between the first light-shielding electrode and the second light-shielding electrode by setting the minimum distance between two adjacent electrodes of the first transistor and the second transistor to be less than the minimum distance between the first light-shielding electrode and the second light-shielding electrode. In the case of the same circuit layout, the electric field generated between the first light-shielding electrode and the second light-shielding electrode is smaller. Even when the first light-shielding electrode and the second light-shielding electrode undergo electrochemical corrosion, charged particles are not easily moved to adjacent transistors, which can avoid signal short circuits in adjacent transistors and further avoid display anomalies on the display substrate. Moreover, by reducing the sizes of the first light-shielding electrode and the second light-shielding electrode, it also helps with the structural arrangement of the display substrate, providing more possibilities for the design of the display substrate and the display device.

[0061] In an exemplary embodiment, one electrode of the first transistor being adjacent to one electrode of the second transistor means that there are no other transistor structures such as electrodes between these two electrodes.

[0062] In an exemplary embodiment, the first light-shielding electrode includes a first main body portion and a first connection portion connected to each other. The first main body portion is configured to block light from the first transistor, and the first connection portion is configured to be connected to the first source electrode through the first via hole; the second light-shielding electrode includes a second main body portion and a second connection portion connected to each other. The second main body portion is configured to block light from the second transistor, and the second connection portion is configured to be connected to the second source electrode through the second via hole.

[0063] In an exemplary embodiment, the first via hole includes a first sub-hole and a second sub-hole communicating with each other. The second sub-hole is located on the side of the first sub-hole closer to the substrate, and the orthographic projection of the second sub-hole on the substrate is within the orthographic projection of the first sub-hole on the substrate; the orthographic projection of the second sub-hole on the substrate is within the orthographic projection of the first connection portion on the substrate, and the orthographic projection of the first sub-hole on the substrate at least partially overlaps with the orthographic projection of the first connection portion on the substrate.

[0064] In an exemplary embodiment, the orthographic projection of the first connection portion on the substrate is within the orthographic projection of the first sub-hole on the substrate.

[0065] In an exemplary embodiment, in a plane parallel to the substrate, the minimum distance between one side edge of the first connecting portion close to the second connecting portion and the edge of the second sub-hole close to the second connecting portion is less than or equal to 1.5 micrometers. For example, the minimum distance between one side edge of the first connecting portion close to the second connecting portion and the edge of the second sub-hole close to the second connecting portion is less than or equal to 1.3 micrometers. The minimum distances between the other side edges of the first connecting portion and the corresponding edges of the second sub-hole can be set as needed, that is, the sizes of the second sub-hole surrounded by the respective edges of the first connecting portion can be set as needed.

[0066] In an exemplary embodiment, the second via hole includes a third sub-hole and a fourth sub-hole that communicate with each other. The fourth sub-hole is located on the side of the third sub-hole close to the substrate. The orthographic projection of the fourth sub-hole on the substrate is within the orthographic projection of the third sub-hole on the substrate; the orthographic projection of the fourth sub-hole on the substrate is within the orthographic projection of the second connecting portion on the substrate, and the orthographic projection of the third sub-hole on the substrate and the orthographic projection of the second connecting portion on the substrate at least partially overlap.

[0067] In an exemplary embodiment, the orthographic projection of the second connecting portion on the substrate is within the orthographic projection of the first sub-hole on the substrate.

[0068] In an exemplary embodiment, in a plane parallel to the substrate, the distance between one side edge of the second connecting portion close to the first connecting portion and the edge of the fourth sub-hole close to the first connecting portion is less than or equal to 1.5 micrometers. For example, the distance between one side edge of the second connecting portion close to the first connecting portion and the edge of the fourth sub-hole close to the first connecting portion can be less than or equal to 1.3 micrometers. The minimum distances between the other side edges of the second connecting portion and the corresponding edges of the fourth sub-hole can be set as needed, that is, the sizes of the fourth sub-hole surrounded by the respective edges of the second connecting portion can be set as needed.

[0069] In an exemplary embodiment, in a direction away from the light-shielding layer, the display substrate includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer arranged in sequence; the first active layer of the first transistor and the second active layer of the second transistor are located above the first insulating layer, the first gate electrode of the first transistor and the second gate electrode of the second transistor are located above the second insulating layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located above the fourth insulating layer; the first source electrode and the first drain electrode are respectively connected to the first active layer through vias, and the second source electrode and the second drain electrode are respectively connected to the second active layer through vias.

[0070] In an exemplary embodiment, the first sub-hole penetrates through the fourth insulating layer, and the second sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, and the third insulating layer; the third sub-hole penetrates through the fourth insulating layer, and the fourth sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, and the third insulating layer.

[0071] In an exemplary embodiment, in a plane parallel to the substrate, the first source electrode and the second source electrode are adjacent.

[0072] In an exemplary embodiment, the display substrate further includes a capacitor located on a side of the light-shielding layer away from the substrate; the capacitor includes a first electrode plate and a second electrode plate sequentially arranged in a direction away from the substrate, the first electrode plate is located above the second insulating layer, and the second electrode plate is located above the third insulating layer; a positive projection of the first electrode plate on the substrate and a positive projection of the second electrode plate on the substrate at least partially overlap. In other embodiments, the capacitor may include a greater number of electrode plates, and the shape and distribution of the electrode plates can be set as needed, and the present invention does not limit this.

[0073] In an exemplary embodiment, the material of the light-shielding layer includes molybdenum metal, and other suitable materials can be selected to form the light-shielding layer as needed, and the present invention does not limit this.

[0074] In an exemplary embodiment, the first transistor and the second transistor can be transistors in a pixel driving circuit, or transistors in a gate driving circuit, or transistors in other circuit structures, and the present invention does not limit this.

[0075] Figure 9 FIG. is a schematic cross-sectional structure diagram of a display substrate in yet another exemplary embodiment, showing two adjacent transistor structures. Figure 9 Differences from Figure 6 lie in the different shapes of the first via hole and the second via hole, and the different sizes of the first connecting portion 222 and the second connecting portion 322. The remaining content can refer to the foregoing description of Figure 6 and will not be elaborated herein.

[0076] Figure 10 FIG. is a schematic cross-sectional structure diagram of the first source electrode and the first connecting portion in yet another exemplary embodiment. Figure 10 Differences from Figure 7 lie in the different dimensional proportional relationships among the first connecting portion 222, the first source electrode 24, and the first via hole. The remaining content can refer to the foregoing description of Figure 7 and will not be elaborated herein. As Figure 10As shown, in the direction perpendicular to the substrate 101, the first via hole includes a first sub-hole K11 and a second sub-hole K12 that are interconnected. The second sub-hole K12 is located on the side of the first sub-hole K11 closer to the substrate 101, and the orthographic projection of the second sub-hole K12 on the substrate 101 is within the range of the orthographic projection of the first sub-hole K11 on the substrate 101. The first sub-hole K11 and the second sub-hole K12 penetrate through the fourth insulating layer 14, exposing the surface of the first connecting portion 222. The orthographic projection of the second sub-hole K12 on the substrate 101 is within the range of the orthographic projection of the first connecting portion 222 on the substrate 101, and the orthographic projection of the first connecting portion 222 on the substrate 101 may be within the range of the orthographic projection of the first sub-hole K11 on the substrate 101. Since the first source electrode 24 is in direct contact with the first connecting portion 222 through the second sub-hole K12, the first connecting portion 222 only needs to contact the first source electrode 24 exposed by the second sub-hole K12 to achieve the connection between the two. By setting the orthographic projection of the second sub-hole K12 on the substrate 101 within the range of the orthographic projection of the first connecting portion 222 on the substrate 101, the first connecting portion 222 can cover the first source electrode 24 exposed by the second sub-hole K12, which helps to ensure a stable connection between the first source electrode 24 and the first connecting portion 222.

[0077] In an exemplary embodiment, the material of the fourth insulating layer 14 may include silicon nitride, etc., and the present invention is not limited thereto. Figure 11 In an exemplary embodiment Figure 8 is a diagram showing the orthographic projection relationship of the first source electrode and the second source electrode on the substrate, showing the orthographic projection relationship of the first source electrode 24, the second source electrode 34, the first connecting portion 222, and the second connecting portion 322 on the substrate 101, Figure 11 only shows a part of the first main body portion 221 and the second main body portion 321. Figure 11 and Figure 8 The difference lies in the different sizes of the first connecting portion 222 and the second connecting portion 322. For the rest, reference can be made to the foregoing description of Figure 8 and will not be elaborated here. Figure 10 For the orthographic projection relationship of the first source electrode and the second source electrode on the substrate in the display substrate with the structure shown, reference can be made to Figure 11 as shown, and will not be elaborated here.

[0078] Combined with Figure 9 and Figure 11As shown, the first source electrode 24 is connected through a first via hole and a first connection portion 222. The first via hole includes a first sub-hole K11 and a second sub-hole K12 that communicate with each other. The second sub-hole K12 is located on the side of the first sub-hole K11 closer to the substrate 101, and the orthographic projection of the second sub-hole K12 on the substrate 101 is within the orthographic projection of the first sub-hole K11 on the substrate 101. The first sub-hole K11 can penetrate through the fourth insulating layer 14, and the second sub-hole K12 can penetrate through the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 to expose the surface of the first connection portion 222. Alternatively, as Figure 9 shown by the second source electrode 34 in, the first sub-hole K11 can be located inside the fourth insulating layer 14, and the second sub-hole K12 can penetrate through the remaining part of the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 to expose the surface of the second connection portion 322. The present invention does not limit the number of sub-holes included in the first via hole and the film layers penetrated by each sub-hole. The orthographic projection of the second sub-hole K12 on the substrate 101 is within the orthographic projection of the first connection portion 222 on the substrate 101, and the orthographic projection of the first connection portion 222 on the substrate 101 can be within the orthographic projection of the first sub-hole K11 on the substrate 101. Since the first source electrode 24 is in direct contact with the first connection portion 222 through the second sub-hole K12, the first connection portion 222 only needs to contact the first source electrode 24 exposed by the second sub-hole K12 to achieve the connection between the two. By setting the orthographic projection of the second sub-hole K12 on the substrate 101 to be within the orthographic projection of the first connection portion 222 on the substrate 101, the first connection portion 222 can cover the first source electrode 24 exposed by the second sub-hole K12, which helps to ensure a stable connection between the first source electrode 24 and the first connection portion 222.

[0079] In an exemplary embodiment, in a plane parallel to the substrate, the minimum distance between the edge of the first connection portion 222 and the edge of the second sub-hole K12 is a third distance D3, and the third distance D3 is less than or equal to 1.5 micrometers. In a plane parallel to the substrate, the minimum distance between the edge of the first source electrode 24 and the edge of the second sub-hole K12 is a fourth distance D4, and the fourth distance D4 can be approximately 3 micrometers. By setting the third distance D3 to be less than or equal to 1.5 micrometers, the first connection portion 222 is kept as small as possible in size, which helps to increase the distance between the first connection portion 222 and the second connection portion 322 and reduce the electric field strength between the first light-shielding electrode and the second light-shielding electrode. Compared with the scheme where the orthographic projections of the first source electrode 24 and the first connection portion 222 coincide, the area of the first connection portion 222 is greatly reduced in this embodiment, and the distance from the second connection portion 322 is increased. With the progress of process technology, the third distance D3 and the fourth distance D4 can be set to larger or smaller values, and the embodiments of the present invention do not limit this.Figure 11 Taking the first connecting portion 222 and the positive projection of the first source electrode 24 as rectangular and the positive projection of the second sub-hole K12 as circular as an example for illustration, the third distance D3 between the four sides of the first connecting portion 222 and the edge of the corresponding second sub-hole K12 is less than or equal to 1.3 microns, and the fourth distance D4 between the four sides of the first source electrode 24 and the edge of the corresponding second sub-hole K12 is approximately 3 microns. The shapes and sizes of the first connecting portion 222, the first source electrode 24, the first sub-hole K11, and the second sub-hole K12 can be set as needed, and the embodiments of the present invention do not limit this.

[0080] In an exemplary embodiment, the second source electrode 34 is connected through a second via hole and a second connecting portion 322. The second via hole includes a third sub-hole K21 and a fourth sub-hole K22 that communicate with each other. The fourth sub-hole K22 is located on the side of the third sub-hole K21 close to the substrate 101, and the positive projection of the fourth sub-hole K22 on the substrate 101 is within the range of the positive projection of the third sub-hole K21 on the substrate 101. The third sub-hole K21 can penetrate the fourth insulating layer 14, and the fourth sub-hole K22 can penetrate the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 to expose the surface of the second connecting portion 322. The positive projection of the fourth sub-hole K22 on the substrate 101 is within the range of the positive projection of the second connecting portion 322 on the substrate 101, and the positive projection of the second connecting portion 322 on the substrate 101 can be within the range of the positive projection of the third sub-hole K21 on the substrate 101. Since the second source electrode 34 is in direct contact with the second connecting portion 322 through the fourth sub-hole K22, therefore, the second connecting portion 322 only needs to contact the second source electrode 34 exposed by the fourth sub-hole K22 to achieve the connection between the two. By setting the positive projection of the fourth sub-hole K22 on the substrate 101 within the range of the positive projection of the second connecting portion 322 on the substrate 101, the second connecting portion 322 can cover the second source electrode 34 exposed by the fourth sub-hole K22, which helps to ensure a stable connection between the second source electrode 34 and the second connecting portion 322.

[0081] In an exemplary embodiment, in a plane parallel to the substrate, the minimum distance between the edge of the second connection portion 322 and the edge of the fourth sub-hole K22 is a fifth distance D5, and the fifth distance D5 is less than or equal to 1.5 micrometers. In a plane parallel to the substrate, the minimum distance between the edge of the second source electrode 34 and the edge of the fourth sub-hole K22 is a sixth distance D6, and the sixth distance D6 can be approximately 3 micrometers. By setting the fifth distance D5 to be less than or equal to 1.5 micrometers, the second connection portion 322 is kept as small as possible in size, which helps to increase the distance from the first connection portion 222 and reduce the electric field strength therebetween. Compared with the scheme where the positive projections of the second source electrode 34 and the second connection portion 322 coincide, the area of the second connection portion 322 is greatly reduced in this embodiment, and the distance from the first connection portion 222 is increased. With the progress of process technology, the fifth distance D5 and the sixth distance D6 can be set to larger or smaller values, and the embodiments of the present invention do not limit this. Figure 11 Taking the positive projections of the second connection portion 322 and the second source electrode 34 as rectangles and the positive projection of the fourth sub-hole K22 as a circle as an example for illustration, the fifth distance D5 between the four sides of the second connection portion 322 and the edge of the corresponding fourth sub-hole K22 is less than or equal to 1.3 micrometers, and the sixth distance D6 between the four sides of the second source electrode 34 and the edge of the corresponding fourth sub-hole K22 is approximately 3 micrometers. The shapes and sizes of the second connection portion 322, the second source electrode 34, the third sub-hole K21, and the fourth sub-hole K22 can be set as needed, and the embodiments of the present invention do not limit this.

[0082] The inventor of the present invention found through experiments that when the first distance D1 is approximately 3 micrometers, Figure 11 the second distance D2 in [reference] is approximately 6.4 micrometers, and the distance between the first connection portion 222 and the second connection portion 322 is far enough, Figure 11 the display substrate with the structure shown in [reference] can successfully complete the reliability test without abnormal display.

[0083] The embodiments of the present invention further provide a display device, including the display substrate described in any of the above embodiments. The display device can be: an OLED display, an LED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function, and the embodiments of the present disclosure do not limit this.

[0084] Although the embodiments disclosed by the present utility model are as above, the content described is only the embodiments adopted for facilitating the understanding of the present utility model, and is not intended to limit the present utility model. Any person skilled in the art within the field to which the present utility model pertains may make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed by the present utility model. However, the scope of patent protection of the present utility model shall still be defined by the appended claims.

Claims

1. A display substrate, characterized in that, Comprising: a substrate, a light-shielding layer disposed on the substrate, and a plurality of transistors disposed on the light-shielding layer; the light-shielding layer includes a first light-shielding electrode and a second light-shielding electrode, and the plurality of transistors includes a first transistor and a second transistor; the first transistor includes a first source electrode and a first drain electrode, the first source electrode is connected to the first light-shielding electrode through a first via hole, the second transistor includes a second source electrode and a second drain electrode, and the second source electrode is connected to the second light-shielding electrode through a second via hole; wherein, at least one of the first source electrode and the first drain electrode is adjacent to at least one of the second source electrode and the second drain electrode. In a plane parallel to the substrate, a minimum distance between two adjacent electrodes of the first transistor and the second transistor is a first distance, a minimum distance between the first light-shielding electrode and the second light-shielding electrode is a second distance, and the first distance is less than the second distance.

2. The display substrate according to claim 1, wherein, The first light-shielding electrode includes a first main body portion and a first connecting portion connected to each other. The first main body portion is configured to shield light from the first transistor, and the first connecting portion is configured to be connected to the first source electrode through the first via hole; The second light-shielding electrode includes a second main body portion and a second connecting portion connected to each other. The second main body portion is configured to shield light from the second transistor, and the second connecting portion is configured to be connected to the second source electrode through the second via hole.

3. The display substrate according to claim 2, wherein The first via hole includes a first sub-hole and a second sub-hole that communicate with each other. The second sub-hole is located on a side of the first sub-hole closer to the substrate, and a positive projection of the second sub-hole on the substrate is within a positive projection of the first sub-hole on the substrate; and / or, The second via hole includes a third sub-hole and a fourth sub-hole that communicate with each other. The fourth sub-hole is located on a side of the third sub-hole closer to the substrate, and a positive projection of the fourth sub-hole on the substrate is within a positive projection of the third sub-hole on the substrate.

4. The display substrate according to claim 3, wherein A positive projection of the second sub-hole on the substrate is within a positive projection of the first connecting portion on the substrate, and a positive projection of the first sub-hole on the substrate and a positive projection of the first connecting portion on the substrate at least partially overlap.

5. The display substrate according to claim 4, wherein A positive projection of the first connecting portion on the substrate is within a positive projection of the first sub-hole on the substrate.

6. The display substrate according to claim 4, wherein In a plane parallel to the substrate, a minimum distance between a side edge of the first connecting portion closer to the second connecting portion and a side edge of the second sub-hole closer to the second connecting portion is less than or equal to 1.5 micrometers.

7. The display substrate according to claim 3, characterized in that, A positive projection of the fourth sub-hole on the substrate is within a positive projection of the second connecting portion on the substrate, and a positive projection of the third sub-hole on the substrate and a positive projection of the second connecting portion on the substrate at least partially overlap.

8. The display substrate according to claim 7, wherein A positive projection of the second connecting portion on the substrate is within a positive projection of the first sub-hole on the substrate.

9. The display substrate according to claim 7, wherein In a plane parallel to the substrate, the distance between one side edge of the second connecting portion close to the first connecting portion and the edge of the fourth sub-hole close to the first connecting portion is less than or equal to 1.5 micrometers.

10. The display substrate according to claim 3, wherein, The display substrate includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially disposed on the light-shielding layer; the first active layer of the first transistor and the second active layer of the second transistor are located above the first insulating layer, the first gate electrode of the first transistor and the second gate electrode of the second transistor are located above the second insulating layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located above the fourth insulating layer; the first source electrode and the first drain electrode are respectively connected to the first active layer through vias, and the second source electrode and the second drain electrode are respectively connected to the second active layer through vias.

11. The display substrate according to claim 10, wherein, The first sub-hole penetrates through the fourth insulating layer, and the second sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, and the third insulating layer; or, the first sub-hole is located within the fourth insulating layer, and the second sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, the third insulating layer, and the remaining portion of the fourth insulating layer; The third sub-hole penetrates through the fourth insulating layer, and the fourth sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, and the third insulating layer; or, the third sub-hole is located within the fourth insulating layer, and the fourth sub-hole sequentially penetrates through the first insulating layer, the second insulating layer, the third insulating layer, and the remaining portion of the fourth insulating layer.

12. The display substrate according to claim 10, wherein Only the fourth insulating layer is provided between the first connecting portion and the first active layer, the first sub-hole is located within the fourth insulating layer, and the second sub-hole penetrates through the remaining portion of the fourth insulating layer; The third sub-hole is located within the fourth insulating layer, and the fourth sub-hole penetrates through the remaining portion of the fourth insulating layer.

13. The display substrate according to claim 1, wherein The material of the light-shielding layer includes molybdenum metal.

14. The display substrate according to any one of claims 1-13, characterized in that, In a plane parallel to the substrate, the first source electrode and the second source electrode are adjacent.

15. A display device, characterized in that, A display substrate including the display substrate according to any one of claims 1-14.

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