SPI (Serial Peripheral Interface) expansion communication circuit and communication system

Abstract

The utility model discloses an SPI (Serial Peripheral Interface) extended communication circuit and a communication system, the SPI extended communication circuit comprises a master device, a plurality of slave devices and a buffer module, a chip selection signal output by a chip selection pin of the master device is output to chip selection pins of the plurality of slave devices through the buffer module, the clock signal output by the clock pin of the master device is output to the clock pins of the multiple slave devices through the buffer module, communication is established between the master device and the multiple slave devices through the buffer module, one master device can control the multiple slave devices at the same time, switching does not need to be conducted through a signal switching switch, SPI resources are saved, and the switching efficiency is improved. And the circuit is simplified.

Description

Technical Field

[0001] This application relates to the technical field of serial communication, and specifically relates to an SPI extended communication circuit and a communication system. Background Art

[0002] In a computer system, the Serial Peripheral Interface (SPI) is an interface that allows serial data exchange between two devices (one is called the master device and the other is called the slave device). SPI is most commonly applied to the communication circuit system between the Central Processing Unit (CPU) of a computer system and peripheral chips. For example, an Energy Metering IC transmits data such as voltage and current to the CPU through SPI.

[0003] However, in the current SPI communication scheme, the CS signal is usually set to control the switch to select and connect the corresponding slave device, and multiple slave devices cannot be controlled simultaneously. Summary of the Utility Model

[0004] In view of the above problems, this application provides an SPI extended communication circuit and a communication system, which can achieve the purpose of simultaneously controlling multiple slave devices by one master device.

[0005] The first aspect of the embodiment of this application provides an SPI extended communication circuit, including: a master device, multiple slave devices, and a buffer module;

[0006] The chip select signal output by the chip select pin of the master device is output to the chip select pins of multiple slave devices through the buffer module;

[0007] The clock signal output by the clock pin of the master device is output to the clock pins of multiple slave devices through the buffer module;

[0008] Communication is established between the master device and multiple slave devices, and between multiple slave devices through the buffer module.

[0009] In some embodiments, the buffer module includes at least one tri-state buffer, and communication is established between the master device and multiple slave devices through the tri-state buffer.

[0010] In some embodiments, communication is established between multiple slave devices through the tri-state buffer.

[0011] In some embodiments, the chip select pins of multiple slave devices are commonly connected to the chip select signal terminal on the output side of the buffer module.

[0012] In some embodiments, the clock pins of multiple said slave devices are commonly connected to the clock signal terminal on the output side of the buffer module.

[0013] In some embodiments, the master device output pin of the master device is connected to the master device signal terminal on the input side of the buffer module, and is connected to the slave device input pin of at least one slave device via the master device signal terminal on the output side of the buffer module;

[0014] The master device signal terminal on the input side of the buffer module corresponds to the master device signal terminal on the output side of the buffer module.

[0015] In some embodiments, the slave device input pins of multiple said slave devices are respectively connected to multiple slave device signal terminals on the output side of the buffer module;

[0016] The slave device output pins of multiple said slave devices are respectively connected to multiple slave device signal terminals on the input side of the buffer module.

[0017] In some embodiments, the slave device output pin of each said slave device is connected to the slave device input pin of the next said slave device, or to the master device input pin of the master device, via the slave device signal terminal on the input side of the buffer module and the slave device signal terminal on the output side of the buffer module.

[0018] In some embodiments, the tri-state buffer is an RS244 series 8-bit tri-state buffer.

[0019] In the second aspect of the embodiments of the present application, a communication system is further provided. The communication system includes the SPI extended communication circuit as described in any one of the above embodiments.

[0020] Advantageous effects of the embodiments of the present application: The chip select signal output by the chip select pin of the master device is output to the chip select pins of multiple slave devices via the buffer module, and the clock signal output by the clock pin of the master device is output to the clock pins of multiple slave devices via the buffer module. By establishing communication between the master device and multiple slave devices via the buffer module, multiple slave devices can be controlled by one master device at the same time, and there is no need for a signal switching switch for switching, saving SPI resources and simplifying the circuit.

[0021] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically given below. Description of the Drawings

[0022] Upon reading the following detailed description of the preferred embodiments, various other advantages and benefits will become apparent to those of ordinary skill in the art. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present application. Moreover, in all the drawings, the same reference numerals are used to denote the same components. In the drawings:

[0023] Figure 1 FIG. 4 is a schematic diagram of the first structure of the SPI extended communication circuit provided by an embodiment of the present application;

[0024] Figure 2 FIG. 5 is a schematic diagram of the second structure of the SPI extended communication circuit provided by an embodiment of the present application;

[0025] Figure 3 FIG. 6 is a schematic diagram of the third structure of the SPI extended communication circuit provided by an embodiment of the present application. Detailed Embodiments

[0026] The embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solutions of the present application more clearly, and therefore are only examples and cannot be used to limit the protection scope of the present application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above drawings are intended to cover non-exclusive inclusion.

[0028] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality" is more than two unless otherwise specifically defined.

[0029] Referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase "the second connection port" at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0030] In the description of the embodiments of the present application, the term "and / or" is merely an association relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0031] In the description of the embodiments of the present application, the term "multiple frames" refers to two or more (including two).

[0032] In the description of the embodiments of the present application, the orientation or positional relationship indicated by technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the embodiments of the present application.

[0033] In the current SPI communication solution, it is usually set that the CS signal controls the switch to select and connect the corresponding slave device, and multiple slave devices cannot be controlled simultaneously. To solve the above technical problems, the embodiments of the present application provide an SPI extended communication circuit. See Figure 1 As shown, the SPI extended communication circuit includes: a master device 100, multiple slave devices 310, and a buffer module 200. The chip select signal output by the chip select pin CS of the master device 100 is output to the chip select pins CS of the multiple slave devices 310 via the buffer module 200; the clock signal output by the clock pin CLK of the master device 100 is output to the clock pins of the multiple slave devices 310 via the buffer module 200; communication is established between the master device 100 and the multiple slave devices 310, and between the multiple slave devices 310 via the buffer module 200.

[0034] In this embodiment, the master device 100 sends a clock signal to the clock pins CLK of multiple slave devices 310 through the buffer module 200, which can ensure the temporal consistency of actions such as signal transmission and signal writing between the master device 100 and the slave devices 310. The master device 100 sends a chip select signal to the chip select pins CS of multiple slave devices 310 through the buffer module 200, so as to select and write corresponding data to the specified slave device 310, which can ensure that the data signal output by the master device 100 can be accurately written into the corresponding slave device 310 when passing through multiple slave devices 310. At this time, the master device 100 can communicate with the specified slave device 310 to avoid conflicts during data transmission. Communication can be established between the master device 100 and the slave devices 310 through the buffer module 200, and communication can also be established between multiple slave devices 310 through the buffer module 200. That is, the data signal output by the master device 100 is output to the corresponding slave device 310 after passing through the buffer module 200. After receiving the data signal, the corresponding slave device 310 screens the data signal according to the chip select signal and the clock signal, writes the data signal marked with the specified flag, and transmits the remaining data signals to the next slave device 310 through the buffer module 200, and so on, until after the last slave device 310 writes the data signal, the remaining data signals are fed back to the master device 100 through the buffer module 200, thereby completing the data writing of the master device 100 to all slave devices 310 and realizing the control of all slave devices 310 by the master device 100. The SPI extended communication circuit in this embodiment does not require signal switching to select a specified slave device 310 to communicate with the master device 100. All slave devices 310 can communicate with the master device 100. The data signal sent by the master device 100 can be sent to multiple slave devices 310 through the buffer module, which not only realizes the simultaneous control of multiple slave devices 310 by the master device 100, but also simplifies the circuit structure.

[0035] In some embodiments, after establishing a mapping table of each slave device 310 and its backend functions, the master device 100 sends a data signal to the buffer module 200. The control data to be written to each slave device 310 is marked in the mapping table, and the mapping table information is transmitted from the master output pin MOSI of the master device 100 to the slave input pin MOSI of the slave device 310. For example, in combination with Figure 1As shown, the mapping table information output by the master device 100 is output to the first slave device 310 via the chip select signal terminal A1 on the input side of the buffer module 200 and the chip select signal terminal Y1 on the output side. The first slave device 310 receives the control data of the corresponding mapping area, and thus writes this part of the control data with the corresponding mark into the first slave device 310. The remaining control data is output to the signal terminal A4 on the input side of the buffer module 200 via its slave device output pin MISO (the signal terminal A4 can be used as the master device signal terminal on the input side), and is output to the slave device input pin MOSI of the second slave device 310 via the signal terminal Y4 on the output side (the signal terminal Y4 can be used as the master device signal terminal on the output side), and so on.

[0036] In some embodiments, in combination with Figure 2 As shown, the buffer module 200 includes at least one tri-state buffer, and communication is established between the master device 100 and multiple slave devices 310 via the tri-state buffer.

[0037] In this embodiment, the tri-state buffer includes multiple input terminals and multiple output terminals, and the multiple input terminals and multiple output terminals correspond to each other one by one. The tri-state buffer can isolate the transmission between different levels, avoid the direct mutual influence of different levels, enable a single circuit to not affect the circuit and the bus by controlling the output, and prevent conflicts with other circuits at the same time. Specifically, the signal received by the input terminal of the tri-state buffer will be amplified and transmitted to the corresponding output terminal. According to the different values of the input signal, the tri-state buffer will set the output terminal to a high level, a low level or a high impedance state. When the input signal is at a high level, the output signal is also at a high level; when the input signal is at a low level, the output signal will become a low level; when the input signal is at a high impedance state, the output terminal will not output any signal.

[0038] In some embodiments, in combination with Figure 2 As shown, the buffer module 200 includes a first tri-state buffer 210. The chip select signal pins CS of the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314 are commonly connected to the chip select signal terminal Y1 on the output side of the first tri-state buffer 210. The clock signal pins CLK of the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314 are commonly connected to the clock signal terminal Y2 on the output side of the first tri-state buffer 210.

[0039] In this embodiment, the output-side signal terminals Y4, Y5, Y6, and Y7 of the first tri-state buffer 210 are connected in a one-to-one correspondence to the slave input pins MOSI of the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314, respectively. The slave output pins MISO of the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314 are connected in a one-to-one correspondence to the input-side signal terminals A5, A6, A7, and A8 of the first tri-state buffer 210, respectively. In this way, communication can be achieved between the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314. The master output pin MOSI of the master device 100 is connected to the input-side signal terminal A4 of the first tri-state buffer 210, and the output-side signal terminal Y8 of the first tri-state buffer 210 is connected to the master input pin MISO of the master device 100.

[0040] In some embodiments, the signal terminal A3 on the input side and the signal terminal Y3 on the output side of the first tri-state buffer 210 can be used as reserved signal terminals for establishing other signal links between the master device 100 and the slave device 310 .

[0041] In some embodiments, combined Figure 3 As shown, the buffer module 200 may include a plurality of tri-state buffers.

[0042] In this embodiment, the number of input terminals and output terminals of the tri-state buffer can be set according to application requirements. When the number of slave devices 310 exceeds the number of output terminals of the tri-state buffer, data transmission between the slave devices can be achieved through multiple tri-state buffers. For example, the last output terminal of the first tri-state buffer outputs a data signal to the corresponding slave device, and the slave device output pin of the slave device can be connected to the first input terminal of the next tri-state buffer, and output the corresponding data signal to the slave device input pin of the next slave device via the corresponding first output terminal, and so on.

[0043] In some embodiments, combined Figure 3 As shown, the number of slave devices 310 on the output side of the buffer module 200 is 8, and the buffer module 200 includes a first tri-state buffer 210 and a second tri-state buffer 220. The first slave device 311, the second slave device 312, the third slave device 313, the fourth slave device 314, the fifth slave device 315, the sixth slave device 316, the seventh slave device 317 and the eighth slave device 318 establish communication with the master device 100 via the first tri-state buffer 210 and the second tri-state buffer 220.

[0044] In this embodiment, the signal terminals Y4, Y5, Y6, and Y7 on the output side of the first tri-state buffer 210 are respectively and correspondingly connected to the slave input pins MOSI of the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314. The slave output pins MISO of the first slave device 311, the second slave device 312, the third slave device 313, and the fourth slave device 314 are respectively and correspondingly connected to the signal terminals A5, A6, A7, and A8 on the input side of the first tri-state buffer 210. The signal terminal Y8 on the output side of the first tri-state buffer 210 is connected to the slave input pin MOSI of the fifth slave device 315. The slave output pins MISO of the fifth slave device 315, the sixth slave device 316, and the seventh slave device 317 are respectively connected to the signal terminals A9, A10, and A11 on the input side of the second tri-state buffer 220. The signal terminals Y9, Y10, and Y11 on the output side of the second tri-state buffer 220 are respectively connected to the slave input pins MOSI of the sixth slave device 316, the seventh slave device 317, and the eighth slave device 318. The slave output pin MISO of the eighth slave device 318 is connected to the master input pin MISO of the master device 100.

[0045] In some embodiments, when the number of slave devices 310 continues to increase, the slave output pin MISO and the slave input pin MOSI of the newly added slave device 310 are both connected to the corresponding signal terminals on the input side and the output side of the second tri-state buffer 220.

[0046] In some embodiments, the number of tri-state buffers in the buffer module 200 can also be increased according to the number of slave devices 310, so that the slave output pin MISO and the slave input pin MOSI of each slave device 310 are both connected to the corresponding signal terminals on the input side and the output side of the tri-state buffer.

[0047] In some embodiments, communication is established between multiple slave devices 310 via tri-state buffers.

[0048] In this embodiment, multiple slave devices 310 can perform data transmission via a tri-state buffer. For example, the master device 100 is connected to the master device signal terminal on the input side of the tri-state buffer, and a data signal is sent to this master device signal terminal. The multiple signal terminals on the input side of the tri-state buffer correspond one by one to the multiple signal terminals on its output side. The slave input pin of the first slave device is connected to the master device signal terminal on the output side of the tri-state buffer, and the slave output pin of the first slave device is connected to the first slave device signal terminal on the input side of the tri-state buffer, and is connected to the second slave device via the first slave device signal terminal on the output side of the tri-state buffer, thereby realizing signal transmission between the first slave device and the second slave device. The slave output pin of the second slave device is connected to the second slave device signal terminal on the input side of the tri-state buffer, and is connected to the third slave device via the second slave device signal terminal on the output side of the tri-state buffer, thereby realizing signal transmission between the second slave device and the third slave device, and so on.

[0049] In some embodiments, in combination with Figure 1 as shown, the chip select pins CS of multiple slave devices 310 are commonly connected to the chip select signal terminal Y1 on the output side of the buffer module 200.

[0050] In this embodiment, the signal of the chip select signal terminal A1 on the input side of the buffer module 200 is output to the chip select signal terminal Y1 on its output side after being processed by the buffer module 200. The chip select signal pin CS of the master device 100 is connected to the chip select signal terminal A1 on the input side of the buffer module 200, and the chip select pins CS of multiple slave devices 310 are commonly connected to the chip select signal terminal Y1 on the output side of the buffer module 200. The master device 100 sends a chip select signal to the chip select pins CS of multiple slave devices 310 through the buffer module 200. Multiple slave devices 310 can be selected simultaneously or not selected simultaneously according to the chip select signal. When the mapping table information output by the master device 100 is output to the first slave device 310 via the chip select signal terminal A1 on the input side and the chip select signal terminal Y1 on the output side of the buffer module 200, the first slave device 310 receives the control data of the corresponding mapped area, and thus writes this part of the marked control data into the first slave device 310, which can ensure that the data signal output by the master device 100 can be accurately written into the corresponding slave device 310. At this time, the master device 100 can communicate with the specified slave device 310 to avoid conflicts during data transmission.

[0051] In some embodiments, the clock pins CLK of multiple slave devices 310 are commonly connected to the clock signal terminal Y2 on the output side of the buffer module 200.

[0052] In this embodiment, the signal of the clock signal terminal A3 on the input side of the buffer module 200 is output to the clock signal terminal Y2 on its output side after being processed by the buffer module 200. The clock signal pin of the master device 100 is connected to the clock signal terminal on the input side of the buffer module 200, and the clock pins CLK of multiple slave devices 310 are commonly connected to the clock signal terminal Y2 on the output side of the buffer module 200. Thus, the buffer module 200 sends a clock signal to the clock pins CLK of multiple slave devices 310, which can ensure the temporal consistency of signal transmission and signal writing between the master device 100 and the slave devices 310.

[0053] In some embodiments, as shown in Figure 1 the master device output pin MOSI of the master device 100 is connected to the master device signal terminal A3 on the input side of the buffer module 200 and is connected to the slave device input pin of at least one slave device 310 via the master device signal terminal Y3 on the output side of the buffer module 200. The master device signal terminal A3 on the input side of the buffer module 200 corresponds to the master device signal terminal Y3 on the output side of the buffer module 200.

[0054] In some embodiments, as shown in Figure 1 the slave device input pins MOSI of multiple slave devices 310 are respectively connected to multiple slave device signal terminals on the output side of the buffer module 200; the slave device output pins MISO of multiple slave devices 310 are respectively connected to multiple slave device signal terminals on the input side of the buffer module 200.

[0055] In some embodiments, the slave device output pin MISO of each slave device 310 is connected to the slave device input pin MOSI of the next slave device 310 or to the master device input pin MISO of the master device 100 via the slave device signal terminal on the input side of the buffer module 200 and the slave device signal terminal on the output side of the buffer module 200.

[0056] In this embodiment, the slave device output pin MISO of each slave device 310 is output to the slave device input pin MOSI of the next slave device 310 via the signal terminal on the input side and the corresponding signal terminal on the output side of the buffer module 200. Moreover, the slave device output pin MISO of the last slave device 310 is connected to the master device input pin MISO of the master device 100 via the slave device signal terminal on the input side of the buffer module 200 and the slave device signal terminal on the output side of the buffer module 200. Designed in this way, data signals can be transmitted between adjacent slave devices 310 and isolated by the buffer module 200.

[0057] In some embodiments, the tri-state buffer is an RS244 series 8-bit tri-state buffer.

[0058] The embodiment of the present application also provides a communication system, and the communication system includes the SPI extended communication circuit described in any one of the above embodiments.

[0059] In some embodiments, the communication system in this embodiment can be applied to a display screen, and multiple slave devices can be connected to multiple partition backlight driving modules in the display screen, so as to realize the control of local backlight in multiple partitions of the display screen by the master device.

[0060] The beneficial effects of the embodiment of the present application: The chip select signal output by the chip select pin of the master device is output to the chip select pins of multiple slave devices via the buffer module, and the clock signal output by the clock pin of the master device is output to the clock pins of multiple slave devices via the buffer module. By setting up communication between the master device and multiple slave devices via the buffer module, multiple slave devices can be controlled by one master device at the same time, and there is no need to switch through a signal switch, saving SPI resources and simplifying the circuit.

[0061] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the above-mentioned division of each functional unit and module is used as an example. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be described in detail here.

[0062] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0063] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be an indirect coupling or communication connection through some interfaces, devices or units, and can be in an electrical, mechanical or other form.

[0064] The units described as separation components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0065] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0066] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An SPI extended communication circuit, characterized in that, Including: A master device, a plurality of slave devices, and a buffer module; The chip select signal output by the chip select pin of the master device is output to the chip select pins of the plurality of slave devices via the buffer module; The clock signal output by the clock pin of the master device is output to the clock pins of the plurality of slave devices via the buffer module; Communication is established between the master device and the plurality of slave devices, and between the plurality of slave devices via the buffer module, and the buffer module is used to amplify the signal on the input side and then output it to the output side.

2. The SPI extended communication circuit according to claim 1, wherein The buffer module includes at least one tri-state buffer, and communication is established between the master device and the plurality of slave devices via the tri-state buffer.

3. The SPI extended communication circuit according to claim 2, wherein Communication is established between the plurality of slave devices via the tri-state buffer.

4. The SPI extended communication circuit according to claim 1, wherein The chip select pins of the plurality of slave devices are commonly connected to the chip select signal terminal on the output side of the buffer module.

5. The SPI extended communication circuit according to claim 1, wherein The clock pins of the plurality of slave devices are commonly connected to the clock signal terminal on the output side of the buffer module.

6. The SPI extended communication circuit according to claim 1, wherein The master device output pin of the master device is connected to the master device signal terminal on the input side of the buffer module, and is connected to the slave device input pin of at least one slave device via the master device signal terminal on the output side of the buffer module; The master device signal terminal on the input side of the buffer module corresponds to the master device signal terminal on the output side of the buffer module.

7. The SPI extended communication circuit according to claim 6, wherein The slave device input pins of the plurality of slave devices are respectively connected to the plurality of slave device signal terminals on the output side of the buffer module; The slave device output pins of the plurality of slave devices are respectively connected to the plurality of slave device signal terminals on the input side of the buffer module.

8. The SPI extended communication circuit according to claim 6, wherein The slave device output pin of each slave device is connected to the slave device input pin of the next slave device, or to the master device input pin of the master device, via the slave device signal terminal on the input side of the buffer module and the slave device signal terminal on the output side of the buffer module.

9. The SPI extended communication circuit according to claim 2, wherein The tri-state buffer is an RS244 series 8-bit tri-state buffer.

10. A communication system, characterized in that, The communication system includes the SPI extended communication circuit according to any one of claims 1 to 9.

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