Debugging board and debugging system of controller

Abstract

The utility model discloses a debugging board and a debugging system of a controller, and relates to the field of circuit debugging, and the debugging board is provided with a plurality of communication interface connectors which are in one-to-one correspondence with communication interfaces in the controller. Various communication signals in the controller can be connected with various simulation devices and debugging devices through the corresponding communication interface connectors, so that the debugging process of various functions of the controller is realized, a development and debugging environment is provided for the controller, various tests, verification and troubleshooting of products are realized, and the debugging efficiency is improved. And the maintenance cost and recall risk of the product are effectively reduced. Communication connection between the controller and the debugging board can be realized directly through plugging of the female connector and the male connector, realization is easy, arrangement of a debugging interface on the controller is avoided, and switch personnel can be effectively helped to simplify the development difficulty, improve the development efficiency and shorten the development period.

Description

Technical Field

[0001] The utility model relates to the field of circuit debugging, in particular to a debugging board and a debugging system of a controller. Background Art

[0002] With the continuous development of automobiles, the controllers used in automobiles are gradually required to realize more and more functions. The complexity and integration of controllers are also getting higher and higher, and the development difficulty is becoming more and more difficult. If the debugging interface is directly set on the circuit board where the controller is located to develop and debug the controller, the cost and size of the controller itself will be greatly increased. Therefore, how to provide a more convenient development and debugging environment for the controller has become a technical problem that needs to be solved urgently. Utility Model Content

[0003] The purpose of the utility model is to provide a debugging board and debugging system for a controller, wherein the controller and the debugging board can achieve communication connection directly by plugging in the provided female connector and male connector, thereby providing a development and debugging environment for the controller, which is easy to implement and avoids setting up a debugging interface on the controller, and can effectively help switch personnel simplify development difficulty, improve development efficiency, and shorten development cycle.

[0004] In order to solve the above technical problems, the present invention provides a debugging board for a controller, comprising:

[0005] N communication interface connectors, the N communication interface connectors corresponding one-to-one to the N communication interfaces in the controller; the communication interfaces include a DAP interface, a UART interface, and a JATG interface, and the communication interface connectors include a DAP connector and / or an XCP connector corresponding to the DAP interface, a UART connector corresponding to the UART interface, and a JTAG connector corresponding to the JATG interface;

[0006] a male connector, the male connector including N pins, the N pins corresponding one-to-one to the N communication interfaces in the controller, the male connector being configured to be plugged into the female connector in the controller; N being a positive integer;

[0007] The female connector includes N jacks, the first ends of the N jacks are connected one-to-one with the N communication interfaces in the controller, the second ends are connected one-to-one with the first ends of the N pins, and the second ends of the N pins are connected one-to-one with the N communication interface connectors.

[0008] Optionally, if the controller is a domain controller of a car, the communication interface includes a JTAG interface, and the communication interface connector includes a JTAG connector corresponding to the JTAG interface;

[0009] The JTAG connector includes:

[0010] A JTAG socket, wherein each socket pin of the JTAG socket is connected to a corresponding pin of the JTAG connector, and the socket pins of the JTAG socket are plugged into the emulator via a flat cable; the socket pins of the JTAG socket are used to access the JTAG signal of the controller;

[0011] a voltage stabilizing module, a first end of which is respectively connected to the pins corresponding to the JTAG connector and the socket pins of the JTAG socket, and a second end of which is grounded;

[0012] a first pull-up resistor, a first end of which is connected to a first preset power source, and a second end of which is connected to an emulation control pin of the JTAG socket;

[0013] a first filter capacitor, a first end of which is grounded;

[0014] a second pull-up resistor, a second end of which is connected to the first preset power supply and the second end of the first filter capacitor respectively, and a second end of which is connected to a power pin of the JTAG socket;

[0015] a first matching resistor, a first end of which is connected to a pin corresponding to the JTAG connector, and a second end of which is connected to a mode selection pin of the JTAG socket;

[0016] a second matching resistor, a first end of which is connected to a pin corresponding to the JTAG connector, and a second end of which is connected to a data output pin of the JTAG socket;

[0017] A third matching resistor has a first end connected to the corresponding pins of the JTAG connector and the clock pin of the JTAG socket, and a second end connected to the test clock pin of the JTAG socket.

[0018] Optionally, if the controller is a domain controller of a car, the communication interface includes a UART interface, and the communication interface connector includes a UART connector corresponding to the UART interface;

[0019] The UART connector includes:

[0020] A UART socket, wherein each socket pin of the UART socket is connected to the corresponding pin of the UART connector, and the socket pin of the UART socket is plugged into the serial port adapter board through a flat cable; the socket pin of the UART socket is used to access the UART signal of the controller;

[0021] a voltage stabilizing module, a first end of which is respectively connected to the pins corresponding to the UART connector and the socket pins of the UART socket, and a second end of which is grounded;

[0022] a second filter capacitor, having a first end connected to the second preset power supply and the mode selection pin of the UART socket respectively, and a second end grounded and connected to the data input pin of the UART socket;

[0023] A third filter capacitor has a first end connected to the second preset power supply and the reset pin of the UART socket respectively, and a second end connected to the ground and the target disconnect pin of the UART socket.

[0024] Optionally, the debugging board further includes an SD card slot, a first end of the SD card slot is connected to the SD interface of the domain controller through the male connector and the female connector, and a second end is connected to the SD card;

[0025] The SD card is used to store the software to be burned;

[0026] The domain controller is used to perform software burning based on the control of the host computer connected to the serial port adapter board and the software to be burned stored in the SD card.

[0027] Optionally, the debugging board also includes a linear voltage regulator, the power supply end of the linear voltage regulator is connected to a third preset power supply, the ground end is grounded, the enable end is connected to the preset universal pin of the domain controller through the male connector and the female connector, and the output end is connected to the fuse pin of the domain controller, and is used to output a fuse power supply based on the enable of the domain controller to control the melting of the electronic fuse in the domain controller.

[0028] Optionally, if the controller is a domain controller of an automobile, the female connector further includes a startup configuration jack connected to a startup mode configuration pin in the domain controller, and the male connector further includes a startup configuration pin correspondingly connected to the startup configuration jack; the debug board further includes:

[0029] a dip switch, wherein a first end of a first channel is connected to a first startup configuration sub-pin of the startup configuration pins, a first end of a second channel is connected to a second startup configuration sub-pin of the startup configuration pins, and a first end of a third channel is connected to a third startup configuration sub-pin of the startup configuration pins;

[0030] a first configuration resistor, a first end of which is connected to the second end of the first channel of the dip switch;

[0031] a second configuration resistor, a first end of which is connected to the second end of the second channel of the dip switch;

[0032] a third configuration resistor, a first end of which is connected to the fourth preset power source and to the second end of the second configuration resistor;

[0033] A fourth configuration resistor has a first end connected to the second end of the third configuration resistor and the second end of the third channel of the dip switch respectively, and a second end grounded and connected to the second end of the first configuration resistor.

[0034] Optionally, if the controller is a processor of a front-view integrated device of a car, the communication interface includes a DAP interface, and the communication interface connector includes a DAP connector corresponding to the DAP interface;

[0035] The DAP connector includes:

[0036] A DAP socket, wherein each socket pin of the DAP socket is connected to a corresponding pin of the DAP connector, and the socket pin of the DAP socket is connected to a cable connector of a DAP debugger; the socket pin of the DAP socket is used to access the DAP signal of the processor;

[0037] a voltage stabilizing module, having a first end connected to the corresponding pins of the DAP connector and the socket pins of the DAP socket, and a second end connected to ground;

[0038] a fourth filter capacitor, having a first end connected to the fifth preset power source and the power pin of the DAP socket, respectively, and a second end connected to ground and to the ground pin of the DAP socket;

[0039] A fifth filter capacitor has a first end connected to the reset pin of the DAP socket and a second end connected to the ground.

[0040] Optionally, if the controller is a computing module of a front-view integrated device of a vehicle, the computing module obtains image information captured by the camera module through a first connector provided in the front-view integrated device and a second connector provided in the camera module; the debugging board further includes:

[0041] a third connector, an output end of which is connected to the input end of the first connector via a first flexible circuit board;

[0042] a fourth connector, an input end of which is connected to an output end of the second connector via a second flexible printed circuit board;

[0043] The FPGA has an input end connected to the output end of the fourth connector and an output end connected to the input end of the third connector, and is used to perform clarity processing on the image information collected by the camera module.

[0044] Optionally, also include:

[0045] a serializer, whose input end is connected to the FPGA via a parallel interface, and is used to convert received image information from parallel data to serial data;

[0046] The FAKRA connector has an input end connected to the output end of the serializer, and an output end connected to the on-board computer via a coaxial cable, and is used to output the image information to the on-board computer for display.

[0047] To solve the above technical problems, the present invention also provides a debugging system, including a controller and a debugging board of the controller as described above, wherein the female connector in the controller is plugged into the male connector in the debugging board of the controller.

[0048] The utility model provides a controller debugging board. The debugging board is provided with a plurality of communication interface connectors corresponding to the various communication interfaces in the controller. The various communication signals in the controller can be connected to various simulation devices and debugging devices through the corresponding communication interface connectors, thereby realizing the debugging process of each function of the controller. This provides a development and debugging environment for the controller, realizes various testing, verification and troubleshooting of products, and effectively reduces the maintenance cost and recall risk of products. The communication connection between the controller and the debugging board can be achieved directly by plugging the provided female and male connectors. This is easy to implement and avoids the need to set up a debugging interface on the controller. It can effectively help switch personnel simplify development difficulty, improve development efficiency, and shorten development cycle.

[0049] The utility model also provides a debugging system, which has the same beneficial effects as the debugging board of the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 A schematic diagram of the structure of a debugging board of a controller provided by the utility model;

[0052] Figure 2 A schematic structural diagram of a debugging board for a vehicle-mounted domain controller provided by the present invention;

[0053] Figure 3 A schematic diagram of the power supply architecture of a debugging board of a vehicle-mounted domain controller provided by the present invention;

[0054] Figure 4 A schematic diagram of the structure of a debugging board for a front-view integrated machine provided by the present invention;

[0055] Figure 5A schematic diagram of the power supply architecture of a debugging board of a front-view integrated device provided by the present invention;

[0056] Figure 6 This is a structural diagram of the debugging system of the first vehicle-mounted domain controller provided by the utility model;

[0057] Figure 7 This is a structural diagram of a debugging system for a second vehicle-mounted domain controller provided by the present invention;

[0058] Figure 8 A schematic diagram of the structure of a JTAG connector provided by the present invention;

[0059] Figure 9 This is a schematic structural diagram of a debugging system for a third vehicle-mounted domain controller provided by the present invention;

[0060] Figure 10 A schematic structural diagram of a UART connector provided by the present invention;

[0061] Figure 11 A schematic diagram of the structure of a debugging system for realizing software burning provided by the utility model;

[0062] Figure 12 A schematic diagram of the structure of a debugging system for achieving fuse breaking provided by the utility model;

[0063] Figure 13 A schematic diagram of the structure of a debugging system for realizing startup mode configuration provided by the utility model;

[0064] Figure 14 A structural diagram of a DAP connector provided by the utility model;

[0065] Figure 15 A schematic structural diagram of an SFI connector provided by the present invention;

[0066] Figure 16 A schematic structural diagram of a UART connector provided by the present invention;

[0067] Figure 17 A schematic diagram of the structure of a SOC JTAG connector provided by the utility model;

[0068] Figure 18 This is a structural diagram of an XCP connector provided by the utility model. DETAILED DESCRIPTION

[0069] The core of this utility model is to provide a debugging board and debugging system for a controller. The controller and the debugging board can achieve communication connection directly by plugging in the provided female connector and male connector, thereby providing a development and debugging environment for the controller. It is easy to implement and avoids setting up a debugging interface on the controller. It can effectively help switch personnel simplify development difficulty, improve development efficiency, and shorten development cycle.

[0070] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0071] Please refer to Figure 1 , Figure 1 The present invention provides a schematic diagram of a controller debugging board; in order to solve the above technical problems, the present invention provides a controller debugging board, comprising:

[0072] N communication interface connectors 2, the N communication interface connectors 2 corresponding one-to-one to the N communication interfaces 1 in the controller; the communication interfaces include a DAP interface, a UART interface, and a JATG interface, and the communication interface connectors include a DAP connector and / or an XCP connector corresponding to the DAP interface, a UART connector corresponding to the UART interface, and a JTAG connector corresponding to the JATG interface;

[0073] A male connector, the male connector including N pins, the N pins corresponding one-to-one to the N communication interfaces 1 in the controller, and the male connector being used to be plugged into the female connector in the controller; N is a positive integer;

[0074] The female connector includes N jacks, the first ends of the N jacks are connected one-to-one with the N communication interfaces 1 in the controller, the second ends are connected one-to-one with the first ends of the N pins, and the second ends of the N pins are connected one-to-one with the N communication interface connectors 2.

[0075] It is understandable that, considering the need for debugging the controller during production applications, this application provides a controller debugging board. A male connector is provided on the debugging board, and a female connector that matches the male connector is provided on the controller. When the controller needs to perform functions such as testing, verification, and troubleshooting, the male connector on the debugging board can be directly plugged into the female connector on the controller. At the same time, a communication interface connector 2 required for controller testing and debugging is provided on the debugging board. The communication interface connector 2 serves as a debugging interface. When the debugging board is connected to the controller, the operator can use these communication interface connectors 2 to test and debug the controller, providing a development and debugging environment for the controller after the debugging board is connected to the controller.

[0076] It should be noted that the N communication interfaces 1 of the controller are generally N different types of communication interfaces 1, which can transmit different types of communication signals required during the operation of the controller to a test device or debugging device such as a simulator through the communication interface 1 and the corresponding communication interface connector 2, thereby realizing functions such as testing, debugging and troubleshooting of the controller. The specific type and implementation method of the communication interface 1 and its corresponding communication interface connector 2 are not particularly limited in this application, and can be adjusted and set according to the specific application controller. The specific type and implementation method of the male connector and the female connector are not particularly limited in this application. The specific material and shape of the jack and the pins can be selected and adjusted according to the actual connection requirements. It is only necessary to realize the connection between the controller and the debugging board. The specific type and implementation method of the controller are not particularly limited in this application. When used in the automotive field, the controller can be a vehicle-mounted domain controller, a controller in a vehicle-mounted front-view integrated machine, etc.

[0077] The utility model discloses a debugging board for a controller, which can provide a development and debugging environment for a vehicle-mounted domain controller, a vehicle-mounted front-view integrated machine, etc., so that operators can perform various tests, verifications and troubleshooting on the product, thereby improving development efficiency and shortening the development cycle. The controller can be connected to a test device or debugging device such as an emulator or a host computer through the debugging board, so that the operator can test and debug the controller through this communication connection. By adjusting circuit parameters and other methods, better performance can be achieved, problems can be discovered and repaired in a timely manner, and the maintenance cost and recall risk of the product can be reduced. After debugging, the product can more accurately realize various functions, thereby ensuring product quality. Through debugging, the user's demand for the function and quality of electronic products can be met, and the user experience can be improved.

[0078] As a specific embodiment, please refer to Figure 2 , Figure 2This is a structural diagram of a debugging board for a vehicle-mounted domain controller provided by the utility model; please refer to Figure 3 , Figure 3 This is a schematic diagram of the power supply architecture of a debugging board of a vehicle-mounted domain controller provided by the present invention; taking the controller as a vehicle-mounted domain controller as an example, Figure 2 As shown in the figure, the debug board for the domain controller's System on a Chip (SOC) includes a JTAG (Joint Test Action Group) connector, a UART (Universal Asynchronous Receiver-Transmitter) connector, an SD (Secure Digital) card slot, an RJ45 (Registered Jack 45) connector, a DIP switch, and a male connector. The debug board cannot function independently and must be connected to the controller's mainboard. Through the design of various circuit components, it is an integrated debug board with functions such as software burning, software debugging, boot mode configuration, fault location, and fuse breaking. The debug board is rigidly connected to the female connector on the controller's mainboard via a male connector. The pins connecting the male and female connectors include those corresponding to power (SOC_3V3), JTAG signals, BOOTMODE (Boot mode) signals, UART signals, SD signals, and RGMII (Reduced Gigabit Media Independent Interface) signals. The UART signal received by the male connector is connected to the corresponding UART header connector through a wire, the JTAG signal is connected to the corresponding JTAG header connector, the SD signal is connected to the SD card slot, the RGMII signal is connected to the PHY (Physical) chip of the debug board, and then connected to the RJ45 connector through the PHY chip, and the BOOTMODE signal is connected to the DIP switch. The power tree of the debug board set for the domain controller is as follows: Figure 3As shown, the controller board's SOC_3V3 power supply is supplied to the debug board's buck circuit via a hardwired male connector. The buck circuit steps down the power supply and outputs a 1.2V voltage to power the Ethernet PHY. The SOC_3V3 power supply is also supplied directly to the Ethernet PHY, providing a separate power source. The controller board's SOC_3V3 power supply also supplies power to the UART connector, JTAG connector, and SD card slot via a hardwired male connector. Furthermore, the debug board includes an LDO (low dropout regulator). The controller board's SOC_3V3 power supply is supplied to the LDO via a hardwired male connector. The LDO then outputs the EFUSE_1V8 power supply required by the SOC's electronic fuse module.

[0079] Please refer to Figure 6 , Figure 6 This is a structural diagram of the debugging system of the first vehicle-mounted domain controller provided by the utility model; it can be understood that the RGMII interface signal inside the SOC is connected to the corresponding jack of the female connector set on the domain controller, and then hard-connected to the male connector of the debugging board, and then connected to the Ethernet PHY chip to realize communication between the PHY chip and the SOC chip. The PHY chip is connected to the RJ45 connector through a medium-related interface, and the RJ45 connector is then connected to the host computer through a network cable, so that the SOC can exchange data with the host computer through the debugging board. For example, when the SOC sends data, the PHY chip translates the received data signal into an electrical signal suitable for the transmission line, and the electrical signal is converted through the RJ45 connector to reach the host computer; when the SOC receives data, when the PHY chip receives the converted electrical signal sent by the host computer through the RJ45 connector, it will convert the received electrical signal into a digital signal and send it to the SOC. This realizes the Ethernet function of the SOC in the domain controller. The Ethernet function can be used to copy software code or data from a local PC (Personal Computer) to the storage chip on the domain controller motherboard using host computer instructions, simplifying the development process and shortening the development cycle. Ethernet serves as a communication bridge between the domain controller and the host computer. When the host computer uses the monitoring tools provided by the operating system, it can use this communication connection to view parameters such as the load rate of each SOC module.

[0080] As a specific embodiment, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the debugging board of the front-view integrated machine provided by the utility model; please refer to Figure 5 , Figure 5This is a schematic diagram of the power supply architecture of a debugging board of a front-view integrated device provided by the present invention; taking the controller of a vehicle-mounted front-view integrated device as an example, Figure 4 As shown, the controller for the in-vehicle front-view camera consists of a system-on-chip (SoC) and a microcontroller unit (MCU). The debug board for the FOV camera includes a male connector, SoC JTAG connector, UART connector, DAP (Debug Access Port) connector, XCP (Universal Calibration Protocol) connector, RJ45 connector, Ethernet PHY, SFI (Scalable SERDES framer interface) connector, FPGA (Field Programmable Gate Array), SERializer, FAKRA (Fachkreis Automobil) connector, and piano-top connector. The debug board cannot function independently and must be connected to the mainboard. Through the design of various circuit components, the debug board integrates functions such as software burning, software debugging, fault location, and image display. The debug board is hard-wired to the female connector on the FOV camera's control mainboard via a male connector. The pins connecting the male and female connectors include power, SoC JTAG signals, DAP signals, UART signals, RGMII signals, and SFI signals. The RGMII signal is connected to the Ethernet PHY, which then outputs to the corresponding connection pins such as the RJ45 connector. Each signal is connected to the corresponding connector through the corresponding pins and jacks. The power tree of the debugging board set for the front-view integrated device is as follows: Figure 5As shown, the debug board requires no external power supply. Power is provided by the motherboard's KL30 (battery power), 3V3_MCU, and 1V8_SOC power supplies via hard-wired male connectors. For the primary buck circuit, the KL30 serves as the power source, and the 3V3_MCU serves as the enable. The primary buck circuit steps down the KL30 voltage and outputs a 3.3V voltage that is supplied to the secondary LDO circuit, secondary buck circuit, FPGA, and Ethernet PHY. The secondary LDO circuit outputs a 1.8V voltage that powers the SERializer load chip, one FPGA power supply, and one Ethernet PHY power supply. The secondary buck circuit outputs a 1.2V voltage that provides a third FPGA power supply and a third Ethernet PHY power supply. The 3V3_MCU power supply is routed to the DAP connector and XCP connector, while the 1V8_SOC power supply is routed to the SFI connector and the SoC JTAG connector, each powering its connected devices. By using the various communication interface connectors 2 and other devices set on the debugging board, the front-view integrated machine can be debugged, fault analyzed, bench tested, and actually tested on a vehicle. The entire debugging board integrates multiple functions and can play a big role in the entire project development process, greatly improving product development efficiency and shortening the development cycle.

[0081] The utility model provides a debugging board for a controller. The debugging board is provided with a plurality of communication interface connectors 2 corresponding one-to-one to each communication interface 1 in the controller. The various communication signals in the controller can be connected to various simulation devices and debugging devices through the corresponding communication interface connectors 2, thereby realizing the debugging process of each function of the controller. This provides a development and debugging environment for the controller, realizes various testing, verification and troubleshooting of products, and effectively reduces the maintenance cost and recall risk of products. The communication connection between the controller and the debugging board can be achieved directly by plugging the provided female and male connectors. This is easy to implement and avoids the need to set up a debugging interface on the controller. It can effectively help switch personnel simplify development difficulty, improve development efficiency, and shorten development cycle.

[0082] Based on the above embodiment:

[0083] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of the debugging system of the second vehicle-mounted domain controller provided by the present invention; please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a JTAG connector provided by the present invention; as an optional embodiment, if the controller is a domain controller of an automobile, the communication interface 1 includes a JTAG interface, and the communication interface connector 2 includes a JTAG connector corresponding to the JTAG interface;

[0084] The JTAG connector includes:

[0085] JTAG socket, each socket pin of the JTAG socket is connected to the corresponding pin of the JTAG connector, and the socket pins of the JTAG socket are plugged into the emulator through a cable; the socket pins of the JTAG socket are used to access the JTAG signal of the controller;

[0086] a voltage regulator module, a first end of which is connected to corresponding pins of the JTAG connector and a socket pin of the JTAG socket, respectively, and a second end of which is grounded;

[0087] A first pull-up resistor R9, having a first end connected to the first preset power supply and a second end connected to the simulation control pin of the JTAG socket;

[0088] A first filter capacitor C1, a first end of which is grounded;

[0089] A second pull-up resistor R5, a second end of which is connected to the first preset power supply and the second end of the first filter capacitor C1 respectively, and a second end of which is connected to the power pin of the JTAG socket;

[0090] a first matching resistor R6, a first end of which is connected to a corresponding pin of the JTAG connector, and a second end of which is connected to a mode selection pin of the JTAG socket;

[0091] A second matching resistor R7, a first end of which is connected to the corresponding pin of the JTAG connector, and a second end of which is connected to the data output pin of the JTAG socket;

[0092] The third matching resistor R8 has a first end connected to the corresponding pins of the JTAG connector and the clock pin of the JTAG socket, and a second end connected to the test clock pin of the JTAG socket.

[0093] It's understood that when the controller is an in-vehicle domain controller, the domain controller's SoC uses JTAG signals to implement some functions during operation. Therefore, a JTAG connector corresponding to JTAG signals can be provided on the debug board. The JTAG connector connects to the JTAG interface on the domain controller via male and female connectors. This JTAG connector allows for software debugging of the domain controller's SoC. The voltage stabilizing module plays the role of signal voltage stabilization, so that the JTAG socket can receive a stable JTAG signal. The first pull-up resistor R9 and the second pull-up resistor R5 are used to maintain the pull-up state of the corresponding pin. The first matching resistor R6, the second matching resistor R7 and the third matching resistor R8 play the role of impedance matching. The first filter capacitor C1 plays the role of filtering. The specific types and implementation methods of the JTAG socket, the voltage stabilizing module, the first pull-up resistor R9, the first filter capacitor C1, the second pull-up resistor R5, the first matching resistor R6, the second matching resistor R7 and the third matching resistor R8 are not specifically limited in this application. The specific number of pins of the JTAG socket used needs to be set according to the type of JTAG signal existing in the controller and the connection requirements of the debugging device required. For example, when it is necessary to connect an emulator through a JTAG connector to debug the controller, considering that the emulator itself has 20 pins, a JTAG socket with 20 pins is also used when setting the JTAG connector. The specific structure of the JTAG connector is not specifically limited in this application and is not limited to the implementation method provided in this embodiment. The present application does not impose any particular limitation on the specific type and implementation of the first preset power supply, and the first preset power supply can be directly implemented using the internal power supply of the SOC.

[0094] As a specific embodiment, Figure 7 As shown in the figure, the JTAG interface signal of the motherboard SOC is connected to the female connector, which is hard-wired to the male connector of the debug board, and then transferred to the JTAG connector. The debug board then connects the JTAG connector to the emulator through a dedicated cable, and finally the emulator is connected to the host computer. The host computer monitors and controls the domain controller by sending and / or receiving JTAG signals. Figure 8As shown in the figure, for the SOC in the domain controller, the JTAG socket in the JTAG connector uses a 20-pin header. The power supply of the JTAG socket is directly connected to the SOC's SOC_3V3 power supply from the male connector. The JTAG communication signals involved in the SOC operation include SOC_TMS (mode select), SOC_TCK (clock), SOC_TDI (data input), SOC_TDO (data output), SOC_TRST (JTAG reset), SOC_EMU0 (emulation control 0), SOC_EMU1 (emulation control 1), and RESET_REQz (warm reset). These JTAG signals are connected from the SOC to the JTAG socket in the JTAG connector through the female and male connectors. At the same time, the emulator is directly plugged into the JTAG socket, thus establishing a communication connection between the emulator and the SOC. At the same time, the peripheral circuit of the JTAG socket is further configured. The voltage stabilization module is specifically implemented using TVS diodes (Transient Voltage Suppressor, transient voltage suppression diodes), including TVS diodes D7, TVS diodes D8, TVS diodes D9, TVS diodes D10, TVS diodes D11, TVS diodes D12, TVS diodes D13, and TVS diodes D14. The voltage stabilization module can effectively suppress surge voltages, allowing the JTAG socket to safely and reliably obtain JTAG signals. This application does not specifically limit the specific type and implementation of the debugging device. Devices such as emulators can be used. Emulators can be used to participate in the entire life cycle of embedded development, performing operations such as chip bringup (power-on startup), software burning, app simulation, testing, failure debugging, and tracing. The emulator supports functions such as single-step debugging, breakpoints, OS debugging, variable / memory / peripheral viewing, code coverage statistics, CPU load analysis, historical code backtracing, and OS scheduling analysis.

[0095] Specifically, by setting up a JTAG connector on the debug board corresponding to the domain controller, the communication connection between the emulator and the domain controller can be established by plugging the JTAG connector and the emulator, and then the emulator can be used to debug the software of the domain controller, helping switch personnel to simplify development difficulty, improve development efficiency, and shorten the development cycle.

[0096] Please refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of the debugging system of the third vehicle-mounted domain controller provided by the present invention; please refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of a UART connector provided by the present invention; as an optional embodiment, if the controller is a domain controller of a car, the communication interface 1 includes a UART interface, and the communication interface connector 2 includes a UART connector corresponding to the UART interface;

[0097] The UART connector includes:

[0098] UART socket, each socket pin of the UART socket is connected to the corresponding pin of the UART connector, and the socket pin of the UART socket is plugged into the serial port adapter board through a flat cable; the socket pin of the UART socket is used to access the UART signal of the controller;

[0099] a voltage stabilizing module, a first end of which is connected to the corresponding pins of the UART connector and the socket pins of the UART socket, respectively, and a second end of which is grounded;

[0100] A second filter capacitor C2, having a first end connected to the second preset power supply and a mode selection pin of the UART socket, respectively, and a second end connected to ground and to a data input pin of the UART socket;

[0101] The third filter capacitor C3 has a first end connected to the second preset power supply and the reset pin of the UART socket respectively, and a second end connected to the ground and the target disconnect pin of the UART socket.

[0102] It is not difficult to understand that when the controller is an on-board domain controller, the SOC of the domain controller will use UART signals to implement some functions during operation. Therefore, a UART connector corresponding to the UART signal can be set on the debugging board, and the UART connector is connected to the UART interface in the domain controller via a male connector and a female connector. Using the UART connector, fault location and troubleshooting of the SOC of the domain controller can be achieved. The voltage regulator module plays the role of signal voltage stabilization, so that the UART socket can receive a stable UART signal, and the second filter capacitor C2 and the third filter capacitor C3 play a filtering role. The specific type and implementation method of the UART socket, the second filter capacitor C2 and the third filter capacitor C3 are not specifically limited in this application. The specific number of pins of the UART socket used needs to be set according to the type of UART signal present in the controller and the connection requirements of the test device required. The specific structure of the UART connector is not specifically limited in this application and is not limited to the implementation method provided in this embodiment. The specific type and implementation method of the second preset power supply are not specifically limited in this application, and can be directly implemented using the internal power supply of the SOC.

[0103] As a specific embodiment, Figure 9As shown in the figure, the UART interface signal of the motherboard SOC is connected to the female connector, which is hard-wired to the male connector of the debug board, and then transferred to the UART connector. The debug board then connects the UART connector to the serial port adapter board via a dedicated cable, and finally the serial port adapter board is connected to the host computer. The host computer is a serial port debugging tool that can help capture, analyze, and debug the serial port transmission data received through the serial port adapter board. Figure 10 As shown, for the SOC in the domain controller, the UART socket in the UART connector uses a 20-pin header. The UART socket is powered directly from the SOC's SOC_3V3 power supply, which is connected to the male connector. The UART communication signals involved in the SOC's operation consist of two parts, corresponding to the SOC's two different domains: the MCU domain and the MAIN domain. The MCU domain's UART signals include MCU_UART0_RXD and MCU_UART0_TXD, while the MAIN domain's UART signals include UART5_RXD and UART5_TXD. MCU_RESETSTATz and RESETSTATz are the reset signals for the MCU and MAIN domains, respectively. These UART signals are connected from the SOC to the UART socket in the UART connector via the female and male connectors. A serial port adapter board is plugged directly into the UART socket. The serial port adapter board transmits serial data received from the SOC to a host computer, which then uses the host computer to analyze the domain controller's data. The voltage stabilization module uses TVS diodes (D1, D2, D3, D4, and D5) to effectively absorb surge voltages and provide protection. By configuring the USB COM ports and baud rates for the two domains, the host computer can capture serial port data from the corresponding domains, helping to locate and analyze faults in the domain controller.

[0104] Specifically, by setting a UART connector on the debugging board corresponding to the domain controller, the communication connection between the serial port adapter board and the domain controller can be established by plugging the UART connector and the serial port adapter board, and then the serial port adapter board and the host computer connected to it can be used to perform data analysis on the domain controller, helping switch personnel to simplify development difficulty, improve development efficiency, and shorten the development cycle.

[0105] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a debugging system for implementing software burning provided by the present invention; as an optional embodiment, the debugging board also includes an SD card slot, a first end of the SD card slot is connected to the SD interface of the domain controller via a male connector and a female connector, and a second end is connected to the SD card;

[0106] SD card is used to store the software to be burned;

[0107] The domain controller is used to control the host computer connected to the serial port adapter board and burn the software to be burned stored in the SD card.

[0108] It is understandable that, considering that SD interface is generally also set in the SOC of domain controller, it is also possible to realize the software burning in the SOC in domain controller by arranging SD card slot on debug board.Simultaneously, because the process of software burning needs to be realized by sending burning instruction, therefore this software burning process is preferably realized on the basis of establishing communication connection between domain controller and host computer, therefore can be realized on the basis of arranging SD card, utilize UART connector to realize whole software burning process by the communication connection established between serial port adapter board and host computer, when the operating personnel sends burning instruction by host computer, controller can receive this burning instruction by serial port adapter board, UART connector, male connector, female connector, UART interface, then carry out software burning by the software to be burned stored in SD interface and SD card.For the specific type of SD card and implementation etc., this application is not particularly limited at this.

[0109] As a specific embodiment, Figure 11 As shown, the motherboard SOC is connected to the debug board's UART connector via a UART interface, and then communicates with the host computer via a serial port adapter board. Simultaneously, the motherboard SOC's SD interface is connected to the debug board's SD card slot, which in turn communicates with the SD card. The SOC communicates with the motherboard's flash and eMMC storage chips via the SPI (Serial Peripheral Interface) bus. This application uses an SD card to store software packages. This storage method allows the software to be compiled directly under the Linux system and then downloaded to the SD card. Operation is simple and fast, and no additional configuration files are required. After connecting the motherboard and debug board, the SOC must first be configured to SD card boot mode and powered on. The operator then enters a programming command on the host computer. The programming command is transmitted to the SOC via the serial port adapter board. The SOC receives and executes the command, mirroring the software on the SD card and sending the mirrored software program to the corresponding flash and eMMC storage chips via the SPI bus, completing the software programming.

[0110] Specifically, by setting an SD card on the debugging board corresponding to the domain controller, and using the connection between the UART connector and the serial port adapter board to establish a communication connection between the host computer and the domain controller, and then using the host computer and the SD card to realize the software burning process of the domain controller, it is simple, effective and easy to implement.

[0111] Please refer to Figure 12 , Figure 12This is a schematic structural diagram of a debugging system for implementing fuse blowing provided by the present invention; as an optional embodiment, the debugging board also includes a linear voltage regulator LDO (LDO circuit), the power supply end of the linear voltage regulator LDO is connected to a third preset power supply, the ground end is grounded, the enable end is connected to a preset universal pin of a domain controller via a male connector and a female connector, and the output end is connected to a fuse pin of the domain controller, and is used to output a fuse power supply based on the enable of the domain controller to control the blowing of an electronic fuse in the domain controller.

[0112] It is not difficult to understand that, considering that the SOC will be designed to achieve anti-piracy protection for the SOC by whether the chip is blown or not, the SOC has a specific fuse pin. When a high level is applied, the current generated can burn the fuse inside, thereby making the program in the chip unreadable and writable and only runnable. Therefore, the fuse will be blown after the product is mass-produced. In response to this situation, the present application further sets a linear voltage regulator source LDO circuit in the debugging board to realize the SOC fuse function. When the SOC needs to be blown, the linear voltage regulator source LDO can output a specific fuse power supply under the control of the domain controller to blow the electronic fuse inside the SOC. The present application does not make any special restrictions on the specific type and implementation method of the third preset power supply, and it can be directly implemented using the internal power supply of the SOC. The present application does not make any special restrictions on the specific type and implementation method of the linear voltage regulator source LDO.

[0113] As a specific embodiment, Figure 12 As shown in the figure, based on the design of the SD card, the SD card can be used to control the SOC fuse. The SD card has built-in fuse software. After connecting the SOC mainboard and the debug board, the SOC is configured to SD card boot mode and the SOC mainboard is powered on. When the SOC fuse needs to be blown, the operator triggers the fuse software in the SD card through a host computer or other means. The SD card outputs the fuse instruction to the SOC. After receiving the fuse instruction, the SOC configures one of its own GPIO pins to a high level. This GPIO pin is sent to the enable terminal of the LDO circuit through a female connector and a male connector. That is, the EFUSE_EN signal is now high, thereby enabling the LDO circuit and controlling the LDO output EFUSE_1V8 power supply to the SOC fuse pin to achieve the blow. The peripheral circuit of the LDO circuit can also be further configured, setting capacitor PC1 for filtering, resistor PR4 as a pull-down resistor, and TVS diode PD1 to suppress surge voltage.

[0114] Specifically, an LDO circuit is set on the debug board corresponding to the domain controller to provide the power supply voltage required for the fuse pin of the SOC to cause the fuse. At the same time, the fuse software in the SD card is used to control the enablement of the LDO circuit, thereby achieving the fuse of the SOC and protecting the internal software program of the SOC.

[0115] Please refer to Figure 13 , Figure 13 This is a schematic diagram of the structure of a debugging system for implementing startup mode configuration provided by the present invention; as an optional embodiment, if the controller is a domain controller of an automobile, the female connector further includes a startup configuration jack connected to the startup mode configuration pin in the domain controller, and the male connector further includes a startup configuration pin correspondingly connected to the startup configuration jack; the debugging board further includes:

[0116] DIP switch SW0, a first end of the first channel is connected to the first startup configuration sub-pin of the startup configuration pins, a first end of the second channel is connected to the second startup configuration sub-pin of the startup configuration pins, and a first end of the third channel is connected to the third startup configuration sub-pin of the startup configuration pins;

[0117] A first configuration resistor R1, a first end of which is connected to the second end of the first channel of the DIP switch SW0;

[0118] A second configuration resistor R2, a first end of which is connected to the second end of the second channel of the DIP switch SW0;

[0119] a third configuration resistor R3, a first end of which is connected to the fourth preset power source and to the second end of the second configuration resistor R2;

[0120] The fourth configuration resistor R4 has a first end connected to the second end of the third configuration resistor R3 and the second end of the third channel of the DIP switch SW0 respectively, and a second end grounded and connected to the second end of the first configuration resistor R1.

[0121] Understandably, given that both the software flashing and SoC fuse-breaking processes require the SoC to be in SD card boot mode, the SoC's boot mode must be configured. Therefore, a boot mode configuration circuit can be added to the debug board, connected to the domain controller's boot configuration pins. The SoC's BOOTMODE interface connects to the test board's boot mode configuration pins: MCU_BOOTMODE[09:00] and BOOTMODE[09:00], for a total of 18 pins. These pins are externally pulled up to power or down to ground. After the motherboard is powered on, the SoC determines the boot mode based on the high and low levels of these 18 pins. During the development phase, two main boot modes are used: OSPI boot mode and SD card boot mode. According to current domain controller product designs, the levels of these 15 pins remain fixed during development, so the boot mode configuration circuit only needs to set the levels of three pins. The boot mode configuration circuit specifically includes a four-channel DIP switch SW0, a first configuration resistor R1, a second configuration resistor R2, a third configuration resistor R3, and a fourth configuration resistor R4. MCU_BOOTMODE_03, BOOTMODE_06, and BOOTMODE_00 are initially configured as high, low, and low on the SoC motherboard. According to the SoC specification, in OSPI boot mode, set Channels 1, 2, and 4 of the 4-channel DIP switch SW0 to off, maintaining the signals in their initial states on the motherboard (MCU_BOOTMODE_03 = 1, BOOTMODE_06 = 0, and BOOTMODE_00 = 0). In SD card boot mode, set Channels 1, 2, and 4 to on, and the signals undergo level conversion under the influence of the first, second, third, and fourth configuration resistors R1, R2, R3, and R4, and their connected fourth preset power supply. MCU_BOOTMODE_03 = 0, BOOTMODE_06 = 1, and BOOTMODE_00 = 1. Since the high voltage level of BOOTMODE_06 is 3.3V, when it needs to be high, it can be directly pulled up to 3.3V through the second configuration resistor R2. The voltage level of BOOTMODE_00 is 1.8V, which requires the third configuration resistor R3 and the fourth configuration circuit to divide the voltage before configuration. The fourth preset power supply can be directly implemented by the internal power supply of the SOC, and this application does not make any special restrictions here.

[0122] Specifically, by setting the dip switch SW0 and the corresponding peripheral circuit, the operator can directly switch the level state of some startup configuration pins of the SOC by adjusting the conduction state of the dip switch SW0, thereby realizing different startup mode configurations, so as to realize software burning and fuse blowing of the SOC.

[0123] Please refer to Figure 14 , Figure 14 This is a schematic diagram of the structure of a DAP connector provided by the present invention; as an optional embodiment, if the controller is a processor of a front-view camera of a car, the communication interface 1 includes a DAP interface, and the communication interface connector 2 includes a DAP connector corresponding to the DAP interface;

[0124] DAP connectors include:

[0125] DAP socket, each socket pin of the DAP socket is connected to the corresponding pin of the DAP connector, and the socket pin of the DAP socket is connected to the cable connector of the DAP debugger; the socket pin of the DAP socket is used to access the DAP signal of the processor;

[0126] a voltage stabilizing module having a first end connected to corresponding pins of the DAP connector and a socket pin of the DAP socket, and a second end connected to ground;

[0127] a fourth filter capacitor JC1 having a first end connected to the fifth preset power source and a power pin of the DAP socket, respectively, and a second end connected to ground and to a ground pin of the DAP socket;

[0128] The fifth filter capacitor JC7 has a first end connected to the reset pin of the DAP socket and a second end connected to the ground.

[0129] It is easy to understand that if you need to set up a debugging board for a front-view camera, you need to set it up according to the specific communication signals and functional requirements of the controller in the front-view camera. The controller in the front-view camera includes SOC and MCU. The MCU of the front-view camera also needs software burning, so you can set up a DAP connector on the debugging board to realize the burning function of the MCU. Figure 14 As shown, the DAP connector's pin signals are connected to the motherboard's MCU via male and female connectors on the debug board. The DAP connector is also connected to the DAP debugger's cable connector, and the DAP debugger's USB port is connected to the host computer. After the debug board and motherboard are connected via the male and female connectors, the motherboard is powered on. The host computer software is then opened and the HEX file is loaded to program the MCU. For the processor, the debug board features a 10-pin CJ20 connector as a DAP connector. Pin 1 connects to the 3V3_MCU power supply, serving as the fifth preset power source. Pins 2, 4, 6, 8, and 10 connect to the MCU_TMS (mode select), MCU_TCK (clock), MCU_TDO (output), MCU_TDI (input), and 3V3_RST_MCU (reset), respectively. Fourth and fifth filter capacitors JC1 and JC7 are provided for filtering, and TVS diodes JD5 and JD6 serve as voltage regulators to effectively absorb surge voltages.

[0130] Please refer to Figure 15 , Figure 15 This is a schematic diagram of the structure of an SFI connector provided by the present invention; considering that the front-view integrated machine also includes SOC, SOC also has the need for software burning, so an SFI connector can be further set on the debugging board to realize the burning function of SOC. Figure 15 As shown, the SFI connector pin signals on the debug board are connected to the motherboard's SoC via a male connector. The SFI connector is also connected to the cable connector of the programmer, and the programmer's USB port is connected to the host computer. After the debug board and motherboard are connected via the male and female connectors, the host computer software loads the BIN file to program the SoC. For the SoC, the debug board features a 12-pin CJ9 header connector as the SFI connector. Pins 1 and 4 connect to the 1V8_SOC power supply, while pins 3, 5, 6, 7, 8, 10, and 12 connect to SFI_CS0 (chip select), SFI_D1 (data 1), SFI_D3 (data 3), SFI_D2 (data 2), SFI_CLK (clock), SFI_D0 (data 0), and SOC_POR_N (SOC reset), respectively.

[0131] Please refer to Figure 16 , Figure 16 This is a schematic diagram of the structure of a UART connector provided by the utility model; please refer to Figure 17 , Figure 17 This is a schematic diagram of the structure of a SOC JTAG connector provided by the utility model; please refer to Figure 18 , Figure 18 This is a structural diagram of an XCP connector provided by the utility model. Furthermore, the SOC and MCU of the front-view all-in-one machine also have the need for software debugging, fault location and troubleshooting, so the debugging board can further be provided with a UART connector, a SOC JTAG connector, an XCP connector and the like to connect to an external communication interface connector 2 to connect external devices, so as to debug, fault locate and analyze the SOC and / or MCU of the front-view all-in-one machine. In addition to the burning function, the DAP connector can also be connected to the Lauterbach simulator and the TRACE host computer in turn to debug the MCU. Based on the data in the MCU collected by the DAP connector, the key points can be located in the list source code window, and the program control button adds a reverse step function to facilitate repeated analysis at the key points of the program and observe the context and register status. The UART connector can be connected to a serial port adapter board, and then the serial port adapter board is connected to the USB port of the host computer, and the MCU and / or SOC can be debugged through the serial port tool. By setting the correct baud rate by the host computer, you can start sending and receiving data from the MCU and / or SOC, and perform basic serial communication tests with the MCU or SOC, such as Figure 16 As shown in the figure, the UART connector uses a 6-pin CJ16 pin header, which can be connected to CR181, CR191 or CR201, CR211 for serial debugging of SOC or MCU. The way the SOC JTAG connector implements the debugging function is similar to the debugging function of the MCU's DAP connector, with only the interface signals being different. Figure 17 As shown, a 10-pin CJ7 is used as the SOC JTAG connector, pin 2 is connected to the 1V8_SOC power supply inside the SOC, and pins 3, 4, 5, 6, 7, 8, and 9 are connected to the SOC_TDI (input), SOC_PRSTN (SOC reset), SOC_TESTEN (test enable), SOC_TDO (output), SOC_TMS (mode selection), SOC_NTRSTN (JTAG reset), and SOC_TDI (input) signals respectively. Since the MCU has no Ethernet interface, the DAP debugging protocol needs to be used to achieve high-speed data transmission during the development phase. At this time, it is also necessary to set up an XCP connector on the debug board as an adapter board to connect to the integrated DAP debugging, and then connect to the measurement and calibration tool (such as CANape) for parameter optimization of the automotive electronic control unit. As shown Figure 18 As shown in the figure, the XCP connector is implemented using the 10-pin CJ22. The signal connection method of CJ22 is the same as that of the DAP connector, and the TVS diode JD5 and TVS diode JD6 can be shared with the DAP connector.

[0132] Specifically, the specific type and quantity of the communication interface connector 2 on the debugging board can be adjusted according to the requirements of software burning, software debugging, fault location and troubleshooting of the SOC and MCU in the front-view all-in-one machine, so as to meet various debugging or testing requirements of the front-view all-in-one machine, help switch personnel simplify development difficulty, improve development efficiency and shorten development cycle.

[0133] As an optional embodiment, if the controller is a computing module of a front-view integrated device of a vehicle, the computing module obtains image information captured by the camera module through a first connector provided in the front-view integrated device and a second connector provided in the camera module; the debugging board further includes:

[0134] a third connector, an output end of which is connected to the input end of the first connector via the first flexible printed circuit board;

[0135] a fourth connector, an input end of which is connected to an output end of the second connector via a second flexible printed circuit board;

[0136] The FPGA has an input end connected to the output end of the fourth connector and an output end connected to the input end of the third connector, and is used to perform clarity processing on image information collected by the camera module.

[0137] It is understandable that the core function of the front-view integrated machine is to be able to display images through the camera. The front-view integrated machine is connected to the camera module arranged in front of the car. It can perceive the road information in front of the car, perceive the relative distance and speed information of the target in front of the car, and output relevant information according to the surrounding environment and the target through the image information detected by the camera, so as to realize ACC (adaptive cruise control), LDW (lane departure warning), AEB (automatic emergency braking) and other functions. During the development stage, the corresponding modules of the debugging board and the host computer can be used to display the corresponding images. The specific types and implementation methods of the first connector, the second connector, the third connector, the fourth connector and the FPGA are not particularly limited in this application. The first connector, the second connector, the third connector and the fourth connector can be implemented by piano cover connectors, and the FPGA can be implemented by FPGA and other methods.

[0138] It should be noted that if Figure 4 As shown, piano cover connectors 1, 2, 3, and 4 are used to implement the first, second, third, and fourth connectors, respectively. The front-view camera's control board and debug board are connected via male and female connectors. Piano cover connector 2 on the camera module is connected to piano cover connector 1 on the mainboard via an FPC (Flexible Printed Circuit). The camera module is responsible for capturing image information and transmitting it to the SOC via the MIPI interface. The SOC then processes the image and communicates the calculated road information to the MCU. Simultaneously, the MCU exchanges information with the vehicle body, which then performs corresponding actions based on the information from the MCU.

[0139] When the debug board's Ethernet PHY is connected to the SOC via the RGMII interface, image information can reach the PHY chip via RGMII communication. After being converted into electrical signals by the PHY chip, it is connected to the RJ45 connector via the media-related interface and then transmitted to the host computer via a network cable. The host computer processes and presents the image. Due to Ethernet transmission, the image is cropped and compressed, reaching only 1M pixels, which means that a low-definition image display is achieved. For example, functions such as ACC, LDW, and AEB can be simulated and stress-tested using this low-definition image display after setting up a test bench. That is, after installing the mainboard, debug board, and corresponding host computer and other auxiliary equipment, this low-definition image display can be used to improve development efficiency, shorten development cycles, and reduce costs.

[0140] Furthermore, considering that the data required for assisted driving ideally requires a certain level of clarity, an FPGA can be incorporated into the debug board, in addition to low-definition image display, to further process the image information received by the camera, enhancing image clarity. This differs from low-definition image display in that the image transmission link is different. The mainboard and debug board are connected via male and female connectors. The camera module's piano cover connector 2 connects to the debug board's piano cover connector 4 via FPC0, and the debug board's piano cover connector 3 connects to the mainboard's piano cover connector 1 via FPC1. Images captured by the camera module are transmitted to the FPGA via the MIPI0 interface, where the FPGA converts the image to produce higher-definition image information. The converted image can be output to the SOC via the MIPI1 interface to facilitate functionality such as assisted driving. Alternatively, it can be processed by subsequent devices and connected to a host computer for direct high-definition display.

[0141] Specifically, after setting up the Ethernet PHY and RJ45 connector on the debug board, the debug board can cooperate with the forward-looking integrated machine to realize low-definition image display of image information detected by the camera module. However, in order to provide clearer images, the FPGA can be further set on the debug board to realize higher-definition image display, thereby helping the forward-looking integrated machine to achieve more accurate vehicle assisted driving.

[0142] As an optional embodiment, the method further includes:

[0143] A serializer, whose input end is connected to the FPGA through a parallel interface, is used to convert the received image information from parallel data to serial data;

[0144] The FAKRA connector has an input end connected to the output end of the serializer, and an output end connected to the on-board computer via a coaxial cable, and is used to output image information to the on-board computer for display.

[0145] It's easy to understand that after the FPGA converts the image, a serializer and FAKRA connector can be further configured. The converted image data from the FPGA is fed to the SERralizer via a parallel interface. The SERralizer converts the parallel image data into serial data and feeds it to the FAKRA connector. This data is then transmitted via a coaxial cable to the CARPC (car-mounted computer). The CARPC processes the image and displays it in the host computer's software. Because the image is fully transmitted in the FPGA-CARPC link, it can reach 2M pixels, enabling high-definition display.

[0146] Specifically, further data processing via the serializer and FAKRA connector enables high-definition image display on the host computer. This high-definition image display can be used for real-world vehicle data collection. For example, when assisted driving requires data collection on various roads, this high-definition image can accurately and real-timely capture information such as road conditions and vehicle driving status, providing valuable data support. Furthermore, the collected high-definition data is more helpful for fault analysis.

[0147] To solve the above technical problems, the present invention also provides a debugging system, including a controller and a debugging board of the controller as described above, wherein the female connector in the controller is plugged into the male connector in the debugging board of the controller.

[0148] For an introduction to a debugging system provided by the present invention, please refer to the embodiment of the debugging board of the controller described above, and the present invention will not be described in detail here.

[0149] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0150] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A debugging board for a controller, characterized in that: include: N communication interface connectors, the N communication interface connectors corresponding one-to-one to the N communication interfaces in the controller; the communication interfaces include a DAP interface, a UART interface, and a JATG interface, and the communication interface connectors include a DAP connector and / or an XCP connector corresponding to the DAP interface, a UART connector corresponding to the UART interface, and a JTAG connector corresponding to the JATG interface; a male connector, the male connector including N pins, the N pins corresponding one-to-one to the N communication interfaces in the controller, the male connector being configured to be plugged into the female connector in the controller; N being a positive integer; The female connector includes N jacks, the first ends of the N jacks are connected one-to-one with the N communication interfaces in the controller, the second ends are connected one-to-one with the first ends of the N pins, and the second ends of the N pins are connected one-to-one with the N communication interface connectors.

2. The debugging board of the controller according to claim 1, characterized in that: If the controller is a domain controller of an automobile, the communication interface includes a JTAG interface, and the communication interface connector includes a JTAG connector corresponding to the JTAG interface; The JTAG connector includes: A JTAG socket, wherein each socket pin of the JTAG socket is connected to a corresponding pin of the JTAG connector, and the socket pins of the JTAG socket are plugged into the emulator via a flat cable; the socket pins of the JTAG socket are used to access the JTAG signal of the controller; a voltage stabilizing module, a first end of which is respectively connected to the pins corresponding to the JTAG connector and the socket pins of the JTAG socket, and a second end of which is grounded; a first pull-up resistor, a first end of which is connected to a first preset power source, and a second end of which is connected to an emulation control pin of the JTAG socket; a first filter capacitor, a first end of which is grounded; a second pull-up resistor, a second end of which is connected to the first preset power supply and the second end of the first filter capacitor respectively, and a second end of which is connected to a power pin of the JTAG socket; a first matching resistor, a first end of which is connected to a pin corresponding to the JTAG connector, and a second end of which is connected to a mode selection pin of the JTAG socket; a second matching resistor, a first end of which is connected to a pin corresponding to the JTAG connector, and a second end of which is connected to a data output pin of the JTAG socket; A third matching resistor has a first end connected to the corresponding pins of the JTAG connector and the clock pin of the JTAG socket, and a second end connected to the test clock pin of the JTAG socket.

3. The debugging board of the controller according to claim 1, characterized in that: If the controller is a domain controller of an automobile, the communication interface includes a UART interface, and the communication interface connector includes a UART connector corresponding to the UART interface; The UART connector includes: A UART socket, wherein each socket pin of the UART socket is connected to the corresponding pin of the UART connector, and the socket pin of the UART socket is plugged into the serial port adapter board through a flat cable; the socket pin of the UART socket is used to access the UART signal of the controller; a voltage stabilizing module, a first end of which is respectively connected to the pins corresponding to the UART connector and the socket pins of the UART socket, and a second end of which is grounded; a second filter capacitor, having a first end connected to the second preset power supply and the mode selection pin of the UART socket respectively, and a second end grounded and connected to the data input pin of the UART socket; A third filter capacitor has a first end connected to the second preset power supply and the reset pin of the UART socket respectively, and a second end connected to the ground and the target disconnect pin of the UART socket.

4. The debugging board of the controller according to claim 3, characterized in that: The debugging board further includes an SD card slot, a first end of the SD card slot being connected to the SD interface of the domain controller through the male connector and the female connector, and a second end of the SD card slot being connected to the SD card; The SD card is used to store the software to be burned; The domain controller is used to perform software burning based on the control of the host computer connected to the serial port adapter board and the software to be burned stored in the SD card.

5. The debugging board of the controller according to claim 4, characterized in that: The debugging board also includes a linear voltage regulator, a power supply end of the linear voltage regulator is connected to a third preset power supply, a ground end is grounded, an enable end is connected to a preset universal pin of the domain controller through the male connector and the female connector, and an output end is connected to a fuse pin of the domain controller, and is used to output a fuse power supply based on the enable of the domain controller to control the melting of an electronic fuse in the domain controller.

6. The debugging board of the controller according to claim 1, characterized in that: If the controller is a domain controller of a car, the female connector further includes a startup configuration jack connected to a startup mode configuration pin in the domain controller, and the male connector further includes a startup configuration pin correspondingly connected to the startup configuration jack; The debugging board also includes: a dip switch, wherein a first end of a first channel is connected to a first startup configuration sub-pin of the startup configuration pins, a first end of a second channel is connected to a second startup configuration sub-pin of the startup configuration pins, and a first end of a third channel is connected to a third startup configuration sub-pin of the startup configuration pins; a first configuration resistor, a first end of which is connected to the second end of the first channel of the dip switch; a second configuration resistor, a first end of which is connected to the second end of the second channel of the dip switch; a third configuration resistor, a first end of which is connected to the fourth preset power source and to the second end of the second configuration resistor; A fourth configuration resistor has a first end connected to the second end of the third configuration resistor and the second end of the third channel of the dip switch respectively, and a second end grounded and connected to the second end of the first configuration resistor.

7. The debugging board of the controller according to claim 1, characterized in that: If the controller is a processor of a front-view camera of a car, the communication interface includes a DAP interface, and the communication interface connector includes a DAP connector corresponding to the DAP interface; The DAP connector includes: A DAP socket, wherein each socket pin of the DAP socket is connected to a corresponding pin of the DAP connector, and the socket pin of the DAP socket is connected to a cable connector of a DAP debugger; the socket pin of the DAP socket is used to access the DAP signal of the processor; a voltage stabilizing module, having a first end connected to the corresponding pins of the DAP connector and the socket pins of the DAP socket, and a second end connected to ground; a fourth filter capacitor, having a first end connected to the fifth preset power source and the power pin of the DAP socket, respectively, and a second end connected to ground and to the ground pin of the DAP socket; A fifth filter capacitor has a first end connected to the reset pin of the DAP socket and a second end connected to the ground.

8. The debugging board of the controller according to claim 1, characterized in that: If the controller is a computing module of a front-view integrated device of a car, the computing module obtains image information collected by the camera module through a first connector provided in the front-view integrated device and a second connector provided in the camera module; The debugging board also includes: a third connector, an output end of which is connected to the input end of the first connector via a first flexible circuit board; a fourth connector, an input end of which is connected to an output end of the second connector via a second flexible printed circuit board; The FPGA has an input end connected to the output end of the fourth connector and an output end connected to the input end of the third connector, and is used to perform clarity processing on the image information collected by the camera module.

9. The debugging board of the controller according to claim 8, characterized in that: Also includes: a serializer, whose input end is connected to the FPGA via a parallel interface, and is used to convert received image information from parallel data to serial data; The FAKRA connector has an input end connected to the output end of the serializer, and an output end connected to the on-board computer via a coaxial cable, and is used to output the image information to the on-board computer for display.

10. A debugging system, characterized in that: The invention comprises a controller and a debugging board of the controller according to any one of claims 1 to 9, wherein the female connector in the controller is plugged into the male connector in the debugging board of the controller.

Images