MLO access system of multi-interface wireless network card

Abstract

The utility model discloses an MLO access system of a multi-interface wireless network card, which is characterized in that the MLO access system comprises a plurality of MLO sockets and FPC (flexible printed circuit) flat cables connected among the sockets, the MLO sockets are respectively arranged on interface chips to be matched, the MLO sockets comprise input, output, time and data signals, and the FPCs are connected with the MLO sockets. The FPC flat cable is inserted into the MLO socket through the electric connection terminals at the two ends, the FPC flat cable and the MLO socket form a single-end wiring mode, and adjustment impedance of 50-70 ohms is achieved. According to the utility model, through the external connection of the MLO socket and the FPC flat cable, the application of the MLO technology in a multi-interface product is realized, the stability of the performance of the multi-interface product is ensured, the customization of the product is avoided, and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to a wireless network card technology, in particular to an MLO access system of a multi-interface wireless network card. Background Art

[0002] MLO is a multi-link aggregation technology that allows devices to utilize two or more frequency bands (such as 2.4GHz, 5GHz, and 6GHz) simultaneously, aggregating the bandwidth of these bands to improve overall wireless performance. Wi-Fi 7 introduced MLO technology, allowing devices to utilize the bandwidth of multiple frequency bands simultaneously, achieving higher speeds and efficiency. However, compatibility remains a challenge. With the large number of older devices on the market, ensuring backward and forward compatibility is a key issue.

[0003] Currently, platforms that support the MLO function are almost all designed based on the M2 or Mini-PCI e interface. For the Wi-Fi 7 technical solution, only a single interface access is supported. When multiple interfaces coexist, compatibility issues with MLO signal access will arise.

[0004] Specifically, the MLO control signal includes four channels: input / output and data / time. When connected to the M2 or Mini-PCI e interface, there are no corresponding MLO control signal connection pins in the two interface chips. Therefore, you need to define the PIN pins yourself. According to the official definition, the settings are:

[0005] PIN14:PCM_IN / I 2SSD_IN(I)(0 / 1.8V)

[0006] PIN20: UART WAKE#(O)(0 / 3.3V)

[0007] PIN32: UART RXD(I)(0 / 1.8V)

[0008] PIN36: UART CTS(I)(0 / 1.8V)

[0009] Defining the two interfaces as above will result in poor platform compatibility or incompatibility, and may even cause product recognition failure or product burnout. The current solution is to customize the product, but this customization limits product usage scenarios, lacks flexibility, and increases user costs. Summary of the Invention

[0010] The purpose of this utility model is to provide an MLO access system for a multi-interface wireless network card. By improving the circuit structure, the compatibility of MLO technology access is improved, the use of multi-interface network cards is supported, product customization is avoided, and the use cost is reduced.

[0011] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: an MLO access system for a multi-interface wireless network card, comprising a plurality of MLO sockets and FPC cables connecting the sockets, wherein the MLO sockets are respectively arranged on each interface chip to be matched, and the MLO sockets include four signals of input, output, time and data. The FPC cable is plugged into the MLO socket through electrical connection terminals at both ends, and the FPC cable and the MLO socket form a single-ended routing mode with an adjustable impedance of 50 to 70 ohms.

[0012] In the above technical solution, the interface chip includes an M2 interface chip and a Mini-PC I e interface chip.

[0013] In the above technical solution, the FPC cable adopts a five-core wire, of which the first, third and fifth wires are ground wires, and the second and fourth wires are signal wires. The corresponding connection socket is a five-pin socket. Each interface chip includes at least a group of two MLO sockets. Each MLO socket is provided with a signal terminal connected to the second and fourth wires of the FPC cable, and a ground terminal for spacing the signal wires. The outer layer of the five-core wire of the FPC cable is wrapped with a shielding layer.

[0014] In the above technical solution, a spring structure is provided in the electrical connection terminals at both ends of the FPC cable, and an access hole is provided on one side of the electrical connection terminal. The core wire is inserted into the access hole and clamped and fixed by the spring structure. The other side of the electrical connection terminal is the electrical connection end that is plugged into the MLO socket.

[0015] In the above technical solution, a reserved resistor or inductor for series connection is provided on the mainboard, corresponding to the periphery of the MLO socket. At an operating frequency of 160 MHz, the reserved resistor or inductor has a deviation impedance of 10-15 ohms.

[0016] The motherboard mentioned in the above technical solution refers to: PCMCIA wireless network card, PCI wireless network card, MiniPCI wireless network card, USB wireless network card, CF / SD wireless network card and other common wireless network card motherboards on the market, especially suitable for motherboards with multiple interfaces, such as M2-M2, M2-miniPC I e, miniPC I e-min iPC I e, a combination of two interfaces, or a combination of M2-M2-M2, M2-miniPCI e-M2, miniPCI e-miniPCI e, M2-miniPCI e-miniPCI e, and so on. The interfaces are connected in series using the access system in the technical solution of the utility model.

[0017] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0018] 1. This utility model adopts the connection method of MLO socket and FPC cable to establish MLO signal transmission between multiple interfaces, improve the compatibility between chip modules, achieve consistency between modules and motherboards, plug and play, avoid product customization, and reduce costs;

[0019] 2. MLO technology requires matching a certain impedance when connected. When using an external FPC cable, a 50-70 ohm adjustment resistor (usually around 60 ohms, which can be tested with an impedance meter) is connected to meet this requirement. The size of the adjustment resistor is changed according to the tested impedance value to achieve the impedance matching requirements between the motherboard and each interface module, realizing the application of MLO technology.

[0020] 3. A combination of two MLO sockets is used. Each MLO socket has two signal transmission lines and three grounding lines to complete the transmission of four signals. The signal lines are separated by grounding wires to form a good decoupling effect and reduce interference and radiation between lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the mainboard pins in the first embodiment of the present utility model;

[0022] Figure 2 Schematic diagram of the Mini-PC IE interface chip in the first embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the M2 interface chip in the first embodiment of the present utility model;

[0024] Figure 4 This is a system structure diagram of the first embodiment of the present utility model;

[0025] Figure 5 This is a structural diagram of the FPC cable in the first embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the FPC cable terminal assembly in Example 1 of the present utility model.

[0027] Among them: 1. Core wire; 2. Shielding layer; 3. Electrical connection terminal; 4. Spring structure. DETAILED DESCRIPTION

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0029] Example 1: See Figures 1 to 6As shown, an MLO access system for a multi-interface wireless network card includes several MLO sockets and FPC cables connecting the sockets. The MLO sockets are respectively set on each interface chip to be matched. The MLO sockets include four signals: input, output, time, and data. The FPC cables are plugged into the MLO sockets through electrical connection terminals at both ends. The FPC cables and the MLO sockets form a single-ended routing method with an adjustable impedance of 50 to 70 ohms.

[0030] In this embodiment, the interface chip includes an M2 interface chip and a Mini-PC 1 e interface chip. Figure 1 The PINs of the MLO control signal lines on the mainboard are shown in the following table:

[0031] Chip PIN GPIO MLO signal line name Net assignment N2 48 DATA OUT WAIKIKI_WSI_DATA_OUT_GPIO48 P1 49 CLOCK OUT WAIKIKI_WSI_CLK_OUT_GPIO49 P2 50 DATA IN WAIKIKI_WSI_DATA_IN_GPIO50 N1 51 CLOCK IN WAIKIKI_WSI_CLK_IN_GPIO51

[0032] The signals drawn from the above pins are connected to the corresponding pins of the M2 interface chip and the Mini-PCI e interface chip through the combination of the socket and the FPC cable, such as Figure 2 、 3 shown.

[0033] like Figure 5 As shown, the FPC cable uses a five-core wire, of which the first, third, and fifth wires are ground wires, and the second and fourth wires are signal wires. The corresponding connection sockets are five-pin sockets. Each interface chip includes at least one group of two connection sockets (combined into four signal lines). Each connection socket is provided with a signal terminal connected to the second and fourth wires of the FPC cable, and a ground terminal for spacing the signal wires. The outer layer of the five-core wire 1 of the FPC cable is wrapped with a shielding layer 2 to ensure transmission quality and avoid radiation and coupling. Figure 4 shown.

[0034] like Figure 6 As shown, a spring structure 4 is provided in the electrical connection terminals 3 at both ends of the FPC cable, and an access hole is provided on one side of the electrical connection terminal 3. The core wire 1 is inserted into the access hole and clamped and fixed by the spring structure 4. The other side of the electrical connection terminal 3 is the electrical connection end that is plugged into the MLO socket.

[0035] On the mainboard, a reserved resistor or inductor for series connection is provided around the corresponding connection socket. At an operating frequency of 160Mhz, the reserved resistor or inductor has a deviation impedance of 10-15 ohms, which improves the flexibility of adjusting the resistance.

[0036] When interference signals appear, the transmission quality will be affected. We mainly adopt the following methods to solve this interference in the product PCB integrated circuit wiring:

[0037] * Connector pin configuration so that ground is around each MLO clock / data pin;

[0038] * Provide grounding protection during the entire MLO clock / data wiring process;

[0039] *Take the MLO signal as a single-ended trace with an impedance of 60 ohms;

[0040] * Use ground vias to limit radiation, and the signal has ground protection and power isolation;

[0041] *MLO lines are isolated from power and all other nets and isolated at all layers.

[0042] The MLO control signal is single-ended and requires 60 ohms to ground. On an empty PCB board, use an impedance tester to perform an impedance test from one end of the mainboard (P in N2, P 1, P2, N1). Based on the tested impedance value, change the resistance of RA7 / RA6 to make the impedance between 50-70 ohms, that is, adjust the resistor matching method.

[0043] In this embodiment, the interface chip is an M2 / Mini-PCI e interface, but is not limited to this. It can be connected to three groups of interfaces or more. The connection method is similar. They are all connected to the motherboard in the form of sockets and external cables, rather than direct connections, thereby avoiding compatibility issues between interfaces and allowing MLO technology to be widely used.

Claims

1. An MLO access system for a multi-interface wireless network card, characterized by: It includes several MLO sockets and FPC cables connecting the sockets. The MLO sockets are respectively set on each interface chip to be matched. The MLO sockets include four signals: input, output, time and data. The FPC cables are plugged into the MLO sockets through electrical connection terminals at both ends. The FPC cables and the MLO sockets form a single-ended routing method with an adjustable impedance of 50 to 70 ohms.

2. The MLO access system of the multi-interface wireless network card according to claim 1, characterized in that: The interface chip includes an M2 interface chip and a Mini-PCIe interface chip.

3. The MLO access system of the multi-interface wireless network card according to claim 1, wherein: The FPC cable uses a five-core wire, of which the first, third, and fifth wires are ground wires, and the second and fourth wires are signal wires. The corresponding MLO socket is a five-pin socket. Each interface chip includes at least a group of two MLO sockets. Each MLO socket is provided with a signal terminal connected to the second and fourth wires of the FPC cable, and a ground terminal for spacing the signal wires. The outer layer of the five-core wire of the FPC cable is wrapped with a shielding layer.

4. The MLO access system of the multi-interface wireless network card according to claim 1 or 3, characterized in that: A spring structure is provided in the electrical connection terminals at both ends of the FPC cable. An access hole is provided on one side of the electrical connection terminal. The five-core wire is plugged into the access hole and clamped and fixed by the spring structure. The other side of the electrical connection terminal is the electrical connection end that is plugged into the MLO socket.

5. The MLO access system of the multi-interface wireless network card according to claim 1, wherein: On the mainboard, a reserved resistor or inductor for series connection is provided around the MLO socket. At an operating frequency of 160 MHz, the reserved resistor or inductor has a deviation impedance of 10-15 ohms.

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