Display device

Abstract

There is provided a display device including a display panel including a display area and a non-display area, and an electrostatic protection circuit disposed in the non-display area. The electrostatic protection circuit includes: a first stage circuit including a 1-1 diode that causes a forward current to flow from a first node to a second node, and a first capacitor and a first resistor connected in parallel to the 1-1 diode; a second stage circuit including a 2-1 diode that causes a forward current to flow from the second node to a third node, and a second capacitor and a second resistor connected in parallel to the 2-1 diode; and a third stage circuit including a 3-1 diode that causes a forward current to flow from the third node to the fourth node, and a third capacitor and a third resistor connected in parallel to the 3-1 diode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0147355, filed on October 31, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device and a mobile electronic device including the display device. More particularly, the present disclosure relates to a display device and a mobile electronic device including the display device that can protect the interior of a display panel from static electricity generated by a ground line and easily discharge static electricity generated inside the display panel to a substrate. Background Art

[0004] As the information society develops, the demand for display devices that can display images in a variety of formats is increasing. Flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays can be used as display devices. Displays that emit light can be organic displays using organic light-emitting diode elements as light-emitting elements or inorganic displays using light-emitting diodes or other light-emitting diode elements as light-emitting elements.

[0005] Depositing organic materials onto a substrate is a step in the manufacturing process of display panels or display devices. A deposition mask is used during this process. During the deposition process, an electrostatic chuck secures the substrate and aligns it with the deposition mask. Using electrostatic force, the electrostatic chuck secures and supports the substrate. In addition to providing stability and adhesion to the substrate, the electrostatic chuck also facilitates the discharge of static electricity generated by the interaction between the substrate and the deposition mask.

[0006] However, if the substrate and the electrostatic chuck are not properly in contact with each other, static electricity may be recharged in the ground line of the substrate. The recharged static electricity may be input to each of the plurality of display panels included in the substrate, causing defects in the display panels. Utility Model Content

[0007] Aspects of the present disclosure provide a display device and a mobile electronic device including the display device, which can protect the interior of the display panel from the influence of static electricity of a ground line arranged on the periphery of a mother substrate and can easily discharge static electricity generated inside the display panel to the periphery of the mother substrate.

[0008] According to an embodiment of the present disclosure, a display device may include: a display panel including a display area and a non-display area, and an electrostatic protection circuit arranged in the non-display area. The electrostatic protection circuit may include: a first-stage circuit including a 1-1 diode that allows a forward current to flow from a first node to a second node to which a first floating line is connected, and a first capacitor and a first resistor connected in parallel to the 1-1 diode; a second-stage circuit including a 2-1 diode that allows a forward current to flow from the second node to a third node to which a second floating line is connected, and a second capacitor and a second resistor connected in parallel to the 2-1 diode; and a third-stage circuit including a 3-1 diode that allows a forward current to flow from a third node to a fourth node, and a third capacitor and a third resistor connected in parallel to the 3-1 diode.

[0009] The first node may be connected to a main ground line of a mother substrate provided for manufacturing the display panel.

[0010] Each of the 1-1th diode, the 2-1th diode, and the 3-1th diode may include a thin film transistor.

[0011] As static electricity input to the first node passes through the first-stage circuit, the second-stage circuit, and the third-stage circuit in sequence, the static electricity input to the first node experiences a voltage drop and is then discharged through the fourth node.

[0012] The first-stage circuit may further include a 1-2 diode that allows a forward current to flow from the second node to the first node, the second-stage circuit may further include a 2-2 diode that allows a forward current to flow from the third node to the second node, and the third-stage circuit may further include a 3-2 diode that allows a forward current to flow from the fourth node to the third node. The first capacitor and the first resistor may be connected in parallel to the 1-2 diode, the second capacitor and the second resistor may be connected in parallel to the 2-2 diode, and the third capacitor and the third resistor may be connected in parallel to the 3-2 diode.

[0013] Each of the 1-2 th diode, the 2-2 th diode, and the 3-2 th diode may include a thin film transistor.

[0014] As static electricity input to the fourth node passes through the third-stage circuit, the second-stage circuit, and the first-stage circuit in sequence, the static electricity input to the fourth node experiences a voltage drop and is then discharged through the first node.

[0015] The fourth node may be connected to a common ground line commonly connected to the plurality of pads in the non-display area.

[0016] The pad may include a display pad unit connected to the circuit board through a common ground line.

[0017] The pad may include a test pad unit for a light emitting test of the display area.

[0018] According to an embodiment of the present disclosure, a mobile electronic device may include a display panel including a display area and a non-display area, and an electrostatic protection circuit disposed in the non-display area. The electrostatic protection circuit may include: a first-stage circuit including a 1-1 diode that allows a forward current to flow from a first node to a second node to which a first floating line is connected, and a first capacitor and a first resistor connected in parallel to the 1-1 diode; a second-stage circuit including a 2-1 diode that allows a forward current to flow from the second node to a third node to which a second floating line is connected, and a second capacitor and a second resistor connected in parallel to the 2-1 diode; and a third-stage circuit including a 3-1 diode that allows a forward current to flow from a third node to a fourth node, and a third capacitor and a third resistor connected in parallel to the 3-1 diode.

[0019] The first node may be connected to a main ground line of a mother substrate provided for manufacturing the display panel.

[0020] Each of the 1-1th diode, the 2-1th diode, and the 3-1th diode may include a thin film transistor.

[0021] As static electricity input to the first node passes through the first-stage circuit, the second-stage circuit, and the third-stage circuit in sequence, the static electricity input to the first node experiences a voltage drop and is then discharged through the fourth node.

[0022] The first-stage circuit may further include a 1-2 diode that allows a forward current to flow from the second node to the first node, the second-stage circuit may further include a 2-2 diode that allows a forward current to flow from the third node to the second node, and the third-stage circuit may further include a 3-2 diode that allows a forward current to flow from the fourth node to the third node, and the first capacitor and the first resistor may be connected in parallel to the 1-2 diode, the second capacitor and the second resistor may be connected in parallel to the 2-2 diode, and the third capacitor and the third resistor may be connected in parallel to the 3-2 diode.

[0023] Each of the 1-2 th diode, the 2-2 th diode, and the 3-2 th diode may include a thin film transistor.

[0024] As static electricity input to the fourth node passes through the third-stage circuit, the second-stage circuit, and the first-stage circuit in sequence, the static electricity input to the fourth node experiences a voltage drop and is then discharged through the first node.

[0025] The fourth node may be connected to a common ground line commonly connected to the plurality of pads in the non-display area.

[0026] The pads may include a display pad unit connected to a circuit board and a test pad unit for a light emitting test of a display area.

[0027] According to an embodiment of the present disclosure, a display panel may include a display area and a non-display area, a display driver configured to generate data signals and voltages for driving the display panel, and an electrostatic protection circuit disposed in the non-display area of ​​the display panel. One end of the electrostatic protection circuit is connected to the display driver via a common ground line, and the other end of the electrostatic protection circuit is connected to a main ground line of a mother substrate used to manufacture the display panel. The electrostatic protection circuit may include a first-stage circuit having a 1-1 diode that allows a forward current to flow from a first node to a second node to which a first floating line is connected, and a first capacitor and a first resistor connected in parallel to the 1-1 diode; a second-stage circuit having a 2-1 diode that allows a forward current to flow from a second node to a third node to which a second floating line is connected, and a second capacitor and a second resistor connected in parallel to the 2-1 diode; and a third-stage circuit having a 3-1 diode that allows a forward current to flow from a third node to a fourth node, and a third capacitor and a third resistor connected in parallel to the 3-1 diode. The first node may be connected to the main ground line, and the fourth node may be connected to the common ground line.

[0028] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become more apparent and easier to understand from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0031] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0032] Figure 3 is a conceptual diagram of a display unit and a touch driver according to an embodiment;

[0033] Figure 4 is a schematic plan view of a display unit of a display device according to an embodiment;

[0034] Figure 5 is a plan view of a touch unit of a display device according to an embodiment;

[0035] Figure 6 yes Figure 5 An enlarged view of area A1 in FIG;

[0036] Figure 7 is an enlarged view of a portion of a display device according to an embodiment;

[0037] Figure 8 It is along Figure 7 A cross-sectional view of a display device according to an embodiment taken along line II';

[0038] Figure 9 is a perspective view of a deposition mask according to an embodiment;

[0039] Figure 10 is a plan view of a mother substrate for manufacturing a display panel according to an embodiment;

[0040] Figure 11 is a diagram schematically illustrating a configuration of a peripheral portion of a display panel according to an embodiment;

[0041] Figure 12 is a circuit diagram of an electrostatic protection circuit according to an embodiment; and

[0042] Figure 13 and Figure 14 1 is a diagram for explaining the operation of the electrostatic protection circuit according to the embodiment. DETAILED DESCRIPTION

[0043] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and comprehensive and will fully convey the scope of the present disclosure to those skilled in the art.

[0044] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers or substrates may also be present. Like reference numerals refer to like components throughout the specification.

[0045] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. Similarly, the second element may also be referred to as the first element.

[0046] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may technically interact with each other in various ways, and the various embodiments may be implemented independently of each other or may be implemented in conjunction with each other.

[0047] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0048] Figure 1 is a schematic perspective view of a display device 10 according to an embodiment. Figure 2 is a schematic cross-sectional view of a display device 10 according to an embodiment.

[0049] In the drawings, the first direction (x direction) refers to a direction parallel to one side of the display device 10, for example, the short side direction of the display device 10 when viewed from the top. The second direction (y direction) refers to a direction parallel to the other side in contact with the upper side of the display device 10, for example, the long side direction of the display device 10 when viewed from the top. The third direction (z direction) refers to the thickness direction of the display device 10. However, the directions mentioned in the embodiments should be understood as relative directions, and the embodiments are not limited to the mentioned directions.

[0050] Examples of the display device 10 may include various electronic devices that provide display screens. For example, the display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be applied as a display unit for a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. In addition, the display device 10 may be applied to wearable devices such as smart watches, wristwatch phones, glasses-type displays, and head-mounted displays (HMDs).

[0051] refer to Figure 1 , the display device 10 has a planar shape similar to a quadrilateral. For example, the display device 10 has a planar shape similar to a quadrilateral having short sides in the x-direction and long sides in the y-direction. In another example, the display device 10 may have a planar shape similar to a square, so that all of the four sides may have substantially equal lengths. Each corner at which the short side extending in the x-direction meets the long side extending in the y-direction is rounded with a predetermined curvature or is a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0052] At least one of the front and rear surfaces of the display device 10 is a display surface. Here, "front" refers to a surface located on one side of a plane, that is, a surface located in the z-direction in the drawings, and "rear" refers to a surface located on the other side of the plane, that is, a surface located in the direction opposite to the z-direction in the drawings. In another example, the display device 10 may be a double-sided display device 10 that displays images on both the front and rear surfaces. However, the following description will focus on an embodiment in which the display surface is located on the front of the display device 10.

[0053] like Figure 1 As depicted in FIG, the display device 10 includes a display panel 100 providing a display screen, a display driver 200, a circuit board 300, and a touch driver 400. The touch driver 400 is configured to detect a user's touch input and may also be referred to as a "touch sensing device."

[0054] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in the x-direction and long sides in the y-direction. Each corner where the short side extending in the x-direction meets the long side extending in the y-direction may be rounded with a predetermined curvature or may be a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape. In addition, the display panel 100 may be formed to be flexible so that it can be bent or folded.

[0055] The display panel 100 may include a main area MA and a sub-area SBA spaced apart from the main area MA.

[0056] The main area MA may include a display area DA having pixels for displaying an image and a non-display area NDA surrounding the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0057] The non-display area NDA may be arranged outside the display area DA. In this case, the non-display area NDA surrounds the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that supplies gate signals to gate lines (not shown).

[0058] The sub-area SBA may protrude from one side of the main area MA. In this case, the sub-area SBA protrudes from the bottom portion of the main area MA along the second direction. The sub-area SBA may be curved so that the sub-area SBA overlaps the main area MA in the z-direction. The sub-area SBA may include the display driver 200, a pad unit connected to the circuit board 300, and a touch driver 400 disposed on the circuit board 300.

[0059] refer to Figure 2 , the display panel 100 includes a display unit DU and a touch unit TSU.

[0060] The display unit DU may include a plurality of pixels PX (see Figure 3 ). Each of the plurality of pixels PX is a basic unit of a display screen. Each of the plurality of pixels PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, but the present disclosure is not limited thereto. When viewed from the top, the plurality of pixels PX may be arranged. For example, the plurality of pixels PX may be arranged in a matrix form, but the present disclosure is not limited thereto.

[0061] The touch unit TSU may be arranged on the display unit DU, but the present disclosure is not limited thereto. For example, the touch unit TSU may be formed using an in-cell touch method like the display unit DU. The touch unit TSU may include a plurality of sensing electrodes RE and driving electrodes TE (see FIG. 1 ) for detecting a user's touch in a capacitive manner. Figure 5 ) and the sensing electrodes RE and the driving electrodes TE (see Figure 5 ) is connected to a plurality of touch driving lines TL of the touch driver 400 (see Figure 5 ) and a plurality of touch sensing lines RL (see Figure 5 ). The touch unit TSU detects input (ie, touch input) and can perform the function of the touch member. The touch unit TSU can determine whether a touch input occurs and calculate the corresponding position as the touch input coordinate. Figures 4 to 7 The display unit DU and the touch unit TSU are described in detail.

[0062] The display unit DU and the touch unit TSU may overlap each other in the z direction. For example, the display area DA may display a screen and detect a touch input.

[0063] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. In this case, the sub-area SBA of the display panel 100 extends from the bottom side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, rolled, etc. For example, Figure 2As depicted in FIG, a portion of the sub-area SBA is bendable on one side of the main area MA, such that another portion of the sub-area SBA overlaps the main area MA in the z-direction. When the sub-area SBA is bent, the sub-area SBA can be arranged below the display panel 100. In addition, the display driver 200, the circuit board 300, and the touch driver 400 can also be arranged below the display panel 100. In this case, the display driver 200, the circuit board 300, and the touch driver 400 can overlap the main area MA of the display panel 100 in the z-direction.

[0064] refer to Figure 1 , the display driver 200 is arranged in the sub-area SBA of the display panel 100. However, in another example, the display driver 200 may be formed as an integrated circuit and mounted on the display panel 100 using a chip on plastic (COP) method or a chip on glass (COG) method.

[0065] The display driver 200 may generate data signals and voltages to drive the display panel 100. In addition, the display driver 200 may supply data voltages to data lines (not shown) of the display panel 100. Furthermore, the display driver 200 may supply power voltages to power lines and gate control signals to gate drivers.

[0066] The circuit board 300 may be arranged in the sub-area SBA of the display panel 100. Leads (not shown herein) of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film. However, the circuit board 300 is not limited thereto. Therefore, the circuit board 300 may be any type of circuit board.

[0067] The circuit board 300 may include a plurality of wires (not shown) for transmitting signals from a main circuit board (not shown) to the display driver 200 or electrically connecting the touch driver 400 to the plurality of driving electrodes TE and sensing electrodes RE of the touch unit TSU.

[0068] The touch driver 400 may be disposed in the sub-area SBA of the display panel 100. Alternatively, the touch driver 400 may be mounted on the circuit board 300.

[0069] The touch driver 400 can determine whether a touch input occurs by detecting a change in capacitance between a plurality of touch electrodes and calculate touch coordinates (ie, position). In another example, the touch driver 400 can be formed as an integrated circuit and mounted on the display panel 100 using a COP method or a COG method.

[0070] Figure 3is a conceptual diagram of a display unit DU and a touch driver 400 according to an embodiment. Figure 4 is a schematic plan view of the display unit DU of the display device 10 according to the embodiment.

[0071] like Figure 3 and Figure 4 As depicted in FIG, the display device 10 includes a display panel 100 including a plurality of pixels PX, a display driver 200 and a touch driver 400.

[0072] The display driver 200 may include a data driver 230 and a display controller 220 .

[0073] The display controller 220 may receive input data R, G, B and timing control signals from an external source (e.g., a host). The timing control signals may include a vertical synchronization signal Vsync indicating a frame period, a horizontal synchronization signal Hsync indicating a horizontal period, and a master clock MCLK that repeats with a predetermined cycle. The input data R, G, B may be RGB data including red image data, green image data, and blue image data. The display controller 220 may use the received input data R, G, B and timing control signals to generate output data signals DR, DG, DB and internal control signals. The internal control signals may include a data driver control signal DCS and a gate driver control signal GCS. The data driver control signal DCS may be sent to the data driver 230, and the gate driver control signal GCS may be sent to the gate driver 210.

[0074] In this example, the display controller 220 may control the operation of the data driver 230 by providing the data driver control signal DCS to the data driver 230. The display controller 220 may control the operation of the gate driver 210 by providing the gate driver control signal GCS to the gate driver 210.

[0075] The data driver 230 may receive the output data signals DR, DG, DB and the data driver control signal DCS from the display controller 220 to generate a data signal using the received output data signals DR, DG, DB and the data driver control signal DCS. The data driver 230 may provide the generated data signal to each of the plurality of pixels PX of the display panel 100 through a plurality of data lines DL1, ..., DLn formed in the display panel 100.

[0076] The gate driver 210 may receive a gate driver control signal GCS from the display controller 220 and generate a gate signal using the received gate driver control signal GCS. The gate driver 210 may provide the generated gate signal to each of the plurality of pixels PX through a plurality of gate lines GL1, ..., GLn formed in the display panel 100. Figure 4 The data line DL is described in detail (see Figure 4 ) and the gate line GL (see Figure 4 ).

[0077] exist Figure 3 In the embodiment, the display driver 200 does not include the gate driver 210. However, in another example, the gate driver 210 may also be included in the display driver 200 that controls the operation of the display panel 100. Therefore, the gate driver 210, the data driver 230, and the display controller 220 may be formed as an integrated circuit. The gate driver 210 may be formed during the TFT process of the display panel 100. Furthermore, in another example, the display controller 220 and the data driver 230 may be combined to form a timing controller embedded driver integrated circuit (TED).

[0078] The display panel 100 may include a plurality of data lines DL (see Figure 4 ) and each of the plurality of gate lines GL (see Figure 4 ) each of multiple pixels PX.

[0079] The frame frequency at which the display driver 200 drives the display panel 100 can be varied. For example, the frame frequency can be variably driven from 1 Hz to 240 Hz according to a user's selection. The display driver 200 can drive the display panel 100 at 60 Hz during one section and change the frame frequency to 120 Hz during another section according to the user's selection.

[0080] The touch area TSA may include a plurality of driving electrodes TE (see Figure 5 ), multiple sensing electrodes RE (see Figure 5 ), multiple touch drive lines TL (see Figure 5 ) and a plurality of touch sensing lines RL (see Figure 5 ). The touch area TSA can detect a touch input from a user by receiving an electrical signal from the touch driver 400 arranged on the circuit board 300 via the touch driving line TL or transmitting an electrical signal detected from the sensing electrode RE to the touch driver 400 via the touch sensing line RL. Specifically, the touch driver 400 can detect a touch input by converting an analog electrical signal detected in the touch area TSA into a digital signal. Figure 5The touch driver 400 is described in detail.

[0081] refer to Figure 4 The display unit DU may include a display area DA and a non-display area NDA. The display unit DU may include a plurality of pixels PX and a plurality of gate lines GL and a plurality of data lines DL connected to the plurality of pixels PX.

[0082] The gate lines GL may supply each of the plurality of pixels PX with a gate signal received from the gate driver 210. The plurality of gate lines GL may extend in the x-direction and may be spaced apart from each other in the y-direction crossing the x-direction.

[0083] The data lines DL may supply each of the plurality of pixels PX with a data signal received from the display driver 200. The plurality of data lines DL may extend in the y-direction and may be spaced apart from each other in the x-direction.

[0084] like Figure 4 As depicted in , the non-display area NDA surrounds the display area DA. The gate driver 210 may be arranged on the left side of the display area DA, and the display driver 200 may be arranged on the bottom portion of the display area DA. However, the present disclosure is not limited to this. Therefore, in another example, the gate driver 210 may be arranged on the right side of the display area DA, and the display driver 200 may be arranged on the top portion of the display area DA. In this case, the non-display area NDA may include a gate driver 210 that transmits a gate signal to the gate line GL, a plurality of fan-out lines FOL that connects the data line DL and the display driver 200, and a plurality of display pad units DP connected to the circuit board 300.

[0085] The display driver 200 may supply a gate driver control signal GCS to the gate driver 210 through a plurality of gate control lines GCL. In this case, the plurality of gate control lines GCL may connect the display driver 200 to the gate driver 210. The gate driver 210 may generate a plurality of gate signals based on the gate driver control signal GCS and sequentially supply the gate signals to each of the plurality of gate lines GL in a set order.

[0086] The display driver 200 may supply a first power supply voltage to a plurality of first power lines VL and a second power supply voltage to a plurality of second power lines (not shown) through the data driver 230. Each of the plurality of pixels PX may receive the first power supply voltage through the first power line VL and the second power supply voltage through the second power line. The first power supply voltage may be a predetermined high-level voltage, and the second power supply voltage may be lower than the first power supply voltage.

[0087] The display pad area DPA and the touch peripheral area TPA may be arranged at the edge of the display panel 100. Figure 4 As shown in , the display pad area DPA and the touch peripheral area TPA are arranged below the display driver 200 in the y direction. However, in another example, the display pad area DPA and the touch peripheral area TPA can be arranged anywhere in the non-display area NDA. The display pad area DPA may include a plurality of display pad units DP. The display pad unit DP may be connected to a main processor (not shown) through a circuit board 300. The display pad unit DP may be connected to the circuit board 300 to receive digital video data, and the digital video data may be supplied to the display driver 200. In addition, the non-display area NDA may include a plurality of touch pad units TP arranged adjacent to the display pad unit DP along the x direction.

[0088] Figure 5 is a plan view of the touch unit TSU of the display device 10 according to the embodiment.

[0089] refer to Figure 5 The touch unit TSU includes a touch area TSA for detecting a user's touch and a touch peripheral area TPA arranged around the touch area TSA. The touch area TSA may overlap with the display area DA of the display panel 100 along the z-direction, and the touch peripheral area TPA may overlap with the non-display area NDA of the display panel 100 along the z-direction.

[0090] The touch unit TSU may include a plurality of driving electrodes TE, a plurality of sensing electrodes RE, a plurality of touch driving lines TL, and a plurality of touch sensing lines RL.

[0091] The circuit board 300 may include a plurality of first circuit pad units DCPD connected to the display pad units DP of the display panel 100, a plurality of second circuit pad units TCPD connected to the touch pad units TP of the display panel 100, and a plurality of touch circuit lines 212 connecting the second circuit pad units TCPD and the touch driver 400. The drive electrodes TE and the sensing electrodes RE of the touch area TSA may be sensor electrodes SEN and are electrically connected to the touch driver 400 via the circuit board 300. The touch area TSA receives electrical signals from the touch driver 400 disposed on the circuit board 300 via the touch drive lines TL and the touch sensing lines RL. Furthermore, the touch area TSA transmits electrical signals detected from the drive electrodes TE and the sensing electrodes RE to the touch driver 400 via the touch drive lines TL and the touch sensing lines RL, respectively.

[0092] The driving electrodes TE may be arranged in the x-direction and the y-direction. The driving electrodes TE may be spaced apart from each other in the x-direction and the y-direction. Each of the plurality of driving electrodes TE may be electrically connected to an adjacent driving electrode TE in the y-direction through a bridging electrode CE (or a connecting member CP).

[0093] Each of the plurality of drive electrodes TE may be connected to each of the plurality of touch pad units TP via a touch drive line TL. Some of the touch drive lines TL may extend to the touch pad unit TP via the lower side of the touch peripheral area TPA. Other touch drive lines TL may extend to the touch pad unit TP via the upper, left, and lower portions of the touch peripheral area TPA. However, in another example, the touch drive line TL may extend to the touch pad unit TP via the right portion of the touch peripheral area TPA. The touch pad unit TP may be connected to the touch driver 400 via the circuit board 300.

[0094] The display pad area DPA including the display pad unit DP and the touch pad unit TP may be arranged at an edge of the sub-area SBA of the display panel 100. The display pad unit DP and the touch pad unit TP may be electrically connected to the circuit board 300 using a low-resistance, high-reliability material such as an anisotropic conductive film.

[0095] The plurality of sensing electrodes RE may extend in the x-direction and may be spaced apart from each other in the y-direction. Thus, the sensing electrodes RE may be arranged in the x-direction and the y-direction. Each of the plurality of sensing electrodes RE may be electrically connected to an adjacent sensing electrode RE along the x-direction through a connecting portion.

[0096] The sensing electrodes RE may be connected to the touch pad unit TP via the touch sensing lines RL. For example, a plurality of sensing electrodes RE arranged on the right side of the touch area TSA may be connected to the touch pad unit TP via the touch sensing lines RL. In this case, the touch sensing lines RL may extend to the touch pad unit TP via the right and lower portions of the touch peripheral area TPA. However, in another example, the touch sensing lines RL may extend to the touch pad unit TP via the upper, right, and lower portions of the touch peripheral area TPA. The touch pad unit TP may be connected to the touch driver 400 via the circuit board 300.

[0097] Each of the driving electrode TE and the sensing electrode RE may include a surface-like pattern made of a transparent conductive layer, or include a grid-like pattern made of an opaque metal along an area where no light-emitting element is arranged. Therefore, the driving electrode TE and the sensing electrode RE may not interfere with the propagation of light emitted from the display area DA.

[0098] A touch drive signal may be transmitted from the touch driver 400 to each of the plurality of drive electrodes TE via one of the plurality of touch drive lines TL. When the touch drive signal is transmitted to each of the plurality of drive electrodes TE, mutual capacitance may be formed between the drive electrode TE and the adjacent sensing electrode RE. When a touch input occurs, the value of the mutual capacitance between the drive electrode TE and the adjacent sensing electrode RE may change. The change in the value of the mutual capacitance between the drive electrode TE and the adjacent sensing electrode RE may be transmitted to the touch driver 400 via the touch sensing line RL. Thus, the touch driver 400 may determine whether a touch input has occurred and calculate the corresponding coordinates (i.e., position) as touch input coordinates. Touch detection may be implemented through mutual capacitance, but the present disclosure is not limited thereto.

[0099] Figure 5 Reference character GND shown in illustrative figures may indicate a ground line formed on the circuit board 300 .

[0100] Figure 5 Reference character DME shown in may indicate a dummy electrode. The driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME may be arranged on the same layer and may be spaced apart from each other.

[0101] Figure 6 yes Figure 5 Magnified view of area A1 in FIG. Figure 7 is an enlarged view of a portion of the display device 10 according to the embodiment.

[0102] like Figure 6 and Figure 7 As depicted in FIG, a plurality of driving electrodes TE are arranged in the x-direction and the y-direction. In this case, the plurality of driving electrodes TE may be spaced apart from each other in the x-direction and the y-direction. Each of the plurality of driving electrodes TE may be electrically connected to an adjacent driving electrode TE via a bridge electrode CE.

[0103] The plurality of sensing electrodes RE may extend in the x-direction and may be spaced apart from each other in the y-direction. The sensing electrodes RE may be arranged in the x-direction and the y-direction. Each of the plurality of sensing electrodes RE may be electrically connected to an adjacent sensing electrode RE in the x-direction via a connecting portion RCE. For example, the connecting portion RCE of the sensing electrode RE may cross between adjacent driving electrodes TE.

[0104] A plurality of bridging electrodes CE may be arranged on a different layer from the drive electrodes TE and the sensing electrodes RE. Each of the plurality of bridging electrodes CE may include a first portion CEa and a second portion CEb. For example, the second portion CEb of each bridging electrode CE may be connected to the drive electrode TE arranged on one side through a first contact hole CNT1 and may extend in another direction DR2. The first portion CEa of each bridging electrode CE may be bent from the second portion CEb in an area overlapping with the sensing electrode RE and may extend in one direction DR1. The first portion CEa may be connected to the drive electrode TE arranged on the other side through a first contact hole CNT1. One direction DR1 may be a direction between the x-direction and the y-direction, and the other direction DR2 may be a direction intersecting the one direction DR1. For example, each of the plurality of bridging electrodes CE may connect a plurality of drive electrodes TE adjacent to each other in the y-direction.

[0105] According to an embodiment, when viewed from a plane, the driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see FIG. Figure 5 ) can be formed into a grid structure or a mesh structure. The driving electrodes TE, the sensing electrodes RE and the dummy electrodes DME (see Figure 5 ) may not overlap with the first to third emission areas EA1 to EA3 of the pixel PX. The bridging electrode CE may not overlap with the first to third emission areas EA1 to EA3. Therefore, the display device 10 can prevent the brightness of light emitted from the first to third emission areas EA1 to EA3 from being reduced by the touch unit TSU.

[0106] Each of the plurality of driving electrodes TE may include a first portion TEa extending in one direction DR1 and a second portion TEb extending in another direction DR2 that may be perpendicular to the one direction DR1. Each of the plurality of sensing electrodes RE may include a first portion REa extending in one direction DR1 and a second portion REb extending in another direction DR2.

[0107] According to an embodiment, when viewed from a plane, the driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see FIG. Figure 5 ) can be formed into a full-surface structure rather than a grid structure or a mesh structure. In this case, the driving electrodes TE, the sensing electrodes RE, and the dummy electrodes DME (see Figure 5 ) may include a transparent conductive material having high light transmittance, such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0108] Each of the plurality of pixels PX may include first to third sub-pixels, and the first to third sub-pixels may include first to third emission areas EA1 to EA3, respectively. For example, the first emission area EA1 may emit light of a first color or red light, the second emission area EA2 may emit light of a second color or green light, and the third emission area EA3 may emit light of a third color or blue light, but the present disclosure is not limited thereto. In another example, the first emission area EA1 may emit green light, the second emission area EA2 may emit blue light, and the third emission area EA3 may emit red light. In yet another example, the first emission area EA1 may emit blue light, the second emission area EA2 may emit red light, and the third emission area EA3 may emit green light.

[0109] Each of the plurality of pixels PX may include one first emission area EA1, two second emission areas EA2, and one third emission area EA3 to express a white grayscale. Thus, light emitted from one first emission area EA1, light emitted from two second emission areas EA2, and light emitted from one third emission area EA3 may be combined to express a white grayscale. However, in another example, the number of first emission areas EA1, second emission areas EA2, and third emission areas EA3 included in each of the plurality of pixels PX may be different from that of the present disclosure.

[0110] Figure 8 It is along Figure 7 1 is a cross-sectional view of the display device 10 according to the embodiment taken along line II′.

[0111] refer to Figure 8 The display panel 100 includes a display unit DU and a touch unit TSU. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL disposed on the substrate SUB, a light emitting element layer EML disposed on the thin film transistor layer TFTL, and an encapsulation layer TFEL disposed on the light emitting element layer EML.

[0112] The substrate SUB may support the display panel 100. The substrate SUB may be made of an insulating material such as a polymer resin. For example, the substrate SUB may be a flexible substrate that can be bent, folded, rolled, etc. For another example, the substrate SUB may include a flexible material and a rigid material.

[0113] The thin film transistor layer TFTL may include first and second buffer layers BF1 and BF2, a light shielding layer BML, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0114] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0115] Each of the plurality of light-shielding layers BML may be disposed on the first buffer layer BF1. For example, each of the plurality of light-shielding layers BML may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. For another example, each of the plurality of light-shielding layers BML may be an organic layer including a black pigment.

[0116] The second buffer layer BF2 may be disposed on the first buffer layer BF1 to cover the light shielding layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0117] The thin film transistor TFT may be arranged on the second buffer layer BF2 and may constitute a corresponding pixel circuit in the plurality of pixels PX. For example, each of the plurality of thin film transistors TFT may be a driving transistor or a switching transistor of the pixel circuit. Each of the plurality of thin film transistors TFT may include a semiconductor region ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. In this case, the drain electrode DE and the source electrode SE of the thin film transistor TFT may be arranged adjacent to the semiconductor region ACT, and the gate electrode GE of the thin film transistor TFT may be arranged on the semiconductor region ACT.

[0118] The semiconductor region ACT, source electrode SE, and drain electrode DE of the thin film transistor TFT may be arranged on the second buffer layer BF2. The semiconductor region ACT may overlap with the gate electrode GE in the thickness direction (i.e., the z-direction) and may be insulated from the gate electrode GE by the gate insulating layer GI. The source electrode SE and the drain electrode DE may be formed on the right and left sides of the semiconductor region ACT, respectively. The source electrode SE and the drain electrode DE may be formed by making the material of the semiconductor region ACT conductive.

[0119] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween.

[0120] A gate insulating layer GI may be disposed on the second buffer layer BF2 to cover the semiconductor region ACT, the source electrode SE, and the drain electrode DE. For example, the gate insulating layer GI may cover the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2 such that the gate insulating layer GI can insulate the semiconductor region ACT from the gate electrode GE. At least one contact hole, through which the first connection electrode CNE1 passes, is defined in the gate insulating layer GI of each of the plurality of thin film transistors TFT.

[0121] A first interlayer insulating layer ILD1 may be disposed on the gate insulating layer GI to cover the gate electrode GE. At least one contact hole through which the first connection electrode CNE1 passes is defined in the first interlayer insulating layer ILD1. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI.

[0122] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 and may overlap the gate electrode GE in the z direction.

[0123] A second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1 to cover the capacitor electrode CPE. At least one contact hole through which the first connection electrode CNE1 passes is defined in the second interlayer insulating layer ILD2 for each of the plurality of thin film transistors TFT. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0124] A first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. At least one of the plurality of first connection electrodes CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT. Another first connection electrode CNE1 may be connected to the source electrode SE.

[0125] A first passivation layer PAS1 may be disposed on the second interlayer insulating layer ILD2 to cover the first connection electrode CNE1. The first passivation layer PAS1 may protect the thin film transistor TFT. At least one contact hole through which the second connection electrode CNE2 passes is defined in the first passivation layer PAS1 of each of the plurality of thin film transistors TFT.

[0126] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first electrode AND of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole provided in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0127] The second passivation layer PAS2 may be disposed on the first passivation layer PAS1 to cover the second connection electrode CNE2. At least one contact hole through which the first electrode AND of the light emitting element ED passes is defined in the second passivation layer PAS2 of each of the plurality of thin film transistors TFT.

[0128] The light-emitting element layer EML may be disposed on the thin film transistor layer TFTL. For example, the light-emitting element layer EML may be disposed on the second passivation layer PAS2. The light-emitting element layer EML may include a light-emitting element ED and a pixel defining layer PDL. Each of the plurality of light-emitting elements ED may include a first electrode AND, a light-emitting layer EL, and a second electrode CAT.

[0129] The first electrode AND may overlap one of the first to third emission areas EA1 to EA3 defined by the pixel defining layer PDL. Figure 8 As shown in FIG, the first electrode AND overlaps the second emission area EA2 and the third emission area EA3. The first electrode AND may be connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0130] The light-emitting layer EL may be disposed on the first electrode AND. For example, the light-emitting layer EL may be, but is not limited to, an organic light-emitting layer made of an organic material. When the light-emitting layer EL is an organic light-emitting layer, if the thin film transistor TFT applies a predetermined voltage to the first electrode AND of the corresponding light-emitting element ED and the second electrode CAT of the light-emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the organic light-emitting layer EL through the hole transport layer and the electron transport layer, respectively. The holes and electrons may combine with each other in the organic light-emitting layer EL to emit light.

[0131] The second electrode CAT may be disposed on the light-emitting layer EL and the pixel-defining layer PDL. For example, the second electrode CAT may be implemented in the form of an electrode that commonly covers all pixels PX rather than being a separate electrode for each pixel PX. For example, the second electrode CAT may be disposed on the light-emitting layer EL in the first emission area EA1, the second emission area EA2, and the third emission area EA3, and on the pixel-defining layer PDL in areas other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0132] The pixel defining layer PDL may define a first emission area EA1, a second emission area EA2, and a third emission area EA3. The pixel defining layer PDL may separate and insulate the first electrodes AND of the plurality of light emitting elements ED from each other. For example, the pixel defining layer PDL is located between two adjacent emission areas. Figure 8 In the embodiment, the second emission area EA2 and the third emission area EA3 are separated by a pixel defining layer PDL interposed therebetween.

[0133] The encapsulation layer TFEL may be disposed on the second electrode CAT to cover the light-emitting element ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust.

[0134] The touch unit TSU may be disposed on the encapsulation layer TFEL. The touch unit TSU may include a third buffer layer BF3, a bridge electrode CE, a first insulating layer SIL1, a driving electrode TE, a sensing electrode RE, and a second insulating layer SIL2.

[0135] The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may serve as a layer having both insulating and optical functions. The third buffer layer BF3 may include at least one inorganic layer. However, in another example, the third buffer layer BF3 may be omitted. In this case, the first insulating layer SIL1 may be disposed on the encapsulation layer TFEL.

[0136] The bridge electrode CE may be disposed on the third buffer layer BF3. The bridge electrode CE may be disposed on a different layer from the driving electrode TE and the sensing electrode RE to connect the driving electrodes TE adjacent to each other in the y direction (see Figure 7 ). For example, the bridging electrode CE can be a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or can be a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy or a stacked structure of APC alloy and indium tin oxide (ITO / APC / ITO). The bridging electrode CE may not overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0137] The first insulating layer SIL1 may be disposed on the third buffer layer BF3 to cover the bridge electrode CE. The first insulating layer SIL1 may serve as a layer having both insulating and optical functions. For example, the first insulating layer SIL1 may be an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0138] The drive electrode TE and the sensing electrode RE may be arranged on the first insulating layer SIL1. Each of the drive electrode TE and the sensing electrode RE may not overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3. The drive electrode TE may overlap with the bridging electrode CE along the thickness direction (i.e., the z direction). Each of the drive electrode TE and the sensing electrode RE may be a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO).

[0139] The second insulating layer SIL2 may be arranged on the first insulating layer SIL1 to cover the drive electrode TE, the sensing electrode RE, and the first insulating layer SIL1. The second insulating layer SIL2 may serve as a layer having both insulating and optical functions. The second insulating layer SIL2 may be made of at least one of the various materials exemplified in the description of the first insulating layer SIL1.

[0140] exist Figure 8 In the embodiment, the bridge electrode CE is formed below the driving electrode TE and the sensing electrode RE, but the present disclosure is not limited thereto. For example, the bridge electrode CE may also be formed above the driving electrode TE and the sensing electrode RE. In this case, the bridge electrode CE may be formed on a different layer from the driving electrode TE and the sensing electrode RE.

[0141] Figure 9 is a perspective view of a deposition mask MK according to an embodiment. Figure 9 The mask MK of the embodiment illustrated in FIG. 5 may be used in a process of depositing at least a portion of the light emitting layer EL of the display panel 100 according to the embodiment.

[0142] refer to Figure 9 , the mask MK according to the embodiment may be a shadow mask in which the mask film MM is disposed on the mask substrate.

[0143] According to an embodiment, the mask MK may include a mask frame MF and a unit mask UM. The mask may also include a mask substrate, and a mask film MM may be arranged on the mask substrate. The mask films MM may be arranged in unit regions arranged in a matrix, and each unit region may be surrounded by a mask rib region. A portion of the mask substrate may be arranged in the mask rib region. The mask rib region may support the mask film MM.

[0144] The mask substrate may include a plurality of cell regions and a mask frame region that does not include the cell regions. The mask frame region may include a mask rib region surrounding each cell region and an outer frame region disposed at the outermost edge of the mask substrate. A mask frame MF may be disposed in the mask frame region. The mask frame MF may include mask ribs surrounding the cell regions.

[0145] The mask rib region may be a region that separates a plurality of unit regions. For example, the plurality of unit regions may be arranged in a matrix form, and the mask rib region may surround each of the plurality of unit regions.

[0146] The unit mask UM may include a mask film MM, and a plurality of openings OP are defined in the unit mask UM. The plurality of unit openings COP are defined by a mask frame MF. The unit openings COP and the unit mask UM covering at least a portion of the unit openings COP may be arranged in each of the plurality of unit regions of the mask substrate. For example, the unit mask UM may overlap with each of the plurality of unit openings COP in the third direction DR3. One unit mask UM may be used in the deposition process of one display panel 100.

[0147] A plurality of cell openings COP may penetrate the mask frame MF in a third direction DR3 (ie, a thickness direction) of the mask MK. The cell openings COP may be formed by partially etching the mask substrate from a back side.

[0148] Figure 10 is a plan view of a mother substrate 1010 for manufacturing the display panel 100 according to an embodiment.

[0149] refer to Figure 10 , a plurality of display panels 100 respectively corresponding to a plurality of unit regions of the mask substrate are placed on a mother substrate 1010 for manufacturing the display panels 100 according to an embodiment.

[0150] The periphery of the mother substrate 1010 is fixed and aligned with the deposition mask during the deposition process by a plurality of electrostatic chucks 1020. In this case, each of the plurality of electrostatic chucks 1020 supports the mother substrate 1010, and the mother substrate 1010 is fixedly attached to the plurality of electrostatic chucks 1020 by electrostatic force.

[0151] In addition to supporting and fixing the mother substrate 1010, the electrostatic chuck 1020 also serves as a discharge path for discharging static electricity generated when the mother substrate 1010 and the deposition mask are in contact with each other. To this end, main ground lines 1030 are arranged on the periphery of the mother substrate 1010. In this example, one of the main ground lines 1030 is arranged at the top portion of the mother substrate 1010, and another of the main ground lines 1030 is arranged at the bottom portion of the mother substrate 1010. The main ground lines 1030 allow static electricity input to the mother substrate 1010 to be discharged through the electrostatic chuck 1020 during the deposition process.

[0152] Figure 11 is a configuration diagram schematically illustrating a peripheral portion of a display panel 100 according to an embodiment. Figure 11 The main grounding wire 1030 in the figure is a reference Figure 10 The main ground line 1030 of the mother substrate 1010 is described.

[0153] refer to Figure 11 , the main ground line 1030 of the mother substrate 1010 is connected to the electrostatic protection circuit 1120 disposed in the non-display area NDA of each display panel 100. The electrostatic protection circuit 1120 prevents static electricity generated in the main ground line 1030 of the mother substrate 1010 from being input to each display panel 100. In addition, the electrostatic protection circuit 1120 discharges static electricity generated inside each display panel 100 through the main ground line 1030 of the mother substrate 1010.

[0154] According to an embodiment, the static electricity protection circuit 1120 includes first and second floating lines F1 and F2 to reduce the voltage level of generated static electricity. The first and second floating lines F1 and F2 are connected to diodes, resistors, and capacitors included in the static electricity protection circuit 1120.

[0155] According to an embodiment, the electrostatic protection circuit 1120 is arranged in the non-display area NDA of the display panel 100 and is interposed between the main ground line 1030 of the mother substrate 1010 and the common ground line 1110 arranged in the non-display area NDA of the display panel 100. For example, one end of the electrostatic protection circuit 1120 is connected to the main ground line 1030, and the other end of the electrostatic protection circuit 1120 is connected to the common ground line 1110.

[0156] The common ground line 1110 is a ground line commonly connected to a plurality of pads of the display panel 100. For example, the pads include a display pad unit DP connected to a circuit board (e.g., FPCB) and a test pad unit VIP for a light emitting test of the display area DA. The display pad unit DP and the test pad unit VIP are electrically connected through the common ground line 1110, and the common ground line 1110 is connected to the electrostatic protection circuit 1120. In this case, the display pad unit DP is arranged in the middle of the common ground line 1110, and the test pad unit VIP is arranged at both ends of the common ground line 1110. Therefore, the display pad unit DP and the test pad unit VIP are connected to the electrostatic protection circuit 1120 through the common ground line 1110.

[0157] The test pad unit VIP and the common ground line 1110 may be removed after the process of manufacturing the display panel 100. For example, Figure 11 , “CL” represents a virtual cutting line CL for separating each display panel 100 from the mother substrate 1010. Therefore, after the display panel 100 is shipped to the customer, the test pad unit VIP among the display pad unit DP and the test pad unit VIP is removed, and the common ground line 1110 and the display pad unit DP are disconnected from each other.

[0158] refer to Figure 12 、 Figure 13 and Figure 14 The electrostatic protection circuit 1120 according to the embodiment of the present disclosure is described in more detail.

[0159] Figure 12 is a circuit diagram of the electrostatic protection circuit 1120 according to an embodiment. Figure 13 and Figure 14 11 is a diagram for explaining the operation of the electrostatic protection circuit 1120 according to the embodiment.

[0160] refer to Figure 12 、 Figure 13 and Figure 14 According to an embodiment, the electrostatic protection circuit 1120 includes a first-stage circuit ST1, a second-stage circuit ST2, and a third-stage circuit ST3. However, this is merely an example, and the present disclosure is not limited thereto. For example, the electrostatic protection circuit 1120 may include fewer than or more than three stages of circuits. In this case, the electrostatic protection circuit 1120 can provide a greater voltage drop effect for static electricity.

[0161] like Figure 12As depicted in FIG, the first-stage circuit ST1 includes a 1-1th diode D1-1 that allows a forward current to flow from a first node N1 to a second node N2 to which a first floating line F1 is connected, and includes a first capacitor C1 and a first resistor R1 connected in series with the first capacitor C1. The first capacitor C1 and the first resistor R1 are connected in parallel to the 1-1th diode D1-1.

[0162] The second-stage circuit ST2 includes a 2-1st diode D2-1 that allows a forward current to flow from the second node N2 to the third node N3 to which the second floating line F2 is connected, and includes a second capacitor C2 and a second resistor R2 connected in series with the second capacitor C2. The second capacitor C2 and the second resistor R2 are connected in parallel to the 2-1st diode D2-1.

[0163] The third stage circuit ST3 includes a 3-1st diode D3-1 that allows a forward current to flow from the third node N3 to the fourth node N4, and includes a third capacitor C3 and a third resistor R3 connected in series with the third capacitor C3. The third capacitor C3 and the third resistor R3 are connected in parallel to the 3-1st diode D3-1.

[0164] The first node N1 is connected to a main ground line 1030 of a mother substrate 1010 for manufacturing the display panel 100. The fourth node N4 is connected to a common ground line 1110 that is commonly connected to a plurality of pads.

[0165] The 1-1 diode D1-1, the 2-1 diode D2-1, and the 3-1 diode D3-1 include thin film transistors T11, T12, and T13, respectively. In this example, the 1-1 diode D1-1, the 2-1 diode D2-1, and the 3-1 diode D3-1 are P-type thin film transistors T11, T12, and T13, respectively. However, the present disclosure is not limited thereto. In another example, the 1-1 diode D1-1, the 2-1 diode D2-1, and the 3-1 diode D3-1 are N-type thin film transistors T11, T12, and T13, respectively.

[0166] refer to Figure 13 , external static electricity 1031 (i.e., surge input 1) generated outside the display panel 100 and input to the first node N1 experiences a voltage drop as it passes through the first-stage circuit ST1 to the third-stage circuit ST3 in sequence, and is then discharged through the fourth node N4 (output 1, 1112).

[0167] External static electricity 1031 can be input to the electrostatic protection circuit 1120 through a portion of the main ground line 1030 of the mother substrate 1010. The external static electricity 1031 initially input to the electrostatic protection circuit 1120 experiences a voltage drop as it passes through the 1-1 diode D1-1, the 2-1 diode D2-1, and the 3-1 diode D3-1 in sequence, and is then discharged through the fourth node N4 (output 1, 1112). For example, if the voltage level of the external static electricity 1031 initially input to the electrostatic protection circuit 1120 is V11, it can become a voltage level of V12, which is lower than V11, in the first floating line F1 after passing through the 1-1 diode D1-1. In addition, the static electricity that has dropped to a voltage level of V12 in the first floating line F1 can become a voltage level of V13, which is lower than V12, in the second floating line F2 after passing through the 2-1 diode D2-1. In addition, static electricity that has dropped to a voltage level of V13 in the second floating line F2 may become a voltage level of V14 lower than V13 at the fourth node N4 after passing through the 3-1st diode D3-1. Therefore, external static electricity 1031 may become a discharged output 1 1112.

[0168] Return Reference Figure 12 The first-stage circuit ST1 further includes a 1-2 diode D1-2 that allows a forward current to flow from the second node N2 to the first node N1. The second-stage circuit ST2 further includes a 2-2 diode D2-2 that allows a forward current to flow from the third node N3 to the second node N2. The third-stage circuit ST3 further includes a 3-2 diode D3-2 that allows a forward current to flow from the fourth node N4 to the third node N3. The first capacitor C1 and the first resistor R1 are connected in parallel to the 1-2 diode, the second capacitor C2 and the second resistor R2 are connected in parallel to the 2-2 diode, and the third capacitor C3 and the third resistor R3 are connected in parallel to the 3-2 diode.

[0169] The 1-2 diode D1-2, the 2-2 diode D2-2, and the 3-2 diode D3-2 include a thin film transistor T21, a thin film transistor T22, and a thin film transistor T23, respectively. In this example, the 1-2 diode D1-2, the 2-2 diode D2-2, and the 3-2 diode D3-2 are respectively a P-type thin film transistor T21, a P-type thin film transistor T22, and a P-type thin film transistor T23. However, the present disclosure is not limited thereto. In another example, the 1-2 diode D1-2, the 2-2 diode D2-2, and the 3-2 diode D3-2 are respectively an N-type thin film transistor T21, an N-type thin film transistor T22, and an N-type thin film transistor T23.

[0170] refer to Figure 14, the internal static electricity 1111 (i.e., surge input 2) input to the fourth node N4 experiences a voltage drop as it passes through the third-stage circuit ST3, the second-stage circuit ST2, and the first-stage circuit ST1 in sequence, and is then discharged through the first node N1 (output 2, 1032).

[0171] Internal static electricity 1111, which is different from external static electricity 1031, can be generated inside the display panel 100 and can be input to the electrostatic protection circuit 1120 through a portion of the common ground line 1110. The internal static electricity 1111 initially input to the electrostatic protection circuit 1120 experiences a voltage drop as it passes through the 3-2 diode D3-2, the 2-2 diode D2-2, and the 1-2 diode D1-2 in sequence, and is then discharged through the first node N1 (output 2, 1032). For example, if the voltage level of the internal static electricity 1111 initially input to the electrostatic protection circuit 1120 is V21, it can become a voltage level of V22, which is lower than V21, in the second floating line F2 after passing through the 3-2 diode D3-2. In addition, the static electricity that has dropped to a voltage level of V22 in the second floating line F2 can become a voltage level of V23, which is lower than V22, in the first floating line F1 after passing through the 2-2 diode D2-2. In addition, static electricity that has dropped to a voltage level of V23 in the first floating line F1 may become a voltage level of V24 lower than V23 at the first node N1 after passing through the 1-2 th diode D1-2.

[0172] The fourth node N4 is connected to a common ground line 1110 that is commonly connected to a plurality of display pad units DP and a test pad unit VIP in the non-display area NDA. The display pad unit DP can be connected to a circuit board, and the test pad unit VIP is used for a light emission test of the display area. As described above, after the display panel 100 is shipped to the customer, the test pad unit VIP is removed from among the display pad unit DP and the test pad unit VIP, and the common ground line 1110 and the display pad unit DP are disconnected from each other.

[0173] In a display device according to an embodiment and a mobile electronic device including the display device, the interior of the display panel 100 can be protected from the static electricity of the main ground line 1030 arranged at the periphery of the mother substrate 1010, and the static electricity generated inside the display panel 100 can be easily discharged to the periphery of the mother substrate 1010.

[0174] In the display device according to the embodiment and the mobile electronic device including the display device, the interior of the display panel can be protected from the static electricity of the ground line arranged on the periphery of the mother substrate, and the static electricity generated inside the display panel can be easily discharged to the periphery of the mother substrate.

[0175] However, the effects of the present disclosure are not limited to the effects described herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

[0176] In the concluding part of the detailed description, it will be appreciated by those skilled in the art that many variations and modifications can be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the preferred embodiments disclosed herein are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, characterized in that: include: a display panel including a display area and a non-display area, and including an electrostatic protection circuit arranged in the non-display area, Wherein, the electrostatic protection circuit includes: a first-stage circuit including a 1-1 diode that allows a forward current to flow from a first node to a second node to which a first floating line is connected, and a first capacitor and a first resistor connected in parallel to the 1-1 diode; a second-stage circuit including a 2-1 diode that allows a forward current to flow from the second node to a third node to which a second floating line is connected, and a second capacitor and a second resistor connected in parallel to the 2-1 diode; and A third-stage circuit includes a 3-1 diode that allows a forward current to flow from the third node to a fourth node, and a third capacitor and a third resistor connected in parallel to the 3-1 diode.

2. The display device according to claim 1, wherein The first node is connected to a main ground line of a mother substrate provided for manufacturing the display panel.

3. The display device according to claim 1, wherein Each of the 1-1th diode, the 2-1th diode, and the 3-1th diode includes a thin film transistor.

4. The display device according to claim 1, wherein As static electricity input to the first node passes through the first-stage circuit, the second-stage circuit, and the third-stage circuit in sequence, the static electricity input to the first node experiences a voltage drop and is then discharged through the fourth node.

5. The display device according to claim 4, wherein: The first-stage circuit further includes a 1-2 diode that allows a forward current to flow from the second node to the first node, the second-stage circuit further includes a 2-2 diode that allows a forward current to flow from the third node to the second node, and the third-stage circuit further includes a 3-2 diode that allows a forward current to flow from the fourth node to the third node, and The first capacitor and the first resistor are connected in parallel to the 1-2 diode, the second capacitor and the second resistor are connected in parallel to the 2-2 diode, and the third capacitor and the third resistor are connected in parallel to the 3-2 diode.

6. The display device according to claim 5, wherein: Each of the 1-2 diode, the 2-2 diode, and the 3-2 diode includes a thin film transistor.

7. The display device according to claim 5, wherein: As static electricity input to the fourth node passes through the third-stage circuit, the second-stage circuit, and the first-stage circuit in sequence, the static electricity input to the fourth node experiences a voltage drop and is then discharged through the first node.

8. The display device according to claim 7, wherein: The fourth node is connected to a common ground line, and the common ground line is commonly connected to a plurality of pads in the non-display area.

9. The display device according to claim 8, wherein: The pad includes a display pad unit connected to a circuit board through the common ground line.

10. The display device according to claim 8, wherein The pads include a test pad unit for a light emitting test of the display area.

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