Board card identification circuit for case and case

Abstract

The utility model discloses a board card identification circuit for a case, which comprises a main control board card, a communication bus connected with the main control board card and a substrate, the communication bus is arranged on the substrate, and a plurality of sub board cards in communication connection with the communication bus can be configured on the substrate. Storage chips are configured on the daughter board cards in a one-to-one correspondence manner, and each storage chip is provided with a plurality of address pins; the substrate is provided with address level pin ends in one-to-one correspondence with the address pins, and the types and / or arrangement sequences of address level signals of the address level pin ends corresponding to the storage chips are different. When the daughter board card is inserted into the case, the storage chip can automatically allocate a specific address according to different types and / or arrangement sequences of the address level signals at the address level pin end at the position of the storage chip, so that a system can automatically identify and configure, the expansion process is greatly simplified, and the learning cost and the operation difficulty of a user are reduced.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a board identification circuit for a chassis and a chassis. Background Art

[0002] Data acquisition chassis, computer chassis, and other chassis often contain multiple independent daughter cards for processing multiple channel signals. Inserting or replacing a new daughter card often requires reconfiguration of the entire system, which may even require downtime. This results in inefficient chassis expansion and maintenance, and increases user operational difficulty.

[0003] Therefore, how to improve the expansion and maintenance efficiency of the chassis has become a technical problem that needs to be solved urgently. Utility Model Content

[0004] In view of this, the present application provides a board identification circuit and a chassis for a chassis to solve the technical problem of how to improve the expansion and maintenance efficiency of the chassis in the related art.

[0005] The present application provides a board identification circuit for a chassis, comprising: a main control board; a communication bus connected to the main control board; and a substrate, wherein the communication bus is arranged on the substrate, and a plurality of daughter boards communicatively connected to the communication bus can be configured on the substrate, the plurality of daughter boards being correspondingly configured with a plurality of memory chips, and the plurality of daughter boards corresponding one-to-one to the plurality of memory chips; for each of the memory chips, there are a plurality of address pins, and the substrate has a plurality of address level pins, corresponding one-to-one to the plurality of address pins, and the types and / or arrangement orders of the address level signals at the address level pin ends corresponding to different memory chips are different.

[0006] In one embodiment, the communication bus is provided on the substrate, and the substrate is installed in the chassis.

[0007] In one embodiment, the substrate is provided with a plurality of daughter card interfaces corresponding one-to-one to the plurality of daughter card interfaces, each of the daughter card interfaces having an address level pin end corresponding one-to-one to the address pin, and the address level pin ends of different daughter card interfaces have different types and / or arrangement orders of address level signals connected thereto.

[0008] In one embodiment, the port connecting each of the daughter boards to the baseboard is a hot-swappable port.

[0009] In one embodiment, a power line and a ground line are also provided on the substrate, wherein each of the daughter board card interfaces includes a power pin and a ground pin, the power line is connected to the power pin, and the ground line is connected to the ground pin; the multiple daughter board card interfaces are connected in parallel through the power line and the ground line.

[0010] In one embodiment, the board identification circuit for the chassis also includes a chassis panel, the substrate is fixedly connected to the chassis panel, and a sub-board mounting position is provided at a position corresponding to each sub-board interface, and the sub-board is fixedly mounted on the sub-board mounting position.

[0011] In one embodiment, the communication bus and the power line are distributed in different wiring layers of the substrate.

[0012] In one embodiment, the communication bus includes an I2C bus, and the storage chip includes an EEPROM chip.

[0013] According to the second aspect, an embodiment of the present application provides a chassis comprising: a chassis body and a board identification circuit for the chassis as described in any one of the first aspects above, which is arranged on the chassis body; the board identification circuit for the chassis can install multiple sub-boards.

[0014] In one embodiment, the connection port for connecting each of the daughter boards to the board identification circuit for the chassis is a hot-swappable port.

[0015] This application has at least the following beneficial effects:

[0016] The board identification circuit for a chassis provided by the present application includes a main control board, a communication bus connected to the main control board 10, and a substrate, wherein the communication bus is arranged on the substrate, and a plurality of daughter boards in communication connection with the communication bus can be configured on the substrate, and the daughter boards are configured with memory chips in a one-to-one correspondence, and a plurality of address pins of each memory chip are connected in a one-to-one correspondence with the address level pin ends on the substrate, and the type and / or arrangement order of the address level signal of the address level pin end corresponding to each memory chip are different. When the daughter board is inserted into the chassis, the memory chip will automatically assign a specific address according to the type and / or arrangement order of the address level signal of the address level pin end at its position, which enables the main control board to accurately identify the location of each daughter board and its function when reading information through the communication bus. In addition, the functional configuration of the corresponding daughter board can be pre-stored in the memory chip, and the main control board can quickly identify and perform corresponding initialization, which improves the automation level of the system. When the user replaces the daughter board or adds a new daughter board, he only needs to insert the new daughter board and the system can automatically identify and configure it, which greatly simplifies the expansion process and reduces the user's learning cost and operation difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a modular schematic diagram of a board identification circuit for a chassis provided according to an embodiment of the present application;

[0019] Figure 2 Schematic diagram of a memory chip configured on a daughterboard provided in an embodiment of the present application;

[0020] Figure 3 1 is a schematic diagram of a daughter card interface in a card identification circuit for a chassis according to an embodiment of the present application;

[0021] Figure 4 This is a schematic diagram of the principle of a board identification circuit for a chassis provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0023] According to an embodiment of the present application, a board identification circuit for a chassis is provided, such as Figures 1 to 4 As shown, the identification circuit includes: a main control board 10, a communication bus 20 connected to the main control board 10, and a substrate 30. The communication bus 20 is arranged on the substrate 30. A plurality of daughter boards 40 communicatively connected to the communication bus 20 can be configured on the substrate 30. The plurality of daughter boards 40 are respectively configured with memory chips 41 in a one-to-one correspondence. The plurality of address pins of each memory chip 41 are connected in a one-to-one correspondence with the address level pin ends on the substrate 30. The type and / or arrangement order of the address level signal of the address level pin end corresponding to each memory chip 41 are different.

[0024] When a daughter card 40 is inserted into the chassis, the memory chip 41 automatically assigns a specific address based on the type and / or order of the address level signals at the address level pins at its location. This allows the main control card 10 to accurately identify the functions and locations of each daughter card 40 when reading information via the communication bus 20. Furthermore, the memory chip 41 can pre-store the functional configurations of the corresponding daughter cards 40, allowing the main control card 10 to quickly identify and initialize them accordingly, improving the system's automation level. When replacing or adding a new daughter card, the user simply inserts the new daughter card 40, and the system automatically identifies and configures it. This greatly simplifies the expansion process and reduces the user's learning curve and operational difficulty.

[0025] In one embodiment, the address pins in the memory chip 41 can be connected to the address level pins on the daughter board interface 31 on the substrate 30, and the address pins in the memory chip 41 can also be connected to the address level pins on the daughter board interface 31 through its corresponding daughter board 40.

[0026] In one embodiment, the memory chip 41 includes an EPROM chip, an EEPROM chip, a flash memory, or other memory chip. In this embodiment, the memory chip 41 can be described using an EEPROM chip as an example. The communication bus 20 can be an SPI bus, an I2C bus, or a UART bus. In this embodiment, the I2C bus is used as an example.

[0027] The I2C bus allows multiple daughter cards 40 to exchange data via two lines, making communication between the daughter cards 40 more efficient. This not only reduces wiring complexity but also supports simultaneous connection of multiple daughter cards 40, enhancing system scalability.

[0028] The EEPROM chip can achieve non-volatile data storage for each daughter card 40, ensuring that it can retain key information after power failure. By storing the address and function configuration of the daughter card 40, the main control card 10 can quickly identify and perform corresponding initialization, improving the automation level of the system.

[0029] The address level pins corresponding to different memory chips 41 are connected to different address level signals. When different level signals and level signals of different arrangement orders are connected to the address level pins, different address instructions are formed. For example, Figure 2 and Figure 3As shown, the memory chip 41 has three address pins: a first pin A0, a second pin A1, and a third pin A2. The corresponding address level pins on the substrate 30 also have three terminals: a first terminal A0', a second terminal A1', and a third terminal A2'. Address level signals can be high or low. Therefore, when the first terminal A0', the second terminal A1', and the third terminal A2' are connected to a high level, they represent "1," and when they are connected to a low level, they represent "0." Therefore, the arrangement of "1" and "0" on the first terminal A0', the second terminal A1', and the third terminal A2' can form eight address instructions: 000, 001, 010, 011, 111, 110, 101, and 100. Therefore, by varying the type and / or arrangement order of the address level signals on the address level pins on the substrate 30, the substrate 30 can clearly identify the locations of all daughter cards 40 within the chassis through hardware-fixed addresses.

[0030] In one embodiment, the port connecting the daughterboard 40 to the baseboard 30 is a hot-swappable port. This hot-swappable port allows users to replace the daughterboard 40 without interrupting system operation. This flexibility not only improves device efficiency but also allows users to be more adaptable to changing application requirements. It provides a more user-friendly operating experience and meets diverse application needs. It enhances the efficiency and scalability of modern electronic system design, making it an ideal choice for building flexible and reliable systems.

[0031] In one embodiment, the substrate 30 has a plurality of daughter card interfaces 31, and each daughter card interface 31 is configured with an address level pin end corresponding to the address pin of each memory chip 41, such as Figure 3 As shown, the address level pins corresponding to each daughter card interface 31 are assigned address level signals by connecting to the auxiliary power supply VCC and the ground GND. Different daughter cards 40 have different address assignments by connecting to different auxiliary power supplies VCC and grounds GND, and by using different connection orders.

[0032] In one embodiment, if Figure 4As shown, the base plate 30 is also provided with a power line 50 and a ground line 60, wherein the daughter card interface 31 includes a power pin and a ground pin, the power line 50 is connected to the power pin, and the ground line 60 is connected to the ground pin; the daughter card interface 31 is connected in parallel via the power line 50 and the ground line 60. The base plate 30 carries the communication bus 20, the power line 50, the ground line 60, and carries multiple daughter card interfaces 31 that can connect to the power supply ports and communication ports of the daughter card 40. Therefore, only one base plate 30 is required to lay out the power supply lines and signal lines of multiple daughter cards 40, which can reduce the communication and power supply lines. At the same time, it eliminates the need for complex wiring within the chassis, reduces the number of cables and connection points inside the chassis, reduces the risk of signal interference and poor contact, improves the reliability of the system, reduces the potential failure rate, and thus enhances the stability of the entire system. In addition, it can also support modular expansion, facilitate system upgrades and maintenance, and can easily replace or add new daughter cards 40 as needed without modifying the entire chassis. Significantly improves maintenance efficiency, reduces downtime and repair costs.

[0033] In one embodiment, in order to prevent the power line 50 from interfering with the communication bus 20 , the power line 50 and the communication bus 20 are distributed on different wiring layers of the substrate 30 .

[0034] In one embodiment, the substrate 30 can be set on the chassis panel and fixedly connected by screws, and a sub-board card 40 mounting position is opened at the corresponding position of each sub-board card interface 31, and the sub-board card 40 is fixedly installed on the sub-board card 40 mounting position. The substrate 30 is installed on the chassis panel, and at the same time, a sub-board card 40 mounting position is reserved on the chassis panel so that the board can be directly locked on the panel through the mounting interface on the panel to achieve a secure fixation. By tightly combining the substrate 30 with the chassis panel, there is no need to install the sub-board cards 40 densely inside the chassis, avoiding the occupation of the internal space of the chassis and optimizing the utilization of the chassis space. At the same time, it can improve the heat dissipation performance of the board and prevent the problem of heat accumulation caused by multiple boards working at the same time affecting the performance of the chassis or system.

[0035] An embodiment of the present application also provides a chassis, which includes: a chassis body and a board identification circuit for the chassis described in any one of the above embodiments arranged on the chassis body; the board identification circuit for the chassis can install multiple daughter boards. When the daughter board is inserted into the chassis, the main control board will automatically assign a specific address to the memory chip according to the location of the memory chip. This enables the main control board to accurately identify the location of each daughter board and its function when reading information through the communication bus. In addition, the functional configuration of the corresponding daughter board can be pre-stored in the memory chip, and the main control board can quickly identify and perform corresponding initialization, which improves the automation level of the system. When the user replaces the board or adds a new board, he only needs to insert the new daughter board, and the system can automatically identify and configure it, which greatly simplifies the expansion process and reduces the user's learning cost and operation difficulty.

[0036] The connection port between the daughter card and the chassis' card identification circuit is a hot-swappable port, allowing users to replace daughter cards without interrupting system operation. This flexibility not only improves device efficiency but also allows users to be more adaptable to changing application requirements. It provides a more user-friendly operating experience and meets diverse application needs. It enhances the efficiency and scalability of modern electronic system design, making it an ideal choice for building flexible and reliable systems.

[0037] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0038] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A board identification circuit for a chassis, characterized in that: include: Main control board; A communication bus connected to the main control board; as well as substrate, wherein The communication bus is provided on the substrate, and a plurality of daughter boards communicatively connected to the communication bus may be configured on the substrate, and the plurality of daughter boards are correspondingly configured with a plurality of memory chips, and the plurality of daughter boards correspond to the plurality of memory chips in a one-to-one manner; Each of the memory chips has a plurality of address pins, and the substrate has a plurality of address level pin ends corresponding one-to-one to the plurality of address pins; The types and / or arrangement orders of the address level signals at the address level pin ends corresponding to different memory chips are different.

2. The board identification circuit for a chassis according to claim 1, wherein: The communication bus is arranged on the substrate, and the substrate is installed in the chassis.

3. The board identification circuit for a chassis according to claim 1, wherein: The substrate is provided with a plurality of daughter card interfaces corresponding one-to-one to the plurality of daughter card interfaces, each of the daughter card interfaces having an address level pin end corresponding one-to-one to the address pin, and the address level pin ends of different daughter card interfaces have different types and / or arrangement orders of address level signals connected thereto.

4. The board identification circuit for a chassis according to claim 1, wherein: The ports connecting the daughter boards to the baseboard are hot-swappable ports.

5. The board identification circuit for a chassis according to claim 3, wherein: The substrate is also provided with a power line and a ground line, wherein Each of the daughter card interfaces includes a power pin and a ground pin, the power line is connected to the power pin, and the ground line is connected to the ground pin; The plurality of daughter card interfaces are connected in parallel via the power line and the ground line.

6. The board identification circuit for a chassis according to claim 5, characterized in that: The communication bus and the power line are distributed in different wiring layers of the substrate.

7. The board identification circuit for a chassis according to claim 3, wherein: It also includes a chassis panel, the base plate is fixedly connected to the chassis panel, and a daughter board installation position is opened at a position corresponding to each daughter board interface, and the daughter board is fixedly installed on the daughter board installation position.

8. The board identification circuit for a chassis according to any one of claims 1 to 7, characterized in that: The communication bus includes an I2C bus, and the storage chip includes an EEPROM chip.

9. A chassis, characterized in that: include: A chassis body and a board identification circuit for a chassis as claimed in any one of claims 1 to 8, which is arranged on the chassis body; The board identification circuit for a chassis can be installed with multiple daughter boards.

10. The chassis according to claim 9, wherein: The connection port for connecting each of the daughter boards to the board identification circuit for the chassis is a hot-swappable port.

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