Shift register, gate drive circuit and display device

Abstract

The utility model provides a shift register, a gate drive circuit and a display device, and relates to the technical field of display, the shift register comprises an input circuit, a first control circuit and an output circuit; the input circuit is respectively connected with an input signal line and a first node, and is configured to write an input signal into the first node under the control of the input signal of the input signal line; the first control circuit is electrically connected with the first node and a first power supply signal line, and is configured to disconnect the first power supply signal line and the first node in a touch control stage; the output circuit is electrically connected with the first node, a clock signal line and an output signal line, and is configured to write a clock signal of the clock signal line into the output signal line under the control of the voltage of the first node. The poor cross grain of the display panel can be improved, and the image quality of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register, a gate driving circuit and a display device. Background Art

[0002] As users' demands for diversified functions of computer products such as notebooks (NB) increase, the application of functions such as finger touch and active pen touch continues to become popular, and the advantages of embedded touch such as in-cell touch display panels continue to emerge.

[0003] Embedded touch generally adopts the intra-frame touch (LHB) mode that alternates between the display stage and the touch stage. During the touch stage, the pull-up node (PU) voltage of the out-of-pit row needs to be maintained at a high level until the end of the touch stage so that the shift register can output the signal normally.

[0004] However, due to transistor leakage in the current shift register, the voltage of the PU node in the pit row is lower than that of the PU node in the non-pit row when it leaves the pit, causing the output signal of the shift register to decrease, resulting in insufficient charging of the corresponding pixel row, causing poor horizontal stripes on the display panel. Utility Model Content

[0005] The present application provides a shift register, a gate drive circuit, and a display device, which can solve the problem of defective horizontal stripes on a display panel caused by a voltage drop at a PU node of the shift register during a touch phase.

[0006] In a first aspect, the present application provides a shift register, the shift register comprising: an input circuit, a first control circuit, and an output circuit;

[0007] The input circuit is connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal of the input signal line;

[0008] The first control circuit is electrically connected to the first node and the first power signal line respectively, and is configured to disconnect the first power signal line from the first node during a touch control phase;

[0009] The output circuit is electrically connected to the first node, the clock signal line, and the output signal line, respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.

[0010] Optionally, the first control circuit includes a reset module and a pull-down module;

[0011] The reset module is electrically connected to the reset signal line, the first node, and the first power signal line, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the reset signal of the reset signal line;

[0012] The pull-down module is electrically connected to the second node, the first node, and the first power signal line respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second node.

[0013] Optionally, the reset module includes a first transistor;

[0014] The control electrode of the first transistor is electrically connected to the first sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the first sub-signal line;

[0015] The first sub-signal line is a signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register, and the target register is located at the next stage of the shift register.

[0016] Optionally, the reset module includes a second transistor;

[0017] The control electrode of the second transistor is electrically connected to the second sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the second sub-signal line.

[0018] Optionally, the second node includes a first pull-down node and a second pull-down node, and the pull-down module includes a first pull-down unit and a second pull-down unit;

[0019] The first pull-down unit is electrically connected to the first pull-down node, the first node, and the first power signal line, respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the first pull-down node;

[0020] The second pull-down unit is electrically connected to the second pull-down node, the first node, and the first power signal line, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second pull-down node.

[0021] Optionally, the first pull-down unit includes a third transistor;

[0022] The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.

[0023] Optionally, the second pull-down unit includes a fourth transistor;

[0024] The fourth transistor has a control electrode electrically connected to the second pull-down node, a first electrode electrically connected to the first node, and a second electrode electrically connected to the first power signal line.

[0025] Optionally, the shift register further includes a first noise reduction circuit;

[0026] The first noise reduction circuit is electrically connected to the first power signal line, the second node, and the second power signal line, respectively, and is configured to write the second power signal of the second power signal line into the second node under the control of the first power signal during the touch phase.

[0027] Optionally, the second node includes a first pull-down node and a second pull-down node, and the first noise reduction circuit includes a first noise reduction module and a second noise reduction module;

[0028] The first noise reduction module is electrically connected to the first power signal line, the first pull-down node, and the second power signal line, respectively, and is configured to write the second power signal into the first pull-down node under the control of the first power signal during the touch phase;

[0029] The second noise reduction module is electrically connected to the first power signal line, the second pull-down node, and the second power signal line, respectively, and is configured to write the second power signal into the second pull-down node under the control of the first power signal during the touch phase.

[0030] Optionally, the first noise reduction module includes a fifth transistor;

[0031] The control electrode of the fifth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the first pull-down node, and the second electrode is electrically connected to the second power signal line.

[0032] Optionally, the second noise reduction module includes a sixth transistor;

[0033] The control electrode of the sixth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the second pull-down node, and the second electrode is electrically connected to the second power signal line.

[0034] Optionally, the shift register further includes a second noise reduction circuit;

[0035] The second noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output signal line, respectively, and is configured to write the second power signal of the second power signal line into the output signal line under the control of the first power signal during the touch stage.

[0036] Optionally, the second noise reduction circuit includes a seventh transistor;

[0037] The control electrode of the seventh transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output signal line, and the second electrode is electrically connected to the second power signal line.

[0038] Optionally, the shift register further includes an output control circuit and a third noise reduction circuit;

[0039] The output control circuit is electrically connected to the first node, the clock signal line, and the output control line, respectively, and is configured to write the clock signal into the output control line under the control of the voltage of the first node;

[0040] The third noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output control line, respectively, and is configured to write the second power signal of the second power signal line into the output control line under the control of the first power signal during the touch phase.

[0041] Optionally, the third noise reduction circuit includes an eighth transistor;

[0042] The control electrode of the eighth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output control line, and the second electrode is electrically connected to the second power signal line.

[0043] In a second aspect, the present application provides a gate driving circuit, which includes a plurality of cascaded shift registers as described in the first aspect.

[0044] In a third aspect, the present application provides a display device, comprising the gate driving circuit as described in the second aspect.

[0045] The present application provides a shift register, gate driver circuit, and display device having at least the following advantages: the shift register includes an input circuit, a first control circuit, and an output circuit. The input circuit is respectively connected to an input signal line and a first node and is configured to write an input signal to the first node under control of an input signal from the input signal line. Thus, the input signal can be written to the first node via the input circuit, and the level of the first node can be changed by the input signal. The first control circuit is respectively electrically connected to the first node and a first power signal line and is configured to disconnect the first power signal line from the first node during a touch phase. Thus, the first node and the first power signal line are disconnected during the touch phase. By writing an input signal having a first level to the input signal line and writing a first power signal having a first level to the first power signal line, both the first node and the first power signal line are at the first level. This can alleviate the problem of a voltage drop at the first node caused by leakage from the first control circuit, thereby maintaining the level of the first node unchanged. Since the output circuit is electrically connected to the first node, the clock signal line and the output signal line respectively, it is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node. Because the voltage of the first node can maintain an unchanged level state during the touch stage, the output circuit can normally output the clock signal under the control of the voltage of the first node, avoiding the problem of insufficient charging of the pixel row corresponding to the shift register, which can improve the horizontal stripes of the display panel and improve the image quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 The following is a schematic diagram showing the structure of a shift register provided by an embodiment of the present application;

[0048] Figure 2 The following is a schematic diagram showing the structure of another shift register provided by an embodiment of the present application;

[0049] Figure 3 A schematic diagram of a state of a first control circuit provided in an embodiment of the present application is exemplarily shown;

[0050] Figure 4 The structure diagram of another shift register provided by an embodiment of the present application is exemplarily shown;

[0051] Figure 5 The following is a schematic diagram showing a state of a first noise reduction circuit provided by an embodiment of the present application;

[0052] Figure 6 Schematic diagram showing the states of the second noise reduction circuit and the third noise reduction circuit provided in an embodiment of the present application;

[0053] Figure 7 Schematic diagram showing voltage changes of a pull-up node of a pit row in the related art;

[0054] Figure 8 A waveform diagram of an output signal of a shift register provided by an embodiment of the present application is exemplarily shown;

[0055] Figure 9 A waveform diagram of an output signal of another shift register provided by an embodiment of the present application is exemplarily shown;

[0056] Figure 10 The following is a schematic diagram showing the level state changes of the signal before and after the touch control phase in an embodiment of the present application;

[0057] Figure 11 An overall timing diagram of a display device provided by an embodiment of the present application is exemplarily shown. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings in some embodiments to clearly and completely describe the technical solutions in some embodiments. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0059] In some embodiments, multiple signals have a first level and a second level. The first level and the second level merely represent that the level of the signal has two states, and do not represent that the first level or the second level has a specific value.

[0060] In some embodiments, the transistor may be a thin film transistor (TFT) or a metal oxide semiconductor (MOS) field effect transistor. The control electrode of the transistor may be a gate electrode, the first electrode may be a source electrode or a drain electrode, and the second electrode may be a drain electrode or a source electrode. For example, the transistor may be an N-type TFT or a P-type TFT, which is not limited in the present embodiment.

[0061] Figure 1The structure diagram of a shift register 10 provided in an embodiment of the present application is exemplarily shown. The shift register 10 includes: an input circuit 101, a first control circuit 102, and an output circuit 103;

[0062] The input circuit 101 is connected to the input signal line Input and the first node PU respectively, and is configured to write the input signal into the first node PU under the control of the input signal of the input signal line Input;

[0063] The first control circuit 102 is electrically connected to the first node PU and the first power signal line LVGL1, and is configured to disconnect the first power signal line LVGL1 from the first node PU during the touch phase.

[0064] The output circuit 103 is electrically connected to the first node PU, the clock signal line CLK, and the output signal line Gout(n), respectively, and is configured to write the clock signal of the clock signal line CLK into the output signal line Gout(n) under the control of the voltage of the first node PU.

[0065] In some embodiments, the shift register 10 can be applied to the gate drive circuit of an embedded touch panel, such as an Incell Touch display panel. The shift register 10 can serve as a gate driver on array (GOA) circuit in the gate drive circuit, also known as a GOA circuit, to provide a gate drive signal to the embedded touch panel.

[0066] In some embodiments, the control terminal and input terminal of the input circuit 101 can be electrically connected to the input signal line Input and receive the input signal transmitted by the input signal line Input. The output terminal of the input circuit 101 can be electrically connected to the first node PU. When the input circuit 101 connects the input signal line Input to the first node PU under the control of the input signal, the input circuit 101 can write the input signal to the first node PU, thereby charging the first node PU so that the first node PU maintains the same level as the input signal.

[0067] In some embodiments, the control terminal of the output circuit 103 can be electrically connected to the first node PU, the input terminal can be electrically connected to the clock signal line CLK, and the output terminal can be electrically connected to the output signal line Gout(n). When the output circuit 103, under the control of the voltage of the first node PU, connects the clock signal line CLK to the output signal line Gout(n), the output circuit 103 can write the clock signal transmitted by the clock signal line CLK to the output signal line Gout(n), thereby outputting the clock signal.

[0068] In some embodiments, an embedded touch panel can be driven using a touch-within-frame (LHB) mode that alternates between display and touch phases. The LHB mode divides a frame into multiple display and touch phases, with the touch phase being placed between two adjacent display phases to achieve a higher touch frequency. Specifically, when a pixel row is scanned, the row scan is temporarily paused and touch recognition is performed. The scan then resumes from the paused pixel row, alternating between the display and touch phases multiple times until a frame is displayed. If the clock signal is pulled low during the touch phase, the display panel is in a hold state.

[0069] In some embodiments, the first control circuit 102 connected to the first node PU in the shift register 10 is configured to disconnect the connection between the first power signal line LVGL1 and the first node PU during the touch stage. In this way, the first power signal of the first power signal line LVGL1 cannot change the voltage of the first node PU, and it is also possible to write a first power signal of the same level as the input signal to the first power signal line LVGL1 during the touch stage so that the level states at both ends of the first control circuit 102 are the same. This can improve the problem of the first node PU leaking electricity to the first power signal line LVGL1 through the first control circuit 102, causing the voltage of the first node PU to decrease. In this way, the voltage of the first node PU can be maintained at the level state after the input signal with the first level is written during the touch stage.

[0070] Specifically, before the touch phase, an input signal having a first level can be written to the input signal line Input, and the input signal having the first level can be written to the first node PU through the input circuit 101. The input signal having the first level charges the first node PU, so that the voltage of the first node PU is in the first level state. During the touch phase, a first power signal having a first level can be written to the first power signal line LVGL1, and the first control circuit 102 is controlled to disconnect the first power signal line LVGL1 from the first node PU. In this way, at both ends of the first control circuit 102, the voltage of the first node PU and the first power signal of the first power signal line LVGL1 are in the same first level state, thereby eliminating the leakage path of the first node PU, so that the voltage of the first node PU can be maintained at the first level during the touch phase.

[0071] Therefore, the problem of the voltage of the first node PU in the shift register 10 decreasing during the touch stage can be improved, and the abnormal output signal of the shift register 10 caused by the voltage decrease of the first node PU can be avoided. The output signal difference between different shift registers 10 can be reduced, and the horizontal stripes caused by the intra-frame touch mode to the embedded touch panel can be improved, thereby improving the touch display effect of the display panel and improving the product image quality.

[0072] In an embodiment of the present application, the shift register 10 includes an input circuit 101, a first control circuit 102, and an output circuit 103. The input circuit 101 is connected to an input signal line Input and a first node PU, respectively, and is configured to write an input signal to the first node PU under control of an input signal from the input signal line Input. Thus, the input signal can be written to the first node PU via the input circuit 101, thereby changing the voltage state of the first node PU via the input signal. The first control circuit 102 is electrically connected to the first node PU and a first power signal line LVGL1, respectively, and is configured to disconnect the first power signal line LVGL1 from the first node PU during a touch phase. Thus, during the touch phase, the first node PU and the first power signal line LVGL1 are disconnected. By writing an input signal having a first level to the input signal line Input and writing a first power signal having a first level to the first power signal line LVGL1, both the first node and the first power signal line are at the first level. This can alleviate the problem of a voltage drop at the first node PU caused by leakage through the first control circuit 102, thereby maintaining the voltage state of the first node PU unchanged. Since the output circuit 103 is electrically connected to the first node PU, the clock signal line CLK and the output signal line Gout(n) respectively, it is configured to write the clock signal of the clock signal line CLK into the output signal line Gout(n) under the control of the voltage of the first node PU. Because the voltage of the first node PU can maintain an unchanged level state during the touch stage, the output circuit 103 can normally output the clock signal under the control of the voltage of the first node PU, avoiding the problem of insufficient charging of the corresponding pixel row of the shift register 10, improving the horizontal stripes of the display panel, and improving the image quality of the display panel.

[0073] Optionally, the first control circuit 102 includes a reset module 1021 and a pull-down module 1022;

[0074] The reset module 1021 is electrically connected to the reset signal line, the first node PU, and the first power signal line LVGL1, and is configured to control the connection and disconnection between the first power signal line LVGL1 and the first node PU under the control of the reset signal of the reset signal line.

[0075] The pull-down module 1022 is electrically connected to the second node PD, the first node PU, and the first power signal line LVGL1, and is configured to control the connection and disconnection of the first power signal line LVGL1 and the first node PU under the control of the voltage of the second node PD.

[0076] In some embodiments, the control terminal of the reset module 1021 can be electrically connected to a reset signal line and receive a reset signal transmitted by the reset signal line. The reset module 1021 is also connected to the first node PU and the first power signal line LVGL1. When the reset module 1021 connects the first node PU to the first power signal line LVGL1 under the control of the reset signal, the voltage of the first node PU can be reset via the first power signal of the first power signal line LVGL1.

[0077] In some embodiments, the control terminal of the pull-down module 1022 can be electrically connected to the second node PD. The pull-down module 1022 is also electrically connected to the first node PU and the first power signal line LVGL1. When the pull-down module 1022, under the control of the voltage of the second node PD, conducts the connection between the first node PU and the first power signal line LVGL1, the first power signal of the first power signal line LVGL1 can be written to the first node PU, thereby maintaining the voltage level of the first node PU consistent with the voltage level of the first power signal.

[0078] In some embodiments, the touch phase can be set between the first display phase and the second display phase. During the touch phase, the reset signal and the voltage of the second node PD can be used to cause the reset module 1021 and the pull-down module 1022 to disconnect the first node PU from the first power signal line LVGL1. In addition, a first power signal having a first level can be written to the first power signal line LVGL1. The first power signal having the first level has the same level as the first-level input signal, thereby preventing the voltage of the first node PU from dropping due to leakage during the touch phase, thereby preventing the level state of the first node PU from changing. During the first display phase and the second display phase, a first power signal having a second level opposite to the first level can be written to the first power signal line LVGL1. When the reset module 1021 and the pull-down module 1022 connect the first node PU to the first power signal line LVGL1, the first power signal having the second level can be written to the first node PU to change the voltage level of the first node PU.

[0079] Optionally, the reset module 1021 includes a first transistor M2;

[0080] The control electrode of the first transistor M2 is electrically connected to the first sub-signal line Out_C(n+1), the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1; the reset signal line includes the first sub-signal line Out_C(n+1);

[0081] The first sub-signal line Out_C(n+1) is a signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register 10 , and the target register is located at the next stage of the shift register 10 .

[0082] In some embodiments, the shift register 10 may be a shift register 10 of a certain stage among a plurality of shift registers 10 cascaded with a gate drive circuit. The register of the next stage of the shift register 10 is the target register in this embodiment. The output control signal written to the output control signal line at the output control terminal of the target register may serve as a reset signal for the shift register 10. The output control signal line connected to the output control terminal of the target register is the first sub-signal line Out_C(n+1) in this embodiment.

[0083] In some embodiments, the first transistor M2 can serve as a reset transistor for the first node PU. When the first transistor M2 is turned on, the voltage of the first node PU is reset by the first power signal of the first power signal line LVGL1. When the first transistor M2 is turned off, the connection between the first node PU and the first power signal line LVGL1 is disconnected. During the touch phase, the first transistor M2 can be turned off to disconnect the first node PU from the first power signal line LVGL1. In addition, by writing a first power signal having a first level equal to the input signal level to the first power signal line LVGL1, the problem of a voltage drop at the first node PU caused by leakage through the first transistor M2 can be alleviated, thereby maintaining the voltage level of the first node PU during the touch phase.

[0084] For example, the first transistor M2 is an N-type TFT. When receiving a high-level reset signal, the first transistor M2 turns on, and when receiving a low-level reset signal, the first transistor M2 turns off. The control electrode of the first transistor M2 can be the gate electrode of the TFT, the first electrode can be the drain electrode of the TFT, and the second electrode can be the source electrode of the TFT. When the TFT is turned on, the source and drain electrodes are conductive, and the first node PU is electrically connected to the first power signal line LVGL1. When the TFT is turned off, the source and drain electrodes are disconnected, and the first node PU is disconnected from the first power signal line LVGL1.

[0085] Optionally, the reset module 1021 includes a second transistor M15;

[0086] The control electrode of the second transistor M15 is electrically connected to the second sub-signal T_RST, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1; the reset signal line includes the second sub-signal T_RST.

[0087] In some embodiments, the second sub-signal T_RST can be a reset signal line connected to an external driving circuit, and the external driving circuit provides a reset signal to the shift register 10, and the reset signal is used to control the turning on or off of the second transistor M15, thereby controlling whether the first power signal of the first power signal line LVGL1 is used to reset the voltage of the first node PU.

[0088] Similarly, the second transistor M15 can also serve as a reset transistor for the first node PU. During the touch phase, the connection between the first node PU and the first power signal line LVGL1 can be disconnected by controlling the second transistor M15 to be turned off. The voltage level of the first node PU can be maintained unchanged during the touch phase, as described above with reference to the first transistor M2. This description will not be repeated here. For example, the second transistor M15 is an N-type TFT. This is merely an example and is not limited in this embodiment of the present application.

[0089] Optionally, the second node PD includes a first pull-down node PD_A and a second pull-down node PD_B, and the pull-down module 1022 includes a first pull-down unit and a second pull-down unit;

[0090] The first pull-down unit is electrically connected to the first pull-down node PD_A, the first node PU, and the first power signal line LVGL1, and is configured to control the connection and disconnection of the first power signal line LVGL1 and the first node PU under the control of the voltage of the first pull-down node PD_A;

[0091] The second pull-down unit is electrically connected to the second pull-down node PD_B, the first node PU, and the first power signal line LVGL1, and is configured to control the connection and disconnection of the first power signal line LVGL1 and the first node PU under the control of the voltage of the second pull-down node PD_B.

[0092] In some embodiments, the pull-down module 1022 includes a first pull-down unit controlled by the voltage of a first pull-down node PD_A, and a second pull-down unit controlled by the voltage of a second pull-down node PD_B. By adjusting the voltages of the first pull-down node PD_A and the second pull-down node PD_B, the first pull-down unit and / or the second pull-down unit can control the connection between the first node PU and the first power signal line LVGL1.

[0093] In some embodiments, during the touch phase, the first pull-down unit and the second pull-down unit can be used to disconnect the first node PU from the first power signal line LVGL1, so that the first power signal of the first power signal line LVGL1 cannot change the voltage level of the first node PU. Furthermore, during the touch phase, a first power signal having a first level, which is the same as the input signal level, can be written to the first power signal line LVGL1. This can alleviate the problem of leakage from the first node PU through the first pull-down unit and the second pull-down unit, which can cause the voltage of the first node PU to drop. As a result, the voltage of the first node PU can remain unchanged during the touch phase.

[0094] Optionally, the first pull-down unit includes a third transistor M8A;

[0095] The control electrode of the third transistor M8A is electrically connected to the first pull-down node PD_A, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first power signal line LVGL1.

[0096] In some embodiments, the third transistor M8A can function as a pull-down transistor for the first node PU. When the third transistor M8A is turned on, the first power signal of the first power signal line LVGL1 is written to the first node PU. When the third transistor M8A is turned off, the connection between the first node PU and the first power signal line LVGL1 is disconnected. During the touch phase, the third transistor M8A can be controlled to be turned off to disconnect the first node PU from the first power signal line LVGL1. Furthermore, by writing a first power signal having a first level, which is the same as the input signal level, to the first power signal line LVGL1, the problem of a voltage drop at the first node PU caused by leakage through the third transistor M8A can be alleviated, thereby maintaining the voltage level of the first node PU during the touch phase.

[0097] For example, the third transistor M8A is an N-type TFT. When the voltage of the first pull-down node PD_A is at a high level, the third transistor M8A is turned on. When the voltage of the first pull-down node PD_A is at a low level, the third transistor M8A is turned off. The control electrode of the third transistor M8A can be the gate electrode of the TFT, the first electrode can be the drain electrode of the TFT, and the second electrode can be the source electrode of the TFT. This is merely an example and is not limited in the present embodiment.

[0098] Optionally, the second pull-down unit includes a fourth transistor M8B;

[0099] The fourth transistor M8B has a control electrode electrically connected to the second pull-down node PD_B, a first electrode electrically connected to the first node PU, and a second electrode electrically connected to the first power signal line LVGL1.

[0100] Similarly, in some embodiments, the fourth transistor M8B can also serve as a pull-down transistor for the first node PU. During the touch phase, the fourth transistor M8B can be turned off to disconnect the first node PU from the first power signal line LVGL1. Reference can be made to the aforementioned description of the third transistor M8A to maintain the voltage level of the first node PU unchanged during the touch phase, which will not be further described here. For example, the fourth transistor M8B is an N-type TFT. This is merely an example and is not a limitation of the present invention.

[0101] Figure 2 The structural diagram of another shift register 10 provided in an embodiment of the present application is exemplarily shown. Figure 2 As shown, the input circuit 101 may include a transistor M1, the output circuit 103 may include a transistor M3 and a capacitor C1, and the first control circuit 102 may include a first transistor M2, a second transistor M15, a third transistor M8A, and a fourth transistor M8B. Figure 2 In the shift register 10 shown, the transistor may be an N-type TFT, the control electrode of the transistor may be the gate electrode of the TFT, the first electrode may be the drain electrode of the TFT, and the second electrode may be the source electrode of the TFT. The first node PU may be a pull-up node (PU), the first power signal line LVGL1 may be an LVGL1 signal line, and the second node PD may be a pull-down node (PD). The second node PD includes a first pull-down node PD_A and a second pull-down node PD_B.

[0102] like Figure 2 As shown, the gate and drain of transistor M1 are electrically connected to the input signal line Input, respectively, and the source is electrically connected to the first node PU, wherein the input signal line Input can be a signal line Out_C connected to the output control terminal of a register cascaded with the shift register 10 and located at the upper level of the shift register 10. The gate of transistor M3 is electrically connected to the first node PU and the first end of the capacitor C1, the drain is electrically connected to the clock signal line CLK, and the source is electrically connected to the output signal line Gout(n). The drains of transistors M2 / M8A / M8B / M15 are electrically connected to the first node PU, respectively, and the sources are electrically connected to the first power signal line LVGL1, respectively. In the touch stage, the first node PU and the first power signal line LVGL1 can be disconnected by controlling the transistors M2 / M8A / M8B / M15 to be cut off.

[0103] like Figure 3As shown, during the first display phase before the touch phase, an input signal having a first level (high level), such as a high voltage signal (VGH) can be input to the input signal line Input. The VGH signal typically has a voltage range of 12 to 25 volts (V). The high-level input signal can charge the first node PU. For example, the input signal pulls the first node PU up to VGH, maintaining the voltage of the first node PU at a high level under the control of the first-level input signal. Then, during the touch phase, a first power signal having a first level can be written to the first power signal line LVGL1. This causes the source and drain electrodes of transistors M2 / M8A / M8B / M15 to all be high, mitigating the voltage drop at the first node PU caused by leakage through transistors M2 / M8A / M8B / M15. Furthermore, since the source and drain electrodes of transistor M1 are both high, the voltage drop at the first node PU caused by leakage through transistor M1 can be mitigated.

[0104] Among them, when the voltage value of the first node PU is equal to the voltage value of the first power signal in the first power signal line LVGL1, the voltage of the first node PU cannot leak to the first power signal line LVGL1 through the first control circuit 102. In this way, there is no leakage path for the first node PU during the touch stage, and the voltage of the first node PU can maintain a high level state until the end of the touch stage.

[0105] Optionally, the shift register 10 further includes a first noise reduction circuit 104;

[0106] The first noise reduction circuit 104 is electrically connected to the first power signal line LVGL1, the second node PD, and the second power signal line LVGL / VGL, respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL into the second node PD under the control of the first power signal during the touch phase.

[0107] In some embodiments, to prevent leakage of the first node PU through the first control circuit 102 during the touch phase, the first control circuit 102 needs to disconnect the first node PU from the first power signal line LVGL1 during the touch phase. Furthermore, the reset module 1021 and the pull-down module 1022 in the first control circuit 102 need to disconnect the first node PU from the first power signal line LVGL1. Specifically, for the pull-down module 1022, the voltage at the second node PD needs to remain unchanged at a constant level during the touch phase, so that the pull-down module 1022 can disconnect the first node PU from the first power signal line LVGL1 during the touch phase.

[0108] like Figure 2As shown, during the touch phase, a third power signal having a second level can be written to the third power signal line VDD_A / VDD_B. The second level can be a low level, and the transistors M5A / M5B are turned off. Furthermore, since the voltage of the first node PU is in a high level state during the touch phase, the transistors M6A / M6B are turned on under the voltage control of the first node PU. The first pull-down node PD_A and the second pull-down node PD_B are respectively connected to the second power signal line LVGL / VGL. Since the second power signal of the second power signal line LVGL / VGL can be a low level power signal, the voltages of the first pull-down node PD_A and the second pull-down node PD_B are both pulled down to a low level state, turning off the transistors M8A / M8B.

[0109] For example, a low voltage signal (VGL) can be written to the third power signal line VDD_A / VDD_B. The VGL signal generally has a voltage range of -6 to -15 V. The low-level second power signal can also be a VGL signal. When the first pull-down node PD_A and the second pull-down node PD_B are connected to the second power signal line LVGL / VGL, respectively, the node voltage is pulled down to VGL. The voltages of the first pull-down node PD_A and the second pull-down node PD_B are both low.

[0110] However, for non-pit rows, although a low-level third power signal is written to the third power signal line VDD_A / VDD_B during the touch stage, the voltage of the second node PD may be in a high-level state due to the presence of residual charge, which will make the transistor M8A / M8B unable to be cut off. When the transistor M8A / M8B is turned on, the first node PU and the first power signal line LVGL1 are conductive, which will cause the first node PU to be pulled high, which will affect some first nodes PU that are reset / pulled down to a low-level state, causing noise in the output signal of the non-pit row.

[0111] In some embodiments, the shift register 10 further includes a first noise reduction circuit 104, which is configured to reduce the noise of the voltage at the second node PD. Specifically, the first noise reduction circuit 104 is electrically connected to the first power signal line LVGL1, the second node PD, and the second power signal line LVGL / VGL, respectively. During a touch phase, a first power signal having a first level can be written to the first power signal line LVGL1. Under control of the first power signal, the first noise reduction circuit 104 writes a second power signal from the second power signal line LVGL / VGL to the second node PD. The second power signal reduces the noise of the voltage at the second node PD, so that during the touch phase, the voltage at the second node PD can control the pull-down module 1022 to disconnect the first node PU from the first power signal line LVGL1.

[0112] Optionally, the second node PD includes a first pull-down node PD_A and a second pull-down node PD_B, and the first noise reduction circuit 104 includes a first noise reduction module and a second noise reduction module;

[0113] The first noise reduction module is electrically connected to the first power signal line LVGL1, the first pull-down node PD_A, and the second power signal line LVGL / VGL, and is configured to write the second power signal into the first pull-down node PD_A under the control of the first power signal during the touch phase;

[0114] The second noise reduction module is electrically connected to the first power signal line LVGL1, the second pull-down node PD_B, and the second power signal line LVGL / VGL, and is configured to write the second power signal into the second pull-down node PD_B under the control of the first power signal during the touch phase.

[0115] In some embodiments, the voltage of the first pull-down node PD_A controls the first pull-down unit, and the voltage of the second pull-down node PD_B controls the second pull-down unit. To control the first pull-down unit to disconnect the first node PU from the first power signal line LVGL1 during the touch phase, the voltage of the first pull-down node PD_A can be reduced by a first noise reduction module. Similarly, to control the second pull-down unit to disconnect the first node PU from the first power signal line LVGL1 during the touch phase, the voltage of the second pull-down node PD_B can be reduced by a second noise reduction module.

[0116] In some embodiments, during the touch stage, a first power signal having a first level can be written to the first power signal line LVGL1, so that the first noise reduction module turns on the connection between the second power signal line LVGL / VGL and the first pull-down node PD_A, and writes the second power signal of the second power signal line LVGL / VGL into the first pull-down node PD_A, and reduces the voltage of the first pull-down node PD_A through the second power signal.

[0117] Optionally, the first noise reduction module includes a fifth transistor M16A;

[0118] The fifth transistor M16A has a control electrode electrically connected to the first power signal line LVGL1 , a first electrode electrically connected to the first pull-down node PD_A, and a second electrode electrically connected to the second power signal line LVGL / VGL.

[0119] In some embodiments, the fifth transistor M16A can function as a noise reduction transistor for the first pull-down node PD_A. When the fifth transistor M16A is turned on, the second power signal of the second power signal line LVGL / VGL is written to the first pull-down node PD_A. When the fifth transistor M16A is turned off, the connection between the first pull-down node PD_A and the second power signal line LVGL / VGL is disconnected. For example, the fifth transistor M16A is an N-type TFT. When the first power signal is a high-level power signal, the fifth transistor M16A is turned on, and when the first power signal is a low-level power signal, the fifth transistor M16A is turned off. The control electrode of the fifth transistor M16A can be the gate electrode of the TFT, the first electrode can be the drain electrode of the TFT, and the second electrode can be the source electrode of the TFT. The high-level first power signal can be a VGH signal, and the low-level first power signal can be a VGL signal. The voltage ranges of the VGH signal and the VGL signal, respectively, refer to the relevant descriptions in the aforementioned embodiments.

[0120] In some embodiments, during the touch stage, a first power signal having a first level can be written to the first power signal line LVGL1, so that the fifth transistor M16A turns on the connection between the second power signal line LVGL / VGL and the second pull-down node PD_B, and the second power signal of the second power signal line LVGL / VGL is written into the second pull-down node PD_B, and the voltage of the second pull-down node PD_B is reduced by the second power signal.

[0121] Optionally, the second noise reduction module includes a sixth transistor M16B;

[0122] The sixth transistor M16B has a control electrode electrically connected to the first power signal line LVGL1 , a first electrode electrically connected to the second pull-down node PD_B, and a second electrode electrically connected to the second power signal line LVGL / VGL.

[0123] In some embodiments, the sixth transistor M16B can function as a noise reduction transistor for the second pull-down node PD_B. When the sixth transistor M16B is turned on, the second power signal of the second power signal line LVGL / VGL is written to the second pull-down node PD_B. When the sixth transistor M16B is turned off, the connection between the second pull-down node PD_B and the second power signal line LVGL / VGL is disconnected. For example, the sixth transistor M16B is an N-type TFT. Similarly, the description of the fifth transistor M16A can be referred to and will not be repeated here. This is merely an example and is not limited to the embodiments of the present application.

[0124] In the embodiment of the present application, the shift register 10 further includes a first noise reduction circuit 104. The first noise reduction circuit 104 is electrically connected to the first power signal line LVGL1, the second node PD, and the second power signal line LVGL / VGL, respectively. The first noise reduction circuit 104 is configured to write the second power signal of the second power signal line LVGL / VGL to the second node PD under the control of the first power signal during the touch phase. In this way, the voltage of the second node PD can be reduced by the second power signal, so that during the touch phase, the voltage of the second node PD can control the pull-down module 1022 to disconnect the first node PU from the first power signal line LVGL1. This can alleviate the problem of the voltage of the first node PU being reduced due to leakage through the pull-down module 1022, and the voltage state of the first node PU can be maintained unchanged.

[0125] Optionally, the shift register 10 further includes a second noise reduction circuit 105;

[0126] The second noise reduction circuit 105 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output signal line Gout(n), respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL into the output signal line Gout(n) under the control of the first power signal during the touch phase.

[0127] In some embodiments, such as Figure 2 As shown, in the touch stage, a first power signal with a first level can be written to the first power signal line LVGL1, and the first level is a high level. For non-pit rows, some first nodes PU that are reset / pulled down to a low level state may be disconnected from the first power signal line LVGL1. Due to the presence of the transistor coupling capacitor in the first control circuit 102, at the moment when the first power signal jumps from the second level to the first level, that is, at the moment when the first power signal is pulled high, the voltage of the first node PU may also be slightly pulled up, causing noise in the output signal of the non-pit row.

[0128] In some embodiments, the shift register 10 further includes a second noise reduction circuit 105, which is configured to reduce noise on the output signal of the output circuit 103. Specifically, the second noise reduction circuit 105 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output signal line Gout(n), respectively. During the touch phase, a first power signal having a first level can be written to the first power signal line LVGL1. Under the control of the first power signal, the second noise reduction circuit 105 can write the second power signal of the second power signal line LVGL / VGL to the output signal line Gout(n). By reducing noise on the output signal of the output circuit 103 through the second power signal, noise generation on the output signal of non-pit-entering rows can be avoided.

[0129] Optionally, the second noise reduction circuit 105 includes a seventh transistor M18;

[0130] The seventh transistor M18 has a control electrode electrically connected to the first power signal line LVGL1 , a first electrode electrically connected to the output signal line Gout(n), and a second electrode electrically connected to the second power signal line LVGL / VGL.

[0131] In some embodiments, the seventh transistor M18 can function as a noise reduction transistor for the output circuit 103. When the seventh transistor M18 is on, the second power signal of the second power signal line LVGL / VGL is written to the output signal line Gout(n) connected to the output terminal of the output circuit 103. When the seventh transistor M18 is off, the output signal line Gout(n) is disconnected from the second power signal line LVGL / VGL. For example, the seventh transistor M18 is an N-type TFT. When the first power signal is a high-level power signal, the seventh transistor M18 is turned on, and when the first power signal is a low-level power signal, the seventh transistor M18 is turned off. The control electrode of the seventh transistor M18 can be the gate electrode of the TFT, the first electrode can be the drain electrode of the TFT, and the second electrode can be the source electrode of the TFT.

[0132] In some embodiments, during the touch stage, a first power signal having a first level can be written to the first power signal line LVGL1, so that the seventh transistor M18 turns on the connection between the second power signal line LVGL / VGL and the second pull-down node PD_B, and the second power signal of the second power signal line LVGL / VGL is written into the second pull-down node PD_B. The voltage of the second pull-down node PD_B is reduced by the second power signal, thereby avoiding noise generation in the non-pit row output signal.

[0133] In the embodiment of the present application, the shift register 10 further includes a second noise reduction circuit 105. The second noise reduction circuit 105 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output signal line Gout(n), respectively. The second noise reduction circuit 105 is configured to write the second power signal of the second power signal line LVGL / VGL to the output signal line Gout(n) under the control of the first power signal during the touch phase. In this way, the second power signal can be written as the output signal to the output signal line Gout(n) during the touch phase, thereby reducing the noise of the output signal of the output circuit 103.

[0134] Optionally, the shift register 10 further includes an output control circuit 106 and a third noise reduction circuit 107;

[0135] The output control circuit 106 is electrically connected to the first node PU, the clock signal line CLK, and the output control line Out_C(n), and is configured to write the clock signal to the output control line Out_C(n) under the control of the voltage of the first node PU;

[0136] The third noise reduction circuit 107 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output control line Out_C(n), respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL into the output control line Out_C(n) under the control of the first power signal during the touch phase.

[0137] In some embodiments, the shift register 10 further includes an output control circuit 106, which is configured to control the on / off state between the clock signal line CLK and the output control line Out_C(n) under the control of the voltage of the first node PU. Figure 2 As shown, the output control circuit 106 includes a transistor M2, which is an N-type TFT. The gate of the transistor M2 is electrically connected to the first node PU, the drain is electrically connected to the clock signal line CLK, and the source is electrically connected to the output control line Out_C(n). When the voltage of the first node PU is in a high-level state, the transistor M2 is turned on, and the clock signal is written to the output control line Out_C(n). When the voltage of the first node PU is in a low-level state, the transistor M2 is turned off, and the clock signal line CLK is disconnected from the output control line Out_C(n). The voltage of the first node PU is in a high-level state, for example, when the voltage of the first node PU is pulled up to VGH, the voltage of the first node PU is in a high-level state.

[0138] However, for non-pit rows, as described in the previous embodiment, the voltage of the second node PD may be high due to the presence of residual charge, causing the first node PU to be pulled high. This may also generate noise in the output control signal of the output control circuit 106. Therefore, in this embodiment, the third noise reduction circuit 107 is used to reduce the noise of the output control signal of the output control circuit 106 to prevent noise from being generated in the output control signal of non-pit rows.

[0139] In some embodiments, the shift register 10 includes a third noise reduction circuit 107, which is configured to reduce noise on the output control signal of the output control circuit 106. Specifically, the third noise reduction circuit 107 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output control line Out_C(n), respectively. During a touch control phase, a first power signal having a first level can be written to the first power signal line LVGL1. Under the control of the first power signal, the third noise reduction circuit 107 writes a second power signal from the second power signal line LVGL / VGL to the output control line Out_C(n), thereby reducing noise on the output control signal via the second power signal.

[0140] Optionally, the third noise reduction circuit 107 includes an eighth transistor M17;

[0141] The eighth transistor M17 has a control electrode electrically connected to the first power signal line LVGL1 , a first electrode electrically connected to the output control line Out_C(n), and a second electrode electrically connected to the second power signal line LVGL / VGL.

[0142] In some embodiments, the eighth transistor M17 can function as a noise reduction transistor for the output control circuit 106. When the eighth transistor M17 is on, the second power signal of the second power signal line LVGL / VGL is written to the output control line Out_C(n) connected to the output control terminal of the output control circuit 106. When the eighth transistor M17 is off, the output control line Out_C(n) is disconnected from the second power signal line LVGL / VGL. For example, the eighth transistor M17 is an N-type TFT. When the first power signal is a high-level power signal, the eighth transistor M17 is turned on, and when the first power signal is a low-level power signal, the eighth transistor M17 is turned off. The control electrode of the eighth transistor M17 can be the gate electrode of the TFT, the first electrode can be the drain electrode of the TFT, and the second electrode can be the source electrode of the TFT.

[0143] In the embodiment of the present application, the shift register 10 further includes an output control circuit 106 and a third noise reduction circuit 107. The output control circuit 106 is electrically connected to the first node PU, the clock signal line CLK, and the output control line Out_C(n), respectively, and is configured to write the clock signal to the output control line Out_C(n) under the control of the voltage of the first node PU. The third noise reduction circuit 107 is electrically connected to the first power signal line LVGL1, the second power signal line LVGL / VGL, and the output control line Out_C(n), respectively, and is configured to write the second power signal of the second power signal line LVGL / VGL to the output control line Out_C(n) under the control of the first power signal during the touch phase. In this way, the second power signal can be written as the output control signal to the output control line Out_C(n) during the touch phase, thereby reducing the noise of the output control signal of the output control circuit 106.

[0144] Figure 4 The structure diagram of another shift register 10 provided in the embodiment of the present application is exemplarily shown. Figure 2 The circuit structure of the shift register 10 shown is as follows: Figure 4 The shift register 10 shown further includes a first noise reduction circuit 104, a second noise reduction circuit 105, and a third noise reduction circuit 107. The first noise reduction circuit 104 may include a fifth transistor M16A and a sixth transistor M16B, the second noise reduction circuit 105 may include a seventh transistor M18, the output control circuit 106 may include a transistor M11, and the third noise reduction circuit 107 may include an eighth transistor M17. Figure 4 In the shift register 10 shown, the transistor may be an N-type TFT, the control electrode of the transistor may be the gate electrode of the TFT, the first electrode may be the drain electrode of the TFT, and the second electrode may be the source electrode of the TFT.

[0145] like Figure 4 As shown, the gate of the fifth transistor M16A is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the first pull-down node PD_A, and the source is electrically connected to the second power signal line LVGL / VGL. The gate of the sixth transistor M16B is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the second pull-down node PD_B, and the source is electrically connected to the second power signal line LVGL / VGL. The gate of the seventh transistor M18 is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the output signal line Gout(n), and the source is electrically connected to the second power signal line LVGL / VGL. The gate of the eighth transistor M17 is electrically connected to the first power signal line LVGL1, the drain is electrically connected to the output control line Out_C(n), and the source is electrically connected to the second power signal line LVGL / VGL.

[0146] like Figure 5 As shown, in the touch stage, a first power signal with a first level can be written to the first power signal line LVGL1, and the first level is a high level, and a second power signal with a second level can be written to the second power signal line LVGL / VGL, and the second level is a low level. Figure 5 In the embodiment, M16 includes M16A / M16B, and the second node PD includes a first pull-down node PD_A and a second pull-down node PD_B. Thus, the fifth transistor M16A and the sixth transistor M16B are turned on, and a low-level second power signal is written to the second node PD. That is, the second power signal is written to the first pull-down node PD_A and the second pull-down node PD_B, thereby pulling down the voltage level of the second node PD. This allows the voltage of the second node PD to remain low during the touch phase. In this way, the voltage of the second node PD can control the reset module 1021 and the pull-down module 1022 to disconnect the first node PU from the first power signal line LVGL1 during the touch phase.

[0147] like Figure 6 As shown, during the touch control phase, a first power signal having a first level (high) can be written to the first power signal line LVGL1, and a second power signal having a second level (low) can be written to the second power signal line LVGL / VGL. Thus, the seventh transistor M18 and the eighth transistor M17 are turned on, and the low-level second power signal is written to the output control line Out_C(n) and the output signal line Gout(n), thereby lowering the level of the output control signal of the output control circuit 106 and the output signal of the output circuit 103. This can reduce noise at the output control terminal of the output control circuit 106 and the output terminal of the output circuit 103, thereby preventing noise from being generated in the output control signal and the output signal.

[0148] An embodiment of the present application further provides a gate driving circuit, which includes a plurality of cascaded shift registers 10 as described in the aforementioned embodiment.

[0149] In some embodiments, the input circuit 101 of the shift register 10 can be connected to the output control terminal of the upper-stage register of the shift register 10 via an input signal line Input, and the output control signal of the upper-stage register is used as the input signal of the shift register 10. The control terminal of the pull-down module 1022 of the first control circuit 102 in the shift register 10 can be electrically connected to the output control terminal of the lower-stage register via a reset signal line, and the output control signal of the lower-stage register is used as the reset signal of the shift register 10.

[0150] For example, Figure 4As shown, the transistor M1 can be connected to the output control terminal of the upper register through the input signal line Input, and the first transistor M2 can be connected to the output control terminal of the next register through the reset signal line. Figure 4 The gate of transistor M4 can be connected to the next-stage register, and the output signal of the next-stage register can be used as the reset signal of this stage, thereby controlling the on / off state of transistor M4. Similarly, transistor M3 of the shift register 10 of this stage can also be connected to the previous-stage register, and the output signal of this stage can be used as the reset signal of the previous-stage register. This will not be further described here.

[0151] The gate driving circuit has the same advantages as those of the shift register 10 in the aforementioned embodiment compared to the related art, and will not be described in detail here.

[0152] An embodiment of the present application further provides a display device, which includes the gate driving circuit according to the aforementioned embodiment.

[0153] The display device has the same advantages as those of the shift register 10 in the aforementioned embodiment compared to the related art, and will not be described in detail here.

[0154] The driving process of a shift register 10 provided in an embodiment of the present application includes:

[0155] In the first display stage, an input signal with a first level is written to the input signal line Input, so that the input circuit 101 writes the input signal with the first level into the first node PU;

[0156] In the touch control stage, a first power signal with a first level is written to the first power signal line LVGL1, and the first control circuit 102 is controlled to disconnect the first power signal line LVGL1 from the first node PU; wherein the first level is the same as the level of the input signal.

[0157] In some embodiments, for a gate drive circuit that drives an embedded touch panel using the intra-frame touch (LHB) mode, during the touch phase, the first node PU in the shift register 10 corresponding to the entry row needs to maintain a level state after exiting the pit until the end of the touch phase, so that the shift register 10 can output a signal normally. Otherwise, during the touch phase, if the voltage of the first node PU decays after exiting the pit, the output signal of the shift register 10 will decrease, resulting in insufficient charging of the corresponding pixel row, causing poor horizontal stripes on the display panel. Such horizontal stripes are called LHB horizontal stripes. For example, Figure 4 In the shift register 10 shown, the voltage of the first node PU needs to be kept at a high level until the touch control phase ends.

[0158] In related technologies, such as Figure 4In the circuit structure shown, if there is no first power signal line LVGL1, the source of the transistor M2 / M8A / M8B / M15 is connected to the second power signal line LVGL / VGL, and the second power signal of the second power signal line LVGL / VGL is in a low-level state during the touch stage, and the signal connected to the gate of the transistor M2 / M8A / M8B / M15 and the PD node are also in a low-level state, then the Vgs of the transistor M2 / M8A / M8B / M15 is 0V, and the 0V TFT leakage current is large. The PU node may continuously leak power to the transistor M2 / M8A / M8B / M15 during the touch stage, resulting in the voltage of the PU node being lower than that of the non-pit row at the end of the touch stage, causing the output signal after the pit to be reduced, and the corresponding pixel row to be insufficiently charged, resulting in the LHB horizontal stripe problem.

[0159] Figure 7 The PU node voltage change of the pit row in the related art is shown as an example. Figure 7 As shown in the figure, during the touch stage, the voltage of the PU node is difficult to maintain a high voltage due to leakage. Figure 7 The simulated voltage drop shown here reaches approximately 11V.

[0160] In some embodiments, in the first display phase before the touch phase, for the pit entry row, an input signal with a first level may be written to the input signal line Input, and under the control of the input signal with the first level, the input circuit 101 may write the input signal with the first level to the first node PU. For example, Figure 4 The shift register 10 shown can write a high-level input signal, such as a VGH signal, to the input signal line Input, control the transistor M1 to turn on, and write the high-level input signal to the first node PU, so that the voltage of the first node PU is pulled up to a high-level state.

[0161] In some embodiments, when entering the touch phase, the first control circuit 102 is controlled to disconnect the first power signal line LVGL1 from the first node PU and write a first power signal having a first level, which is the same as the input signal level, to the first power signal line LVGL1. That is, during the first display phase, an input signal having a first level is first written to the input signal line Input, causing the voltage of the first node PU to be at the first level. Then, when entering the touch phase, the first power signal having the first level is written to the first power signal line LVGL1. In this way, while the first control circuit 102 disconnects the first node PU from the first power signal line LVGL1, the first power signal in the first power signal line LVGL1 is at the same level as the voltage of the first node PU. This can alleviate the problem of a voltage drop at the first node PU caused by leakage of electricity from the first control circuit 102 to the first power signal line LVGL1, thereby maintaining the voltage of the first node PU at the first level during the touch phase. Moreover, when the voltage value of the first node PU is equal to the voltage value of the first power signal, the leakage path of the first node PU can be eliminated, the output signal of the shift register 10 is reduced, and the horizontal stripes of the display panel caused by the reduction can be avoided, thereby improving the display effect of the display panel.

[0162] Figure 8 The waveform diagram of the output signal of the shift register 10 of the embodiment of the present application is shown as an example. Figure 8 As shown, the voltage of the first node PU can maintain a level state for a long time in the touch stage, and the direct touch stage ends. Figure 8 The voltage waveform of the first node PU shows that the voltage drop of the first node PU is only 2.13V, compared with Figure 7 The voltage drop of the first node PU is greatly improved, and the abnormal output signal of the shift register 10 can be reduced, thereby improving the horizontal stripe defect of the display panel.

[0163] In some embodiments, for non-pit entry rows, during the touch phase, a first power signal having a first level can be written to the first power signal line LVGL1, and a second power signal having a second level can be written to the second power signal line LVGL / VGL, with the first and second levels having opposite phases. Thus, under the control of the first power signal, the first noise reduction circuit 104, the second noise reduction circuit 105, and the third noise reduction circuit 107 write the second power signal of the second power signal line LVGL / VGL to the second node PD, the output signal line Gout(n), and the output control line Out_C(n), respectively. This reduces the voltage at the second node PD, the output signal of the output circuit 103, and the output control signal of the output control circuit 106, thereby preventing noise from being generated in the output signal and the output control signal.

[0164] Figure 9 The waveform diagram of the output signal of the shift register 10 of the non-pit row in the embodiment of the present application is exemplarily shown, as shown in FIG. Figure 9 As shown, by reducing the noise of the voltage of the second node PD, the output signal of the output circuit 103, and the output control signal of the output control circuit 106 during the touch stage, the shift register 10 of the non-entry row can output the signal normally, which can avoid the noise generated by the output signal and the output control signal, and can reduce the difference between different shift registers 10, thereby improving the touch display effect of the display panel and enhancing the product image quality.

[0165] In the embodiment of the present application, an input signal is written to the input signal line Input during the first display phase, causing the input circuit 101 to write the input signal to the first node PU. In the touch phase, a first power signal having a first level is written to the first power signal line LVGL1, and the first control circuit 102 is controlled to disconnect the first power signal line LVGL1 from the first node PU. The first level is the same as the level of the input signal. In this way, the voltage at the first node PU can be maintained at the first level during the touch phase, allowing the output circuit 103 to normally output a clock signal under the control of the voltage at the first node PU. This avoids the problem of insufficient charging of the corresponding pixel row of the shift register 10, improves the horizontal stripes on the display panel, and enhances the image quality of the display panel.

[0166] The driving process of the shift register 10 provided in the embodiment of the present application further includes:

[0167] In the second display phase, a first power signal with a second level is written to the first power signal line LVGL1, and a clock signal is written to the clock signal line CLK, so that the output circuit 103 writes the clock signal to the output signal line Gout(n);

[0168] The first display stage also includes:

[0169] A first power signal of a second level is written into the first power signal line LVGL1 , wherein the signals corresponding to the first level and the second level have opposite phases.

[0170] In some embodiments, the touch stage can be set between the first display stage and the second display stage. In the first display stage and the second display stage, a first power signal of a second level with a phase opposite to the first level can be written to the first power signal line LVGL1, so that the reset module 1021 and the pull-down module 1022 in the first control circuit 102 turn on the connection between the first node PU and the first power signal line LVGL1. The reset module 1021 and the pull-down module 1022 can write the first power signal with the second level to the first node PU to change the level state of the voltage of the first node PU.

[0171] In some embodiments, since the scanning of the entry row is paused and touch recognition is performed during the touch stage, for example, Figure 4 The shift register 10 shown can pull down the level of the clock signal line CLK, keeping the clock signal on the clock signal line CLK at a low level during the touch phase. In the second display phase after the touch phase, a normal clock signal can be written to the clock signal line CLK for the entry row, causing the output circuit 103 to write the clock signal to the output signal line Gout(n), resuming scanning from the paused pixel row.

[0172] Optionally, the shift register 10 further includes a pull-up circuit 108 , which is electrically connected to the third power signal line VDD_A / VDD_B and the second node PD respectively;

[0173] The first display stage also includes:

[0174] Writing a third power signal of the first level to the third power signal line VDD_A / VDD_B so that the pull-up circuit 108 conducts the connection between the second node PD and the third power signal line VDD_A / VDD_B, and writing the third power signal of the first level to the second node PD;

[0175] The second display stage also includes:

[0176] Writing a third power signal of the first level to the third power signal line VDD_A / VDD_B so that the pull-up circuit 108 conducts the connection between the second node PD and the third power signal line VDD_A / VDD_B, and writing the third power signal of the first level to the second node PD;

[0177] The touch phase also includes:

[0178] Writing a third power signal of a second level to the third power signal line VDD_A / VDD_B so that the pull-up circuit 108 disconnects the second node PD from the third power signal line VDD_A / VDD_B;

[0179] The time point at which the first power signal jumps from the second level to the first level is delayed by a first time period relative to the time point at which the third power signal jumps from the first level to the second level; the time point at which the first power signal jumps from the first level to the second level is advanced by a first time period relative to the time point at which the third power signal jumps from the second level to the first level;

[0180] The first duration is greater than or equal to the row scanning duration and less than or equal to twice the row scanning duration; the row scanning duration indicates the duration required to scan a row of pixels.

[0181] In some embodiments, the pull-up circuit 108 may include: Figure 4 The transistor M5A and the transistor M5B in the shift register 10 shown may be N-type TFTs, the gate and drain of the transistor M5A and the transistor M5B being electrically connected to the third power signal line VDD_A / VDD_B, respectively, and the source of the transistor M5A and the transistor M5B being electrically connected to the first pull-down node PD_A and the second pull-down node PD_B, respectively.

[0182] In some embodiments, during the touch phase, a third power signal having a second level can be written to the third power signal line VDD_A / VDD_B to cause the pull-up circuit 108 to disconnect the second node PD from the third power signal line VDD_A / VDD_B. For example, the low-level third power signal can be used to control transistors M5A and M5B to turn off. During the first display phase and the second display phase, a third power signal having a first level can be written to the third power signal line VDD_A / VDD_B to cause the pull-up circuit 108 to connect the second node PD to the third power signal line VDD_A / VDD_B. In this way, the pull-up circuit 108 can write the third power signal having a first level to the second node PD. For example, the high-level third power signal can be used to control transistors M5A and M5B to turn on, allowing the high-level third power signal to be written to the first pull-down node PD_A and the second pull-down node PD_B.

[0183] Among them, the high-level third power supply signal can be a VGH signal, the VGH signal can control the N-type transistor M5A and the transistor M5B to turn on, and the low-level third power supply signal can be a VGL signal, the VGL signal can control the N-type transistor M5A and the transistor M5B to turn off. The VGH voltage range and the VGL voltage range refer to the relevant descriptions in the aforementioned embodiments.

[0184] In some embodiments, for non-pit rows, although a low-level third power signal is written to the third power signal line VDD_A / VDD_B during the touch stage, the voltage of the second node PD may be in a high-level state due to the presence of residual charge, which will make the transistor M8A / M8B unable to be turned off. When the transistor M8A / M8B is turned on, the first node PU and the first power signal line LVGL1 are connected, which will cause the first node PU to be raised too high, resulting in the risk of multiple outputs flickering.

[0185] Therefore, after entering the touch phase, a third power signal at the second level can be written to the third power signal line VDD_A / VDD_B first, and then after a first delay, a first power signal at the first level can be written to the first power signal line LVGL1. This causes the first power signal to transition from the second level to the first level after a first delay when entering the touch phase. Similarly, before exiting the touch phase, a first power signal at the second level can be written to the first power signal line LVGL1 first, and then after a first delay, a third power signal at the first level can be written to the third power signal line VDD_A / VDD_B.

[0186] In this way, after entering the touch control phase, at the time when the first power signal jumps from the second level to the first level, the pull-down module 1022 in the first control circuit 102 has already disconnected the first node PU from the first power signal line LVGL1 under the control of the voltage of the second node PD. Furthermore, before exiting the touch control phase, at the time when the third power signal jumps from the second level to the first level, the first power signal on the first power signal line LVGL1 has already changed to the second level.

[0187] Figure 10 The example shows the level state change of the signal before and after the touch stage in the embodiment of the present application. Figure 10 As shown, for Figure 4 In the shift register 10 shown, in the first display stage, the third power signal of the third power signal line VDD_A / VDD_B is at a high level, the second power signal of the second power signal line LVGL / VGL is at a low level, and the first power signal of the first power signal line LVGL1 is at a low level. The level states of the signals in the second display stage are the same as those in the first display stage and will not be described in detail here. After entering the touch stage, the third power signal of the third power signal line VDD_A / VDD_B first becomes a low level, and after a first time delay, the first power signal of the first power signal line LVGL1 becomes a high level. Before exiting the touch stage, the first power signal of the first power signal line LVGL1 first becomes a low level, and after a first time delay, the third power signal of the third power signal line VDD_A / VDD_B becomes a high level.

[0188] That is, the time point at which the first power signal jumps from the second level to the first level is delayed by a first duration relative to the time point at which the third power signal jumps from the first level to the second level; and the time point at which the first power signal jumps from the first level to the second level is advanced by a first duration relative to the time point at which the third power signal jumps from the second level to the first level. The first duration is 1 to 2 hours, indicating that the first duration is greater than or equal to the row scanning duration and less than or equal to twice the row scanning duration, and H represents the duration required to scan a row of pixels.

[0189] Figure 11 The overall timing diagram of a display device according to an embodiment of the present application is shown as an example. Figure 11 As shown, the time of one frame in LHB mode may include at least the first display phase (Display Time), the touch phase (TouchTime) and the second display phase (Display Time). The first power signal may be a signal marked as LVGL1, the clock signal may include signals marked as CLK1~8, the second power signal may include signals marked as VGL / LVGL, the third power signal may include signals marked as VDDO / VDDE, Out1~4 represent output signals, and Figure 11 Also shown are the frame start signal STV, the reset signal Treset, and the source driving signal (Source) output by the source driving circuit in the display device.

[0190] Current embedded touch panels, such as in-cell touch display panels, are increasingly pursuing higher refresh rates while supporting active pen touch. This places a higher demand on the PU node's ability to maintain voltage during the touch phase. This is because a higher refresh rate shortens the charging time of a single pixel. For example, increasing the refresh rate from 60 Hz to 120 Hz cuts the pixel charging time in half. This, in turn, increases the leakage time of the PU node, significantly impacting the shift register output. In particular, when the shift register operates at high temperatures, transistors M2 / M6 / M8 drift more severely, leading to more severe PU node leakage. This can lead to insufficient shift register output, resulting in horizontal streaks on the display panel.

[0191] While it's possible to shift the transistor's threshold voltage (Vth) positively by adjusting the process to reduce transistor 0V leakage, the improvement is minimal and will reduce the shift register's noise immunity. Alternatively, reducing the duration of the touch phase—for example, a touch phase of 180µs is generally effective—can significantly limit active pen applications. This is because the touch phase is too short to support the touch phase duration requirements of mainstream active pens, which typically require a touch phase of approximately 400µs. Therefore, existing improvements cannot meet the touch display requirements of high-refresh-rate in-cell touch panels.

[0192] In the shift register 10 provided in the embodiment of the present application, the voltage at the first node PU can maintain a constant level during the touch phase, allowing the shift register 10 to output a clock signal normally, avoiding the problem of insufficient charging of the corresponding pixel row. This can improve the horizontal stripes of the display panel and enhance the image quality of the display panel, especially the image quality of high-refresh-rate embedded touch panels such as in-cell touch display panels. In addition, although the structure of the shift register 10 provided in the embodiment of the present application includes more components, the process flow remains unchanged, and the number of masks is not increased, so the cost remains unchanged. Therefore, the shift register 10 provided in the embodiment of the present application, while maintaining the original process and cost, effectively solves the problem of the voltage drop of the first node PU after the pit by eliminating the leakage path of the first node PU, avoiding the abnormal display problem of embedded touch panels caused by the excessively long touch phase. It is suitable for products such as mobile terminals (Mobile), NBs, and portable computers (Tablet PCs, TPCs).

[0193] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0194] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0195] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0196] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0197] The shift register, gate drive circuit and display device provided by the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A shift register, characterized in that: The shift register includes: an input circuit, a first control circuit, and an output circuit; The input circuit is connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal of the input signal line; The first control circuit is electrically connected to the first node and the first power signal line respectively, and is configured to disconnect the first power signal line from the first node during a touch control phase; The output circuit is electrically connected to the first node, the clock signal line, and the output signal line, respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.

2. The shift register according to claim 1, wherein: The first control circuit includes a reset module and a pull-down module; The reset module is electrically connected to the reset signal line, the first node, and the first power signal line, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the reset signal of the reset signal line; The pull-down module is electrically connected to the second node, the first node, and the first power signal line respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second node.

3. The shift register according to claim 2, wherein: The reset module includes a first transistor; The control electrode of the first transistor is electrically connected to the first sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the first sub-signal line; The first sub-signal line is a signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register, and the target register is located at the next stage of the shift register.

4. The shift register according to claim 2, wherein: The reset module includes a second transistor; The control electrode of the second transistor is electrically connected to the second sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the second sub-signal line.

5. The shift register according to claim 2, wherein: The second node includes a first pull-down node and a second pull-down node, and the pull-down module includes a first pull-down unit and a second pull-down unit; The first pull-down unit is electrically connected to the first pull-down node, the first node, and the first power signal line, respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the first pull-down node; The second pull-down unit is electrically connected to the second pull-down node, the first node, and the first power signal line, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second pull-down node.

6. The shift register according to claim 5, wherein: The first pull-down unit includes a third transistor; The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.

7. The shift register according to claim 5, wherein: The second pull-down unit includes a fourth transistor; The fourth transistor has a control electrode electrically connected to the second pull-down node, a first electrode electrically connected to the first node, and a second electrode electrically connected to the first power signal line.

8. The shift register according to any one of claims 1 to 7, wherein: The shift register further includes a first noise reduction circuit; The first noise reduction circuit is electrically connected to the first power signal line, the second node, and the second power signal line, respectively, and is configured to write the second power signal of the second power signal line into the second node under the control of the first power signal during the touch phase.

9. The shift register according to claim 8, wherein: The second node includes a first pull-down node and a second pull-down node, and the first noise reduction circuit includes a first noise reduction module and a second noise reduction module; The first noise reduction module is electrically connected to the first power signal line, the first pull-down node, and the second power signal line, respectively, and is configured to write the second power signal into the first pull-down node under the control of the first power signal during the touch phase; The second noise reduction module is electrically connected to the first power signal line, the second pull-down node, and the second power signal line, respectively, and is configured to write the second power signal into the second pull-down node under the control of the first power signal during the touch phase.

10. The shift register according to claim 9, wherein: The first noise reduction module includes a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the first pull-down node, and the second electrode is electrically connected to the second power signal line.

11. The shift register according to claim 9, wherein: The second noise reduction module includes a sixth transistor; The control electrode of the sixth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the second pull-down node, and the second electrode is electrically connected to the second power signal line.

12. The shift register according to any one of claims 1 to 7, wherein: The shift register further includes a second noise reduction circuit; The second noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output signal line, respectively, and is configured to write the second power signal of the second power signal line into the output signal line under the control of the first power signal during the touch stage.

13. The shift register according to claim 12, wherein: The second noise reduction circuit includes a seventh transistor; The control electrode of the seventh transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output signal line, and the second electrode is electrically connected to the second power signal line.

14. The shift register according to any one of claims 1 to 7, wherein: The shift register further includes an output control circuit and a third noise reduction circuit; The output control circuit is electrically connected to the first node, the clock signal line, and the output control line, respectively, and is configured to write the clock signal into the output control line under the control of the voltage of the first node; The third noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output control line, respectively, and is configured to write the second power signal of the second power signal line into the output control line under the control of the first power signal during the touch phase.

15. The shift register according to claim 14, wherein: The third noise reduction circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output control line, and the second electrode is electrically connected to the second power signal line.

16. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of cascaded shift registers according to any one of claims 1 to 15.

17. A display device, characterized in that: The display device includes the gate driving circuit according to claim 16.

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