Shift register unit, gate drive circuit and display device

Abstract

The utility model provides a shift register unit, a gate drive circuit and a display device, and belongs to the technical field of display. In the shift register unit, the register circuit can transmit signals with different potentials to the control node in different time periods under the control of the input signal, the clock signal and other signals, so that the transmission circuit and the output circuit can transmit signals with different potentials to the control node under the potential control of the control node. And signals with different potentials are output through the connected output ends in different time periods. Therefore, the shift register unit can be a mixed circuit of the P-type transistor and the N-type transistor, the overall circuit structure is simple, and the output reliability is good.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, and a display device. Background Art

[0002] A gate drive circuit is a circuit used to transmit gate drive signals to multiple rows of pixels in a display panel, driving them to emit light. Furthermore, with the advancement of display technology and the need for narrow bezel designs, gate drive on array (GOA) technology is often used to integrate the gate drive circuit onto the display panel. Accordingly, the gate drive circuit is also referred to as a GOA circuit.

[0003] Currently, a GOA circuit typically includes multiple cascaded shift register units (also known as GOA cells), which are connected one-to-one to multiple rows of pixels and are used to output gate drive signals to the multiple rows of pixels row by row to drive them to emit light. However, the current GOA cell structure is relatively complex. Utility Model Content

[0004] A shift register unit, a gate drive circuit, and a display device are provided to solve the problem of a relatively complex GOA unit structure in related technologies. The technical solution is as follows:

[0005] In one aspect, a shift register unit is provided, comprising:

[0006] a register circuit, connected to the input terminal, the first clock terminal, the second clock terminal, the first power terminal, the second power terminal, and the control node, respectively, and configured to control the connection and disconnection between the first power terminal and the control node, and the connection and disconnection between the second power terminal and the control node in response to an input signal provided by the input terminal, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal, and the first power terminal and the second power terminal are connected to the control node in different time periods;

[0007] a transmission circuit, connected to the control node, the third clock terminal, the third power terminal, and the cascade output terminal, respectively, and configured to control the connection and disconnection between the third clock terminal and the cascade output terminal, and the connection and disconnection between the third power terminal and the cascade output terminal, in response to the potential of the control node, so as to output a cascade signal to other shift register units of the cascade via the cascade output terminal, and the third clock terminal and the third power terminal are respectively connected to the cascade output terminal in different time periods;

[0008] The output circuit is respectively connected to the control node, the fourth clock terminal, the fourth power supply terminal and the scan output terminal, and is used to control the on-off connection between the fourth clock terminal and the scan output terminal, and to control the on-off connection between the fourth power supply terminal and the scan output terminal in response to the potential of the control node, so as to output a scan signal to the pixels in the display panel through the scan output terminal, and the fourth clock terminal and the fourth power supply terminal are respectively connected to the scan output terminal in different time periods.

[0009] Optionally, the register circuit includes:

[0010] a first register subcircuit, connected to the input terminal, the first clock terminal, the first power terminal, the second power terminal, the first intermediate node, the second intermediate node, and the third intermediate node, respectively, and configured to control the connection and disconnection between the first power terminal and the first intermediate node, and the connection and disconnection between the first power terminal and the second intermediate node, in response to the input signal, and control the connection and disconnection between the second power terminal and the third intermediate node, in response to the first clock signal;

[0011] The second register sub-circuit is respectively connected to the input end, the first clock end, the second clock end, the first intermediate node, the second intermediate node, the third intermediate node and the control node, and is used to control the connection and disconnection of the first intermediate node and the control node in response to the first clock signal, control the connection and disconnection of the second intermediate node and the control node in response to the second clock signal, and control the connection and disconnection of the third intermediate node and the control node in response to the input signal.

[0012] Optionally, the first register sub-circuit includes: a first transistor, a second transistor, and a third transistor; and the first transistor and the second transistor are type I transistors, and the third transistor is a type II transistor;

[0013] The gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first intermediate node;

[0014] The gate of the second transistor is connected to the input terminal, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the second intermediate node;

[0015] A gate of the third transistor is connected to the first clock terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is connected to the third intermediate node.

[0016] Optionally, the second register sub-circuit includes: a fourth transistor, a fifth transistor, and a sixth transistor; and the fifth transistor is a type I transistor, and the fourth transistor and the sixth transistor are type II transistors;

[0017] The gate of the fourth transistor is connected to the first clock terminal, the first electrode of the fourth transistor is connected to the first intermediate node, and the second electrode of the fourth transistor is connected to the control node;

[0018] The gate of the fifth transistor is connected to the second clock terminal, the first electrode of the fifth transistor is connected to the second intermediate node, and the second electrode of the fifth transistor is connected to the control node;

[0019] A gate of the sixth transistor is connected to the input terminal, a first electrode of the sixth transistor is connected to the third intermediate node, and a second electrode of the sixth transistor is connected to the control node.

[0020] Optionally, the transmission circuit includes: a seventh transistor and an eighth transistor; and the seventh transistor is a type I transistor, and the eighth transistor is a type II transistor;

[0021] The gate of the seventh transistor is connected to the control node, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the cascade output terminal;

[0022] A gate of the eighth transistor is connected to the control node, a first electrode of the eighth transistor is connected to the third clock terminal, and a second electrode of the eighth transistor is connected to the cascade output terminal.

[0023] Optionally, the output circuit includes: a ninth transistor and a tenth transistor; and the ninth transistor is a type I transistor, and the tenth transistor is a type II transistor;

[0024] The gate of the ninth transistor is connected to the control node, the first electrode of the ninth transistor is connected to the fourth power supply terminal, and the second electrode of the ninth transistor is connected to the scan output terminal;

[0025] A gate of the tenth transistor is connected to the control node, a first electrode of the tenth transistor is connected to the fourth clock terminal, and a second electrode of the tenth transistor is connected to the scan output terminal.

[0026] Optionally, the shift register unit further includes:

[0027] A signal enhancement circuit is connected between the output circuit and the scan output terminal, and is also connected to the fifth power supply terminal and the sixth power supply terminal respectively, and is used to enhance the scan signal output by the output circuit based on the fifth power supply signal provided by the fifth power supply terminal and the sixth power supply signal provided by the sixth power supply terminal, and then transmit it to the scan output terminal.

[0028] Optionally, the signal enhancement circuit comprises: an even number of inverters connected in cascade;

[0029] Each of the inverters includes an eleventh transistor and a twelfth transistor connected in series between the fifth power supply terminal and the sixth power supply terminal; and the eleventh transistor is a type I transistor, and the twelfth transistor is a type II transistor.

[0030] Optionally, among the even number of inverters, the potential of the fifth power supply signal provided by the fifth power supply terminal connected to the last inverter is greater than the potential of the fifth power supply signal provided by the fifth power supply terminals connected to other inverters except the last inverter, and the potential of the sixth power supply signal provided by the sixth power supply terminal connected to the last inverter is greater than or equal to the potential of the sixth power supply signal provided by the sixth power supply terminals connected to other inverters, and the output terminal of the last inverter is directly connected to the scan output terminal.

[0031] Optionally, the third power supply terminal, the fourth power supply terminal and the fifth power supply terminal connected to the other inverter are all shared with the first power supply terminal;

[0032] And / or, the sixth power supply terminal connected to the other inverter is shared with the second power supply terminal;

[0033] And / or, the third clock end is shared with the first clock end.

[0034] Optionally, in the shift register unit, the first-type transistor is an N-type transistor, and the second-type transistor is a P-type transistor.

[0035] Optionally, the shift register unit further includes: a capacitor connected between the second power supply terminal and the control node.

[0036] In another aspect, a gate drive circuit is provided, comprising: a plurality of cascaded shift register units as described in the above aspect, wherein a cascade output terminal of each stage of the shift register unit is connected to an input terminal of the shift register unit of another stage of the cascade;

[0037] Furthermore, the plurality of cascaded shift register units include a plurality of groups of shift register units, and each group of shift register units includes at least two cascaded shift register units;

[0038] The at least two shift register units are alternately connected to the at least two fourth clock terminals in a one-to-one correspondence, and the multiple groups of shift register units share the at least two fourth clock terminals.

[0039] Optionally, each group of the shift register units includes two shift register units, and the two shift register units are alternately connected to the two fourth clock terminals in a one-to-one correspondence.

[0040] In another aspect, a display device is provided, comprising: a display panel, and the gate driving circuit as described in the above another aspect; the display panel comprises a plurality of pixels;

[0041] The gate driving circuit is connected to the plurality of pixels via a scan output terminal and is used for transmitting a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0042] In summary, the beneficial effects brought about by the technical solution provided by this application may at least include:

[0043] Provided are a shift register unit, a gate drive circuit, and a display device. Because the register circuit in the shift register unit can transmit signals of varying potentials to a control node at different time periods under the control of signals such as an input signal and a clock signal, both the transmission circuit and the output circuit can output signals of varying potentials via their connected output terminals at different time periods under the control of the potential of the control node. Therefore, the shift register unit can be a hybrid circuit of P-type and N-type transistors, resulting in a simple overall circuit structure and good output reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 1 is a structural diagram of a shift register unit provided in an embodiment of the present application;

[0046] Figure 2 is a structural diagram of another shift register unit provided in an embodiment of the present application;

[0047] Figure 3 This is a structural diagram of another shift register unit provided in an embodiment of the present application;

[0048] Figure 41 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present application;

[0049] Figure 5 This is a schematic flow chart of a driving method for a shift register unit provided in an embodiment of the present application;

[0050] Figure 6 is a timing diagram of a shift register unit provided by an embodiment of the present disclosure;

[0051] Figure 7 This is a timing simulation diagram of a shift register unit provided by an embodiment of the present disclosure;

[0052] Figure 8 is a timing simulation diagram of another shift register unit provided by an embodiment of the present disclosure;

[0053] Figure 9 is a structural diagram of a gate drive circuit provided by an embodiment of the present disclosure;

[0054] Figure 10 This is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0056] It should be noted that the transistors used in the embodiments of the present application can all be thin film transistors (TFTs) or field effect transistors (FETs), or other devices with similar characteristics. For example, the field effect transistors can be metal-oxide-semiconductor (MOS) field effect transistors, also known as MOS transistors. Furthermore, based on their function in the circuit, the transistors used in the embodiments of the present application are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control electrode, which can also be referred to as the gate, the signal input end is the source electrode, and the signal output end is the drain electrode. Furthermore, the switching transistors used in the embodiments of the present application can include either a P-type transistor or an N-type transistor, wherein a P-type transistor is turned on when the gate potential is low and is turned off when the gate potential is high; an N-type transistor is turned on when the gate potential is high and is turned off when the gate potential is low. Furthermore, the multiple signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the full text.

[0057] Figure 1 Schematic diagram of the structure of a shift register unit provided in an embodiment of the present application. Figure 1 As shown, the shift register unit includes: a register circuit 01, a transmission circuit 02 and an output circuit 03.

[0058] Register circuit 01 is connected to input terminal IN, first clock terminal CK1, second clock terminal CK2, first power terminal V1, second power terminal V2, and control node PU, respectively. Register circuit 01 is configured to control the connection between first power terminal V1 and control node PU, and the connection between second power terminal V2 and control node PU, in response to an input signal provided by input terminal IN, a first clock signal provided by first clock terminal CK1, and a second clock signal provided by second clock terminal CK2. Furthermore, register circuit 01 is configured to control the connection between first power terminal V1 and control node PU, and control the connection between second power terminal V2 and control node PU, with the first power terminal V1 and the second power terminal V2 being connected to control node PU at different time periods.

[0059] For example, the register circuit 01 can control the first power terminal V1 to be conductive with the control node PU and the second power terminal V2 to be disconnected from the control node PU when the potential of the input signal provided by the input terminal IN is a first potential, the potential of the first clock signal provided by the first clock terminal CK1 is a second potential, and the potential of the second clock signal provided by the second clock terminal CK2 is a first potential, so that the first power signal provided by the first power terminal V1 can be transmitted to the control node PU. The register circuit 01 can also control the first power terminal V1 to be disconnected from the control node PU and control the second power terminal V2 to be conductive with the control node PU when the potential of the input signal provided by the input terminal IN is a second potential, the potential of the first clock signal provided by the first clock terminal CK1 is a second potential, and the potential of the second clock signal provided by the second clock terminal CK2 is a first potential, so that the second power signal provided by the second power terminal V2 can be transmitted to the control node PU. In this way, under the control of the register circuit 01, the first power terminal V1 and the second power terminal V2 can be conductive with the control node PU in different time periods. Of course, this is only a schematic illustration of part of the operating principle of the register circuit 01.

[0060] Optionally, in an embodiment of the present application, the first potential can be a high potential relative to the second potential. That is, the first potential can be a high potential, and the second potential can be a low potential. Furthermore, as previously described, for an N-type transistor, the high potential can be an effective potential, and the low potential can be an ineffective potential. For a P-type transistor, the low potential can be an effective potential, and the high potential can be an ineffective potential. Of course, in some other embodiments, the first potential can also be a low potential relative to the second potential. On this basis, combined with the working principle of the above-mentioned register circuit 01, it can be seen that the register circuit 01 includes both N-type transistors and P-type transistors.

[0061] Optionally, the first clock signal provided by the first clock terminal CK1 and the second clock signal provided by the second clock terminal CK2 may be inverted clock signals. That is, during the same time period, the potential of the first clock signal and the potential of the second clock signal may be exactly opposite. For example, when the potential of the first clock signal is a first potential (e.g., a high potential), the potential of the second clock signal may be a second potential (e.g., a low potential); conversely, when the potential of the first clock signal is a low potential, the potential of the second clock signal may be a high potential.

[0062] Optionally, the potential of the first power signal provided by the first power terminal V1 can be a low potential, and the potential of the second power signal provided by the second power terminal V2 can be a high potential. Accordingly, in the embodiment of the present application, the first power terminal V1 can also be referred to as the pull-down power terminal VGL, and the second power terminal V2 can be referred to as the pull-up power terminal VGH. In this way, based on the control circuit 01 controlling the first power terminal V1 and the second power terminal V2 to be connected to the control node PU in different time periods, the potential of the control node PU can be controlled to be a high potential and a low potential in different time periods. Of course, in some other embodiments, the potential of the first power signal provided by the first power terminal V1 can also be a high potential, and the potential of the second power signal provided by the second power terminal V2 can also be a low potential.

[0063] The transmission circuit 02 is connected to the control node PU, the third clock terminal CK3, the third power terminal V3, and the cascade output terminal Next, respectively. Furthermore, the transmission circuit 02 is configured to control the connection and disconnection between the third clock terminal CK3 and the cascade output terminal Next, and the connection and disconnection between the third power terminal V3 and the cascade output terminal Next, in response to the potential of the control node PU, so as to output a cascade signal to the shift register units of other stages of the cascade via the cascade output terminal Next. Furthermore, the third clock terminal CK3 and the third power terminal V3 are connected to the cascade output terminal Next during different time periods.

[0064] For example, when the potential of the control node PU is at a first potential, the transmission circuit 02 can control the third power supply terminal V3 to be connected to the cascade output terminal Next, and control the third clock terminal CK3 to be disconnected from the cascade output terminal Next, so that the third power supply signal provided by the third power supply terminal V3 can be transmitted to the other stages of the cascaded shift register unit via the cascade output terminal Next. That is, the cascade signal transmitted to the other stages of the shift register unit at this time is the third power supply signal. When the potential of the control node PU is at a second potential, the transmission circuit 02 can control the third power supply terminal V3 to be disconnected from the cascade output terminal Next, and control the third clock terminal CK3 to be connected to the cascade output terminal Next, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the other stages of the cascaded shift register unit via the cascade output terminal Next. That is, the cascade signal transmitted to the other stages of the shift register unit at this time is the third clock signal. In this way, under the control of the transmission circuit 02, the third clock terminal CK3 and the third power supply terminal V3 can be connected to the cascade output terminal Next in different time periods. On this basis, it can also be determined that the transmission circuit 02 can also include both N-type transistors and P-type transistors.

[0065] Optionally, the third clock signal provided by the third clock terminal CK3 and the first clock signal provided by the first clock terminal CK1 can be in-phase clock signals. That is, during the same time period, the potential of the third clock signal and the potential of the first clock signal can be exactly the same. For example, when the potential of the first clock signal is the first potential (e.g., a high potential), the potential of the third clock signal can also be the first potential (e.g., a high potential); conversely, when the potential of the first clock signal is a low potential, the potential of the third clock signal can also be a low potential. Based on this, in some embodiments, the third clock terminal CK3 and the first clock terminal CK1 can be shared.

[0066] Optionally, the potential of the third power signal provided by the third power terminal V3 may be a low potential. Accordingly, in the embodiment of the present application, the third power terminal V3 may also be referred to as a pull-down power terminal VGL.

[0067] Optionally, the cascade output terminal Next can be used to connect to the input terminal IN of other shift register units in the cascade to provide input signals to the input terminals IN of other stages of shift register units, that is, the cascade signal outputted via the cascade output terminal Next can be used as an input signal. Figure 1 As shown, its input terminal IN can be connected to a separate start signal terminal GSTV to receive a start signal provided by the start signal terminal GSTV, and output a cascade signal via the cascade output terminal Next in response to the start signal to achieve cascade driving.

[0068] Alternatively, the cascade output terminal Next of the i-th stage shift register unit may be connected to the input terminal IN of the i+L-th stage shift register unit. Here, 1≤i≤ML, M is the total number of cascaded multi-stage shift register units, M≥1, and L is a positive integer greater than or equal to 1. For example, L may be 1, that is, every two adjacent stages of shift register units may be cascaded.

[0069] The output circuit 03 is connected to the control node PU, the fourth clock terminal CK4, the fourth power terminal V4, and the scan output terminal Gate, respectively. Furthermore, the output circuit 03 is configured to control the connection and disconnection between the fourth clock terminal CK4 and the scan output terminal Gate, and the connection and disconnection between the fourth power terminal V4 and the scan output terminal Gate, in response to the potential of the control node PU, so as to output scan signals to pixels in the display panel via the scan output terminal Gate. Furthermore, the fourth clock terminal CK4 and the fourth power terminal V4 are connected to the scan output terminal Gate during different time periods.

[0070] For example, when the potential of the control node PU is at a first potential, the output circuit 03 can control the fourth power terminal V4 to be connected to the scan output terminal Gate, and control the fourth clock terminal CK4 to be disconnected from the scan output terminal Gate, so that the fourth power signal provided by the fourth power terminal V4 can be transmitted to the pixel via the scan output terminal Gate. In other words, the scan signal transmitted to the pixel at this time is the fourth power signal. When the potential of the control node PU is at a second potential, the output circuit 03 can control the fourth power terminal V4 to be disconnected from the scan output terminal Gate, and control the fourth clock terminal CK4 to be connected to the scan output terminal Gate, so that the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the pixel via the scan output terminal Gate. In other words, the scan signal transmitted to the pixel at this time is the fourth clock signal. In this way, a single pulse output can be achieved. In other words, under the control of the output circuit 03, the fourth clock terminal CK4 and the fourth power terminal V4 can be connected to the scan output terminal Gate in different time periods. Based on this, it can also be determined that the output circuit 03 can also include both N-type transistors and P-type transistors.

[0071] Optionally, the fourth clock terminal CK4 and other clock terminals may be independent of each other. At least two stages of cascaded shift register units may be connected to different fourth clock terminals CK4.

[0072] Optionally, the potential of the fourth power signal provided by the fourth power terminal V4 may be a low potential. Accordingly, in the embodiment of the present application, the fourth power terminal V4 may also be referred to as a pull-down power terminal VGL.

[0073] Optionally, the scan output terminal Gate may be used to connect to a pixel circuit in a pixel to control the pixel circuit to drive a light-emitting element in the pixel to emit light based on a received scan signal.

[0074] For example, a display panel may include multiple rows and columns of pixels. The scan output terminal Gate of each shift register unit can be connected to the data write transistor included in the pixel circuit of a row of pixels via a gate line to transmit a gate drive signal to the data write transistor. The data write transistor, in response to the gate drive signal, controls the data line to transmit a data signal to the drive transistor in the pixel circuit, so that the drive transistor drives the light-emitting element to emit light based on the data signal. The multi-stage shift register unit can transmit the gate drive signal to the multiple rows of pixels row by row, scanning the pixels row by row to emit light, thereby implementing scan drive. Accordingly, the gate drive signal is also referred to as a scan signal. Moreover, because the potential of the fourth power signal provided by the fourth power terminal V4 is low, the scan signal here can refer to the gate drive signal transmitted to the P-type data write transistor. In other words, the shift register unit can implement a P-gate shift output and is a P-gate shift register unit. Of course, the signal types here are only for illustrative purposes. For example, in some embodiments, the signal output via the scan output terminal Gate can also be the light control signal EM transmitted to the light control transistor in the pixel circuit. This is not limited in the present embodiment.

[0075] Based on the above example records, it can be seen that the shift register unit provided in the embodiment of the present application includes both P-type transistors and N-type transistors. On the basis that the P-type transistor is PMOS and the N-type transistor is NMOS, the shift register unit can be a hybrid CMOS architecture. In addition, in the shift register unit provided in the embodiment of the present application, because different circuits respond to the potential of the same control node PU, the required input signal is output to the other level shift register units through the cascade output terminal Next, and the required scan signal is output to the pixel circuit through the scan output terminal Gate, that is, the cascade drive and the scan drive can be controlled independently of each other, and the two will not affect each other. Therefore, it can be seen that compared with the embodiment in which the cascade signal and the scan signal are output through the same output terminal, the cascade function can be avoided from being affected by a large load, and the load resistance is improved, so that the output flexibility and reliability of the shift register unit are better, that is, the shift register unit can reliably realize the cascade drive while also reliably driving the pixel to emit light.

[0076] In summary, embodiments of the present application provide a shift register unit. Because the register circuit in this shift register unit can transmit signals of different potentials to a control node at different time periods under the control of signals such as an input signal and a clock signal, both the transmission circuit and the output circuit can output signals of different potentials via the connected output terminals at different time periods under the control of the potential of the control node. Therefore, it can be seen that this shift register unit can be a hybrid circuit of P-type and N-type transistors, with a simple overall circuit structure and good output reliability.

[0077] Optionally, Figure 2 Schematic diagram of another shift register unit provided in an embodiment of the present application. Figure 2 As shown, the register circuit 01 may include: a first register sub-circuit 011 and a second register sub-circuit 012 .

[0078] The first register sub-circuit 011 can be connected to the input terminal IN, the first clock terminal CK1, the first power terminal V1, the second power terminal V2, the first intermediate node N1, the second intermediate node N2, and the third intermediate node N3, respectively. Furthermore, the first register sub-circuit 011 can be configured to control the connection between the first power terminal V1 and the first intermediate node N1, the connection between the first power terminal V1 and the second intermediate node N2, and the connection between the second power terminal V2 and the third intermediate node N3 in response to an input signal.

[0079] For example, when the potential of the input signal is at a first potential, the first register sub-circuit 011 can control the first power terminal V1 to be conductively connected to the first intermediate node N1, and to the second intermediate node N2, so that the low-potential first power signal provided by the first power terminal V1 can be transmitted to the first intermediate node N1 and the second intermediate node N2, that is, the potential of the first intermediate node N1 and the second intermediate node N2 can be controlled to be low. Furthermore, when the potential of the input signal is at a second potential, the first register sub-circuit 011 can control the first power terminal V1 to be disconnected from the first intermediate node N1, and to be disconnected from the second intermediate node N2. Furthermore, when the potential of the first clock signal is at a first potential, the first register sub-circuit 011 can control the first power terminal V1 to be disconnected from the first intermediate node N1, and to be conductively connected to the second intermediate node N3, so that the high-potential second power signal provided by the second power terminal V2 can be transmitted to the third intermediate node N3, that is, the potential of the third intermediate node N3 can be controlled to be high. On this basis, it can also be determined that the first register sub-circuit 011 may also include both N-type transistors and P-type transistors.

[0080] The second register sub-circuit 012 can be connected to the input terminal IN, the first clock terminal CK1, the second clock terminal CK2, the first intermediate node N1, the second intermediate node N2, the third intermediate node N3, and the control node PU, respectively. Furthermore, the second register sub-circuit 012 can be configured to control the connection between the first intermediate node N1 and the control node PU in response to the first clock signal, control the connection between the second intermediate node N2 and the control node PU in response to the second clock signal, and control the connection between the third intermediate node N3 and the control node PU in response to the input signal.

[0081] For example, the second register sub-circuit 012 can control the first intermediate node N1 to be disconnected from the control node PU when the potential of the first clock signal is the first potential; and can control the first intermediate node N1 to be conductive with the control node PU when the potential of the first clock signal is the second potential, so that the low-potential first power signal transmitted to the first node N1 can be further transmitted to the control node PU, that is, the potential of the control node PU can be controlled to be low. The second register sub-circuit 012 can control the second intermediate node N2 to be conductive with the control node PU when the potential of the second clock signal is the first potential, so that the low-potential first power signal transmitted to the second intermediate node N2 can be further transmitted to the control node PU, that is, the potential of the control node PU can be controlled to be low; and can control the second intermediate node N2 to be disconnected from the control node PU when the potential of the second clock signal is the second potential. The second register sub-circuit 012 can disconnect the third intermediate node N3 from the control node PU when the input signal has a first potential. Furthermore, when the input signal has a second potential, the second register sub-circuit 012 can connect the third intermediate node N3 to the control node PU, allowing the high-potential second power signal transmitted to the third intermediate node N3 to be further transmitted to the control node PU. This allows the control node PU to maintain a high potential. Based on this, it can also be determined that the second register sub-circuit 012 may include both N-type and P-type transistors.

[0082] In this way, with the mutual cooperation of the first register sub-circuit 011 and the second register sub-circuit 012, the first power supply terminal V1 and the second power supply terminal V2 can be connected to the control node PU in different time periods respectively, thereby outputting a low-potential first power supply signal and a high-potential second power supply signal to the control node PU in different time periods to control the potential of the control node PU to be low or high.

[0083] Optionally, Figure 3 This is a structural diagram of another shift register unit provided in an embodiment of the present application. Figure 3 As shown, the shift register unit may further include: a signal enhancement circuit 04.

[0084] The signal enhancement circuit 04 can be connected between the output circuit 03 and the scan output terminal Gate, and can also be connected to the fifth power terminal V5 and the sixth power terminal V6, respectively. Furthermore, the signal enhancement circuit 04 can be used to enhance the scan signal output by the output circuit 03 based on a fifth power signal provided by the fifth power terminal V5 and a sixth power signal provided by the sixth power terminal V6, and then transmit the enhanced signal to the scan output terminal Gate.

[0085] For example, the enhancement process can be an inversion process. Of course, in order to make the potential after the enhancement process the same as the potential before the enhancement, the signal enhancement circuit 04 can perform an even number of inversion processes on the scan signal output by the output circuit 03 and transmit it to the scan output terminal Gate. In this way, the driving capability of the shift register unit can be enhanced, so that the shift register unit can reliably output the required scan signal to the pixel circuit via the scan output terminal Gate, thereby enabling the pixel circuit to reliably drive the light-emitting element to emit light. Of course, in some other embodiments, the signal enhancement circuit 04 can also be connected between the transmission circuit 02 and the cascade output terminal Next in the same way to achieve the same enhancement effect and improve the cascade drive capability of the shift register unit.

[0086] Optionally, Figure 3 The connection point between the signal boost circuit 04 and the output circuit 03 is identified as node PD. Based on this, it can be understood that the output circuit 03 can control the connection between the fourth power supply terminal V4 and the fourth clock terminal CK4 and the node PD in response to the potential of the control node PU, that is, it can control the potential of the node PD. The signal boost circuit 04 then boosts the potential of the node PD and outputs it through the scan output terminal Gate.

[0087] Optionally, the potential of the fifth power signal provided by the fifth power terminal V5 can be a low potential, and the potential of the sixth power signal provided by the sixth power terminal V6 can be a high potential. Accordingly, in the embodiment of the present application, the fifth power terminal V5 can also be referred to as the pull-down power terminal VGL, and the sixth power terminal V6 can be referred to as the pull-up power terminal VGH.

[0088] Optionally, Figure 4 Schematic diagram of the circuit structure of a shift register unit provided in an embodiment of the present application. Figure 4 As shown, the first register sub-circuit 011 may include: a first transistor T1, a second transistor T2, and a third transistor T3. In addition, the first transistor T1 and the second transistor T2 may be type I transistors, and the third transistor T3 may be a type II transistor.

[0089] The gate of the first transistor T1 may be connected to the input terminal IN, the first electrode of the first transistor T1 may be connected to the first power supply terminal V1, and the second electrode of the first transistor T1 may be connected to the first intermediate node N1.

[0090] A gate of the second transistor T2 may be connected to the input terminal IN, a first electrode of the second transistor T2 may be connected to the first power supply terminal V1 , and a second electrode of the second transistor T2 may be connected to the second intermediate node N2 .

[0091] A gate of the third transistor T3 may be connected to the first clock terminal CK1 , a first electrode of the third transistor T3 may be connected to the second power supply terminal V2 , and a second electrode of the third transistor T3 may be connected to the third intermediate node N3 .

[0092] Optionally, in combination with the foregoing description, one of the type-1 transistor and the type-2 transistor here can be N-type and the other can be P-type. That is, one transistor can be an N-type transistor (e.g., NMOS) and the other transistor can be a P-type transistor (e.g., PMOS). For example, on the basis that the first potential is a high potential and the second potential is a low potential, the type-1 transistor can be an N-type transistor and the type-2 transistor can be an N-type transistor.

[0093] Optionally, continue to refer to Figure 4 It can be seen that the second register sub-circuit 012 may include: a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. In addition, the fifth transistor T5 may be a type I transistor (e.g., an N-type transistor), and the fourth transistor T4 and the sixth transistor T6 may be type II transistors (e.g., P-type transistors).

[0094] The gate of the fourth transistor T4 may be connected to the first clock terminal CK1 , the first electrode of the fourth transistor T4 may be connected to the first intermediate node N1 , and the second electrode of the fourth transistor T4 may be connected to the control node PU.

[0095] A gate of the fifth transistor T5 may be connected to the second clock terminal CK2 , a first electrode of the fifth transistor T5 may be connected to the second intermediate node N2 , and a second electrode of the fifth transistor T5 may be connected to the control node PU.

[0096] A gate of the sixth transistor T6 may be connected to the input terminal IN, a first electrode of the sixth transistor T6 may be connected to the third intermediate node N3, and a second electrode of the sixth transistor T6 may be connected to the control node PU.

[0097] Optionally, continue to refer to Figure 4It can be seen that the transmission circuit 02 may include: a seventh transistor T7 and an eighth transistor T8. In addition, the seventh transistor T7 may be a type I transistor (eg, an N-type transistor), and the eighth transistor T8 may be a type II transistor (eg, a P-type transistor).

[0098] The gate of the seventh transistor T7 may be connected to the control node PU, the first electrode of the seventh transistor T7 may be connected to the third power supply terminal V3, and the second electrode of the seventh transistor T7 may be connected to the cascade output terminal Next.

[0099] A gate of the eighth transistor T8 may be connected to the control node PU, a first electrode of the eighth transistor T8 may be connected to the third clock terminal CK3 , and a second electrode of the eighth transistor T8 may be connected to the cascade output terminal Next.

[0100] Optionally, continue to refer to Figure 4 It can be seen that the output circuit 03 may include a ninth transistor T9 and a tenth transistor T10. In addition, the ninth transistor T9 may be a type I transistor (eg, an N-type transistor), and the tenth transistor T10 may be a type II transistor (eg, a P-type transistor).

[0101] The gate of the ninth transistor T9 may be connected to the control node PU, the first electrode of the ninth transistor T9 may be connected to the fourth power supply terminal V4, and the second electrode of the ninth transistor T9 may be connected to the scan output terminal Gate.

[0102] A gate of the tenth transistor T10 may be connected to the control node PU, a first electrode of the tenth transistor T10 may be connected to the fourth clock terminal CK4, and a second electrode of the tenth transistor T10 may be connected to the scan output terminal Gate.

[0103] It is understandable that, combined with Figure 3 and Figure 4 On the basis that the shift register unit further includes a signal enhancement circuit 04 , the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 included in the output circuit 03 can be connected to the node PD to be indirectly connected to the scan output terminal Gate through the signal enhancement circuit 04 .

[0104] Optionally, continue to refer to Figure 4 It can be seen that the signal enhancement circuit 04 may include: an even number of cascaded inverters F. That is, the signal enhancement circuit 04 may perform an even number of enhancement processes on the scan signal output by the output circuit 03 and then transmit the enhanced signal to the scan output terminal Gate.

[0105] Each inverter F may include an eleventh transistor T11 and a twelfth transistor T12 connected in series between the fifth power supply terminal V5 and the sixth power supply terminal V6. Furthermore, the eleventh transistor T11 may be a first-type transistor (e.g., an N-type transistor), and the twelfth transistor T12 may be a second-type transistor (e.g., a P-type transistor).

[0106] Example, reference Figure 4 The signal enhancement circuit 04 shown includes two inverters F. That is, the signal enhancement circuit 04 can perform two enhancements on the scan signal output by the output circuit 03 before transmitting it to the scan output terminal Gate. An inverter F can also be called a group of buffer transistors.

[0107] To distinguish, Figure 4 In the figure, the inverter F directly connected to the output circuit 03 (i.e., the node PD) of the two inverters F is identified as F-1, and the eleventh transistor T11 and the twelfth transistor T12 included in the inverter F-1 are identified as T11-1 and T12-1, respectively; and the inverter F directly connected to the scan output terminal Gate is identified as F-2, and the eleventh transistor T11 and the twelfth transistor T12 included in the inverter F-2 are identified as T11-2 and T12-2, respectively.

[0108] In which, the gate of the eleventh transistor T11-1 and the gate of the twelfth transistor T12-1 can both be connected to the output circuit O3 (i.e., node PD), the first electrode of the eleventh transistor T11-1 can be connected to the fifth power supply terminal V5, the first electrode of the twelfth transistor T12-1 can be connected to the sixth power supply terminal V6, the second electrode of the eleventh transistor T11-1 and the second electrode of the twelfth transistor T12-1 can both be connected to the gate of the eleventh transistor T11-2 and the gate of the twelfth transistor T12-2, the first electrode of the eleventh transistor T11-2 can be connected to the fifth power supply terminal V5, the first electrode of the twelfth transistor T12-2 can be connected to the sixth power supply terminal V6, and the second electrode of the eleventh transistor T11-2 and the second electrode of the twelfth transistor T12-2 can both be connected to the scan output terminal Gate.

[0109] Optionally, continue to refer to Figure 4 It can also be seen that the shift register unit described in the embodiment of the present application may further include: a capacitor C1 connected between the second power supply terminal V2 and the control node PU. The capacitor C1 can be used to maintain the potential of the control node PU to ensure good potential stability of the control node PU.

[0110] Optionally, continue combining Figure 4It can be seen that among the even-numbered inverters F, the potential of the fifth power signal provided by the fifth power terminal V5 connected to the last inverter F can be less than or equal to the potential of the fifth power signal provided by the fifth power terminal V5 connected to the other inverters F except the last inverter F, and the potential of the sixth power signal provided by the sixth power terminal V6 connected to the last inverter F can be greater than or equal to the potential of the sixth power signal provided by the sixth power terminal V6 connected to the other inverters F. It can be understood that the potential magnitude relationship here can refer to the magnitude relationship of the absolute value of the potential. For example, the low potential of the power signal provided by VGL2 and the low potential of the power signal provided by VGL1 can differ by about 2V. For example, the low potential Vgl2 of the power signal provided by VGL2 can be -5V, and the low potential Vgl1 of the power signal provided by VGL1 can be -7V.

[0111] Among them, the output end of the last inverter F is directly connected to the scan output end Gate. That is, for Figure 4 For example, the last inverter F can be inverter F-2. Figure 4 In the figure, the fifth power supply terminal V5 connected to the last inverter F (e.g., F-2) is identified as VGL2, and the fifth power supply terminal V5 connected to the other inverters F (e.g., F-1) except the last inverter F is identified as VGL1. Similarly, the sixth power supply terminal V6 connected to the last inverter F-2 is identified as VGH2, and the sixth power supply terminal V6 connected to the other inverters F-1 is identified as VGH1. That is, in the embodiment of the present application, dual VGH (i.e., VGH1 & VGH2) and dual VGL (i.e., VGL1 & VGL2) can be used to power the shift register unit. In this way, by flexibly adjusting Vgl2 and / or Vgl1, Vgl1-Vgl2 can be made as small as possible from the threshold voltage Vth of the eleventh transistor T11 (e.g., T11-2) in the last inverter F, thereby ensuring that the eleventh transistor T11-2 can be fully turned off when it needs to be turned off. The effect of using dual VGH is similar and will not be repeated. Of course, in some other embodiments, a single VGH and a single VGL power supply may also be used, that is, any inverter F in the shift register unit is connected to the same VGH (eg, VGH1 ) and VGL (eg, VGL1 ).

[0112] Optionally, combined Figures 1 to 4It can also be seen that the third power supply terminal V3, the fourth power supply terminal V4, and the fifth power supply terminal V5 connected to other inverters F (such as F-1) can all be shared with the first power supply terminal V1. For example, they are all the same pull-down power supply terminal VGL1. And / or, the sixth power supply terminal V6 connected to other inverters F (such as F-1) can be shared with the second power supply terminal V2. For example, they are all the same pull-up power supply terminal VGH1. And / or, the third clock terminal CK3 can be shared with the first clock terminal CK1. For example, they are all the same clock terminal CK. The second clock terminal CK2 can be CKN. The fourth clock terminal can be CB1. In this way, the number of signal terminals required to be set can be simplified, wiring is facilitated, and costs are saved.

[0113] It can be understood that, based on the use of single VGH and single VGL power supply, the fifth power supply terminal V5 connected to the last inverter (e.g., F-2) can also be shared with the first power supply terminal V1, and the sixth power supply terminal V6 connected to the last inverter (e.g., F-2) can also be shared with the second power supply terminal V2.

[0114] Combined with the previous records, we can see that Figure 4 The shift register unit shown may include three parts: a register circuit 01 (also called a shift register structure), a transmission circuit 02 (also called a transmission unit), and an output circuit 03 and a signal enhancement circuit 04 (also called an output unit).

[0115] The shift register structure includes three N-type transistors and four N-type transistors, forming a hybrid P-type + N-type TFT architecture. Combined with clock signals provided by the first clock terminal CK1 and the second clock terminal CK2 (e.g., CK and CKN), the input signal provided by the input terminal IN can be shifted and latched, registering it at the control node PU. Capacitor C1 ensures latch stability. This shift register structure is a key architecture, demonstrating its simplicity and the small number of components required.

[0116] The transmission unit includes 1 P-type transistor and 1 N-type transistor, which is similar to a group of diodes or a buffer tube. The transmission function of this group of diodes can be used to shift and latch the signal to the control node PU, and further transmit it to the input terminal IN of other stages of the cascaded shift register unit by controlling the output of the third clock terminal CK3 (e.g., CK) to achieve cascade output.

[0117] The output unit includes multiple sets of P-type transistors and N-type transistors connected in series (i.e., multiple sets of diodes). It can shift-latch the signal at the control node PU and output the signal at the node PD by coordinating with the output of the fourth clock terminal CK4 (e.g., CB1). The signal at the node PD then controls the subsequent multiple stages of diodes to achieve the scanning output of the scanning signal.

[0118] That is, Figure 4 The shift register unit shown includes 7 P-type transistors, 7 N-type transistors and 1 capacitor, and belongs to the shift register unit of 14T1C architecture. Of course, it is not limited to the design of 14T1C architecture. For example, in some other embodiments, the signal enhancement circuit 04 may not be provided. Based on the connection of the two-stage cascaded shift register unit to different fourth clock terminals CK4, it can be considered that Figure 4 The structure shown is driven by four groups of clock signals (CK, CKN, CB1 and CB2), CB1 is the fourth clock terminal CK4 connected to the current stage shift register unit, and CB2 is the fourth clock terminal CK4 connected to the next stage shift register unit cascaded with the current stage shift register unit. Figure 4 The structure shown requires two sets of power supply signals (VGH1 / VGL1 & VGH2 / VGL2) to drive. And, Figure 4 In the illustrated structure, the cascade output terminal Next and the scan output terminal Gate are independent of each other. The required input signal can be transmitted to the input terminal IN of the shift register unit in the other stages of the cascade via the cascade output terminal Next, thereby achieving cascade drive. Furthermore, the required drive signal can be transmitted to the pixel circuit via the scan output terminal Gate, thereby achieving scan drive. The shift register unit provided in the embodiments of the present application has a simple structure and relatively rich functionality.

[0119] In summary, embodiments of the present application provide a shift register unit. Because the register circuit in this shift register unit can transmit signals of different potentials to a control node at different time periods under the control of signals such as an input signal and a clock signal, both the transmission circuit and the output circuit can output signals of different potentials via the connected output terminals at different time periods under the control of the potential of the control node. Therefore, it can be seen that this shift register unit can be a hybrid circuit of P-type and N-type transistors, with a simple overall circuit structure and good output reliability.

[0120] The embodiment of the present application also provides a driving method of a shift register unit, which is used to drive the shift register unit described in the above embodiment. Figure 5 As shown, the method includes:

[0121] Step 501, in the first stage, the register circuit controls the first power supply terminal to be connected to the control node and controls the second power supply terminal to be disconnected from the control node in response to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal and the second clock signal provided by the second clock terminal. The transmission circuit controls the third power supply terminal to be connected to the cascade output terminal and controls the third clock terminal to be disconnected from the cascade output terminal in response to the potential of the control node. The output circuit controls the fourth power supply terminal to be connected to the scan output terminal and controls the fourth clock terminal to be disconnected from the scan output terminal in response to the potential of the control node, so that the third power supply signal provided by the third power supply terminal is transmitted to the cascade output terminal, and the fourth power supply signal provided by the fourth power supply terminal is transmitted to the scan output terminal.

[0122] Step 502, the second stage, the register circuit controls the first power supply terminal to be disconnected from the control node and controls the second power supply terminal to be connected to the control node in response to the input signal, the first clock signal and the second clock signal, the transmission circuit controls the third power supply terminal to be disconnected from the cascade output terminal and controls the third clock terminal to be connected to the cascade output terminal in response to the potential of the control node, the output circuit controls the fourth power supply terminal to be disconnected from the scan output terminal and controls the fourth clock terminal to be connected to the scan output terminal in response to the potential of the control node, so that the third clock signal provided by the third clock terminal is transmitted to the cascade output terminal, and the fourth clock signal provided by the fourth clock terminal is transmitted to the scan output terminal.

[0123] Optionally, Figure 4 As an example, the structure shown in FIG. 1 is a structure in which the first potential is a high potential and the second potential is a low potential. Figure 6 shows a schematic diagram of the working timing of a shift register unit, Figure 7 The corresponding Figure 6 The simulation diagram of the working timing diagram is shown. Figure 6 and Figure 7 , the driving principle of the shift register unit is described as follows:

[0124] (1) In phase t1, the potential of the input signal provided by the input terminal IN (i.e., the start signal terminal GSTV) can be a high potential, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can be a low potential, and the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CKN) can be a high potential. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can all be controlled to be turned on, and the sixth transistor T6 can be controlled to be turned off. In this way, the first power supply terminal V1 (i.e., VGL1) can be connected to the first intermediate node N1, the first power supply terminal V1 can be connected to the second intermediate node N2, and the second power supply terminal V2 (i.e., VGH1) can be connected to the third intermediate node N3, and the first intermediate node N1 can be connected to the control node PU, the second intermediate node N2 can be connected to the control node PU, and the third intermediate node N3 can be disconnected from the control node PU. Furthermore, the low-potential first power signal provided by the first power terminal V1 can be first transmitted to the first intermediate node N1 and the second intermediate node N2 via the turned-on first transistor T1 and the turned-on second transistor T2, respectively, and then transmitted to the control node PU via the turned-on fourth transistor T4 and the turned-on fifth transistor T5. Furthermore, the high-potential second power signal provided by the second power terminal V2 can be transmitted only to the third intermediate node N3 via the turned-on third transistor T3, and not further to the control node PU. That is, in this phase t1, the potentials of the first intermediate node N1, the second intermediate node N2, and the control node PU can all be controlled to be low, and the potential of the third intermediate node N3 can be controlled to be high.

[0125] On this basis, the eighth transistor T8 and the tenth transistor T10 can be controlled to be turned on, and the seventh transistor T7 and the ninth transistor T9 can be controlled to be turned off. In this way, the third clock terminal CK3 (i.e., CK) can be turned on and the cascade output terminal Next, and the third power supply terminal V3 (i.e., VGL1) can be disconnected from the cascade output terminal Next; and the fourth clock terminal CK4 (i.e., CB1) can be turned on and the node PD can be disconnected, and the fourth power supply terminal V4 (i.e., VGL1) can be disconnected from the node PD. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the cascade output terminal Next via the turned-on eighth transistor T8, and the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the node PD via the turned-on tenth transistor T10. Moreover, in this stage t1, the potential of the third clock signal can be a low potential, and the potential of the fourth clock signal can be a low potential. Accordingly, it can be seen that in this stage t1, a low-level input signal can be transmitted to the input terminal IN of the other stage shift register unit via the cascade output terminal Next, and a low-level fourth clock signal can be first output to the node PD. After passing through the two inverters F-1 and F-2, the low-level fourth clock signal is subjected to signal amplification processing before being transmitted to the scan output terminal Gate. That is, in this stage t1, a low-level scan signal can be transmitted to the pixel via the scan output terminal Gate.

[0126] (2) In phase t2, the potential of the input signal provided by the input terminal IN (i.e., the start signal terminal GSTV) can be a low potential, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can be a high potential, and the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CKN) can be a low potential. Accordingly, the sixth transistor T6 can be controlled to be turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be controlled to be turned off. In this way, the first power supply terminal V1 (i.e., VGL1) can be disconnected from the first intermediate node N1, the first power supply terminal V1 can be disconnected from the second intermediate node N2, and the second power supply terminal V2 (i.e., VGH1) can be disconnected from the third intermediate node N3, and the first intermediate node N1 can be disconnected from the control node PU, the second intermediate node N2 can be disconnected from the control node PU, and the third intermediate node N3 can be connected to the control node PU. Furthermore, the potentials of the first intermediate node N1, the second intermediate node N2, and the control node PU can all be maintained at the low potentials of the previous stage (i.e., stage t1), and the low potential signal of the control node PU is transmitted to the third intermediate node N3 via the turned-on sixth transistor T6, causing the potential of the third intermediate node N3 to become low. That is, in stage t2, the potentials of the first intermediate node N1, the second intermediate node N2, the third intermediate node N3, and the control node PU can all be controlled to be low potentials.

[0127] On this basis, at the same stage t1, the eighth transistor T8 and the tenth transistor T10 can still be controlled to be turned on, and the seventh transistor T7 and the ninth transistor T9 can still be controlled to be turned off. In this way, the third clock terminal CK3 (i.e., CK) can still be turned on and the cascade output terminal Next, and the third power supply terminal V3 (i.e., VGL1) can still be disconnected from the cascade output terminal Next; and the fourth clock terminal CK4 (i.e., CB1) can be turned on and the node PD can be disconnected, and the fourth power supply terminal V4 (i.e., VGL1) can be disconnected from the node PD. Furthermore, the third clock signal provided by the third clock terminal CK3 can still be transmitted to the cascade output terminal Next via the turned-on eighth transistor T8, and the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the node PD via the turned-on tenth transistor T10. Moreover, at this stage t2, the potential of the third clock signal can be a high potential, and the potential of the fourth clock signal can be a high potential. Accordingly, it can be seen that in this stage t2, a high-potential input signal can be transmitted to the input terminal IN of the other stage shift register unit via the cascade output terminal Next, and a high-potential fourth clock signal can be first output to the node PD. After passing through the two inverters F-1 and F-2, the high-potential fourth clock signal is subjected to signal amplification processing before being transmitted to the scan output terminal Gate. That is, in this stage t2, a high-potential scan signal can be transmitted to the pixel via the scan output terminal Gate.

[0128] (3) In phase t3, the potential of the input signal provided by the input terminal IN (i.e., the start signal terminal GSTV) can be a low potential, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can be a low potential, and the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CKN) can be a high potential. Accordingly, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can all be controlled to be turned on, and the first transistor T1 and the second transistor T2 can all be controlled to be turned off. In this way, the first power supply terminal V1 (i.e., VGL1) can be disconnected from the first intermediate node N1, the first power supply terminal V1 can be disconnected from the second intermediate node N2, and the second power supply terminal V2 (i.e., VGH1) can be connected to the third intermediate node N3, and the first intermediate node N1 can be connected to the control node PU, the second intermediate node N2 can be connected to the control node PU, and the third intermediate node N3 can be connected to the control node PU. Furthermore, the high-potential second power supply signal provided by the second power supply terminal V2 can be first transmitted to the third intermediate node N3 via the turned-on third transistor T3, and then transmitted to the control node PU via the turned-on sixth transistor T6. Furthermore, the high-potential signal transmitted to the control node PU can be transmitted to the first intermediate node N1 and the second intermediate node N2 via the turned-on fourth transistor T4 and fifth transistor T5, respectively. That is, at this stage t3, the potentials of the first intermediate node N1, the second intermediate node N2, the third intermediate node N3, and the control node PU can all be controlled to be high.

[0129] On this basis, the seventh transistor T7 and the ninth transistor T9 can be controlled to be turned on, and the eighth transistor T8 and the tenth transistor T10 can be controlled to be turned off. In this way, the third power supply terminal V3 (i.e., VGL1) can be connected to the cascade output terminal Next, and the third clock terminal CK3 (i.e., CK) can be disconnected from the cascade output terminal Next; and the fourth power supply terminal V4 (i.e., VGL1) can be connected to the node PD, and the fourth clock terminal CK4 (i.e., CB1) can be disconnected from the node PD. Furthermore, the low-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the cascade output terminal Next via the turned-on seventh transistor T7, and the low-potential fourth power supply signal provided by the fourth power supply terminal V4 can be transmitted to the node PD via the turned-on ninth transistor T9. Accordingly, it can be seen that at this stage t3, a low-potential input signal can be transmitted to the input terminal IN of the other stage shift register unit via the cascade output terminal Next. A low-potential fourth power signal can first be output to the node PD. After passing through the two inverters F-1 and F-2, the low-potential fourth power signal undergoes signal amplification processing before being transmitted to the scan output terminal Gate. That is, at this stage t3, a low-potential scan signal can be transmitted to the pixel via the scan output terminal Gate. In this way, a single signal scan output is completed.

[0130] And, it can be understood that the working process of the two inverters F-1 and F-2 is as follows:

[0131] Based on the output of a low-level signal to node PD, the twelfth transistor T12-1 in inverter F-1 can be controlled to turn on, and the eleventh transistor T11-1 in inverter F-1 can be controlled to turn off. This allows the sixth power supply terminal V6 (i.e., VGH1) to be conductive with inverter F-2, while the fifth power supply terminal V5 (i.e., VGL1) is disconnected from inverter F-2. Furthermore, the high-level sixth power supply signal provided by the sixth power supply terminal V6 can be transmitted to inverter F-2 via the turned-on twelfth transistor T12-1. This further allows the eleventh transistor T11-2 in inverter F-2 to be controlled to turn on, and the twelfth transistor T12-2 in inverter F-2 to be controlled to turn off. Accordingly, the fifth power supply terminal V5 (i.e., VGL2) can be conductive with the scan output terminal Gate, while the sixth power supply terminal V6 (i.e., VGH2) is disconnected from the scan output terminal Gate. Furthermore, the low-potential fifth power signal provided by the fifth power terminal V5 can be transmitted to the scan output terminal Gate through the turned-on eleventh transistor T11-2, thereby achieving signal enhancement processing on the low-potential signal transmitted to the node PD and then outputting it through the scan output terminal Gate.

[0132] Based on the high-level signal output to node PD, the eleventh transistor T11-1 in inverter F-1 can be controlled to turn on, and the twelfth transistor T12-1 in inverter F-1 can be controlled to turn off. This allows the fifth power supply terminal V5 (i.e., VGL1) to be conductive with inverter F-2, while the sixth power supply terminal V6 (i.e., VGH1) is disconnected from inverter F-2. Furthermore, the low-level fifth power supply signal provided by the fifth power supply terminal V5 can be transmitted to inverter F-2 via the turned-on eleventh transistor T11-1. This further allows the twelfth transistor T12-2 in inverter F-2 to be controlled to turn on, and the eleventh transistor T11-2 in inverter F-2 to be controlled to turn off. Accordingly, the sixth power supply terminal V6 (i.e., VGH2) can be conductive with the scan output terminal Gate, while the fifth power supply terminal V5 (i.e., VGL2) is disconnected from the scan output terminal Gate. Furthermore, the high-potential sixth power signal provided by the sixth power terminal V6 can be transmitted to the scan output terminal Gate through the turned-on twelfth transistor T12-2, thereby achieving signal enhancement processing on the high-potential signal transmitted to the node PD and then outputting it through the scan output terminal Gate.

[0133] Optionally, in Figure 6 and Figure 7 On the basis, taking the case where two adjacent stages of shift register units are cascaded and the two stages of shift register units in the cascade are respectively connected to different fourth clock terminals CK4 (ie, CB1 and CB2), Figure 8 The working timing simulation timing diagram of the multi-stage shift register unit is also schematically shown. Figure 8 It can be seen that the clock signals provided by CB1 and CB2 can determine the pulse width of the scan signal output through the scan output terminal Gate and the gap between the output pulses. Figure 8 The cascade output terminals of the cascaded 4-stage shift register units are marked as Next <1> 、Next <2> 、Next <3> and Next <4> , mark the scan output terminal Gate as Gate <1> 、Gate <2> 、Gate <3> and Gate <4> .

[0134] It is understandable that since the driving method of the shift register unit can have substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the driving method of the shift register unit will not be repeatedly described here for the purpose of brevity.

[0135] The embodiment of the present application also provides a gate drive circuit. Figure 9As shown, the gate drive circuit includes: a plurality of cascaded shift register units (also called GOA units) as described in the above embodiments, wherein the cascade output terminal Next of each stage of the shift register unit is connected to the input terminal IN of the other stages of the cascaded shift register unit. The scan output terminal Gate of each stage of the shift register unit can be connected to the pixel.

[0136] Figure 9 The diagram schematically shows four cascaded GOA units, which are labeled as Gate GOA1, Gate GOA2, Gate GOA3 and Gate GOA4 respectively.

[0137] Furthermore, the plurality of cascaded shift register units may include a plurality of groups of shift register units, and each group of shift register units may include at least two cascaded shift register units.

[0138] At least two shift register units may be alternately connected to at least two fourth clock terminals CK4 in a one-to-one correspondence, and multiple groups of shift register units may share at least two fourth clock terminals CK4.

[0139] That is, multiple GOA units can be divided into multiple groups. Each group of GOA units can share at least two fourth clock terminals CK4, and at least two shift register units in each group of GOA units can be alternately connected to the at least two fourth clock terminals CK4. In other words, a multi-phase clock can be used to drive the gate drive circuit.

[0140] Optionally, refer to Figure 9 , each group of shift register units shown therein includes two shift register units, and the two shift register units are connected alternately in sequence with two fourth clock terminals CK4 (respectively identified as CB1 and CB2) in a one-to-one correspondence. For example, Gate GOA1 and Gate GOA2 can be divided into a group of shift register units, and Gate GOA1 can be connected to CB1, and Gate GOA2 can be connected to CB2; Gate GOA3 and Gate GOA4 can be divided into a group of shift register units, and Gate GOA3 can be connected to CB1, and Gate GOA4 can be connected to CB2, and so on. This belongs to the use of a two-phase clock. In addition, refer to Figure 9 It can also be seen that each GOA unit can also be connected to the clock terminals CK and CKN respectively, and the clock signals provided by CK and CKN can be used by the shift register architecture and transmission unit in each GOA unit. In other words, each GOA unit can access three sets of clock terminals.

[0141] It is understandable that, since the gate driving circuit can have substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the gate driving circuit will not be repeatedly described here for the purpose of brevity.

[0142] The present application also provides a display device. Figure 10 As shown, the display device includes: a display panel 100 and a gate driving circuit 000 as described in the above embodiment.

[0143] The display panel 100 includes a plurality of pixels ( Figure 10 Not shown). Figure 9 The gate driving circuit 000 is connected to a plurality of pixels via a scan output terminal Gate and is used to transmit a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0144] Optionally, the display device described in the embodiments of the present application may be any product or component with a display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, or a liquid crystal display device. Furthermore, the display device may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, and e-books.

[0145] It is understandable that, since the display device can have substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0146] It should be noted that the terms used in the examples of this application are only used to explain the examples and are not intended to limit this application. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this application should have the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0147] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0148] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0149] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0150] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection.

[0151] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0152] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A shift register unit, characterized in that: The shift register unit includes: a register circuit, connected to the input terminal, the first clock terminal, the second clock terminal, the first power terminal, the second power terminal, and the control node, respectively, and configured to control the connection and disconnection between the first power terminal and the control node, and the connection and disconnection between the second power terminal and the control node in response to an input signal provided by the input terminal, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal, and the first power terminal and the second power terminal are connected to the control node in different time periods; a transmission circuit, connected to the control node, the third clock terminal, the third power terminal, and the cascade output terminal, respectively, and configured to control the connection and disconnection between the third clock terminal and the cascade output terminal, and the connection and disconnection between the third power terminal and the cascade output terminal, in response to the potential of the control node, so as to output a cascade signal to other shift register units of the cascade via the cascade output terminal, and the third clock terminal and the third power terminal are respectively connected to the cascade output terminal in different time periods; The output circuit is respectively connected to the control node, the fourth clock terminal, the fourth power supply terminal and the scan output terminal, and is used to control the on-off connection between the fourth clock terminal and the scan output terminal, and to control the on-off connection between the fourth power supply terminal and the scan output terminal in response to the potential of the control node, so as to output a scan signal to the pixels in the display panel through the scan output terminal, and the fourth clock terminal and the fourth power supply terminal are respectively connected to the scan output terminal in different time periods.

2. The shift register unit according to claim 1, wherein: The register circuit comprises: a first register subcircuit, connected to the input terminal, the first clock terminal, the first power terminal, the second power terminal, the first intermediate node, the second intermediate node, and the third intermediate node, respectively, and configured to control the connection and disconnection between the first power terminal and the first intermediate node, and the connection and disconnection between the first power terminal and the second intermediate node, in response to the input signal, and control the connection and disconnection between the second power terminal and the third intermediate node, in response to the first clock signal; The second register sub-circuit is respectively connected to the input end, the first clock end, the second clock end, the first intermediate node, the second intermediate node, the third intermediate node and the control node, and is used to control the connection and disconnection of the first intermediate node and the control node in response to the first clock signal, control the connection and disconnection of the second intermediate node and the control node in response to the second clock signal, and control the connection and disconnection of the third intermediate node and the control node in response to the input signal.

3. The shift register unit according to claim 2, wherein: The first register sub-circuit includes: a first transistor, a second transistor and a third transistor; and the first transistor and the second transistor are type I transistors, and the third transistor is a type II transistor; The gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first intermediate node; The gate of the second transistor is connected to the input terminal, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the second intermediate node; A gate of the third transistor is connected to the first clock terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is connected to the third intermediate node.

4. The shift register unit according to claim 2, wherein: The second register sub-circuit includes: a fourth transistor, a fifth transistor and a sixth transistor; and the fifth transistor is a type I transistor, and the fourth transistor and the sixth transistor are type II transistors; The gate of the fourth transistor is connected to the first clock terminal, the first electrode of the fourth transistor is connected to the first intermediate node, and the second electrode of the fourth transistor is connected to the control node; The gate of the fifth transistor is connected to the second clock terminal, the first electrode of the fifth transistor is connected to the second intermediate node, and the second electrode of the fifth transistor is connected to the control node; A gate of the sixth transistor is connected to the input terminal, a first electrode of the sixth transistor is connected to the third intermediate node, and a second electrode of the sixth transistor is connected to the control node.

5. The shift register unit according to any one of claims 1 to 4, characterized in that: The transmission circuit includes: a seventh transistor and an eighth transistor; and the seventh transistor is a type I transistor, and the eighth transistor is a type II transistor; The gate of the seventh transistor is connected to the control node, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the cascade output terminal; A gate of the eighth transistor is connected to the control node, a first electrode of the eighth transistor is connected to the third clock terminal, and a second electrode of the eighth transistor is connected to the cascade output terminal.

6. The shift register unit according to any one of claims 1 to 4, characterized in that: The output circuit includes: a ninth transistor and a tenth transistor; and the ninth transistor is a type I transistor, and the tenth transistor is a type II transistor; The gate of the ninth transistor is connected to the control node, the first electrode of the ninth transistor is connected to the fourth power supply terminal, and the second electrode of the ninth transistor is connected to the scan output terminal; A gate of the tenth transistor is connected to the control node, a first electrode of the tenth transistor is connected to the fourth clock terminal, and a second electrode of the tenth transistor is connected to the scan output terminal.

7. The shift register unit according to any one of claims 1 to 4, characterized in that: The shift register unit further includes: A signal enhancement circuit is connected between the output circuit and the scan output terminal, and is also connected to the fifth power supply terminal and the sixth power supply terminal respectively, and is used to enhance the scan signal output by the output circuit based on the fifth power supply signal provided by the fifth power supply terminal and the sixth power supply signal provided by the sixth power supply terminal, and then transmit it to the scan output terminal.

8. The shift register unit according to claim 7, wherein: The signal enhancement circuit includes: an even number of cascaded inverters; Each of the inverters includes an eleventh transistor and a twelfth transistor connected in series between the fifth power supply terminal and the sixth power supply terminal; and the eleventh transistor is a type I transistor, and the twelfth transistor is a type II transistor.

9. The shift register unit according to claim 8, wherein: Among the even-numbered inverters, the potential of the fifth power supply signal provided by the fifth power supply terminal connected to the last inverter is less than or equal to the potential of the fifth power supply signal provided by the fifth power supply terminals connected to the other inverters except the last inverter, and the potential of the sixth power supply signal provided by the sixth power supply terminal connected to the last inverter is greater than or equal to the potential of the sixth power supply signal provided by the sixth power supply terminals connected to the other inverters, and the output terminal of the last inverter is directly connected to the scan output terminal.

10. The shift register unit according to claim 9, wherein: The third power supply terminal, the fourth power supply terminal and the fifth power supply terminal connected to the other inverters are all shared with the first power supply terminal; And / or, the sixth power supply terminal connected to the other inverter is shared with the second power supply terminal; And / or, the third clock end is shared with the first clock end.

11. The shift register unit according to claim 3 or 4, characterized in that: In the shift register unit, the first-type transistor is an N-type transistor, and the second-type transistor is a P-type transistor.

12. The shift register unit according to any one of claims 1 to 4, characterized in that: The shift register unit further includes a capacitor connected between the second power supply terminal and the control node.

13. A gate drive circuit, characterized in that: The gate drive circuit comprises: a plurality of cascaded shift register units according to any one of claims 1 to 12, wherein the cascade output end of each stage of the shift register unit is connected to the input end of the shift register unit of the other stages of the cascade; Furthermore, the plurality of cascaded shift register units include a plurality of groups of shift register units, and each group of shift register units includes at least two cascaded shift register units; The at least two shift register units are alternately connected to the at least two fourth clock terminals in a one-to-one correspondence, and the multiple groups of shift register units share the at least two fourth clock terminals.

14. The gate driving circuit according to claim 13, wherein: Each group of the shift register units includes two shift register units, and the two shift register units are connected to the two fourth clock terminals in a one-to-one correspondence and alternately in sequence.

15. A display device, characterized in that: The display device comprises: a display panel, and the gate driving circuit according to claim 13 or 14; the display panel comprises a plurality of pixels; The gate driving circuit is connected to the plurality of pixels via a scan output terminal and is used for transmitting a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

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