Array substrate and display panel

Abstract

The utility model provides an array substrate and a display panel, and belongs to the technical field of liquid crystal displays. The thin film transistor is positioned on one side of the substrate; the flat layer is located on the side, away from the substrate, of the thin film transistor; the passivation layer is located on the side, away from the substrate, of the flat layer; the pixel electrode layer is located on the side, away from the substrate, of the passivation layer; the via hole penetrates through the flat layer and the passivation layer, and the pixel electrode layer is connected with the thin film transistor through the via hole; wherein the orifice of the via hole comprises at least one chamfer; and / or at least one channel communicated with the via hole is arranged at the orifice of the via hole.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate and a display panel. BACKGROUND

[0002] A TFT-LCD (Thin Film Transistor Liquid Crystal Display) includes two substrates arranged oppositely, and liquid crystal between the two substrates; in actual use, it is necessary to coat alignment liquid PI (Polyimide), which forms an alignment layer that can align the liquid crystal. However, the current liquid crystal display has the problem of poor display, for example, there is display mura at low gray scale. SUMMARY

[0003] Based on the background technology, the present disclosure provides an array substrate and a display panel.

[0004] In a first aspect, an array substrate is provided, comprising a plurality of sub-pixel regions, the sub-pixel region comprising:

[0005] a substrate;

[0006] a thin film transistor located on one side of the substrate;

[0007] a planar layer located on a side of the thin film transistor away from the substrate;

[0008] a passivation layer located on a side of the planar layer away from the substrate;

[0009] a pixel electrode layer located on a side of the passivation layer away from the substrate;

[0010] a via hole penetrating through the planar layer and the passivation layer, the pixel electrode layer being connected to the thin film transistor through the via hole;

[0011] wherein the aperture of the via hole comprises at least one chamfer; and / or the aperture of the via hole comprises at least one channel communicating with the via hole.

[0012] In an exemplary embodiment, the aperture comprises the channel, and the sub-pixel region further comprises:

[0013] a first metal layer located on the hole wall of the via hole, the pixel electrode layer being connected to the thin film transistor through the first metal layer;

[0014] The first metal layer includes a first portion located in the channel and a second portion located in the via, and a projection of the second portion on the substrate covers a projection of the via on the substrate.

[0015] In an exemplary embodiment, the first portion is located on a side of the passivation layer facing away from the substrate.

[0016] In an exemplary embodiment, in a thickness direction of the substrate, a distance between a surface of a portion of a channel bottom of the channel facing away from the substrate and the substrate is smaller than a maximum distance between a surface of the second portion facing away from the substrate and the substrate.

[0017] In an exemplary embodiment, the passivation layer includes a vertical distance between a surface of a portion of the channel region facing away from the substrate and the substrate that is greater than a vertical distance between a surface of a portion of the passivation layer not located in the channel region facing away from the substrate and the substrate.

[0018] In an exemplary embodiment, a distance between a surface of a portion of a channel bottom of the channel facing away from the substrate and the substrate is equal to a maximum distance between a surface of the second portion facing away from the substrate and the substrate; and the sub-pixel region further includes:

[0019] an insulating layer located on a side of the passivation layer facing away from the substrate, a projection of the insulating layer on the substrate does not overlap a projection of the aperture on the substrate;

[0020] The channel is located in the insulating layer, and the channel exposes the first portion or the channel and the first portion include the insulating layer therebetween.

[0021] In an exemplary embodiment, in a thickness direction of the substrate, a distance between a surface of the first portion facing away from the substrate and the substrate is smaller than a maximum distance between a surface of the second portion facing away from the substrate and the substrate.

[0022] The first portion is located on a side of the planarization layer facing away from the substrate.

[0023] In an exemplary embodiment, a vertical distance between a surface of a portion of the planarization layer located in the channel region facing away from the substrate and the substrate is greater than a vertical distance between a surface of a portion of the planarization layer not located in the channel region facing away from the substrate and the substrate.

[0024] In an exemplary embodiment, the sub-pixel region comprises the trench, the pixel electrode layer comprises a plurality of pixel electrode strips, and the gap between the trench and the pixel electrode strips is communicated.

[0025] In an exemplary embodiment, the sub-pixel region further comprises:

[0026] a second metal layer located on a side of the passivation layer facing away from the substrate;

[0027] wherein a footprint of the second metal layer on the substrate is located outside a footprint of the aperture on the substrate and does not overlap with a footprint of the trench bottom on the substrate.

[0028] In an exemplary embodiment, a distance between a surface of the first portion on a side facing away from the substrate and the substrate is smaller than a maximum distance between a surface of the second portion on a side facing away from the substrate and the substrate, and the first metal layer is located on a side of the second metal layer facing away from the substrate.

[0029] In an exemplary embodiment, the array substrate further comprises a plurality of data lines, and the data lines are connected to thin film transistors in the sub-pixel regions in a same column;

[0030] wherein a footprint of the second metal layer on the substrate does not overlap with a footprint of the data lines on the substrate.

[0031] In an exemplary embodiment, a plurality of the trenches are included, and the plurality of the trenches are located on different sides of the via with respect to the pixel electrode layer.

[0032] In an exemplary embodiment, a footprint of the trench on the substrate comprises at least one of a zigzag shape, a straight line shape, and a curved shape.

[0033] In an exemplary embodiment, a height of a trench bottom of the trench on a side close to the aperture is smaller than a height of the trench bottom on a side away from the aperture.

[0034] wherein the height is a distance between the trench bottom and the substrate in a thickness direction of the substrate.

[0035] In an exemplary embodiment, the via comprises:

[0036] a first sub-aperture located on the planar layer;

[0037] a second sub-aperture located on the passivation layer, and a footprint of the second sub-aperture on the substrate falls within a footprint of the first sub-aperture on the substrate.

[0038] wherein at least a footprint of the second sub-aperture on the substrate comprises a plurality of rounded corners.

[0039] In a second aspect, a display panel is provided, comprising a first substrate and a second substrate arranged oppositely, and liquid crystal located between the first substrate and the second substrate, the first substrate being configured as the array substrate of any one of the first aspect.

[0040] The array substrate and the display panel described above are provided with at least one chamfer at the aperture of the via in the sub-pixel region, so that the provision of the chamfer is conducive to the inflow of PI into the via, so that the liquid substance such as PI at the aperture can flow into the via, avoiding the accumulation of PI liquid at the aperture, thereby ensuring the film thickness uniformity of the PI layer. On the other hand, the aperture of the via is provided with a channel communicating with the via, so that the PI can be guided through the channel, thereby guiding the PI liquid into the via, and the PI liquid can also be prevented from accumulating at the aperture, thereby ensuring the film thickness uniformity of the PI layer.

[0041] The array substrate and the display panel described above are provided with at least one chamfer at the aperture of the via in the sub-pixel region, so that the provision of the chamfer is conducive to the inflow of PI into the via, so that the liquid substance such as PI at the aperture can flow into the via, avoiding the accumulation of PI liquid at the aperture, thereby ensuring the film thickness uniformity of the PI layer. On the other hand, the aperture of the via is provided with a channel communicating with the via, so that the PI can be guided through the channel, thereby guiding the PI liquid into the via, and the PI liquid can also be prevented from accumulating at the aperture, thereby ensuring the film thickness uniformity of the PI layer.

[0042] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the present disclosure can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following will specifically describe the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art descriptions. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0044] Figure 1 A cross-sectional structure diagram of the aperture region of the display region AA in the related art is shown;

[0045] Figure 2 A plan view schematic diagram of the array substrate is shown;

[0046] Figure 3 A plan view schematic diagram of part of the sub-pixel region in the array substrate is shown;

[0047] Figure 4 A plan view schematic diagram of the second sub-via is shown; Figure 3 An enlarged schematic diagram of the AA1 region is shown;

[0048] Figure 5 A plan view schematic diagram of the second sub-via is shown;

[0049] Figure 6 An enlarged schematic view of the shape design of the via in the AA1 region in Figure 3

[0050] Figure 7 An enlarged schematic view of the AA3 region in Figure 6

[0051] Figures 8-12 A specific structural schematic view of the AA1 region in Figure 3

[0052] Figure 13 A planar schematic view of the channel is shown;

[0053] Figure 14 An enlarged schematic view of the channel design at the via in Figure 8

[0054] Figure 15a , Figure 16a , Figure 17a , Figure 18a , Figure 19a , Figure 20a , Figure 21a , Figure 22-23 are cross-sectional schematic views of several array substrates provided in the embodiments of the present disclosure at B-B of Figure 8 15b,

[0055] , Figure 16b , Figure 17b , Figure 18b , Figure 19b , Figure 20b , Figure 21b respectively correspond to 15a, Figure 16a , Figure 17a , Figure 18a , Figure 19a , Figure 20a , Figure 21a are cross-sectional schematic views of the channel in the X direction of Figure 8

[0056] Figures 24a-24c respectively show cross-sectional schematic views of three channels;

[0057] Figure 25 A cross-sectional structural schematic view of a display panel in the embodiments of the present disclosure is shown;

[0058] Figure 26 A cross-sectional structural schematic view of an array substrate in a display panel in the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0059] ​​​​​In order to make the above objectives, characteristics and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0060] In the present specification, "electrically connected" and "coupled" include a case where constituent elements are connected together through an element having some electrical effect. The element having some electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having some electrical effect include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0061] In the present specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0062] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as an open, inclusive meaning, i.e., "including, but not limited to".

[0063] The "same layer" in the embodiments of the present application refers to the relationship between a plurality of film layers formed by the same material after the same step (for example, one patterning process). The "same layer" here does not always mean that the thicknesses of the plurality of film layers are the same or that the heights of the plurality of film layers in a cross-sectional view are the same. The polygons in the present specification are not strictly in the sense that they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and there can be some small deformations due to tolerances.

[0064] In the embodiments of the present application, the source and the drain of the transistor are symmetrical, so the source and the drain can be interchangeable. In the embodiments of the present application, one of the source and the drain of the transistor can be referred to as a first electrode, and the other of the source and the drain can be referred to as a second electrode.

[0065] In the related art, there are inevitably a plurality of hole regions on the array substrate of the two substrates, which can be regarded as low-lying regions on the array substrate. Due to the influence of these low-lying regions, the liquid crystal display has the problem of display failure. Please refer to Figure 1 Figure 1 ​A cross-sectional structure diagram of the hole region of the display region AA in the related art is shown as Figure 1 As shown, the hole region includes: a substrate 100', a first metal layer 200' located on the side of the substrate 100' away from the substrate, a first passivation layer 300' located on the side of the first metal layer 200' away from the substrate, an organic layer 400' located on the side of the first passivation layer away from the substrate, a second passivation layer 500' located on the side of the organic layer away from the substrate, a second metal layer 600' located on the side of the second passivation layer away from the substrate, and a PI layer 700' located on the side of the second metal layer away from the substrate. When the alignment liquid is coated, due to the surface tension of the alignment liquid, the PI will gather around the hole region H, so that the thickness of the alignment layer PI formed around the hole region H is higher, resulting in PI mura on the screen at low gray scale (32 or 64 gray scale).

[0066] Therefore, the present disclosure proposes to provide a flow guide structure in the hole region of the display region AA, so as to guide the liquid around the hole, such as PI liquid, into the via through the flow guide structure, thereby avoiding the PI liquid from gathering at the hole, and improving the film thickness uniformity of the formed alignment layer. The flow guide structure can be configured as a chamfer at the hole of the via, or as a channel at the hole.

[0067] Next, an array substrate and a display panel provided by an embodiment of the present disclosure will be exemplarily described in combination with the drawings.

[0068] Referring to Figures 2 to 8 As shown, the array substrate provided by the present embodiment can include a substrate 10, and a display region AA and a non-display region NAA located on one side of the substrate 10.

[0069] The display region AA includes a plurality of sub-pixel regions, and each sub-pixel region includes a thin film transistor Q, a pixel electrode layer 102, and a via 11. The pixel electrode layer 102 is connected to the thin film transistor Q through the via 11.

[0070] Specifically, each sub-pixel region can include the following structure:

[0071] a substrate 10;

[0072] a thin film transistor Q located on one side of the substrate 10;

[0073] a planarization layer 70 located on the side of the thin film transistor Q away from the substrate 10;

[0074] a passivation layer 90 located on the side of the planarization layer 70 away from the substrate 10;

[0075] a pixel electrode layer 102 located on the side of the passivation layer 90 away from the substrate 10;

[0076] The via 11 penetrates the planar layer 70 and the passivation layer 90, and the pixel electrode layer 102 is connected to the thin film transistor Q through the via 11.

[0077] The aperture of the via 11 includes at least one chamfer, and / or the aperture of the via 11 includes at least one channel 114 in communication with the via 11, and the bottom of the channel 114 is located on any one of the planar layer 70, the passivation layer 90 and the pixel electrode layer 102.

[0078] The array substrate in the embodiment can be used as a driving substrate of a liquid crystal display, and a pixel driving circuit is arranged on the array substrate. Figure 2 As shown in Figure 2 A plan view of the array substrate is shown, which can include a display area AA and a non-display area NAA. The display area AA includes a plurality of sub-pixel areas, and the plurality of sub-pixel areas are arranged in an array. One sub-pixel area corresponds to one sub-pixel. A pixel driving circuit can be included in each sub-pixel area, and the pixel driving circuit can include a thin film transistor Q. Specifically, the display area AA can include a plurality of gate lines GL and a plurality of data lines DL. The area formed by the intersection of the plurality of gate lines GL and the plurality of data lines DL is the sub-pixel area. The gate line GL is used to provide a start signal to the thin film transistor Q to start the thin film transistor Q, and can be used to provide a stop signal to the thin film transistor Q to stop the thin film transistor Q. The data line DL is used to input a data voltage to the thin film transistor Q, which can be loaded into the pixel electrode 102 connected to the thin film transistor Q, thereby driving the liquid crystal in the liquid crystal display to deflect, and then displaying a picture.

[0079] In the embodiment, the array substrate can be an array substrate of an ADS (Advanced Super Dimension Switch) liquid crystal display. In this case, the sub-pixel area can further include a common electrode 81, and the common electrode 81 can be located between the planar layer 70 and the passivation layer 90. Alternatively, the array substrate can be an array substrate of a TN type liquid crystal display. In this case, the common electrode 81 is located on a color filter substrate arranged opposite to the array substrate, and the array substrate includes a pixel electrode 102.

[0080] In the embodiment, the flow guiding structure (chamfer and channel 114) at the via 11 is suitable for the above two array substrates.

[0081] As shown in Figure 6 A cross-sectional structure schematic diagram of an array substrate of an ADS / HADS (High Advanced Super Dimension Switch) liquid crystal display is shown, as shown in Figure 6As shown, in the sub-pixel area, in the normal direction of the substrate 10, it includes a thin film transistor Q, a planar layer 70, a common electrode 81 layer, a passivation layer 90 and a pixel electrode layer 102. Specifically, the thin film transistor Q may include a gate 20 located on one side of the substrate 10, a gate insulating layer (31, 32) located on the side of the gate 20 facing away from the substrate 10, a semiconductor layer 40 located on the side of the gate insulating layer (31, 32) facing away from the substrate 10, a source and drain layer located on the side of the semiconductor layer 40 facing away from the substrate 10, and an insulating layer 130 (31, 32) located on the side of the source and drain layer facing away from the substrate 10.

[0082] Among them, such as Figure 6 As shown, the gate insulating layer (31, 32) may include a first gate insulating layer 31 and a second gate insulating layer 32 located on the side of the first gate insulating layer 31 away from the substrate 10, the source and drain layer may include a source electrode 52 and a drain electrode 51, the source electrode 52 and the drain electrode 51 are both electrically connected to the semiconductor layer, and there is no overlap between the two; the gate insulating layer (31, 32) may include a first gate insulating layer 31 and a second gate insulating layer 32, the first gate insulating layer 31 may be an inorganic material, and the second gate insulating layer 32 may be an organic material, or the first gate insulating layer 31 may be an organic material, and the second gate insulating layer 32 may be an inorganic material.

[0083] Among them, the flat layer 70 and the passivation layer 90 can cover the entire surface of the substrate 10, that is, the flat layer 70 and the passivation layer 90 are present in both the display area AA and the non-display area NAA; specifically, the via hole 11 in each sub-pixel area can be located in the flat layer 70 and the passivation layer 90, and the via hole 11 passes through the flat layer 70 and the passivation layer 90, and the pixel electrode layer 102 is connected to the source electrode 52 or the drain electrode 51 in the source and drain layer through the via hole 11. It should be noted that the pixel electrode layer 102 may include a plurality of pixel electrodes 102, thereby, a planar electric field can be formed between the plurality of pixel electrodes 102.

[0084] Among them, such as Figure 6 As shown, a first interlayer dielectric layer 61 and a second interlayer dielectric layer 62 may be further included between the planar layer 70 and the source / drain layer.

[0085] The planar layer 70 may be formed of an organic material, or may be formed of an inorganic material, or may include both organic and inorganic materials.

[0086] Correspondingly, the via hole 11 may also penetrate the first interlayer dielectric layer 61 and the second interlayer dielectric layer 62. The penetration means that the via hole 11 penetrates the first interlayer dielectric layer 61 and the second interlayer dielectric layer 62 in the normal direction.

[0087] like Figure 6As shown, the first metal layer 101 is formed on the hole wall of the via 11, the material of the first metal layer 101 can be the same as the material of the pixel electrode layer 102, or can be different from the material of the pixel electrode layer 102, in the case of different materials, the impedance between the pixel electrode 102 and the thin film transistor Q can be balanced through the first metal layer 101. Exemplarily, the material of the first metal layer 101 can be the same as the material of the pixel electrode 102, such as both being indium tin oxide ITO.

[0088] As shown, the pixel electrode layer 102 is connected with the first metal layer 101, and the first metal layer 101 is connected with the drain of the thin film transistor Q, so that the pixel electrode layer 102 realizes the connection with the thin film transistor Q through the connected first metal layer 101.

[0089] In some example A, as shown in Figure 4 , Figure 4 As shown in Figure 3 As shown in the enlarged schematic view of the AA1 area, Figure 3 As shown in the plan view of the partial sub-pixel area of the display area, the hole opening of the via 11 includes at least one chamfer, for example, one chamfer or multiple chamfers, in the case of multiple chamfers in this example A, the multiple chamfers can be distributed around the hole opening, that is, chamfers are arranged at different positions of the hole opening, so as to improve the flow guide of the PI liquid at each position of the hole opening. Among them, due to the existence of the chamfer, it is beneficial for the PI liquid to flow into the via 11. In some examples, the chamfer refers to cutting the edge at the hole opening into a certain bevel, which can guide the flow of the PI liquid. In yet some examples, the chamfer refers to setting the shape of the hole opening as a circular hole opening, a special-shaped hole opening, or a hole opening with a round corner 112a.

[0090] In some example B, as shown in Figures 8-12 , Figure 3 As shown in the specific structure schematic view of the AA1 area, Figures 8-12 As shown, the hole opening of the via 11 includes at least one channel 114 communicating with the via 11, for example, one channel 114 or multiple channels 114, the channel 114 can be located on one side of the via 11, or on different sides of the via 11. Please refer to Figure 15a-Figure 2 0, Figure 8 As shown in the cross-sectional view of the B-B direction, Figure 15a-Figure 16a As shown in one implementation of the example B, the bottom of the channel 114 can be flush with the highest plane of the second part, as shown in Figures 17a-21a As shown in another implementation of the example B, the bottom of the channel 114 can be lower than the highest plane of the second part, as shown inAs shown, the bottom of the channel 114 can be located on any one of the planar layer 70, the passivation layer 90 and the pixel electrode layer 102. In this way, the PI liquid can be guided through the channel 114, so as to be guided into the via hole 11, and the PI liquid is prevented from accumulating at the aperture.

[0091] In the present example B, the bottom of the channel 114 is located on the planar layer 70, which means that the plane where the bottom is located is within the planar layer 70, so that the distance between the channel 114 and the substrate 10 in the normal direction of the substrate 10 is less than or equal to the distance between the side of the planar layer 70 away from the substrate 10 and the substrate 10. This distance is also referred to as a vertical distance. Similarly, the bottom of the channel 114 is located on the passivation layer 90, which means that the plane where the bottom is located is within the passivation layer 90, so that the distance between the channel 114 and the substrate 10 in the normal direction of the substrate 10 is less than or equal to the distance between the side of the passivation layer 90 away from the substrate 10 and the substrate 10. This distance is also referred to as a vertical distance.

[0092] In the present example B, the bottom of the channel 114 is located on the planar layer 70, which means that the plane where the bottom is located is within the planar layer 70, so that the distance between the channel 114 and the substrate 10 in the normal direction of the substrate 10 is less than or equal to the distance between the side of the planar layer 70 away from the substrate 10 and the substrate 10. This distance is also referred to as a vertical distance. Similarly, the bottom of the channel 114 is located on the passivation layer 90, which means that the plane where the bottom is located is within the passivation layer 90, so that the distance between the channel 114 and the substrate 10 in the normal direction of the substrate 10 is less than or equal to the distance between the side of the passivation layer 90 away from the substrate 10 and the substrate 10. This distance is also referred to as a vertical distance.

[0093] In some examples C, the aperture of the via hole 11 includes at least one chamfer, and at least one channel 114 communicating with the via hole 11 at the aperture of the via hole 11, so as to improve the guiding effect of the PI liquid.

[0094] In some embodiments, the chamfer refers to setting the shape of the aperture to a circular aperture, a special-shaped aperture, or an aperture with a chamfer 112a. For example, as shown in Figure 4 As shown, a schematic diagram of the orthographic projection of the aperture on the substrate 10 is shown, and the orthographic projection of the aperture on the substrate 10 can be a polygon, a circle, an ellipse or other shapes with chamfers. The angle of each endpoint of the polygon can be greater than 90 degrees.

[0095] In some embodiments, in combination with Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the via hole 11 can include:

[0096] a first sub-hole 111 formed in the planar layer 70;

[0097] a second sub-hole 112 formed in the passivation layer 90, and the orthographic projection of the second sub-hole 112 on the substrate 10 falls within the orthographic projection of the first sub-hole 111 on the substrate 10;

[0098] At least the edge of the normal projection of the second sub-hole 112 on the substrate 10 comprises a plurality of rounded corners 112a.

[0099] In this embodiment, the second sub-hole 112 located in the passivation layer 90 can have at least one chamfer, which can be configured as a rounded corner 112a.

[0100] Exemplarily, as Figure 5 shown, a plan view of the second sub-hole 112 is shown, as Figure 5 shown in (a), the normal projection of the second sub-hole 112 on the substrate 10 is a rectangle, and each end point of the rectangle is a rounded corner 112a, and the center of the rounded corner 112a falls within the normal projection of the second sub-hole 112 on the substrate 10. As Figure 5 shown in (c), the normal projection of the second sub-hole 112 on the substrate 10 is a rectangle, and each end point of the rectangle is a rounded corner 112a, and the center of the rounded corner 112a falls outside the normal projection of the second sub-hole 112 on the substrate 10, so that a gap is formed at the aperture, which can facilitate the flow of PI liquid into the via 11. As Figure 5 shown in (b), the normal projection of the second sub-hole 112 on the substrate 10 is a rectangle, and part of the end points of the rectangle are rounded corners 112a, and part of the end points are obtuse angles. Wherein, the normal projection of the second sub-hole 112 on the substrate 10 is a rectangle, which can include one rounded corner 112a or a plurality of rounded corners 112a.

[0101] Wherein, the rounded corner 112a is not necessarily a segment of a circular arc, but can also be a segment of an elliptical arc. As Figure 5 shown in (d), the normal projection of the second sub-hole 112 on the substrate 10 is a rectangle, and part of the end points of the rectangle are rounded corners 112a, which can be a segment of an elliptical arc.

[0102] Wherein, in the case of including a plurality of rounded corners 112a, the radii corresponding to the arcs on the plurality of rounded corners 112a can be the same or not exactly the same.

[0103] In some embodiments, the chamfer can be disposed close to the pixel electrode layer 102. Exemplarily, a plurality of chamfers can be disposed on the side of the via 11 close to the pixel electrode layer 102, which can facilitate the flow of PI liquid near the pixel electrode layer 102, thereby improving PI mura.

[0104] In some embodiments, as Figure 4 shown, the normal projection of the first sub-hole 111 on the substrate 10 is a rectangle, which can also include at least one chamfer, which can be a rounded corner or other shaped chamfer.

[0105] In some embodiments, as Figure 6 and Figure 7 shown, Figure 7 An enlarged schematic view of the AA3 region in FIG. 1 is shown in FIG. 2. Figure 6 An enlarged schematic view of the AA3 region in FIG. 1 is shown in FIG. 2. Figure 7 As shown in FIG. 2, the via 11 has a slope 113 inclined toward the bottom of the via 11 at least at the hole wall located at the rounded corner 112a; wherein the vertical distance from the side of the substrate 10 close to the highest plane of the second portion to the slope 113 is less than the depth of the via 11.

[0106] In the embodiment, the chamfering can be combined with the inclined hole wall. Figure 7 As shown in FIG. 2, the chamfering can also refer to cutting the corner at the hole opening into a certain slope, wherein the slope is referred to as the slope 113, the slope 113 is inclined toward the bottom of the hole, for example, the vertical distance between one end of the slope 113 and the hole opening and the other end and the substrate 10 is less than the vertical distance from the hole opening to the substrate 10, and the hole opening at the slope 113 is a rounded corner 112a again. Thus, by the rounded corner 112a and the slope 113, the PI liquid flow can be strengthened, thereby avoiding the PI liquid from gathering around the via 11 to a greater extent, so that the PI liquid can flow into the via 11 as much as possible.

[0107] In an example, the surface of the slope 113 can be a smooth circular arc surface, thereby facilitating the PI liquid to flow into the via 11.

[0108] Next, the channel 114 provided at the hole opening will be described in combination with FIG. 3. Figure 8-Figure 23 Next, the channel 114 provided at the hole opening will be described in combination with FIG. 3.

[0109] Wherein, Figures 8-12 is a specific structural schematic view of the AA1 region in FIG. 1, Figure 3 is a planar schematic view of the channel 114, Figure 13 is a specific structural schematic view of the AA1 region in FIG. 1, Figure 14 is an enlarged schematic view of the channel design at the via in FIG. 1, Figure 8 is a cross-sectional schematic view at B-B. Figure 15a-Figure 23 is a cross-sectional schematic view at B-B. Figure 8 is a cross-sectional schematic view at B-B.

[0110] In some embodiments, a plurality of channels 114 or one channel 114 can be included, and in the case of including one channel 114, the channel 114 can be located at different sides of the via 11 from the pixel electrode strip, which can be referred to in combination with FIG. 4. Figures 9-11 As shown in FIG. 4, the orthographic projection of the channel 114 on the substrate 10 and the orthographic projection of the pixel electrode on the substrate 10 are located at different sides of the via 11; or in yet another example, as shown in FIG. 5, the channel 114 can be located at the same side of the via 11 as the pixel electrode strip. Figure 12

[0111] Wherein, in the case of including a plurality of channels 114, in an example, as shown in FIG. 6, the orthographic projection of the channel 114 on the substrate 10 and the orthographic projection of the pixel electrode on the substrate 10 are located at different sides of the via 11. Figure 8 ​As shown, the multiple channels 114 can be located on the same side of the via hole 11. In this case, the multiple channels 114 and the pixel electrode strips can be located on different sides of the via hole 11; or Figure 12 As shown, the plurality of channels 114 and the pixel electrode strips may be located on the same side of the via hole 11 .

[0112] In another example, the plurality of channels 114 may be distributed on different sides of the via hole 11, such as Figures 9-11 As shown, the plurality of channels 114 may be distributed on at least two sides of the via hole 11, as shown in FIG. Figure 10 As shown, multiple channels 114 are located on opposite sides of the via hole 11, as shown in FIG. Figure 11 As shown, multiple channels 114 are located on two adjacent sides of the via hole 11, as shown in FIG. Figure 9 As shown, the plurality of channels 114 may be located on three adjacent sides of the via hole 11 . In some other examples, the plurality of channels 114 may be distributed around the via hole 11 (not shown in the figure).

[0113] In this case, the plurality of channels 114 may include a channel 114 on the same side as the pixel electrode, for example, Figure 12 As shown, the plurality of channels 114 may include the channel 114 on the same side as the pixel electrode. Alternatively, the plurality of channels 114 may not include the channel 114 on the same side as the pixel electrode, as shown in FIG. Figures 8-11 shown.

[0114] In some examples, when a plurality of channels 114 are included, the intervals between the plurality of channels 114 may be uniform or non-uniform.

[0115] In some examples, such as Figure 14 As shown, in the case of including multiple channels 114, the dimensions of the multiple channels 114 may be the same or different, wherein the dimensions may include the length L, width W of the channel 114 in the planar direction, and the depth of the channel 114. Exemplarily, the length, width, and depth of the multiple channels 114 may be the same. As another example, at least one of the length, width, and depth of the multiple channels 114 may be different. For example, the length and width of the multiple channels 114 may be the same, but the depth may be slightly different; or, the length and depth of the multiple channels 114 may be the same, but the width may be slightly different; or, the width and depth of the multiple channels 114 may be the same, but the length may be slightly different. Alternatively, the length, width, and depth of the multiple channels 114 may all be different.

[0116] In some other examples, for the same channel 114, the depth of the channel 114 may be non-uniform, and it may be configured to have a depth distribution that is conducive to the diversion of the PI liquid. For example, the height of the bottom of the channel 114 close to the orifice may be smaller than the height of the bottom away from the orifice, wherein the height may be the vertical distance between the bottom of the channel 114 and the substrate 10, and the vertical distance refers to the distance between the bottom of the channel 114 and the substrate 10 in the normal direction of the substrate 10.

[0117] In this example, a section of the channel 114 region in the bottom of the channel 114 close to the hole side can be called a first channel region 114a, and a section of the channel 114 region in the bottom of the channel 114 away from the hole side can be called a second channel region 114b, wherein the depth of the first channel region 114a can be greater than the depth of the second channel region 114b.

[0118] In one implementation of this example, a step is formed between the first channel region 114a and the second channel region 114b, so that the PI liquid can first enter the second channel region 114b away from the orifice, and then flow to the first channel region 114a close to the orifice under the action of gravity, thereby flowing into the via 11.

[0119] In one implementation of this example, Figure 24a As shown, Figure 24a and Figure 21b Shown Figure 20a Schematic diagram of the channel in the length direction, as shown in Figure 24a As shown, a smooth transition is formed between the first channel region 114a and the second channel region 114b, so that the entire groove bottom can be a slope inclined toward the via 11, and the slope can be 10 degrees to 45 degrees, such as 10 degrees, 15 degrees, 20 degrees, 25 degrees, 28 degrees, 30 degrees, 35 degrees, 40 degrees, and 45 degrees. Thus, through the slope 113, the flow rate of the PI liquid in the channel 114 region can be increased, and the PI liquid gathered around the via 11 can be quickly introduced into the via 11.

[0120] In some embodiments, the opening of the via hole may include at least one chamfer and at least one channel, wherein the channel may be separated from the position of the chamfer, or at least one channel may be connected to the chamfer to improve the diversion effect.

[0121] In some embodiments, the shape of the channel 114 can be configured to facilitate the flow of the PI liquid, such as the channel 114 can be a streamlined channel 114. For example, the orthographic projection of the channel 114 on the substrate 10 includes at least one of a broken line shape, a straight line shape, and a curved line shape. Figure 13As shown in (a), the orthogonal projection of the channel 114 on the substrate 10 is a broken line, so that the impact of the PI liquid is improved at the bending position, which is conducive to guiding the PI liquid into the via hole 11. Figure 13 As shown in (b), the orthogonal projection of the channel 114 on the substrate 10 is a straight line, which is also conducive to guiding the PI liquid into the via hole 11. Figure 13 As shown in (c), the orthogonal projection of the channel 114 on the substrate 10 is a curved line, so that the impact of the PI liquid is improved in the curved channel 114, which is conducive to guiding the PI liquid into the via hole 11.

[0122] As shown in FIGS. 15-21, the first metal layer 101 is further included in the sub-pixel region and located on the hole wall of the via hole 11, and the pixel electrode layer 102 is connected to the thin film transistor Q through the first metal layer 101.

[0123] The first metal layer 101 includes a first part 101a located in the channel and a second part 101b located in the via hole, and the orthogonal projection of the second part 101b on the substrate covers the orthogonal projection of the via hole on the substrate.

[0124] In this example, the first metal layer 101 can be provided in the same layer as the pixel electrode layer 102, which means that the first metal layer 101 and the pixel electrode layer 102 are both located on the side of the passivation layer 90 away from the substrate 10, and can be formed simultaneously in the same process.

[0125] The first metal layer 101 can be the topmost layer of the array substrate, and the surface of the first metal layer 101 can be flush with the surface of the pixel electrode layer 102, or the surface of the first metal layer 101 can be lower than the surface of the pixel electrode layer 102, for example, the vertical distance between the surface of the first metal layer 101 away from the substrate 10 and the substrate 10 can be less than the vertical distance between the surface of the pixel electrode layer 102 away from the substrate 10 and the substrate 10.

[0126] In some examples, the orthogonal projection of the second part 101b of the first metal layer 101 on the substrate 10 covers the orthogonal projection of the hole on the substrate 10, and the first metal layer 101 is located on the hole wall of the via hole 11, and the pixel electrode layer 102 is connected to the thin film transistor Q through the first metal layer 101.

[0127] The first metal layer 101 can include a first part 101a located in the channel and a second part 101b located in the via hole. As shown in FIGS. 17-21, the orthogonal projection of the first part 101a on the substrate can coincide with the orthogonal projection of the channel bottom on the substrate, and the orthogonal projection of the second part 101b on the substrate can cover the orthogonal projection of the via hole on the substrate.

[0128] In this embodiment, the first portion 101a refers to the portion of the first metal layer 101 covering the bottom of the channel.

[0129] In some examples of this embodiment, the plane where the bottom of the channel 114 is located can be flush with the plane where the second portion is located; or, in the direction of the normal of the substrate 10, the distance between the plane where the bottom of the channel 114 is located and the substrate 10 is smaller than the maximum distance between the surface on the side of the second portion away from the substrate 10 and the substrate 10, so that the bottom of the channel is lower than the highest plane of the second portion. Or, in other examples, the bottom of the channel can be higher than the highest plane of the surface on the side of the second portion away from the substrate 10.

[0130] Wherein, the highest plane refers to the plane where the maximum vertical distance between the surface on the side of the second portion 101b away from the substrate 10 and the substrate is located, and in some examples, the orthographic projection of the second portion 101b on the substrate 10 can cover the orthographic projection of the aperture on the substrate 10, in which case, the highest plane can also be referred to as the plane where the aperture is located.

[0131] In some examples #1, for a channel 114, as shown in Figure 15a and Figure 16a , the bottom of the channel 114 can be flush with the highest plane of the second portion, which can mean that the included angle between the bottom of the channel and the highest plane of the second portion is 0 degrees / 180 degrees, or the included angle between the bottom of the channel and the highest plane of the second portion can be located in -5 degrees-5 degrees. Exemplarily, in the case where the bottom of the channel 114 is flush with the highest plane of the second portion, the channel 114 is formed after the first metal layer 101, and the first portion 101a of the first metal layer 101 exposed by the channel is sufficient. In this example, the channel wall of the channel 114 can be higher than the highest plane of the second portion, so that when the PI liquid is formed, the PI liquid will flow in the channel 114 and flow into the via 11.

[0132] In yet other examples #2, as shown in Figures 17a-21a , the bottom of the channel 114 can also be lower than the highest plane of the second portion. In this way, the channel 114 can be formed before the first metal layer 101, so that the PI liquid can be guided to flow into the via 11 without increasing the film thickness of the region where the thin film transistor Q of the sub-pixel region is located.

[0133] In this example #2, the bottom of the channel 114 includes the first portion of the first metal layer 101, wherein the channel 114 can be entirely the first metal layer 101, in which case, the orthographic projection of the channel on the substrate can be located within the orthographic projection of the first metal layer on the substrate, as shown in Figure 24bAs shown, the trench bottom of the channel is all the first metal layer, and the outer contour of the channel's orthographic projection on the substrate partially overlaps the outer contour of the first metal layer on the substrate; as shown Figure 24c As shown, the trench bottom of the channel is all the first metal layer, and the outer contour of the channel's orthographic projection on the substrate falls within the outer contour of the first metal layer on the substrate. Alternatively, part of the channel 114 is the first metal layer 101, and part of the channel 114 is not the first metal layer 101 (such as a passivation layer, a planarization layer), as shown Figure 24a As shown, part of the trench bottom of the channel is the first metal layer, and part of the trench bottom of the channel is a planarization layer. Alternatively, the trench bottom of the same channel 114 includes both the first metal layer 101 and the second metal layer 140, as shown Figure 16b As shown, part of the trench bottom of the channel is the first metal layer, and part of the trench bottom of the channel is the second metal layer. Specifically, this will be described in detail in some optional examples of subsequent example #2.

[0134] In an example of the present embodiment, the first portion 101a can be flush with the second portion 101b, as shown Figure 14 and Figure 15a That is, the vertical distance between the surface of the first portion 101a away from the substrate and the substrate can be equal to the maximum vertical distance between the second portion 101b and the substrate.

[0135] Alternatively, the first portion 101a can be lower than the second portion 101b, as shown Figures 16a-21a As shown, the maximum distance between the surface of the first portion 101a away from the substrate and the substrate can be less than the maximum vertical distance between the second portion 101b and the substrate.

[0136] Of course, in some embodiments, the first metal layer 101 can only include the second portion 101b, and the first metal layer 101 can not be provided at the channel, as shown Figure 22 As shown, the first metal layer 101 can be in communication with the channel 114, and the first metal layer 101 can not include part located in the channel 114, so that the channel 114 is formed outside the first metal layer 101, that is, the orthographic projection of the channel 114 on the substrate 10 can be located outside the orthographic projection of the first metal layer 101 on the substrate 10. In this case, the channel can be located on different sides of the via from the pixel electrode layer, and the height of the portion of the first metal layer 101 close to the channel can be less than the height of the portion close to the pixel electrode layer.

[0137] In some embodiments, as shown Figure 23As shown, a second metal layer 140 may be formed outside the first metal layer 101. The thickness of the second metal layer 140 may be greater than or equal to the thickness of the first metal layer 101. The channel 114 may be located in the second metal layer 140. For example, the second metal layer 140 may include a plurality of metal strips, with the channel 114 formed between the plurality of metal strips, and the channel 114 is connected to the first metal layer 101. In this case, the bottom of the channel 114 may be located in the passivation layer 90, that is, the passivation layer 90 serves as the bottom of the channel 114.

[0138] For example, the first metal layer 101 may include a first portion 101a located in the trench 114. Figures 15a-21a As shown, the orthographic projection of the channel 114 on the substrate 10 is U-shaped, and its opening leads to the via 11. The channel 114 may include three channel walls, wherein at least one of the three channel walls may include the first metal layer 101, that is, the first metal layer 101 covers the channel walls and the bottom of the channel 114. In this way, at least the plane where the bottom of the channel 114 is located is lower than the surface of the first metal layer 101 facing away from the substrate 10. In other words, the vertical distance from the surface of the first metal layer 101 (first portion 101a) on the bottom of the channel 114 facing away from the substrate 10 to the substrate 10 is smaller than the vertical distance from the surface of the first metal layer 101 (second portion 101b) at other locations facing away from the substrate 10 to the substrate 10. In this way, a step difference can be formed on at least the first metal layer 101, which allows the PI liquid on the first metal layer 101 to flow into the channel 114 and then into the via 11.

[0139] Exemplarily, the first metal layer 101 includes a first portion 101a and a second portion 101b , wherein the orthographic projection of the first portion 101a on the substrate 10 overlaps with the orthographic projection of the channel 114 on the substrate 10 , and the orthographic projection of the second portion 101b on the substrate 10 does not overlap with the channel 114 .

[0140] like Figures 15a-21a As shown, the first portion 101a of the first metal layer 101 in the trench is located on the side of the passivation layer facing away from the substrate. In this case, the trench bottom can be flush with the highest plane of the second portion, or the trench bottom can be lower than the highest plane of the second portion.

[0141] like Figure 15a and Figure 16aAs shown, the bottom of the trench can be flush with the highest plane of the second portion, for example, for a trench 114 in an optional example of some example #1, the bottom of the trench 114 can be flush with the highest plane of the second portion, and then the first metal layer 101 can be exposed by the trench 114, and the side of the first metal layer 101 away from the substrate 10 can further include an insulating layer 130, which can serve as a trench wall. As an example, the sub-pixel region further includes:

[0142] The insulating layer 130 is located on the side of the passivation layer 90 away from the substrate 10, and the orthographic projection of the insulating layer on the substrate does not overlap with the orthographic projection of the aperture on the substrate.

[0143] The trench is located in the insulating layer, which can expose the first metal layer 101 or not expose the first metal layer 101, in the case of exposing the first metal layer 101 by the trench 114, the trench wall includes the insulating layer 130, and the orthographic projection of the insulating layer 130 on the substrate 10 does not overlap with the orthographic projection of the aperture on the substrate 10. In the case of not exposing the first metal layer 101, the bottom of the trench can be higher than the first portion 101a, so that the trench and the first portion include an insulating layer.

[0144] In this example, the insulating layer 130 can be formed on the side of the first metal layer 101 away from the substrate 10, and the trench 114 can be formed by the step difference on the insulating layer 130, so that the bottom of the trench 114 away from the substrate 10 can be the first metal layer 101.

[0145] In some examples, a second metal layer 140 can also be formed on the periphery of the first metal layer 101, and the thickness of the second metal layer 140 can be greater than or equal to the thickness of the first metal layer 101, Figure 16a As shown, in the case where the second metal layer 140 is equal to the thickness of the first metal layer 101, the insulating layer 130 can be formed on the side of the second metal layer 140 away from the substrate 10, so that the second metal layer 140 can raise the plane height of the periphery of the first metal layer 101, thereby facilitating the formation of the trench 114 later.

[0146] The orthographic projection of the insulating layer 130 on the substrate 10 can also overlap with the orthographic projection of the first metal layer 101 on the substrate 10. Figure 16a As shown, the orthographic projection of the insulating layer 130 on the substrate 10 can also overlap with the orthographic projection of the first metal layer 101 on the substrate 10.

[0147] The material of the insulating layer 130 can be an organic material or an inorganic material. When the inorganic material is used, the first metal layer 101 below can be protected from water and oxygen corrosion. The vertical distance d2 between the surface of the insulating layer 130 away from the substrate 10 and the substrate 10 can be less than the vertical distance d1 between the surface of the pixel electrode layer 102 away from the substrate 10 and the substrate 10. Alternatively, the vertical distance d2 between the surface of the insulating layer 130 away from the substrate 10 and the substrate 10 can be slightly greater than the vertical distance d1 between the surface of the pixel electrode layer 102 away from the substrate 10 and the substrate 10.

[0148] In the formation of the channel 114 of the present example, if only the first metal layer 101 is included, as shown in FIG. 2, the insulating layer 130 can be formed on the side of the first metal layer 101 away from the substrate 10 after the formation of the first metal layer 101. Then, the insulating layer 130 is etched to a depth equal to the thickness of the insulating layer 130, thereby etching a plurality of channels 114, so that the channels 114 expose the first metal layer 101. In this way, the depth of the channel 114 can be greater than or equal to the thickness of the insulating layer 130. Figure 15a

[0149] In the formation of the channel 114 of the present example, if the second metal layer 140 is included, as shown in FIG. 3, the second metal layer 140 and the first metal layer 101 can be formed at the same time. Then, the insulating layer 130 is formed on the side of the second metal layer 140 away from the substrate 10. Then, the insulating layer 130 is etched to a depth equal to the thickness of the insulating layer 130, thereby etching a plurality of channels 114, so that the channels 114 expose the first metal layer 101. In this way, the PI liquid flows into the second metal layer 140 in the channel 114, and then flows from the second metal layer 140 to the first metal layer 101 and into the via 11. The thickness of the second metal layer 140 can be greater than the thickness of the first metal layer 101, that is, the vertical distance between the surface of the second metal layer 140 away from the substrate 10 and the substrate 10 is greater than the vertical distance between the surface of the first metal layer 101 away from the substrate 10 and the substrate 10. Figure 16a In this embodiment, as shown in FIG. 4, the first metal layer can be entirely included in some of the channels 114, and the insulating layer can be included in some of the channels. For example, the insulating layer in some of the channels is partially etched to ensure that the bottom of the channel is flush with the distance between the surface of the first portion away from the substrate and the substrate.

[0150] Figure 15b In this embodiment, as shown in FIG. 5, the first metal layer can be entirely included in some of the channels 114, and the insulating layer can be included in some of the channels. For example, the insulating layer in some of the channels is partially etched to ensure that the bottom of the channel is flush with the distance between the surface of the first portion away from the substrate and the substrate.

[0151] In this embodiment, as shown in FIG. 5, the first metal layer can be entirely included in some of the channels 114, and the insulating layer can be included in some of the channels. For example, the insulating layer in some of the channels is partially etched to ensure that the bottom of the channel is flush with the distance between the surface of the first portion away from the substrate and the substrate. Figure 16b ​​As shown, in the length direction of the channel, the bottom of the channel may include the second metal layer and the first metal layer.

[0152] Next, an array substrate in which the bottom of the trench can be lower than the highest plane of the second portion is exemplified.

[0153] In one example, the minimum distance between the surface of the first portion 101a facing away from the substrate 10 and the substrate 10 is less than the maximum vertical distance between the surface of the second portion 101b facing away from the substrate 10 and the substrate 10. The minimum distance between the surface of the first portion 101a facing away from the substrate 10 and the substrate 10 is the vertical distance d4 between the surface of the first metal layer 101 in the channel 114 facing away from the substrate 10 and the substrate 10, and the maximum vertical distance between the surface of the second portion 101b facing away from the substrate 10 and the substrate 10 can be the vertical distance d3 between the surface of the first metal layer 101 at the orifice facing away from the substrate 10 and the substrate 10.

[0154] In this example, the channel 114 can be obtained by etching the first metal layer 101, and the etching depth can be less than the thickness of the first metal layer 101. The bottom of the channel 114 can include the first metal layer 101, but the thickness of the first metal layer 101 in the channel 114 is less than the thickness of the first metal layer 101 outside the channel 114 (i.e., the channel wall). In other words, the step difference is formed on the first metal layer 101. The depth of the channel 114 formed in this way is smaller, but it still has a certain diversion effect.

[0155] like Figures 17a-21a As shown, in the case where the bottom of the channel can be lower than the highest plane of the second part, and the first part 101a is located on the side of the passivation layer facing away from the substrate, the passivation layer can include a vertical distance between the surface of the part located in the channel region facing away from the substrate and the substrate, which is greater than the vertical distance between the surface of the part of the passivation layer not located in the channel region facing away from the substrate and the substrate.

[0156] In this way, the minimum distance between the surface of the first portion 101 a facing away from the substrate 10 and the substrate 10 is smaller than the maximum vertical distance between the surface of the second portion 101 b facing away from the substrate 10 and the substrate 10 .

[0157] In one implementation of this example, Figure 17a As shown, the channel 114 may be obtained by partially etching the passivation layer 90 , so that the channel wall also includes the passivation layer 90 .

[0158] like Figure 17aAs shown, the passivation layer 90 can be partially etched, so that the passivation layer 90 can include a portion located at the channel wall and a portion located at the bottom of the channel, and the depth of the channel 114 can be equal to or greater than the thickness of the first metal layer 101. The vertical distance between the surface of the portion of the passivation layer 90 located at the channel wall facing away from the substrate 10 and the substrate 10 is greater than the vertical distance between the surface of the portion of the passivation layer 90 located at the bottom of the channel facing away from the substrate 10 and the substrate 10. In this way, a step difference can be formed on the plane where the passivation layer 90 is located. In this example, as Figure 17a As shown, the channel wall of the channel 114 includes a passivation layer 90 and a first metal layer 101 located on the side of the passivation layer 90 facing away from the substrate 10, and the area where the bottom of the channel 114 is located includes the first metal layer 101, wherein the passivation layer 90 includes a portion located on the channel wall and a portion located on the bottom of the channel. In one example, the thickness of the portion of the passivation layer 90 located on the channel wall can be greater than the thickness of the portion located in the bottom area.

[0159] In the formation Figure 17a In the case of the trench 114 shown, after forming the passivation layer 90, the portion of the passivation layer 90 at the bottom of the trench can be etched, and the etching depth can be less than the thickness of the passivation layer 90. Then, the first metal layer 101 can be formed, such as by electroplating, deposition, etc., so that the trench wall includes the first metal layer 101 and the passivation layer 90, and the first metal layer 101 is formed on the surface of the trench bottom. In this way, the vertical distance between the surface of the first metal layer 101 at the bottom of the trench 114 facing away from the substrate 10 and the substrate 10 can be less than the vertical distance between the surface of the first metal layer 101 at other positions facing away from the substrate 10 and the substrate 10, thereby achieving a diversion effect. In this example, the depth of the trench 114 is greater than the thickness of the first metal layer 101.

[0160] like Figure 17b As shown, in the length direction of the channel (ie, the extending direction of the channel toward the via hole), the bottom of the channel may include a passivation layer and a first metal layer.

[0161] In some other examples, such as Figure 19a and Figure 18a As shown, the bottom of the trench may be lower than the highest plane of the second portion, and the first portion 101a may be located on a side of the planar layer facing away from the substrate.

[0162] In one implementation of this example, Figure 19aAs shown, the channel 114 can be obtained by completely etching the passivation layer 90. In this case, the channel wall includes the passivation layer 90, and the channel bottom of the channel does not include the passivation layer 90. The first portion 101a is formed on the flat layer, and the vertical distance between the surface of the portion of the flat layer located in the channel region facing away from the substrate and the substrate can be equal to the vertical distance between the surface of the portion of the flat layer not located in the channel region facing away from the substrate and the substrate.

[0163] When forming the trench 114, the passivation layer 90 can be completely etched in the trench bottom area, and the flat layer 70 is not etched. Then, the first metal layer 101 is formed, such as by electroplating, deposition, etc., so that the trench includes the first metal layer 101, the passivation layer 90 and the flat layer 70, and the first metal layer 101 is formed on the surface of the trench bottom.

[0164] like Figure 19b As shown, in the length direction of the channel, the bottom of the channel may include a flat layer and a first metal layer, and the passivation layer may serve as a channel wall of the channel.

[0165] The length direction refers to the extending direction of the channel toward the via hole.

[0166] In one implementation of this example, Figure 18a As shown, the trench 114 can be obtained by completely etching the passivation layer 90 and partially etching the planarization layer 70. The trench wall also includes the passivation layer 90 and the planarization layer 70. The vertical distance between the surface of the portion of the planarization layer 70 located at the trench wall facing away from the substrate 10 and the substrate 10 is greater than the vertical distance between the surface of the portion of the planarization layer 70 located at the trench bottom facing away from the substrate 10 and the substrate 10. In this way, a step can be formed on the planarization layer 70, thereby forming the subsequent morphology of the trench 114.

[0167] like Figure 18a As shown, the channel walls of the channel 114 include the first metal layer 101, the passivation layer 90, and the planarization layer 70. The bottom of the channel 114 includes the first metal layer 101. The passivation layer 90 only includes the portion located at the channel walls, and does not include the passivation layer 90 in the bottom region. The planarization layer 70 includes a portion located at the channel walls and a portion located at the bottom region. In one example, the thickness of the portion of the planarization layer 70 located at the channel walls can be greater than the thickness of the portion located at the bottom region. Thus, the vertical distance between the surface of the portion of the planarization layer 70 located at the channel walls facing away from the substrate 10 and the substrate 10 is greater than the vertical distance between the surface of the portion of the planarization layer 70 located at the bottom region facing away from the substrate 10 and the substrate 10.

[0168] When forming the trench 114, the passivation layer 90 can be completely etched in the trench bottom region, and the portion of the planarization layer 70 located at the trench bottom can be partially etched, with the etching depth being less than the thickness of the planarization layer 70. Subsequently, the first metal layer 101 can be formed, for example, by electroplating, deposition, or the like, so that the trench wall includes the first metal layer 101, the passivation layer 90, and the planarization layer 70, and the first metal layer 101 is formed on the surface of the trench bottom. In this way, the vertical distance between the surface of the first metal layer 101 at the trench bottom of the trench 114 facing away from the substrate 10 and the substrate 10 can be less than the vertical distance between the surface of the first metal layer 101 on the trench wall facing away from the substrate 10 and the substrate 10, thereby achieving a diversion effect. In this case, the depth of the trench 114 is at least greater than the sum of the thicknesses of the passivation layer 90 and the first metal layer 101.

[0169] like Figure 18b As shown, in the length direction of the channel (ie, the extending direction of the channel toward the via hole), the bottom of the channel may include a flat layer and a first metal layer, and the passivation layer may serve as a channel wall of the channel.

[0170] In some embodiments, the sub-pixel area may further include a second metal layer 140, which may be located on the side of the passivation layer 90 facing away from the substrate 10; wherein, the orthographic projection of the second metal layer 140 on the substrate 10 may be located outside the orthographic projection of the orifice on the substrate 10, and has no overlap with the orthographic projection of the groove bottom on the substrate 10.

[0171] The second metal layer 140 can be used to assist in the formation of the channel 114 . For example, it can raise the height of the film layer around the via hole 11 , thereby facilitating the formation of the channel 114 .

[0172] In one example of this embodiment, if the highest plane of the second portion 101b is flush with the bottom of the trench, as shown in FIG. Figure 16a As shown, the second metal layer 140 can be provided in the same layer as the first metal layer 101, and the orthographic projections of the first metal layer 101 and the second metal layer 140 on the substrate 10 may not overlap. The first metal layer 101 and the second metal layer 140 may be insulated or connected. In the case of insulation, the second metal layer 140 and the first metal layer 101 may be located on different sides of the via 11. As shown in Example #1 above, the arrangement of the second metal layer 140 can make the plane around the via 11 flush, and the insulating layer 130 can be located on the side of the second metal layer 140 facing away from the substrate 10.

[0173] In one example of this embodiment, if the highest plane of the second portion 101b is flush with the bottom of the trench, as shown in FIG. Figure 23As shown, the channel wall of the channel 114 may include the second metal layer 140. When forming the channel 114, the second metal layer 140 may be etched to a depth equal to the thickness of the second metal layer 140. For example, the second metal layer 140 may be etched into a plurality of metal strips, with the channel 114 formed between the metal strips and connected to the via 11. In this example, since the first metal layer 101 and the second metal layer 140 do not overlap, the first metal layer 101 and the second metal layer 140 may be formed simultaneously, and then the second metal layer 140 may be etched to form the channel 114 connected to the edge of the via 11.

[0174] Among them, Figure 23 As shown, the first metal layer 101 may include a portion located on the side of the second metal layer close to the substrate. Thus, when forming the array substrate of this embodiment, a via hole may be formed first, and the first metal layer 101 may be deposited in the via hole. The first metal layer 101 includes at least a target area 101c close to the channel. The first metal layer 101 in the target area 101c may be roughly flush with the surface of the passivation layer. Then, the second metal layer is deposited on the side of the first metal layer 101 facing away from the substrate, and the second metal layer is formed on the side of the passivation layer facing away from the substrate. The second metal layer is then etched to form multiple channels.

[0175] In this example, the thickness of the second metal layer 140 may be greater than or equal to the thickness of the first metal layer 101 .

[0176] In some other examples of the above example #2 (the highest plane of the second portion 101b is higher than the bottom of the trench), as shown in FIG. Figures 19a-21a As shown, the second metal layer 140 and the first metal layer 101 can be arranged in different layers. For example, the first metal layer 101 can be located on the side of the second metal layer 140 facing away from the substrate 10. In this way, the channel wall can include the second metal layer 140 and the first metal layer 101. That is, the first metal layer 101 can include a first portion 101a located at the bottom of the channel 114 and a second portion 101b located at the channel wall. The second portion 101b can be located on the second metal layer 140. In this example, the first metal layer 101 and the second metal layer 140 can be formed separately.

[0177] In the formation Figure 19a When the array substrate is shown, a passivation layer can be formed, and a second metal layer 140 can be formed on one side of the passivation layer. Then, the second metal layer 140 and the passivation layer are etched to a depth equal to the thickness of the second metal layer 140 and the passivation layer. Then, a first metal layer is formed on the via hole, thereby obtaining the first part and the second part of the first metal layer 101. Figure 19bAs shown, in the length direction of the channel (i.e. the extension direction of the channel to the via), the channel bottom of the channel can include the planar layer and the first metal layer, and the passivation layer and the second metal layer can serve as the channel wall of the channel.

[0178] In forming the array substrate Figure 21a As shown, in forming the array substrate, the passivation layer can be formed, and the second metal layer 140 can be formed on one side of the passivation layer, then the second metal layer 140, the passivation layer and the planar layer are etched, the etching depth is greater than the thickness of the second metal layer 140 and the passivation layer, then the first metal layer is formed on the via again, so as to obtain the first part and the second part of the first metal layer 101. As shown in Figure 21b As shown, in the length direction of the channel (i.e. the extension direction of the channel to the via), the channel bottom of the channel can include the planar layer and the first metal layer, and the passivation layer, the planar layer and the second metal layer can serve as the channel wall of the channel.

[0179] For example, in forming the array substrate of this structure, the second metal layer 140 can be formed first, then the second metal layer 140 is etched to obtain the channel 114 in communication with the via 11, and then the first metal layer 101 is formed on the via 11, the first metal layer 101 includes the part covering the second metal layer 140 and the part covering the channel bottom of the channel 114. The second metal layer 140 and the first metal layer 101 can be electrically connected, and the orthographic projection of the second metal layer 140 on the substrate 10 can not overlap with the opening area of the sub-pixel area, that is, the second metal layer 140 does not invade the opening area, affecting the aperture ratio of the sub-pixel area.

[0180] In this example, the second metal layer 140 can be formed of transparent conductive material, such as transparent metal or metal oxide, so that the second metal layer 140 does not need to strictly avoid invading the opening area, that is, the second metal layer 140 can partially overlap with the opening area of the sub-pixel area.

[0181] For example, as shown in FIG. 20, the second metal layer can further include the part located on the side of the second part 101b close to the substrate.

[0182] In the above description of FIG. 15- Figure 23 All the above examples are described by taking the channel and the pixel electrode layer located on different sides of the via as an example, but it does not mean that the channel and the pixel electrode layer are limited to be located on different sides of the via.

[0183] In some examples, the array substrate further includes a plurality of data lines, the data lines are connected to the thin film transistors Q in the sub-pixel areas in the same column; wherein the orthographic projection of the second metal layer 140 on the substrate 10 does not overlap with the orthographic projection of the data lines on the substrate 10. In this way, no capacitance is formed between the second metal layer 140 and the data lines, so as not to affect the circuit characteristics of the pixel driving circuit of the entire array substrate.

[0184] In a further example, as shown in Figure 12 the first metal layer 101 is connected with the pixel electrode layer 102, wherein the pixel electrode layer 102 comprises a plurality of pixel electrode strips, and the channel 114 can be communicated with the gap between the pixel electrode strips.

[0185] In the case that the pixel electrode layer 102 comprises a plurality of pixel electrode strips, the pixel electrode layer 102 is configured as a slit electrode, and the slit is the gap between the pixel electrode strips. In this way, in the case that the slit is communicated with the channel 114, the channel 114 leading to the via hole 11 can be formed from the pixel electrode layer 102, and since the height of the pixel electrode layer 102 is greater than the height of the first metal layer 101 (e.g., the vertical distance between the surface of the pixel electrode layer 102 away from the substrate 10 and the substrate 10 is greater than the vertical distance between the surface of the first metal layer 101 away from the substrate 10 and the substrate 10), the channel 114 can be formed around the via hole 11 to be inclined to the via hole 11, thereby facilitating the flow of the PI liquid.

[0186] In this example, a plurality of channels 114 can be located on the same side of the via hole 11 as the pixel electrode layer 102.

[0187] In some embodiments, a display panel is also provided, as shown in Figure 25 and Figure 26 a cross-sectional structure diagram of the display panel is shown, as shown in Figure 25 which can comprise a first substrate 100 and a second substrate 200, the first substrate 100 and the second substrate 200 are oppositely arranged, and a liquid crystal 300 can be arranged between the first substrate 100 and the second substrate 200.

[0188] As shown in Figure 26 the first substrate is configured as the array substrate of any of the above embodiments, wherein an alignment layer 120 is included between the first substrate and the liquid crystal, and the alignment layer 120 comprises a portion located in the via hole 11 of the array substrate.

[0189] In the case that the display panel is an ADS type display panel, the common electrode 81 and the pixel electrode 102 are included on one side of the array substrate; or in the case that the display panel is a TN display panel, the pixel electrode 102 is included on one side of the first substrate, and the common electrode 81 is included on the side of the second substrate close to the first substrate, and a vertical electric field is formed between the pixel electrode 102 and the common electrode 81.

[0190] In some examples, as shown in the figure, a common electrode line can also be included, which can be located on the side of the common electrode 81 away from the substrate and connected with the common electrode 81.

[0191] The connection may be an electrical connection.

[0192] like Figure 25 As shown, an alignment layer 120 is provided on a side of the first substrate close to the second substrate. The alignment layer 120 is located between the liquid crystal and the first substrate. Since a guide structure is formed at the via hole 11 of the sub-pixel area of ​​the array substrate, when the alignment layer 120 is formed, the PI liquid can be guided into the via hole 11 through the guide structure, thereby forming the alignment layer 120 in the via hole 11.

[0193] The thickness of the alignment layer 120 in the via hole 11 may be less than or equal to the depth of the via hole 11 .

[0194] Among them, such as Figure 26 As shown, in the case where the channel 114 is included, the alignment layer 120 is also included in the channel 114, and the thickness of the alignment layer 120 in the channel 114 can be less than the thickness of the alignment layer 120 in the via hole 11. In one example, the thickness of the alignment layer 120 in the channel 114 can be less than or equal to the depth of the channel 114.

[0195] The second substrate 200 may include a transparent substrate, a black matrix layer located on one side of the transparent substrate, the black matrix layer including multiple openings, and color filter layers disposed in the openings. The color filter layers may include a green color filter layer, a red color filter layer, and a blue color filter layer. The orthographic projection of each color filter layer on the array substrate may cover the pixel electrodes on the array substrate. The orthographic projection of the black matrix layer on the array substrate may cover the gate lines GL, data lines DL, and thin film transistors Q on the array substrate, and may not overlap with the openings in the sub-pixel regions.

[0196] In some examples, a plurality of support pillars 400 are further interspersed between the first substrate and the second substrate.

[0197] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0198] Finally, it should be noted that the terms "first" and "second", and the like, herein do not denote any order, quantity, combination or importance, but are used to identify one element from another, and do not imply referring to a certain number of terms, but are only used to identify an element from another, unless otherwise specified. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0199] The above detailed description of the array substrate and the display panel provided by the present disclosure has been described in detail, and the principles and embodiments of the present disclosure are described by applying specific examples. The above description of the embodiments is only used to help understand the method and core idea of the present disclosure; at the same time, for those skilled in the art, according to the idea of the present disclosure, the specific embodiments and application scope will be changed; in summary, the content of the specification should not be understood as a limitation of the present disclosure.

[0200] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practice of the disclosed application. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice within the art to which the present disclosure pertains. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0201] It should be understood that the present disclosure is not limited to the precise structures described and shown in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the claims appended hereto.

[0202] As used herein, the term "one embodiment", "an embodiment", or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Further, it is noted that the word "comprises" or "comprising" or any other variation thereof, is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0203] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present disclosure can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the specification.

[0204] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0205] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. An array substrate, characterized in that: The device comprises a plurality of sub-pixel regions, wherein the sub-pixel regions include: substrate (10); a thin film transistor (Q), located on one side of the substrate (10); a planar layer (70) located on a side of the thin film transistor (Q) facing away from the substrate (10); a passivation layer (90) located on a side of the planar layer (70) facing away from the substrate (10); a pixel electrode layer (102), located on a side of the passivation layer (90) facing away from the substrate (10); a via hole (11) passing through the planar layer (70) and the passivation layer (90), wherein the pixel electrode layer (102) is connected to the thin film transistor (Q) through the via hole (11); The opening of the via hole (11) includes at least one chamfer; and / or the opening of the via hole (11) includes at least one channel (114) communicating with the via hole (11).

2. The array substrate according to claim 1, wherein: The aperture includes the channel (114), and the sub-pixel region further includes: A first metal layer (101) is located on the hole wall of the via hole (11), and the pixel electrode layer (102) is connected to the thin film transistor (Q) through the first metal layer (101); The first metal layer (101) comprises a first portion located in the channel (114) and a second portion located in the via hole (11), and an orthographic projection of the second portion on the substrate (10) covers an orthographic projection of the via hole (11) on the substrate (10).

3. The array substrate according to claim 2, wherein: The first portion is located on a side of the passivation layer (90) facing away from the substrate (10).

4. The array substrate according to claim 3, wherein: In the thickness direction of the substrate (10), the distance between the surface of the first portion located at the bottom of the channel (114) on the side facing away from the substrate (10) and the substrate (10) is smaller than the maximum distance between the surface of the second portion on the side facing away from the substrate (10) and the substrate (10).

5. The array substrate according to claim 4, wherein: The vertical distance between the surface of the passivation layer (90) located in the channel (114) region and the side facing away from the substrate (10) and the substrate (10) is greater than the vertical distance between the surface of the portion of the passivation layer (90) not located in the channel (114) region and the side facing away from the substrate (10) and the substrate (10).

6. The array substrate according to claim 3, wherein: The distance between the surface of the first portion located at the bottom of the channel (114) facing away from the substrate (10) and the substrate (10) is equal to the maximum distance between the surface of the second portion facing away from the substrate (10) and the substrate (10); the sub-pixel area further includes: an insulating layer (130) located on a side of the passivation layer (90) facing away from the substrate (10), wherein an orthographic projection of the insulating layer (130) on the substrate (10) does not overlap with an orthographic projection of the aperture on the substrate (10); The channel (114) is located in the insulating layer (130), and the channel (114) exposes the first portion, or the insulating layer (130) is included between the channel (114) and the first portion.

7. The array substrate according to claim 2, wherein: In the thickness direction of the substrate (10), the distance between the surface of the first part facing away from the substrate (10) and the substrate (10) is smaller than the maximum distance between the surface of the second part facing away from the substrate (10) and the substrate (10); The first portion is located on a side of the flat layer (70) facing away from the substrate (10).

8. The array substrate according to claim 7, wherein: The vertical distance between the surface of the portion of the flat layer (70) located in the channel (114) region that is away from the substrate (10) and the substrate (10) is greater than the vertical distance between the surface of the portion of the flat layer (70) not located in the channel (114) region that is away from the substrate (10) and the substrate (10).

9. The array substrate according to any one of claims 1 to 8, characterized in that: The sub-pixel region includes the channel (114), the pixel electrode layer (102) includes a plurality of pixel electrode strips, and the channel (114) is connected to the gaps between the pixel electrode strips.

10. The array substrate according to any one of claims 2 to 8, characterized in that: The sub-pixel area further includes: a second metal layer (140) located on a side of the passivation layer (90) facing away from the substrate (10); The orthographic projection of the second metal layer (140) on the substrate (10) is located outside the orthographic projection of the orthographic opening on the substrate (10), and does not overlap with the orthographic projection of the bottom of the channel (114) on the substrate (10).

11. The array substrate according to claim 10, wherein: The distance between the surface of the first part facing away from the substrate (10) and the substrate (10) is smaller than the maximum distance between the surface of the second part facing away from the substrate (10) and the substrate (10), and the first metal layer (101) is located on the side of the second metal layer (140) facing away from the substrate (10).

12. The array substrate according to claim 10, wherein: The array substrate further comprises a plurality of data lines (DL), wherein the data lines (DL) are connected to the thin film transistors (Q) in the sub-pixel regions in the same column; The orthographic projection of the second metal layer (140) on the substrate (10) does not overlap with the orthographic projection of the data line on the substrate (10).

13. The array substrate according to claim 1, wherein: It comprises a plurality of channels (114), wherein the plurality of channels (114) and the pixel electrode layer (102) are located on different sides of the via hole (11).

14. The array substrate according to claim 1, wherein: The orthographic projection of the channel (114) on the substrate (10) includes at least one of a folded line shape, a straight line shape, and a curved line shape.

15. The array substrate according to any one of claims 1 to 12, characterized in that: The height of the bottom of the channel (114) close to the orifice is smaller than the height of the bottom of the channel (114) away from the orifice; The height is the distance between the bottom of the channel (114) and the substrate (10) in the thickness direction of the substrate (10).

16. The array substrate according to claim 1, wherein: The via hole (11) comprises: a first sub-hole (111), located in the flat layer (70); a second sub-hole (112) located in the passivation layer (90), wherein an orthographic projection of the second sub-hole (112) on the substrate (10) falls within an orthographic projection of the first sub-hole on the substrate (10); Wherein, at least the orthographic projection of the second sub-hole on the substrate (10) includes a plurality of rounded corners.

17. A display panel, characterized in that: The invention comprises a first substrate and a second substrate arranged opposite to each other, and a liquid crystal (300) located between the first substrate (100) and the second substrate (200), wherein the first substrate (100) is configured as an array substrate according to any one of claims 1 to 16; Wherein, an alignment layer (120) is included between the first substrate and the liquid crystal, and the alignment layer (120) includes a portion located in the via hole (11) of the array substrate.

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