Array circuit with high display quality and liquid crystal display
By electrically connecting the data line to the drain of the pixel transistor in a liquid crystal display in a stepped manner, column flip control is achieved, which solves the problem of increased power consumption caused by changes in the polarity of the data line and improves the display quality and product competitiveness.
Patent Information
- Application Number
- CN202422807943.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-18
AI Technical Summary
When existing liquid crystal displays undergo dot flipping, the polarity of the data line changes, resulting in increased power consumption and reduced product competitiveness.
By electrically connecting the data lines to the transistor drains of the pixels in the pixel array in a stepwise manner, column flipping control is achieved, thereby reducing display power consumption.
While ensuring display quality, it reduces display power consumption and improves product competitiveness.
Smart Images
Figure CN223450545U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to liquid crystal display polarity reversal technical field, especially relates to a high display quality's array circuit and liquid crystal display. BACKGROUND
[0002] With the development of display technology, liquid crystal display (Liquid Crystal Display, for short LCD) gradually replaces cathode ray tube (Cathode Ray Tube, for short CRT) display device due to the advantages of light, thin and low radiation, and becomes the most common display device in computer, smart phone, mobile phone, car navigation device, electronic book and other information terminals. The panel of liquid crystal display mainly includes array substrate and color film substrate that are boxed together and sandwich liquid crystal therebetween, wherein the array substrate is formed with scanning line, data line, pixel electrode and thin film transistor, and the color film substrate is formed with common electrode, and the pixel electrode and the corresponding common electrode constitute a pixel. Each pixel electrode is controlled by the thin film transistor, and when the thin film transistor is opened, the pixel is charged in the opening time, and after the thin film transistor is turned off, the pixel voltage will be maintained until the next scanning time to be recharged.
[0003] The polarity of the pixel array in the panel of the liquid crystal display cannot be fixed at a certain value, otherwise, the liquid crystal molecules in the liquid crystal display will have polarization phenomenon, thereby gradually losing the optical rotation characteristic, in order to avoid the characteristic of the liquid crystal molecules being destroyed, the pixel array must be polarity reversed. The commonly used driving modes include dot inversion, column inversion, line inversion and the like.
[0004] Compared with other driving modes, the dot inversion mode has higher display quality, but when the dot inversion mode is used, the data line polarity is always in the polarity change state, so that the power consumption data increases, and the product competitiveness is reduced. SUMMARY
[0005] The existing liquid crystal display panel has the problem that when the dot inversion is carried out, the data line polarity is always in the polarity change state, so that the power consumption data increases, and the product competitiveness is reduced.
[0006] In view of the above problem, the application provides a high display quality array circuit and liquid crystal display, which realizes dot inversion when carrying out column inversion control by stepwise electrically connecting the data line and the transistor drain of the pixel in the pixel array, so as to reduce the display power consumption while ensuring the display quality.
[0007] In a first aspect, a high display quality array circuit comprises:
[0008] A plurality of gate scanning lines;
[0009] A plurality of data lines;
[0010] a plurality of pixel units;
[0011] pixels in the plurality of pixel units are arranged to form a pixel array;
[0012] the plurality of gate scanning lines are respectively electrically connected with the gate electrodes of the corresponding pixel triodes in the pixel array for scanning driving;
[0013] the plurality of data lines are respectively electrically connected with the drain electrodes of the pixel triodes in different columns of the pixel array in sequence.
[0014] In combination with the array circuit with high display quality of the first aspect of the utility model, in a first possible implementation, the pixel unit comprises:
[0015] an R pixel and its triode, a G pixel and its triode, and a B pixel and its triode;
[0016] the R pixel and its triode, the G pixel and its triode, and the B pixel and its triode in each pixel unit are arranged laterally;
[0017] the plurality of gate scanning lines are respectively electrically connected with the gate electrodes of the triode of the R pixel, the triode of the G pixel, and the triode of the B pixel in each row.
[0018] In combination with the array circuit with high display quality of the first aspect of the utility model, in a second possible implementation, the pixel unit comprises:
[0019] an R pixel and its triode, a G pixel and its triode, and a B pixel and its triode;
[0020] the R pixel and its triode, the G pixel and its triode, and the B pixel and its triode in each pixel unit are arranged longitudinally;
[0021] the plurality of gate scanning lines are respectively electrically connected with the gate electrodes of the triode of each:
[0022] R pixel row
[0023] or
[0024] G pixel row
[0025] or
[0026] B pixel row
[0027] .
[0028] In combination with the first or second possible implementation of the first aspect of the utility model, in a third possible implementation, the plurality of data lines are respectively and in sequence stepwise electrically connected with the drain electrodes of the pixel triodes in the pixel array.
[0029] In combination with the third possible implementation manner of the first aspect of the present application, in the fourth possible implementation manner, the plurality of data lines are sequentially and stepwise electrically connected to the drain electrodes of the pixel triodes in the pixel array in the first direction, the slope of the connecting dotted line of the drain electrode of the pixel triode in the first direction is less than zero, and the longest connecting dotted line is the first diagonal line of the pixel array.
[0030] In combination with the third possible implementation manner of the first aspect of the present application, in the fifth possible implementation manner, the plurality of data lines are sequentially and stepwise electrically connected to the drain electrodes of the pixel triodes in the pixel array in the second direction, the slope of the connecting dotted line of the drain electrode of the pixel triode in the second direction is greater than zero, and the longest connecting dotted line is the second diagonal line of the pixel array.
[0031] The second aspect relates to a liquid crystal display comprising the array circuit with high display quality.
[0032] The array circuit with high display quality and the liquid crystal display are implemented, the data lines are sequentially and stepwise electrically connected to the drain electrodes of the pixel triodes in the pixel array, so that point inversion can be realized when column inversion control is performed, the display quality is ensured, and the display power consumption is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0034] Figure 1 is a schematic diagram of the array circuit with high display quality in the present application;
[0035] Figure 2 is a schematic diagram of the polarity of the first inversion of the array circuit with high display quality in the present application;
[0036] Figure 3 is a schematic diagram of the polarity of the second inversion of the array circuit with high display quality in the present application;
[0037] Figure 4 is a schematic diagram of the first diagonal line in the first direction of the array circuit with high display quality in the present application;
[0038] Figure 5 is a schematic diagram of the second diagonal line in the second direction of the array circuit with high display quality in the present application. DETAILED DESCRIPTION
[0039] The technical solutions in the utility model will be clearly and completely described below in combination with the drawings in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the utility model belongs. The terms used in the specification of the utility model are only for the purpose of describing specific embodiments and are not intended to limit the utility model. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0041] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0042] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.
[0043] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0044] The existing liquid crystal display panel is in a polarity change state when point flipping, so that the power consumption data increases, and the product competitiveness is reduced.
[0045] In order to solve the above problems, the application provides an array circuit and a liquid crystal display with high display quality. The data line (SL, S1, S2, S3, S4, S5, S6, SR) is connected to the triode drain of the pixel in the pixel array in a ladder shape. When the column inversion control is performed, the dot inversion can be realized, the display quality is ensured, and the display power consumption is reduced.
[0046] In a first aspect, the application provides an array circuit with high display quality. The array circuit comprises a plurality of gate scanning lines (G1, G2, G3, G4, G5), a plurality of data lines (SL, S1, S2, S3, S4, S5, S6, SR), and a plurality of pixel units. The pixels in the plurality of pixel units are arranged to form a pixel array. The plurality of gate scanning lines (G1, G2, G3, G4, G5) are respectively connected to the gate of the triode of the corresponding pixel in the pixel array to perform scanning driving. The plurality of data lines (SL, S1, S2, S3, S4, S5, S6, SR) are respectively connected to the drain of the triode of the pixel in different columns of the pixel array.
[0047] The gate scanning line (G1, G2, G3, G4, G5) performs scanning driving. The pixel unit comprises an R pixel, a G pixel, and a B pixel. The gate scanning line (G1, G2, G3, G4, G5) is connected to the gate of the triode of the R pixel, the G pixel, and the B pixel. The data line (SL, S1, S2, S3, S4, S5, S6, SR) is connected to the drain of the triode of the R pixel, the G pixel, and the B pixel.
[0048] In the embodiment, the data line (SL, S1, S2, S3, S4, S5, S6, SR) is connected to the drain of the triode of the pixel in the pixel array in a ladder shape. That is, the data line (SL, S1, S2, S3, S4, S5, S6, SR) is connected to the drain of the triode of the pixel in different columns in sequence. The connection is in a ladder shape.
[0049] In a preferred embodiment, the pixel unit comprises an R pixel and its triode, a G pixel and its triode, and a B pixel and its triode. The R pixel and its triode, the G pixel and its triode, and the B pixel and its triode in each pixel unit are arranged horizontally. The plurality of gate scanning lines (G1, G2, G3, G4, G5) are respectively connected to the gate of the triode of the R pixel, the G pixel, and the B pixel in each row.
[0050] In the embodiment, the pixels in each column of the pixel array are the same. The pixels in each row are arranged in sequence.
[0051] In a preferred embodiment, the pixel unit comprises: an R pixel and its triode, a G pixel and its triode, a B pixel and its triode; the R pixel and its triode, the G pixel and its triode, and the B pixel and its triode in each pixel unit are arranged longitudinally; a plurality of gate scanning lines (G1, G2, G3, G4, G5) are electrically connected with the gate of the triode of each R pixel row, the triode of each G pixel row, or the triode of each B pixel row, respectively.
[0052] In the embodiment, the pixels in each row of the pixel array are the same, and the pixels in each column are arranged in sequence.
[0053] In a preferred embodiment, as Figure 1 , Figure 1 is a schematic diagram of the array circuit with high display quality in the utility model; a plurality of data lines (SL, S1, S2, S3, S4, S5, S6, SR) are electrically connected with the drain of the pixel triode in the pixel array in sequence. The plurality of data lines (SL, S1, S2, S3, S4, S5, S6, SR) are electrically connected with the drain of the pixel triode in the first direction of the pixel array in sequence, the slope of the connecting dotted line of the drain of the pixel triode in the first direction is less than zero, and the longest connecting dotted line is the first diagonal line of the pixel array, as Figure 4 , Figure 4 is a schematic diagram of the first diagonal line in the first direction of the array circuit with high display quality in the utility model.
[0054] In the embodiment, since the connection is in a ladder connection, the connecting dotted line connects the triode of the pixels in different columns, and when the ladder column is flipped, only the polarity of the pixels on the connecting dotted line in the first direction is the same, as Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the first flipped polarity of the array circuit with high display quality in the utility model; Figure 3 is a schematic diagram of the second flipped polarity of the array circuit with high display quality in the utility model.
[0055] In the embodiment, the connecting dotted line is only used to illustrate the ladder trend and belongs to a non-existent connecting line.
[0056] In a preferred embodiment, the plurality of data lines are electrically connected with the drain of the pixel triode in the second direction of the pixel array in sequence, the slope of the connecting dotted line of the drain of the pixel triode in the second direction is greater than zero, and the longest connecting dotted line is the second diagonal line of the pixel array, as Figure 5 , Figure 5 is a schematic diagram of the second diagonal line in the second direction of the array circuit with high display quality in the utility model.
[0057] In the embodiment, since the connection of the step connection is the triode of the pixels of different columns, only the polarity of the pixels on the connection dotted line in the second direction is the same when the step column flip is performed, like Figure 2 and Figure 3 , Figure 2 is the polarity schematic diagram of the first flip of the high display quality array circuit in the utility model; Figure 3 is the polarity schematic diagram of the second flip of the high display quality array circuit in the utility model.
[0058] In the second aspect, a liquid crystal display comprises the high display quality array circuit of the first aspect.
[0059] The high display quality array circuit and the liquid crystal display of the utility model are implemented by the step connection of the data line and the triode drain of the pixels in the pixel array, so that the dot flip can be realized when the column flip control is performed, the display quality is ensured, and the display power consumption is reduced.
[0060] The above is only the preferred embodiment of the utility model, and does not limit the utility model, and any modification, equivalent replacement, improvement, etc. within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. An array circuit with high display quality, characterized in that: include: a plurality of gate scanning lines; Multiple data lines; multiple pixel units; The pixels in the plurality of pixel units are arranged to form a pixel array; The plurality of gate scanning lines are respectively electrically connected to the gates of the corresponding pixel transistors in the pixel array to perform scanning driving; The plurality of data lines are electrically connected to the drain electrodes of the pixel transistors in different columns in the pixel array in sequence.
2. The array circuit with high display quality according to claim 1, characterized in that: The pixel unit includes: R pixel and its transistor, G pixel and its transistor, B pixel and its transistor; The R pixel and its triode, the G pixel and its triode, and the B pixel and its triode in each pixel unit are arranged horizontally; The plurality of gate scanning lines are electrically connected to the gates of the triodes of the R pixels, the triodes of the G pixels, and the triodes of the B pixels in each row, respectively.
3. The array circuit with high display quality according to claim 1, wherein: The pixel unit includes: R pixel and its transistor, G pixel and its transistor, B pixel and its transistor; The R pixel and its triode, the G pixel and its triode, and the B pixel and its triode in each pixel unit are arranged vertically; The plurality of gate scanning lines are respectively connected to each: R pixel row transistor or G pixel row transistor or The gates of the transistors in the B pixel row are electrically connected.
4. The array circuit with high display quality according to claim 2 or 3, characterized in that: The plurality of data lines are respectively and sequentially electrically connected to the drain electrodes of the pixel transistors in the pixel array in a stepwise manner.
5. The array circuit with high display quality according to claim 4, characterized in that: The multiple data lines are respectively and sequentially electrically connected in a stepped manner to the drains of the pixel transistors in a first direction in the pixel array, the slope of the drain connection dotted line of the pixel transistors in the first direction is less than zero, and the longest connection dotted line is the first diagonal line of the pixel array.
6. The array circuit with high display quality according to claim 4, characterized in that: The multiple data lines are respectively and sequentially electrically connected in a stepped manner to the drains of the pixel transistors in the second direction in the pixel array, the slope of the drain connection dotted line of the pixel transistors in the second direction is greater than zero, and the longest connection dotted line is the second diagonal line of the pixel array.
7. A liquid crystal display, characterized in that: An array circuit with high display quality comprising the array circuit according to any one of claims 1 to 6.