485 one-master multi-slave communication circuit based on data recorder

Abstract

The utility model discloses a 485 one-master multi-slave communication circuit based on a data recorder, and relates to the technical field of data recorders, a slave CPU is connected with a DI in a 485 chip U2 through a No.4 line, the CPU is connected with a DE in the 485 chip U2 through a No.3 line, the CPU is connected with an RO in the 485 chip U2 through a No.1 line, an RE in the 485 chip U2 is connected with a No.2 line, the No.2 line and the No.3 line are connected in parallel through a line, and the line is connected with the ground. The DE and the RE in the slave CPU are pulled down to the ground through the resistor, the receiver output of the 485 chip U2 is enabled, the RO output is effective, the receiving output end RO of the U2 changes along with the data of the bus, the level of the bus A and the level of the bus B are not affected, and then the data receiving of the main CPU is not affected, so that the situation that the whole data recorder system is abnormal due to certain unknown interference in the prior art is avoided, and the reliability of the data recorder is improved. And therefore, all data loss is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to data recorder technical field, concretely is a kind of 485 one master multi-slave communication circuit based on data recorder. BACKGROUND

[0002] 485 communication network is a kind of digital multipoint system using differential balanced transmission, generally adopts master-slave communication mode, that is, one host computer carries multiple slaves, and the host computer and multiple slaves adopt half-duplex communication mode, so 485 communication is widely used with the advantages of low cost and simple design.

[0003] At present, 485 communication network mostly adopts the mode that host computer inquires slave response, that is, host computer polls slave on bus one by one, and slave responds to host computer according to polling mechanism, so as to avoid signal conflict on bus caused by simultaneous sending of multiple slaves in 485 communication network.

[0004] However, in actual application, data loss phenomenon of all slave devices will occur due to abnormality of one slave. For example, 64-way data recorder has 8 built-in acquisition modules, each acquisition module has a single-chip microcomputer for communication with host CPU. When one module fails, 485 bus will be occupied, and data cannot be transmitted and received in time, so that other normal modules cannot work normally. As data recorder, it is necessary to record measured object for a long time, which will cause data recorder to be unable to work normally, waste time and cause waste of production resources. Therefore, technical innovation and design optimization are needed to optimize the 485 one master multi-slave communication circuit based on data recorder. CONTENT OF UTILITY MODEL

[0005] To solve the above problems, the present application provides a kind of 485 one master multi-slave communication circuit based on data recorder, DE and RE in slave CPU are pulled down to ground through resistance, enable of receiver output of 485 chip U2 is enabled, RO output is valid, and the level of bus A and B is not affected by the change of data of the receiving output end RO of U2, so that the host CPU receiving data is not affected, so that the whole data recorder system is abnormal due to unknown interference before, and data loss is avoided.

[0006] The technical scheme adopted by the embodiment of the present application to solve the technical problem is:

[0007] A kind of 485 one master multi-slave communication circuit based on data recorder, comprising:

[0008] The host CPU module is connected with 485 bus;

[0009] A plurality of acquisition boards, and a plurality of the connecting plates are connected with 485 bus.

[0010] In a possible implementation, the main CPU module comprises a main CPU and a 485 chip U1, and the 485 bus comprises a 485A line and a 485B line.

[0011] In a possible implementation, the main CPU is connected with DI in the 485 chip U1 through a No. 4 line, the main CPU is connected with DE in the 485 chip U1 through a No. 3 line, the main CPU is connected with RO in the 485 chip U1 through a No. 1 line, a No. 2 line and the No. 3 line are connected in series with a resistor, the No. 1 line is connected in series with a resistor, the two resistors are connected in parallel with each other and connected with a power supply.

[0012] In a possible implementation, GND in the 485 chip U1 is connected with the ground through a No. 5 line, A in the 485 chip U1 is connected with the 485A line through a No. 6 line, a resistor is connected in series on the No. 6 line, the No. 6 line is connected with the power supply through a line, a resistor is arranged on the line, B in the 485 chip U1 is connected with the 485B line through a No. 7 line, a resistor is arranged on the No. 7 line, the No. 7 line is connected with the ground through a line, a resistor is arranged on the line, VCC in the 485 chip U1 is connected with the power supply through a No. 8 line.

[0013] In a possible implementation, the collection board comprises a 485 chip U2 and a slave CPU.

[0014] In a possible implementation, the slave CPU is connected with DI in the 485 chip U2 through a No. 4 line, the CPU is connected with DE in the 485 chip U2 through a No. 3 line, the CPU is connected with RO in the 485 chip U2 through a No. 1 line, RE in the 485 chip U2 is connected with a No. 2 line, the No. 2 line and the No. 3 line are connected in parallel through a line, the line is connected with the ground, a resistor is arranged on the line, DE and RE are pulled down to the ground through a resistor R9, the receiver output of the 485 chip U2 is enabled, the RO output is valid, and the RO of U2 changes with the data of the bus.

[0015] In a possible implementation, GND in the 485 chip U2 is connected with the ground through a No. 5 line, A in the 485 chip U2 is connected with the 485A line through a No. 6 line, a resistor is arranged on the No. 6 line, B in the 485 chip U2 is connected with the 485B line through a No. 7 line, a resistor is arranged on the No. 7 line, VCC in the 485 chip U2 is connected with an electrical element through a No. 8 line.

[0016] In summary, the utility model has at least one of the following beneficial technical effects:

[0017] 1. When the main CPU communicates with normal modules such as slave CPU 2, the first slave CPU is always in receiving mode and does not send out unordered interference signals when another slave CPU sends collected data, so that other road collection modules can still operate normally, thereby avoiding the previous abnormality of the entire data recorder system caused by unknown interference, and further avoiding the loss of all data.

[0018] 2. The DE and RE in the slave CPU are pulled down to the ground through a resistor, enabling the receiver output of the 485 chip U2 and the RO output, and the RO output of U2 does not affect the levels of bus A and B, and further does not affect the main CPU to receive data. BRIEF DESCRIPTION OF DRAWINGS

[0019] Fig. 1 is a schematic diagram of the overall structure of the utility model;

[0020] Fig. 2 is a schematic diagram of the circuit of the utility model; DETAILED DESCRIPTION

[0021] The technical solutions in the utility model will be described clearly and completely in combination with the drawings in the utility model, and the forms of each structure described in the following embodiments are only examples, and the appliance rack involved in the utility model is not limited to each structure described in the following embodiments, and all other embodiments obtained by the person skilled in the art without making creative efforts belong to the protection scope of the utility model.

[0022] The embodiment introduces a specific structure of a 485 one-master multi-slave communication circuit based on a data recorder, and specifically refers to Figs. 1-2 The 485 one-master multi-slave communication circuit based on a data recorder comprises:

[0023] A main CPU module is connected with a 485 bus.

[0024] A plurality of collection boards are connected with the 485 bus.

[0025] Further, the main CPU module comprises a main CPU and a 485 chip U1, and the 485 bus comprises a 485A line and a 485B line.

[0026] Further, the main CPU is connected with DI in the 485 chip U1 through a No. 4 line, the main CPU is connected with DE in the 485 chip U1 through a No. 3 line, the main CPU is connected with RO in the 485 chip U1 through a No. 1 line, a resistor is connected in series between a No. 2 line and a No. 3 line, a resistor is connected in series with a No. 1 line, and the two resistors are connected in parallel with a power supply.

[0027] Further, the GND in the 485 chip U1 is connected with the ground through the No.5 line, the A in the 485 chip U1 is connected with the 485A line through the No.6 line, and a resistor is connected in series on the No.6 line, the No.6 line is connected with the power supply through a line, and a resistor is arranged on the line, the B in the 485 chip U1 is connected with the 485B line through the No.7 line, a resistor is arranged on the No.7 line, the No.7 line is connected with the ground through a line, and a resistor is arranged on the line, and the VCC in the 485 chip U1 is connected with the power supply through the No.8 line.

[0028] Further, the collection board comprises a 485 chip U2 and a slave CPU.

[0029] When a single-chip microcomputer of the collection board is reset or abnormal, for example, the slave CPU 1 is abnormal, the pin of the slave CPU 1 is in a high resistance state, since the DE and RE are pulled down to the ground through the resistor R9 at this time, the receiver output of the 485 chip U2 is enabled, the RO output is valid, the RO of the U2 changes with the data of the bus, and meanwhile, the levels of the bus A and B are not affected.

[0030] Further, the slave CPU is connected with the DI in the 485 chip U2 through the No.4 line, the slave CPU is connected with the DE in the 485 chip U2 through the No.3 line, the slave CPU is connected with the RO in the 485 chip U2 through the No.1 line, the RE in the 485 chip U2 is connected with the No.2 line, the No.2 line and the No.3 line are connected in parallel through a line, the line is connected with the ground, and a resistor is arranged on the line, the DE and the RE are pulled down to the ground through the resistor R9, the receiver output of the 485 chip U2 is enabled, the RO output is valid, and the RO of the U2 changes with the data of the bus.

[0031] Further, the GND in the 485 chip U2 is connected with the ground through the No.5 line, the A in the 485 chip U2 is connected with the 485A line through the No.6 line, a resistor is arranged on the No.6 line, the B in the 485 chip U2 is connected with the 485B line through the No.7 line, a resistor is arranged on the No.7 line, and the VCC in the 485 chip U2 is connected with the electrical element through the No.8 line.

[0032] When an exception occurs from the CPU, the pin of the CPU is in a high resistance state, and since DE and RE are pulled down to the ground through the resistance at this time, the receiver output enable of the 485 chip U2 is enabled, the RO output is valid, the receiving output end RO of U2 changes with the data of the bus, and does not affect the level of the bus A and B, and since DE is in a low level output and is in a high resistance state, it also does not affect the level of the bus A and B. When the main CPU communicates with a normal module such as the slave CPU 2, and another slave CPU sends the collected data, since the first slave CPU is always in a receiving mode, it will not send an unordered interference signal, so that other road collection modules can still operate normally. The slave CPU single-chip microcomputer of the collection board can still normally collect data after being successfully reset, thereby avoiding the abnormality of the entire data recorder system caused by some unknown interference in the past, and avoiding the loss of all data.

[0033] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the utility model, and are not limited to the implementation. For ordinary skilled persons in the art, other different forms of changes or variations can be made on the basis of the above description. Here, it is not necessary and impossible to exhaust all the implementation. The obvious changes or variations derived therefrom are still within the protection scope of the utility model.

Claims

1. A 485 master multi-slave communication circuit based on a data logger, characterized by, The utility model relates to a kind of 485 acquisition system, including: Main CPU module, which is connected with 485 bus; Several acquisition boards, and several acquisition boards are connected with 485 bus; The main CPU is connected with DI in 485 chip U1 by No.4 line, the main CPU is connected with DE in 485 chip U1 by No.3 line, the main CPU is connected with RO in 485 chip U1 by No.1 line, No.2 line and No.3 line are connected with a resistor in series, No.1 line is connected with a resistor in series, two resistors are connected with power supply in parallel with each other; GND in 485 chip U1 is connected with ground by No.5 line, A in 485 chip U1 is connected with 485A line by No.6 line, and resistor is connected in series on No.6 line, No.6 line is connected with power supply by line, resistor is arranged on the line, B in 485 chip U1 is connected with 485B line by No.7 line, resistor is arranged on No.7 line, No.7 line is connected with ground by line, resistor is arranged on the line, VCC in 485 chip U1 is connected with power supply by No.8 line.

2. A 485 master multi-slave communication circuit based on a data logger as claimed in claim 1, characterized in that: The main CPU module includes main CPU and 485 chip U1, and the 485 bus includes 485A line and 485B line.

3. A 485 master multi-slave communication circuit based on a data logger as claimed in claim 1, characterized in that: The acquisition board includes 485 chip U2 and slave CPU.

4. A 485 master multi-slave communication circuit based on a data logger as claimed in claim 3, characterized in that: The slave CPU is connected with DI in 485 chip U2 by No.4 line, the CPU is connected with DE in 485 chip U2 by No.3 line, the CPU is connected with RO in 485 chip U2 by No.1 line, RE in 485 chip U2 is connected with No.2 line, No.2 line and No.3 line are connected in parallel by line, the line is connected with ground, and resistor is arranged on the line.

5. A 485 master multi-slave communication circuit based on a data logger as claimed in claim 4, characterized in that: GND in 485 chip U2 is connected with ground by No.5 line, A in 485 chip U2 is connected with 485A line by No.6 line, resistor is arranged on No.6 line, B in 485 chip U2 is connected with 485B line by No.7 line, resistor is arranged on No.7 line, VCC in 485 chip U2 is connected with electrical element by No.8 line.

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