Electrical measurement circuit of display panel
By designing an electrical testing circuit for performing interval testing on the gate drive circuits of odd and even rows in a display panel, the problem of high missed detection rate is solved and the yield of the display panel is improved.
Patent Information
- Application Number
- CN202422481667.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-10-14
AI Technical Summary
Existing electrical testing solutions for display panels suffer from a high missed detection rate, which results in a decrease in yield.
An electrical testing circuit design is adopted to perform interval testing on the gate driving circuits of odd and even rows. The first and second electrical testing units are respectively connected to the gate driving circuits of odd and even rows at intervals, thereby realizing effective detection of short circuits of adjacent row gate lines.
It effectively reduces the missed inspection rate, improves the yield rate of display panels, prevents defective products from entering subsequent processes, and improves product quality.
Smart Images
Figure CN223486087U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electrical measurement technology for display panels, and in particular to an electrical measurement circuit for display panels. Background Technology
[0002] In recent years, display devices have shown a trend towards high integration and low cost. To achieve low cost and narrow bezels, existing display panels mostly adopt GOA (Gate driver on Array) technology, which directly fabricates the gate driver circuit on the array substrate. This eliminates the space occupied by IC bonding and fan-out areas, resulting in cost reductions in materials and manufacturing processes, as well as narrower bezels on both sides of the gate lines of the display panel. However, short circuits can easily occur between traces in GOA products, leading to display malfunctions.
[0003] To effectively detect display panel malfunctions, test circuits are typically installed in the terminal area of the Thin Film Transistor (TFT) substrate. These test circuits are designed with multiple test pads. After the TFT substrate and color filter (CF) substrate are assembled into a liquid crystal cell, test signals are connected to the test pads using a jig probe, which illuminates the panel and thus detects display malfunctions.
[0004] However, existing electrical testing solutions suffer from high false negative rates due to improper settings of the electrical testing circuits and testing points. This results in defective products flowing to subsequent processes, leading to significant product waste and reduced display quality. Utility Model Content
[0005] Existing LCD panels have a high rate of missed detections and a low yield rate during testing.
[0006] To address the aforementioned issues, an electrical testing circuit for display panels is proposed. By performing interval tests on the gate driving circuits of odd-numbered rows and even-numbered rows, short circuits in adjacent odd-numbered or even-numbered row gate lines can be effectively detected, thus solving the problem of high false negative rates and decreased yield during the testing of liquid crystal display panels.
[0007] An electrical testing circuit for a display panel, comprising:
[0008] First electrical measurement unit;
[0009] Second electrical measurement unit;
[0010] The first electrical testing unit is connected at intervals to the odd-numbered row gate driving circuit of the array circuit of the display panel, and is used to perform interval testing on the odd-numbered row gate driving circuit;
[0011] The second electrical testing unit is connected at intervals to the even-numbered row gate driving circuit of the array circuit of the display panel, and is used to perform interval testing on the even-numbered row gate driving circuit.
[0012] In conjunction with the electrical testing circuit of the display panel described in this utility model, in a first possible embodiment, the first electrical testing unit includes:
[0013] First electrical test trace;
[0014] Second electrical test trace;
[0015] The first group of electrical measurement points;
[0016] The second group of electrical testing points;
[0017] The first electrical test trace is electrically connected to the gate of the odd-numbered array of gate lines of the odd-numbered row gate drive circuit through the first set of electrical test points.
[0018] The second electrical test trace is electrically connected to the gate of the even array of gate lines of the odd-numbered row gate drive circuit through the second set of electrical test points.
[0019] In conjunction with the first possible embodiment of this utility model, in the second possible embodiment, the second electrical measuring unit includes:
[0020] Third electrical test wiring;
[0021] Fourth electrical test wiring;
[0022] The third group of electrical measurement points;
[0023] The fourth group of electrical testing points;
[0024] The third electrical test trace is electrically connected to the gate of the odd-numbered array of gate lines of the even-numbered row gate drive circuit through the third set of electrical test points.
[0025] The fourth electrical test trace is electrically connected to the gate of the even-numbered array of gate lines of the even-numbered row gate drive circuit through the fourth set of electrical test points.
[0026] In conjunction with the first possible embodiment of this utility model, in the third possible embodiment, the first electrical measuring unit further includes:
[0027] First test pad;
[0028] Second test pad;
[0029] The first test pad is electrically connected to the first electrical test trace;
[0030] The second test pad is electrically connected to the second electrical test trace.
[0031] In conjunction with the third possible embodiment of this utility model, and in the fourth possible embodiment, the second electrical measuring unit further includes:
[0032] Third test pad;
[0033] Fourth test pad;
[0034] The third test pad is electrically connected to the third electrical test trace;
[0035] The fourth test pad is electrically connected to the fourth electrical test trace.
[0036] In conjunction with the fourth and fifth possible embodiments of this utility model, the odd-numbered row gate driving circuit and the even-numbered row gate driving circuit are respectively wired on both sides of the display panel and electrically connected to the driving IC of the display panel.
[0037] By implementing the electrical testing circuit of the display panel described in this utility model, and performing interval testing on the odd-numbered row gate driving circuit and the even-numbered row gate driving circuit, even if a short circuit occurs in adjacent odd-numbered or even-numbered row gate lines, it can be effectively detected, thus solving the problem of high false negative rate and decreased yield when testing liquid crystal display panels. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a schematic diagram of the gate driving circuit of a display panel in the prior art;
[0040] Figure 2 This is a schematic diagram of the electrical measurement circuit for the odd-numbered rows of gate drive lines in a display panel in the prior art.
[0041] Figure 3 This is a schematic diagram of the electrical measurement circuit for the even-numbered rows of the gate drive lines in a display panel in the prior art.
[0042] Figure 4 This is a schematic diagram of the electrical measurement circuit for the odd-numbered rows of the gate drive lines of the display panel in this utility model.
[0043] Figure 5 This is a schematic diagram of the electrical measurement circuit for the even-numbered rows of the gate drive circuit of the display panel in this utility model. Detailed Implementation
[0044] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.
[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0046] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0047] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.
[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.
[0049] Existing LCD panels have a high rate of missed detections and a low yield rate during testing.
[0050] To address the above problems, an electrical measurement circuit for a display panel is proposed.
[0051] An electrical testing circuit for a display panel includes a first electrical testing unit and a second electrical testing unit; the first electrical testing unit is connected at intervals to the odd-numbered row gate driving circuits of the array circuit of the display panel, and is used to perform interval testing on the odd-numbered row gate driving circuits; the second electrical testing unit is connected at intervals to the even-numbered row gate driving circuits of the array circuit of the display panel, and is used to perform interval testing on the even-numbered row gate driving circuits.
[0052] like Figure 1 , Figure 1 This is a schematic diagram of the gate driving circuit of a display panel in the prior art; the odd-numbered row gate driving lines include G1, G3, G5, G7, G9, ..., and the even-numbered row gate driving lines include G2, G4, G6, G8, G10, ... The odd-numbered row gate driving lines and the even-numbered row gate driving lines are respectively arranged on both sides of the display panel. Adjacent odd-numbered row gate driving lines and even-numbered row gate driving lines are prone to short circuits in the fanout area.
[0053] In existing technologies, such as Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the electrical measurement circuit for the odd-numbered rows of gate drive lines in a display panel in the prior art. Figure 3 This is a schematic diagram of the electrical measurement circuit for the even-numbered rows of the gate drive lines in a display panel in the prior art.
[0054] If there is a short circuit between two adjacent rows of gate drive lines in the Fanout area of the display, for example, G1 and G3 are short-circuited in the Fanout area, using Figure 2 The electrical testing method cannot detect it because VGG-ODD will turn on all the gate drive lines on the left side and charge and discharge all the odd rows of the display panel, so there is a possibility of missing detection.
[0055] In this embodiment, by performing interval tests on the odd-numbered row gate driving circuits and the even-numbered row gate driving circuits, short circuits in adjacent odd-numbered or even-numbered row gate lines can be effectively detected, solving the problem of high false negative rates and decreased yield during testing of liquid crystal display panels. Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of the electrical measurement circuit for the odd-numbered rows of the gate drive lines of the display panel in this utility model. Figure 5 This is a schematic diagram of the electrical measurement circuit for the even-numbered rows of the gate driving circuit in the display panel of this utility model. The first electrical measurement unit and the second electrical measurement unit are used to drive the odd-numbered row gate driving circuit and the even-numbered row gate driving circuit at intervals.
[0056] Specifically, such as Figure 4The first electrical measurement unit includes a first electrical measurement trace 110, a second electrical measurement trace 120, a first set of electrical measurement points 130, and a second set of electrical measurement points 140. The first electrical measurement trace 110 is electrically connected to the gates of the odd-numbered row gate driving circuit through the first set of electrical measurement points 130. The second electrical measurement trace 120 is electrically connected to the gates of the even-numbered row gate driving circuit through the second set of electrical measurement points 140.
[0057] In this embodiment, the first electrical test trace 110 is electrically connected to G1, G5, G9, ... in the odd-numbered rows, and the second electrical test trace 120 is electrically connected to G3, G7, ... in the odd-numbered rows. If G1 and G3 are short-circuited in the Fanout region, ... Figure 4 The electrical testing circuit can detect this. The specific principle is as follows: When the first electrical test trace 110 (VGG-ODD1) is turned on at a high level, only the rows containing G1, G5, G9, etc. are lit, while the rows containing G3, G7, etc. are not lit. If G1 and G3 are short-circuited, then the row containing G3 will also be lit. At this time, relevant personnel can quickly determine the short-circuit status of this display screen and test whether there is an open circuit or other defects in the Fanout. This allows them to determine that the display screen is abnormal and will not proceed to the next process, thereby improving the product yield.
[0058] Specifically, the second electrical measurement unit includes a third electrical measurement trace 210, a fourth electrical measurement trace 220, a third group of electrical measurement points 230, and a fourth group of electrical measurement points 240; the third electrical measurement trace 210 is electrically connected to the gates of the odd-numbered array gate lines of the even-numbered row gate driving circuit through the third group of electrical measurement points 230; the fourth electrical measurement trace 220 is electrically connected to the gates of the even-numbered array gate lines of the even-numbered row gate driving circuit through the fourth group of electrical measurement points 240.
[0059] In this embodiment, the third electrical test trace 210 is electrically connected to G2, G6, G10, ... in the odd-numbered rows, and the fourth electrical test trace 220 is electrically connected to G4, G8, ... in the odd-numbered rows. If G2 and G4 are short-circuited in the Fanout region, ... Figure 5 The electrical testing circuit can detect this. The specific principle is as follows: When the third electrical test trace 210 (VGG-EVEN1) is turned on at a high level, only rows such as G2, G6, and G10 are lit, while rows such as G4 and G8 are not lit. If G2 and G4 are short-circuited, then the row containing G2 will also be lit. At this time, relevant personnel can quickly determine the short-circuit status of the display screen and test whether there is an open circuit or other defects in the Fanout. This allows them to determine that the display screen is abnormal and will not proceed to the next process, thereby improving the product yield.
[0060] Furthermore, the first electrical testing unit also includes a first test pad 150 and a second test pad 160; the first test pad 150 is electrically connected to the first electrical testing trace 110; and the second test pad 160 is electrically connected to the second electrical testing trace 120.
[0061] Furthermore, the second electrical testing unit also includes a third test pad 250 and a fourth test pad 260; the third test pad 250 is electrically connected to the third electrical testing trace 210; and the fourth test pad 260 is electrically connected to the fourth electrical testing trace 220.
[0062] The electrical testing circuit of the display panel implementing this utility model performs interval testing on the odd-numbered row gate driving circuit and the even-numbered row gate driving circuit. In this way, even if a short circuit occurs in the adjacent odd-numbered or even-numbered row gate lines, it can be effectively detected, thus solving the problem of high false negative rate and low yield when testing liquid crystal display panels.
[0063] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. An electrical testing circuit for a display panel, characterized in that, include: First electrical measurement unit; Second electrical measurement unit; The first electrical testing unit is connected at intervals to the odd-numbered row gate driving circuit of the array circuit of the display panel, and is used to perform interval testing on the odd-numbered row gate driving circuit; The second electrical testing unit is connected at intervals to the even-numbered row gate driving circuit of the array circuit of the display panel, and is used to perform interval testing on the even-numbered row gate driving circuit.
2. The electrical testing circuit for the display panel according to claim 1, characterized in that, The odd-numbered row gate driving circuit and the even-numbered row gate driving circuit are respectively wired on both sides of the display panel and electrically connected to the driving IC of the display panel.
3. The electrical testing circuit for the display panel according to claim 2, characterized in that, The first electrical measurement unit includes: First electrical test trace; Second electrical test trace; The first group of electrical measurement points; The second group of electrical testing points; The first electrical test trace is electrically connected to the gate of the odd-numbered array of gate lines of the odd-numbered row gate drive circuit through the first set of electrical test points. The second electrical test trace is electrically connected to the gate of the even array of gate lines of the odd-numbered row gate drive circuit through the second set of electrical test points.
4. The electrical testing circuit for the display panel according to claim 3, characterized in that, The second electrical measurement unit includes: Third electrical test wiring; Fourth electrical test wiring; The third group of electrical measurement points; The fourth group of electrical testing points; The third electrical test trace is electrically connected to the gate of the odd-numbered array of gate lines of the even-numbered row gate drive circuit through the third set of electrical test points. The fourth electrical test trace is electrically connected to the gate of the even-numbered array of gate lines of the even-numbered row gate drive circuit through the fourth set of electrical test points.
5. The electrical testing circuit for the display panel according to claim 3, characterized in that, The first electrical measurement unit also includes: First test pad; Second test pad; The first test pad is electrically connected to the first electrical test trace; The second test pad is electrically connected to the second electrical test trace.
6. The electrical testing circuit for the display panel according to claim 4, characterized in that, The second electrical measurement unit also includes: Third test pad; Fourth test pad; The third test pad is electrically connected to the third electrical test trace; The fourth test pad is electrically connected to the fourth electrical test trace.