Drive controller and display device

Abstract

The utility model relates to a driving controller and a display device. The driving controller includes: a luminance controller that calculates a load of an input image signal; an overcurrent control determiner comparing the load and a reference load, and outputting an enable signal corresponding to a result of comparing the load and the reference load; a current sensor receiving an input current through a first voltage line transmitting a first driving voltage, comparing the input current and a reference current in response to the enable signal, and outputting a first signal corresponding to a result of comparing the input current and the reference current; a switching circuit connected between a second voltage line and a first node, and adjusting a current flowing between the second voltage line and the first node in response to a gate control signal; and a current controller outputting the gate control signal corresponding to the current in response to the first signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0143723, filed on October 25, 2023, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure described herein relate to a display device including a drive controller. Background Technology

[0004] Electronic devices that provide images to users (such as smartphones, digital cameras, laptops, navigation systems, monitors, or smart TVs) include display devices for displaying images. The display device generates images and provides the generated images to the user via a screen.

[0005] The display device includes a display panel and a drive controller for controlling the display panel. Since the drive controller provides data signals to the display panel, and the current corresponding to the data signals is supplied to the pixels of the display panel, a given image can be displayed. Utility Model Content

[0006] Embodiments of this disclosure may provide a drive controller capable of preventing excessive power consumption of the display panel and a display device including the display panel.

[0007] According to an embodiment, the drive controller includes: a brightness controller that calculates the load of the input image signal; an overcurrent control determiner that compares the load and a reference load and outputs an enable signal corresponding to the result of comparing the load and the reference load; a current sensor that receives an input current through a first voltage line transmitting a first drive voltage, compares the input current and a reference current in response to the enable signal, and outputs a first signal corresponding to the result of comparing the input current and the reference current; a switching circuit connected between a second voltage line and a first node, and adjusts the current flowing between the second voltage line and the first node in response to a gate control signal; and a current controller that outputs a gate control signal corresponding to the current in response to the first signal.

[0008] In one embodiment, the switching circuit may include a current-regulating transistor connected between the second voltage line and the first node and configured to receive a gate control signal.

[0009] In one embodiment, when the current is an overcurrent, the current controller can output a gate control signal to reduce the current flowing through the current regulating transistor.

[0010] In this embodiment, the current-regulating transistor may be a field-effect transistor.

[0011] In one embodiment, the current controller may include a positive voltage generator that outputs a positive voltage in response to a first signal.

[0012] In an embodiment, the positive voltage generator may include: a transistor including a first electrode, a second electrode, and a gate electrode for receiving a first signal; a first resistor connected between a voltage line receiving a power supply voltage and the first electrode of the transistor; and a second resistor connected between the second electrode of the transistor and a ground terminal, wherein the positive voltage may be the voltage of the second electrode of the transistor.

[0013] In an embodiment, the current controller may further include a sensing resistor connected between the first node and the second node, and the current controller may output a gate control signal corresponding to the sum of the voltage and positive voltage of the first node.

[0014] In an embodiment, the current controller may further include: a first amplifier that outputs a sense voltage corresponding to the sum of the voltage and positive voltage of the first node; and a second amplifier that compares the sense voltage with a reference voltage and outputs a gate control signal corresponding to the result of comparing the sense voltage with the reference voltage.

[0015] In this embodiment, when the load is less than the reference load, the overcurrent control determiner can output an active level enable signal, and when the load is greater than the reference load, the overcurrent control determiner can output an inactive level enable signal.

[0016] In this embodiment, when the enable signal is at an active level, the current sensor can compare the input current and the reference current and output a first signal corresponding to the result of comparing the input current and the reference current; and when the enable signal is at an inactive level, the current sensor can output a first signal at an inactive level.

[0017] In an embodiment, the second voltage line can transmit a second driving voltage having a voltage level different from that of the first driving voltage.

[0018] According to an embodiment, the display device includes: a display panel including pixels; a drive controller electrically connected to a first voltage line transmitting a first drive voltage and a second voltage line transmitting a second drive voltage, and receiving an input image signal and outputting an image data signal; and a data drive circuit providing a data signal corresponding to the image data signal to the display panel. The drive controller includes: a brightness controller that calculates the load of the input image signal; an overcurrent control determiner that compares the load and a reference load, and outputs an enable signal corresponding to the result of comparing the load and the reference load; a current sensor that receives an input current through the first voltage line, compares the input current and a reference current in response to the enable signal, and outputs a first signal corresponding to the result of comparing the input current and the reference current; a switching circuit connected between the second voltage line and a first node, and adjusting the current flowing between the second voltage line and the first node in response to a gate control signal; and a current controller that outputs a gate control signal corresponding to the current in response to the first signal.

[0019] In one embodiment, the switching circuit may include a current-regulating transistor connected between the second voltage line and the first node and configured to receive a gate control signal.

[0020] In one embodiment, when the current is an overcurrent, the current controller can output a gate control signal to reduce the current flowing through the current regulating transistor.

[0021] In one embodiment, the current controller may include a positive voltage generator that outputs a positive voltage in response to a first signal.

[0022] In an embodiment, the positive voltage generator may include: a transistor including a first electrode, a second electrode, and a gate electrode for receiving a first signal; a first resistor connected between a voltage line receiving a power supply voltage and the first electrode of the transistor; and a second resistor connected between the second electrode of the transistor and a ground terminal, wherein the positive voltage may be the voltage of the second electrode of the transistor.

[0023] In an embodiment, the current controller may further include a sensing resistor connected between the first node and the second node, and the current controller may output a gate control signal corresponding to the sum of the voltage and positive voltage of the first node.

[0024] In an embodiment, the current controller may further include: a first amplifier that outputs a sense voltage corresponding to the sum of the voltage and positive voltage of the first node; and a second amplifier that compares the sense voltage with a reference voltage and outputs a gate control signal corresponding to the result of comparing the sense voltage with the reference voltage.

[0025] In this embodiment, when the load is less than the reference load, the overcurrent control determiner can output an active enable signal. When the load is greater than the reference load, the overcurrent control determiner can output an inactive enable signal. When the enable signal is active, the current sensor can compare the input current and the reference current and output a first signal corresponding to the comparison result. When the enable signal is inactive, the current sensor can output an inactive first signal.

[0026] In one embodiment, the pixel may be electrically connected to a first voltage line and a second voltage line. Attached Figure Description

[0027] The above and other features of this disclosure will become clear from the detailed description of embodiments of the present disclosure with reference to the accompanying drawings.

[0028] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 2 This is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 4 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0032] Figure 5 This is a block diagram illustrating an embodiment of the drive controller.

[0033] Figure 6 It is shown Figure 5 The diagram shows the scaling factor of the brightness controller.

[0034] Figure 7 This is a diagram showing the input current based on the load.

[0035] Figure 8 This is a diagram showing the first drive voltage according to the load.

[0036] Figure 9 This is a circuit diagram of a current controller and switching circuit according to an embodiment of the present disclosure.

[0037] Figure 10A , Figure 10B , Figure 11A and Figure 11B It is used to describe Figure 9 The diagram shows the operation of the current controller and switching circuit.

[0038] Figure 12It is a graph showing the change in current according to a positive voltage.

[0039] Figure 13A and Figure 13B It is a graph showing the change in current according to a positive voltage.

[0040] Figure 14 An example is shown based on the current of the load. Detailed Implementation

[0041] In this specification, the expressions that a first component (or area, layer, part, etc.) is "on" a second component, "connected to" or "coupled to" a second component indicate that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is located between the two.

[0042] The same reference numerals / symbols indicate the same components. Furthermore, in the drawings, the thickness, scale, and dimensions of the components are exaggerated for the sake of the effectiveness of the description of the technical content.

[0043] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. The terms are used only to distinguish one component from another. For example, unless the context clearly indicates otherwise, without departing from the scope and spirit of this invention, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component." The singular form is intended to include the plural form.

[0044] Furthermore, the terms "below," "under," "above," and "over" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0045] It will be understood that the terms “comprising,” “including,” “having,” etc., indicate the presence of the features, numbers, steps, operations, elements or components or combinations thereof described in this specification, without excluding the presence of one or more other features, numbers, steps, operations, elements or components or combinations thereof, or other possibilities.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly defined herein, terms such as those defined in a generally accepted dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formalized sense.

[0047] Embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0048] Figure 1 This is a perspective view of a display device DD according to an embodiment of the present disclosure, and Figure 2 This is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0049] Reference Figure 1 and Figure 2 The display device DD can be a device activated by an electrical signal. According to this disclosure, the display device DD can be a small or medium-sized display device for mobile phones, tablet computers, car navigation systems, or game consoles, or a large display device for televisions or monitors. The above-described display devices are provided by way of example only, and it will be apparent that the display device DD can include any other type of display device without departing from the concept of this invention. In a plan view, the display device DD is rectangular in shape, having a long side (or long side) in a first direction DR1 and a short side (or short side) in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited to this. For example, the display device DD can be implemented in various shapes. The display device DD can display an image IM on a display surface IS parallel to each of the first direction DR1 and the second direction DR2, so as to face a third direction DR3. The display surface IS on which the image IM is displayed can correspond to the front surface of the display device DD.

[0050] In this embodiment, the orientation of the front (or upper / top) surface and rear (or lower / bottom) surface of each component relative to the image IM is defined. The front and rear surfaces may be opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3.

[0051] The separation distance between the front and rear surfaces in the third direction DR3 can correspond to the thickness of the display device DD in the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can conceptually be relative and can be changed to different directions.

[0052] The display device DD can sense external input applied from the outside. External input can include various types of input provided from outside the display device DD. According to embodiments of this disclosure, the display device DD can sense external input from a user applied from the outside. The user's external input can be one of various types of external input (such as a part of his / her body, light, heat, his / her eyes, or pressure), or a combination of said external inputs. Furthermore, depending on the structure of the display device DD, the display device DD can sense external input from a user applied to the side or rear surface of the display device DD, and this disclosure is not limited to any one embodiment. As an example of this disclosure, external input can include input introduced through an input device (e.g., a stylus, an active pen, a touch pen, an electronic pen, or an E-pen).

[0053] The display surface IS of the display device DD can be divided into a display area DA and a non-display area NDA. The display area DA can refer to the area where the image IM is displayed. The user visually perceives the image IM through the display area DA. In an embodiment, in a plan view, the display area DA is shown in the shape of a quadrilateral with rounded vertices. However, this is shown as an example. The display area DA can have various shapes and is not limited to this embodiment.

[0054] The non-display area NDA is adjacent to the display area DA. The non-display area NDA may have a given color. The non-display area NDA may surround the display area DA. Thus, the shape of the display area DA may be substantially defined by the non-display area NDA. However, this is shown as an example. The non-display area NDA may be provided only on one side adjacent to the display area DA, or it may be omitted. The display device DD according to embodiments of this disclosure may include various embodiments and is not limited to any one embodiment.

[0055] like Figure 2 As shown, the display device DD may include a display module DM and a window WM disposed on or throughout the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0056] The display panel DP according to embodiments of this disclosure can be a light-emitting display panel. For example, the display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel can include inorganic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots, quantum rods, etc. The following description will be given under the condition that the display panel DP is an organic light-emitting display panel.

[0057] The display panel DP can output an image IM, and the output image IM can be displayed through the display surface IS.

[0058] An input sensing layer (ISP) can be disposed on a display panel (DP) to sense external input. The input sensing layer (ISP) can be directly disposed on the display panel (DP). According to embodiments of this disclosure, the input sensing layer (ISP) can be formed on the display panel (DP) using the same process as the display panel (DP). That is, when the input sensing layer (ISP) is directly disposed on the display panel (DP), an internal adhesive film (not shown) is not disposed between the input sensing layer (ISP) and the display panel (DP). However, an internal adhesive film can be disposed between the input sensing layer (ISP) and the display panel (DP). In this case, the input sensing layer (ISP) is not manufactured using the same process as the display panel (DP). That is, the input sensing layer (ISP) can be manufactured using a process independent of the process of the display panel (DP) and can then be fixed to the upper surface of the display panel (DP) by the internal adhesive film.

[0059] The window WM can be formed of a transparent material capable of outputting an image IM. For example, the window WM can be formed of glass, sapphire, plastic, etc. The illustration shows a window WM implemented using a single layer. However, this disclosure is not limited thereto. For example, the window WM may include multiple layers.

[0060] Meanwhile, although not shown, the non-display area NDA of the aforementioned display device DD may correspond to an area defined on a region of the window WM by printing a material including a given color. As an example of this disclosure, the window WM may include a light-blocking (or light-shielding) pattern for defining the non-display area NDA. The light-blocking pattern is a colored organic film, which may be formed, for example, by coating.

[0061] The window WM can be coupled to the display module DM via an adhesive film. As an example of this disclosure, the adhesive film may include an optically clear adhesive (OCA) film. However, the adhesive film is not limited to this. For example, the adhesive film may include typical adhesives or adhesives. For example, the adhesive film may include an optically clear resin (OCR) film or a pressure-sensitive adhesive (PSA) film.

[0062] An anti-reflective layer may also be disposed between the window WM and the display module DM. The anti-reflective layer reduces the reflectivity of external light incident from above the window WM. According to embodiments of this disclosure, the anti-reflective layer may include a phase retarder and a polarizer. The phase retarder may be of the film type or the liquid crystal coating type. The polarizer may also be of the film type or the liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystal arranged in a given direction. The phase retarder and polarizer may be implemented using a single polarizing film.

[0063] As an example of this disclosure, the antireflective layer may also include a color filter. The arrangement of the color filter can be considered from multiple pixels PX included in the display panel DP (see...). Figure 3 The color of the generated light is determined. In addition, the anti-reflective layer may also include a light-blocking pattern.

[0064] The display module DM can display an image IM based on electrical signals and can send / receive information about external inputs. The display module DM can be defined by an effective area AA and an ineffective area NAA. The effective area AA can be defined as the region through which the image IM output from the display module DM passes. Furthermore, the effective area AA can be defined as the region where the external input applied from the outside is sensed by the input sensing layer ISP.

[0065] The inactive region NAA is adjacent to the active region AA. For example, the inactive region NAA may surround the active region AA. However, this is shown as an example. For example, the inactive region NAA may be defined in various shapes and is not limited to any one embodiment. According to an embodiment, the active region AA of the display module DM may correspond to at least a portion of the display region DA.

[0066] The display device DD may further include a main circuit board MCB, a flexible circuit film D-FCB, a driver chip DIC, a drive controller 100, and a voltage generator 300. The main circuit board MCB can be connected to the flexible circuit film D-FCB to electrically connect to the display panel DP. The flexible circuit film D-FCB is connected to the display panel DP to electrically connect the display panel DP to the main circuit board MCB. The main circuit board MCB may include multiple driving elements. The multiple driving elements may include circuit units for driving the display panel DP. The driver chip DIC may be mounted on the flexible circuit film D-FCB.

[0067] As an example of this disclosure, the flexible circuit film D-FCB may include a first flexible circuit film D-FCB1, a second flexible circuit film D-FCB2, and a third flexible circuit film D-FCB3. The driver chip DIC may include a first driver chip DIC1, a second driver chip DIC2, and a third driver chip DIC3. The first flexible circuit film D-FCB1, the second flexible circuit film D-FCB2, and the third flexible circuit film D-FCB3 may be spaced apart from each other in a first direction DR1 and may be connected to the display panel DP to electrically connect the display panel DP to the main circuit board MCB. The first driver chip DIC1 may be mounted on the first flexible circuit film D-FCB1. The second driver chip DIC2 may be mounted on the second flexible circuit film D-FCB2. The third driver chip DIC3 may be mounted on the third flexible circuit film D-FCB3. However, this disclosure is not limited thereto. For example, the display panel DP may be electrically connected to the main circuit board MCB through a single flexible circuit film, and only one driver chip may be mounted on a single flexible circuit film. In addition, the display panel DP can be electrically connected to the main circuit board MCB through four or more flexible circuit films, and the driver chips can be mounted on the flexible circuit films respectively.

[0068] exist Figure 2 The diagram illustrates a structure in which a first driver chip DIC1, a second driver chip DIC2, and a third driver chip DIC3 are respectively mounted on a first flexible circuit film D-FCB1, a second flexible circuit film D-FCB2, and a third flexible circuit film D-FCB3, but this disclosure is not limited thereto. For example, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 can be directly mounted on a display panel DP. In this case, the portion of the display panel DP on which the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are mounted can be bent, such that the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are disposed on the rear surface of the display module DM. Furthermore, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 can be directly mounted on a main circuit board MCB.

[0069] The input sensing layer ISP can be electrically connected to the main circuit board MCB via a flexible circuit film D-FCB. However, this disclosure is not limited thereto. That is, the display module DM may additionally include a separate flexible circuit film for electrically connecting the input sensing layer ISP and the main circuit board MCB.

[0070] In this embodiment, the drive controller 100 and voltage generator 300 can be mounted on the main circuit board MCB. The drive controller 100 and voltage generator 300 can be electrically connected to the display panel DP via the main circuit board MCB and the flexible circuit film D-FCB.

[0071] The display device DD also includes a housing EDC that houses the display module DM. The housing EDC may be coupled to the window WM to define the exterior of the display device DD. The housing EDC can absorb external impacts and prevent foreign objects / moisture from penetrating into the display module DM, thereby protecting the components housed within the housing EDC. Furthermore, as an example of this disclosure, the housing EDC may be provided as a combination of multiple housing components.

[0072] Figure 3 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0073] Reference Figure 3 The display device DD includes a drive controller 100, a data drive circuit 200, a voltage generator 300, a scan drive circuit 400, and a display panel DP. The drive controller 100, the data drive circuit 200, and the scan drive circuit 400 can be referred to as drive circuits that provide data signals to the pixels PX of the display panel DP.

[0074] The drive controller 100 receives the input image signal RGB and the control signal CTRL. The drive controller 100 converts the input image signal RGB into an image data signal DS and outputs it as the image data signal DS. The drive controller 100 outputs a scan control signal SCS and a data control signal DCS.

[0075] The data drive circuit 200 receives a data control signal DCS and an image data signal DS from the drive controller 100. The data drive circuit 200 converts the image data signal DS into a data signal and then outputs the data signal to multiple data lines DL1 to DLm, described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DS. The data drive circuit 200 can be set to... Figure 2 The driver chip DIC shown is located in the DIC.

[0076] The display panel DP includes first scan lines SCL1 to SCLn, second scan lines SSL1 to SSLn, data lines DL1 to DLm, and pixels PX. n and m are each positive integers.

[0077] The display panel (DP) can be divided into an effective area (AA) and an ineffective area (NAA). Pixels (PX) can be set within the effective area (AA), and the scan drive circuit (400) can be set within the ineffective area (NAA).

[0078] The first scan lines SCL1 to SCLn and the second scan lines SSL1 to SSLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data drive circuit 200 in a direction away from the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0079] Multiple pixels PX are electrically connected to the first scan lines SCL1 to SCLn, the second scan lines SSL1 to SSLn, and the data lines DL1 to DLm. For example, pixels belonging to the first row can be connected to scan lines SCL1 and SSL1. Furthermore, pixels belonging to the second row can be connected to scan lines SCL2 and SSL2.

[0080] Each of the multiple pixels PX includes a light-emitting element ED (see reference). Figure 4 ) and the pixel circuit PXC (refer to) used to control the emission of the light-emitting element ED. Figure 4 The pixel circuit PXC may include multiple transistors and capacitors. The scan drive circuit 400 may include transistors formed using the same process as the pixel circuit PXC. In an embodiment, the light-emitting element ED may be an organic light-emitting diode. However, this disclosure is not limited thereto.

[0081] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0082] The scan drive circuit 400 receives a scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit 400 can output a first scan signal to the first scan lines SCL1 to SCLn, and can output a second scan signal to the second scan lines SSL1 to SSLn.

[0083] In this embodiment, the scan drive circuit 400 may be disposed within the inactive region NAA adjacent to the first side of the active region AA. The first scan lines SCL1 to SCLn and the second scan lines SSL1 to SSLn extend from the scan drive circuit 400 in the first direction DR1.

[0084] In another embodiment, the scan driving circuits can be respectively disposed on the first side and the second side of the effective region AA. For example, the scan driving circuit disposed on the first side of the effective region AA can provide a first scan signal to the first scan lines SCL1 to SCLn, and the scan driving circuit disposed on the second side of the effective region AA can provide a second scan signal to the second scan lines SSL1 to SSLn.

[0085] Voltage generator 300 generates the voltages required for the operation of display panel DP. In this embodiment, voltage generator 300 generates the initialization voltage VINT required for the operation of display panel DP. In addition to the initialization voltage VINT, voltage generator 300 can also generate various voltages required for the operation of display panel DP, drive controller 100, data drive circuit 200, and scan drive circuit 400.

[0086] In one embodiment, the display device DD receives a first driving voltage ELVDD and a second driving voltage ELVSS from an external source (e.g., a host processor, main processor, or graphics processor) via a first voltage line VL1 and a second voltage line VL2. The first driving voltage ELVDD and the second driving voltage ELVSS can be provided to the display panel DP and the drive controller 100. In another embodiment, the voltage level of the first driving voltage ELVDD can be higher than the voltage level of the second driving voltage ELVSS.

[0087] Figure 4 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0088] Pixel PX includes a light-emitting element (ED) and pixel circuitry (PXC). Pixel PX is connected to data lines DL1 to DLm (see reference). Figure 3 The i-th data line DLi and the first scan lines SCL1 to SCLn (refer to) Figure 3 The j-th first scan line SCLj and the second scan lines SSL1 to SSLn (refer to) Figure 3 Let SSLj be the j-th second scan line in ). i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n. Figure 3 Each of the plurality of pixels PX shown can have the same as Figure 4 The circuit diagram of pixel PX shown has the same circuit configuration.

[0089] The pixel circuit PXC may include at least one transistor electrically connected to a light-emitting element ED and used to provide a current corresponding to the data signal Di transmitted from the data line DL1 to the light-emitting element ED. In an embodiment, the pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor Cst. Each of the first transistor T1, the second transistor T2, and the third transistor T3 is an N-type transistor using an oxide semiconductor as the semiconductor layer. However, this disclosure is not limited thereto. For example, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. In an embodiment, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be an N-type transistor, and the other transistors of the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors. Furthermore, the circuit configuration of the pixel according to this disclosure is not limited to... Figure 4 .exist Figure 4 The pixel circuit PXC shown is merely an example. For instance, the configuration of the pixel circuit PXC can be modified and implemented.

[0090] Reference Figure 4 The first scan line SCLj can transmit the first scan signal SCj, and the second scan line SSLj can transmit the second scan signal SSj. The data line DLi transmits the data signal Di. The data signal Di can have the same input to the display device DD (see reference). Figure 3 The voltage level corresponding to the RGB input image signal.

[0091] The first voltage line VL1 and the third voltage line VL3 can transmit the first driving voltage ELVDD and the initialization voltage VINT to the pixel circuit PXC, and the second voltage line VL2 can transmit the second driving voltage ELVSS to the cathode (or second terminal) of the light-emitting element ED.

[0092] The first transistor T1 includes a first electrode connected to the first voltage line VL1, a second electrode electrically connected to the anode (or first terminal) of the light-emitting element ED, and a gate electrode connected to the first electrode of the capacitor Cst. Depending on the switching operation of the second transistor T2, the first transistor T1 can supply drive current to the light-emitting element ED in response to the data signal Di transmitted via the data line DLi.

[0093] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the first scan line SCLj. The second transistor T2 can be turned on according to the first scan signal SCj transmitted through the first scan line SCLj, and can transmit the data signal Di from the data line DLi to the gate electrode of the first transistor T1.

[0094] The third transistor T3 includes a first electrode connected to the third voltage line VL3, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the second scan line SSLj. The third transistor T3 can be turned on according to the second scan signal SSj transmitted through the second scan line SSLj, and can transmit the initialization voltage VINT to the anode of the light-emitting element ED.

[0095] As described above, the first electrode of capacitor Cst is connected to the gate electrode of the first transistor T1, and the second electrode of capacitor Cst is connected to the second electrode of the first transistor T1. The structure of pixel PX according to the embodiment is not limited to... Figure 4 The structure shown is as follows. Within a pixel PX, the number of transistors, the number of capacitors, and the connection relationships between transistors and capacitors can be changed or modified.

[0096] Figure 5 This is a block diagram illustrating an embodiment of the drive controller 100.

[0097] In the functions of the drive controller 100, only components associated with the voltage control function used to adjust power consumption are included. Figure 5 As shown in the image. Except... Figure 5 In addition to the components shown, the drive controller 100 may also include components associated with various functions (e.g., components associated with the function of converting the input image signal RGB into an image data signal DS, and components associated with the function of outputting a scan control signal SCS and a data control signal DCS in response to the control signal CTRL).

[0098] Reference Figure 5 The drive controller 100 includes a current sensor 110, a current controller 120, a switching circuit 130, a brightness controller 140, and an overcurrent control determinant 150.

[0099] The current sensor 110 receives the input current IN_I from the first voltage line VL1. The first voltage line VL1 can be a transmission line. Figure 3The wiring of the first drive voltage ELVDD is shown in the diagram. Current sensor 110, in response to the enable signal ALT_EN from overcurrent control determinant 150, compares the input current IN_I and the reference current RI, and outputs a first signal ALT. Current controller 120, in response to the first signal ALT, outputs a gate control signal GCTRL. Switching circuit 130, in response to the gate control signal GCTRL, adjusts the current flowing to the second voltage line VL2.

[0100] The brightness controller 140 calculates the load LD of the input image signal RGB. In an embodiment, the brightness controller 140 can adjust the brightness on the display panel DP (refer to) based on the load LD of the input image signal RGB. Figure 3 The brightness of the image displayed in the image sensor 110 is determined by adjusting the gray level of the input image signal RGB based on the load LD. The brightness controller 140 can output an image data signal DS obtained by adjusting the gray level of the input image signal RGB based on the load LD. The overcurrent control determiner 150 compares the load LD from the brightness controller 140 with a reference load LD_TH and outputs an enable signal ALT_EN corresponding to the comparison result. The enable signal ALT_EN can be provided to the current sensor 110. In an embodiment, when the load LD is less than the reference load LD_TH, the overcurrent control determiner 150 outputs an active enable signal ALT_EN. When the load LD is greater than or equal to the reference load LD_TH, the overcurrent control determiner 150 outputs an inactive enable signal ALT_EN.

[0101] In this embodiment, when the enable signal ALT_EN from the overcurrent control determiner 150 is at an active level, the current sensor 110 compares the input current IN_I with the reference current RI. When the value of the input current IN_I is greater than the value of the reference current RI, the current sensor 110 can output a first active signal ALT.

[0102] Figure 6 It is shown Figure 5 A graph of the scaling factor SF of the brightness controller 140 shown.

[0103] Reference Figure 5 and Figure 6 The brightness controller 140 can calculate the load LD for one frame based on the input image signal RGB. The load LD can have a value between 0% and 100%. For example, when the input image signal RGB corresponds to a completely black image (e.g., grayscale 0), the load LD can be 0%. Furthermore, when the input image signal RGB corresponds to a completely white image (e.g., grayscale 255), the load LD can be 100%. Additionally, when the input image signal RGB corresponds to grayscale 224, the load LD can be 75%.

[0104] The brightness controller 140 can output an image data signal DS obtained by adjusting the grayscale of the input image signal RGB through a calculation-based load LD.

[0105] To output an image data signal DS by adjusting the grayscale of the input image signal RGB, the brightness controller 140 can calculate a scaling factor SF. The scaling factor SF can have a value less than or equal to "1". For example, when the scaling factor SF is 1, the grayscale level of the image data signal DS can be the same as the grayscale level of the input image signal RGB. As another example, when the scaling factor SF is 0.5, the grayscale level of the image data signal DS can be reduced to half the grayscale level of the input image signal RGB.

[0106] In this embodiment, the value of the scaling factor SF can be set differently depending on the load LD. For example, as the load LD increases (i.e., becomes closer to 100%), the scaling factor SF can decrease; as the load LD decreases (i.e., becomes closer to 0%), the scaling factor SF can increase to 1.

[0107] The luminance controller 140 can calculate the load LD based on the sum of the RGB values ​​of the input image signal for one frame (hereinafter referred to as the "total grayscale"). Below, the scaling factor SF can be 0.3 when the total grayscale corresponds to a pure white image (255G). When the total grayscale corresponds to 224G, the scaling factor SF can be 0.4. When the total grayscale corresponds to a pure black image (0G), the scaling factor SF can be 1. In this document, "G" represents grayscale.

[0108] When the total grayscale of the input image signal RGB indicates a high grayscale, that is, when the power consumption of the display panel DP is expected to be high, the brightness controller 140 reduces the grayscale of the image data signal DS according to the scaling factor SF, thereby lowering it below the grayscale of the input image signal RGB. As a result, it may be possible to prevent the display panel DP (refer to...) Figure 3 Damaged due to overcurrent.

[0109] Reference Figure 5 When the load LD is greater than a given value, the brightness controller 140 can output an image data signal DS whose grayscale is adjusted according to the scaling factor SF (i.e., the grayscale is reduced). Correspondingly, the display panel DP (reference) Figure 3 The current consumption can be reduced.

[0110] When the load LD is greater than or equal to the reference load LD_TH, the overcurrent control determiner 150 outputs an inactive enable signal ALT_EN. When the load LD is less than the reference load LD_TH, the overcurrent control determiner 150 outputs an active enable signal ALT_EN.

[0111] When the enable signal ALT_EN from the overcurrent control determiner 150 is at an inactive level, the current sensor 110 outputs an inactive first signal ALT. When the enable signal ALT_EN from the overcurrent control determiner 150 is at an active level, the current sensor 110 compares the input current IN_I with the reference current RI. When the enable signal ALT_EN is at an active level and the value of the input current IN_I is greater than the value of the reference current RI, the current sensor 110 can output an active first signal ALT.

[0112] Figure 7 This is a diagram showing the input current IN_I based on the load LD.

[0113] Reference Figure 3 , Figure 5 and Figure 7 Because the brightness of the image to be displayed in the display panel DP increases as the load LD increases, the amount of input current IN_I input through the first voltage line VL1 needs to increase.

[0114] In the first load range LD1, where the load LD is less than or equal to the reference load LD_TH (e.g., 75%), the input current IN_I can be lower than the reference current RI. In the second load range LD2, where the load LD is greater than the reference load LD_TH, the input current IN_I can be higher than the reference current RI.

[0115] Figure 8 This is a diagram showing the first drive voltage ELVDD based on the load LD.

[0116] Reference Figure 3 , Figure 5 and Figure 8 The voltage level of the first drive voltage ELVDD can be varied depending on the load LD. In an embodiment, in a first load range LD1 where the load LD is less than or equal to the reference load LD_TH (e.g., 75%), the first drive voltage ELVDD can be increased to the maximum voltage VMAX. In an embodiment, in a second load range LD2 where the load LD is greater than the reference load LD_TH, the first drive voltage ELVDD can be maintained at the minimum voltage VMIN.

[0117] The power consumption of the display panel (DP) can be calculated by multiplying the input current IN_I and the first driving voltage ELVDD. For example, in the second load range LD2, when the input current IN_I is 20A and the first driving voltage ELVDD is 18V, the power consumption can be 360W (=20A×18V). For example, in the first load range LD1, when the input current IN_I is 18A and the first driving voltage ELVDD is 24V, the power consumption can be 432W (=18A×24V).

[0118] In the second load range LD2, because the first drive voltage ELVDD is 18V, the power consumption of the display panel DP can remain at a consistent level. However, in the first load range LD1, even when the input current IN_I is 18A while displaying an image with a given level of brightness at the state where the first drive voltage ELVDD is increased to the maximum voltage VMAX (e.g., 24V), the power consumption may increase. This sudden increase in power may exceed the specifications of the display device DD and may sometimes damage the display device DD.

[0119] Figure 9 This is a circuit diagram of the current controller 120 and the switching circuit 130 according to an embodiment of the present disclosure.

[0120] Reference Figure 9 The switching circuit 130 includes a current-adjusting transistor TR_I, a resistor Rf, and a capacitor Cf. The current-adjusting transistor TR_I is connected between the second voltage line VL2 and the first node N1, and includes a gate electrode connected to the third node N3.

[0121] A resistor Rf is connected between the current controller 120 and the third node N3. A capacitor Cf is connected between the third node N3 and the ground terminal. The resistor Rf and capacitor Cf can function as a low-pass filter. The low-pass filter removes high-frequency components from the gate control signal GCTRL output from the current controller 120, thus allowing it to be provided to the third node N3. In this embodiment, the gate control signal GCTRL output from the current controller 120 can be directly provided to the third node N3, i.e., the gate electrode of the current regulating transistor TR_I.

[0122] The current controller 120 includes a sensing resistor Rs, a first resistor R1, a second resistor R2, a transistor TR_S, a first amplifier AMP1, and a second amplifier AMP2. The sensing resistor Rs is connected between a first node N1 and a second node N2. The second node N2 is connected to a ground terminal. The transistor TR_S includes a first electrode connected to the first resistor R1, a second electrode connected to a fourth node N4, and a gate electrode that receives a first signal ALT. The second electrode of the transistor TR_S is connected to the first node N1. The gate electrode of the transistor TR_S receives the first signal ALT. The first resistor R1 is connected between a fourth voltage line VL4 and the first electrode of the transistor TR_S. The second resistor R2 is connected between the fourth node N4 and the ground terminal. In an embodiment, the fourth voltage line VL4 receives a second power supply voltage VDD2.

[0123] When the first signal ALT input to the gate electrode of transistor TR_S is at an inactive level (e.g., low), transistor TR_S is off. When transistor TR_S is off, the positive voltage VPLUS of the fourth node N4 can be 0V. When the first signal ALT input to the gate electrode of transistor TR_S is at an active level (e.g., high), transistor TR_S is on. When transistor TR_S is on, the positive voltage VPLUS of the fourth node N4 can be obtained by dividing the second supply voltage VDD2 by the sum of the resistances of the first resistor R1 and the second resistor R2, and then multiplying the result by the resistance of the second resistor R2. In an embodiment, when the first signal ALT is active, the positive voltage VPLUS of the fourth node N4 can be higher than 0V and lower than the second supply voltage VDD2. The first resistor R1, the second resistor R2, and the transistor TR_S can be referred to as a positive voltage generator, which generates the positive voltage VPLUS in response to the first signal ALT.

[0124] The first amplifier AMP1 includes a first input terminal (+) connected to the first node N1 and the fourth node N4, a second input terminal (-) connected to the second node N2, and an output terminal for output sensing voltage VSENSE.

[0125] The second amplifier AMP2 includes a first input terminal (+) for receiving a reference voltage VREF, a second input terminal (-) for receiving a sensed voltage VSENSE, and an output terminal for outputting a gate control signal GCTRL. The second amplifier AMP2 can receive a first power supply voltage VDD1 and can be connected to a ground terminal.

[0126] When the display device DD (reference) Figure 1 During operation, the current Ip can flow between the second voltage line VL2 and the sensing resistor Rs. The output of the first amplifier AMP1 is the sensing voltage VSENSE corresponding to the voltage difference between the first node N1 and the second node N2. That is, the sensing voltage VSENSE can be the voltage level corresponding to the current Ip.

[0127] The second amplifier AMP2 outputs a gate control signal GCTRL corresponding to the difference between the sensed voltage VSENSE and the reference voltage VREF.

[0128] In this embodiment, the current-adjusting transistor TR_I may be a field-effect transistor (FET). The current-adjusting transistor TR_I can transfer current to the first node N1 corresponding to the voltage level of the gate control signal GCTRL input to the gate electrode of the current-adjusting transistor TR_I.

[0129] Figure 10A , Figure 10B, Figure 11A and Figure 11B It is used to describe Figure 9 The diagram shows the operation of the current controller 120 and the switching circuit 130.

[0130] Figure 10A This is a diagram illustrating the operation of the current controller 120 and the switching circuit 130 in the second load range LD2, where the first signal ALT is at an inactive level and overcurrent does not flow to the second voltage line VL2.

[0131] Reference Figure 5 , Figure 7 and Figure 10A In the second load interval LD2 where the load LD is greater than the reference load LD_TH, the overcurrent control determinant 150 outputs an inactive enable signal ALT_EN.

[0132] When the enable signal ALT_EN is at an inactive level, the current sensor 110 outputs an inactive first signal ALT. When the first signal ALT is at an inactive level, the transistor TR_S remains in the off state.

[0133] In this configuration, when the current Ip between the second voltage line VL2 and the ground terminal is 18A and the sensing resistor Rs is 2mΩ, the voltage level at the first input terminal (+) of the first amplifier AMP1 is 36mV. When the gain of the first amplifier AMP1 is 50, the sensed voltage VSENSE output from the first amplifier AMP1 can be 1.8V.

[0134] When the reference voltage VREF is 2.4V, because VREF is higher than the sensing voltage VSENSE, the second amplifier AMP2 can output a gate control signal GCTRL corresponding to the voltage level of the first power supply voltage VDD1 (i.e., 12V). In other words, the voltage level of the gate control signal GCTRL can be 12V.

[0135] The current regulation transistor TR_I can be fully turned on in response to the 12V gate control signal GCTRL input to the gate electrode of the current regulation transistor TR_I.

[0136] In other words, when the overcurrent does not flow to the second voltage line VL2, the current controller 120 and the switching circuit 130 do not need to adjust the current Ip.

[0137] Figure 10B This is a diagram illustrating the operation of the current controller 120 and the switching circuit 130 in the second load range LD2, where the first signal ALT is at an inactive level and an overcurrent flows to the second voltage line VL2.

[0138] Reference Figure 5 , Figure 7 and Figure 10B In the second load interval LD2 where the load LD is greater than the reference load LD_TH, the overcurrent control determinant 150 outputs an inactive enable signal ALT_EN.

[0139] When the enable signal ALT_EN is at an inactive level, the current sensor 110 outputs an inactive first signal ALT. When the first signal ALT is at an inactive level, the transistor TR_S remains in the off state.

[0140] In this configuration, when the current Ip between the second voltage line VL2 and the ground terminal is 30A and the sensing resistor Rs is 2mΩ, the voltage level at the first input terminal (+) of the first amplifier AMP1 is 60mV. When the gain of the first amplifier AMP1 is 50, the sensed voltage VSENSE output from the first amplifier AMP1 can be 3.0V.

[0141] When the reference voltage VREF is 2.4V, and the sensed voltage VSENSE is higher than the reference voltage VREF, the voltage level of the gate control signal GCTRL output from the second amplifier AMP2 can be lower than the first power supply voltage VDD1 (GCTRL<12V).

[0142] The current regulating transistor TR_I can adjust the current Ip flowing between the second voltage line VL2 and the sensing resistor Rs in response to the gate control signal GCTRL input to the gate electrode of the current regulating transistor TR_I. When the voltage level of the gate control signal GCTRL input to the gate electrode of the current regulating transistor TR_I decreases, the current Ip can decrease.

[0143] For example, when the current Ip decreases from 30A to 24A, even if the first drive voltage ELVDD remains at a constant voltage, the display panel DP (reference) Figure 3 The power consumption can also be reduced.

[0144] In other words, when an overcurrent flows to the second voltage line VL2, the current controller 120 and the switching circuit 130 can adjust the current Ip, and therefore, the power consumption of the display panel DP can be reduced.

[0145] Figure 11A This is a diagram used to describe the operation of the current controller 120 and the switching circuit 130 in the first load interval LD1 where the overcurrent does not flow to the second voltage line VL2.

[0146] Reference Figure 5 , Figure 7 and Figure 11A In the first load interval LD1 where the load LD is less than the reference load LD_TH, the overcurrent control determinant 150 outputs an effective level enable signal ALT_EN.

[0147] When the enable signal ALT_EN is active, the current sensor 110 compares the input current IN_I with the reference current RI. When the input current IN_I is less than the reference current RI, the current sensor 110 can output a deactivated first signal ALT. When the first signal ALT is deactivated, the transistor TR_S remains off.

[0148] In this configuration, when the current Ip between the second voltage line VL2 and the ground terminal is 10A and the sensing resistor Rs is 2mΩ, the voltage level at the first input terminal (+) of the first amplifier AMP1 is 20mV. When the gain of the first amplifier AMP1 is 50, the sensed voltage VSENSE output from the first amplifier AMP1 can be 1.0V.

[0149] When the reference voltage VREF is 2.4V, because VREF is higher than the sensing voltage VSENSE, the second amplifier AMP2 can output a gate control signal GCTRL corresponding to the voltage level of the first power supply voltage VDD1 (i.e., 12V). In other words, the voltage level of the gate control signal GCTRL can be 12V.

[0150] The current regulation transistor TR_I can be fully turned on in response to the 12V gate control signal GCTRL input to the gate electrode of the current regulation transistor TR_I.

[0151] In other words, when the overcurrent does not flow to the second voltage line VL2, the current controller 120 and the switching circuit 130 do not need to adjust the current Ip.

[0152] Figure 11B This is a diagram used to describe the operation of the current controller 120 and the switching circuit 130 in the first load interval LD1 where an overcurrent flows to the second voltage line VL2.

[0153] Reference Figure 5 , Figure 7 and Figure 11B In the first load interval LD1 where the load LD is less than the reference load LD_TH, the overcurrent control determinant 150 outputs an effective level enable signal ALT_EN.

[0154] When the enable signal ALT_EN is at an active level, the current sensor 110 outputs the first active signal ALT. When the first active signal ALT is at an active level, the transistor TR_S is turned on.

[0155] When transistor TR_S is turned on, the voltage at the fourth node N4 can be a voltage lower than the second supply voltage VDD2 due to the first resistor R1 and the second resistor R2. For example, the voltage at the fourth node N4, i.e., the positive voltage VPLUS, can be 60mV.

[0156] In this case, when the current Ip between the second voltage line VL2 and the ground terminal is 30A and the sensing resistor Rs is 2mΩ, the voltage level of the first node N1 is 60mV.

[0157] The voltage level at the first input terminal (+) of the first amplifier AMP1 can be 120mV, obtained by adding the voltage at the first node N1 and the positive voltage VPLUS at the fourth node N4. When the gain of the first amplifier AMP1 is 50, the sensed voltage VSENSE output from the first amplifier AMP1 can be 6V.

[0158] When the reference voltage VREF is 2.4V, and the sensed voltage VSENSE is higher than the reference voltage VREF, the voltage level of the gate control signal GCTRL output from the second amplifier AMP2 can be lower than the first power supply voltage VDD1(GCTRL). <VDD1)。

[0159] The current regulating transistor TR_I can adjust the current Ip flowing between the second voltage line VL2 and the sensing resistor Rs in response to the gate control signal GCTRL input to the gate electrode of the current regulating transistor TR_I. When the voltage level of the gate control signal GCTRL input to the gate electrode of the current regulating transistor TR_I decreases, the current Ip can decrease.

[0160] For example, when the current Ip decreases from 30A to 18A, even if the first drive voltage ELVDD remains at a consistent voltage, the display panel DP (reference) Figure 3 The power consumption can also be reduced.

[0161] In other words, when an overcurrent flows to the second voltage line VL2, the current controller 120 and the switching circuit 130 can adjust the current Ip, and therefore, the power consumption of the display panel DP can be reduced.

[0162] exist Figure 10A , Figure 10B , Figure 11A and Figure 11B In this document, the values ​​of the current Ip, the resistance of the sensing resistor Rs, and the voltage levels of the sensing voltage VSENSE, the reference voltage VREF, the gate control signal GCTRL, and the first power supply voltage VDD1 are provided as examples only, and this disclosure is not limited thereto.

[0163] Figure 12This is a graph showing the change in current Ip according to the positive voltage VPLUS.

[0164] Reference Figure 11B and Figure 12 The positive voltage VPLUS can be determined by the voltage level of the second power supply voltage VDD2 and the resistance values ​​of the first resistor R1 and the second resistor R2.

[0165] exist Figure 11B In the example shown, when the current Ip is 30A due to the overcurrent flowing to the second voltage line VL2, the current Ip can be adjusted according to the voltage level of the positive voltage VPLUS.

[0166] For example, when the positive voltage VPLUS is 0V, 0.3V, 0.6V, 0.9V or 1.2V, the current Ip can be adjusted to 24A, 21A, 18A, 15A or 12A.

[0167] In other words, the display panel DP (refer to) Figure 3 The power consumption can be adjusted according to the characteristics of the display panel DP by setting the resistance values ​​of the first resistor R1 and the second resistor R2, so that the voltage level of the positive voltage VPLUS is optimally set.

[0168] Figure 13A and Figure 13B This shows the positive voltage VPLUS (refer to) Figure 9 A graph showing the change in current Ip.

[0169] Figure 13A This example illustrates the variation of current Ip from frame 11 (F11) to frame 14 (F14) when the positive voltage VPLUS is 0.6V. Figure 13B This example illustrates the variation of current Ip from frame 21 (F21) to frame 24 (F24) when the positive voltage VPLUS is 1.2V.

[0170] Reference Figure 5 , Figure 9 , Figure 13A and Figure 13B When the load LD is less than the reference load LD_TH, the first signal ALT is set to an active level, and therefore, the transistor TR_S is turned on.

[0171] like Figure 13A As shown, when the positive voltage VPLUS is 0.6V, the current Ip can be 18A at frame 12 F12 and frame 13 F13.

[0172] like Figure 13B As shown, when the positive voltage VPLUS is 1.2V, the current Ip can be 12A at frame 22 F22 and frame 23 F23.

[0173] In other words, even if the load LD remains at the same value of 70%, the current Ip can be adjusted according to the voltage level of the positive voltage VPLUS.

[0174] Based on the display panel DP (refer to) Figure 3 Based on the characteristics of the image shown in the image, the voltage level of the positive voltage VPLUS can be determined to be the optimal value.

[0175] Figure 14 The current Ip is shown based on the load LD.

[0176] Reference Figure 8 , Figure 9 and Figure 14 In the first load range LD1, where the load LD is less than or equal to the reference load LD_TH (e.g., 75%), the first drive voltage ELVDD can be increased to the maximum voltage VMAX. Accordingly, in the first load range LD1, the current Ip must be maintained at a low current level (e.g., 18A) for the display panel DP (refer to...). Figure 3 The power consumption can be kept below the baseline level.

[0177] In the second load range LD2 where the load LD is greater than the reference load LD_TH, the first drive voltage ELVDD can be maintained at the minimum voltage VMIN.

[0178] Accordingly, even if the current Ip in the second load zone LD2 remains at a slightly higher current level than the current Ip in the first load zone LD1 (e.g., 24A), the power consumption of the display panel DP can remain below the reference level.

[0179] The display device with the above configuration can prevent the power consumption of the display panel from exceeding a reference level when a transient overcurrent flows in the display panel. Accordingly, it can prevent the display panel from being damaged due to a sudden increase in power consumption.

[0180] Although this disclosure has been described with reference to embodiments thereof, it will be readily understood by those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A drive controller, characterized in that, The drive controller includes: The brightness controller is configured to calculate the load of the input image signal; An overcurrent control determiner is configured to compare the load and a reference load and output an enable signal corresponding to the result of the comparison between the load and the reference load. A current sensor is configured to receive an input current via a first voltage line through which a first drive voltage is transmitted, compare the input current with a reference current in response to the enable signal, and output a first signal corresponding to the result of comparing the input current with the reference current. A switching circuit, connected between a second voltage line and a first node, is configured to adjust the current flowing between the second voltage line and the first node in response to a gate control signal; and A current controller is configured to output a gate control signal corresponding to the current in response to the first signal.

2. The drive controller according to claim 1, characterized in that, The switching circuit includes a current-regulating transistor connected between the second voltage line and the first node and configured to receive the gate control signal.

3. The drive controller according to claim 2, characterized in that, When the current is an overcurrent, the current controller outputs the gate control signal to reduce the current flowing through the current regulating transistor.

4. The drive controller according to claim 2, characterized in that, The current-regulating transistor is a field-effect transistor.

5. The drive controller according to claim 1, characterized in that, The current controller includes: A positive voltage generator is configured to output a positive voltage in response to the first signal.

6. The drive controller according to claim 5, characterized in that, The positive voltage generator includes: A transistor includes a first electrode, a second electrode, and a gate electrode that receives the first signal; A first resistor is connected between the voltage line receiving the power supply voltage and the first electrode of the transistor; and A second resistor is connected between the second electrode of the transistor and the ground terminal, and The positive voltage is the voltage of the second electrode of the transistor.

7. The drive controller according to claim 5, characterized in that, The current controller also includes a sensing resistor connected between the first node and the second node, and The current controller outputs a gate control signal corresponding to the sum of the voltage of the first node and the positive voltage.

8. The drive controller according to claim 7, characterized in that, The current controller also includes: A first amplifier is configured to output a sensed voltage corresponding to the sum of the voltage and the positive voltage at the first node; and A second amplifier is configured to compare the sensed voltage and a reference voltage, and output a gate control signal corresponding to the result of comparing the sensed voltage and the reference voltage.

9. The drive controller according to claim 1, characterized in that, The overcurrent control determiner is configured to: When the load is less than the reference load, the enable signal with an effective level is output; and When the load is greater than the reference load, the enable signal is output at an inactive level.

10. A display device, characterized in that, The display device includes: Display panel, including pixels; A drive controller, electrically connected to a first voltage line transmitting a first drive voltage and a second voltage line transmitting a second drive voltage, is configured to receive an input image signal and output an image data signal; and The data driving circuit is configured to provide the display panel with a data signal corresponding to the image data signal. The drive controller includes: A brightness controller is configured to calculate the load of the input image signal; An overcurrent control determiner is configured to compare the load and a reference load and output an enable signal corresponding to the result of the comparison between the load and the reference load. A current sensor is configured to receive an input current through the first voltage line, compare the input current with a reference current in response to the enable signal, and output a first signal corresponding to the result of comparing the input current with the reference current. A switching circuit, connected between the second voltage line and the first node, is configured to adjust the current flowing between the second voltage line and the first node in response to a gate control signal; and A current controller is configured to output a gate control signal corresponding to the current in response to the first signal.

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