Board card testing device based on superconducting quantum computing room temperature regulation and control case system
By designing a board test device with a matrix switch combination array and a USB adapter, the problems of low testing efficiency and poor reliability of superconducting quantum computing room temperature control chassis system were solved, and efficient and reliable multi-channel testing was achieved.
Patent Information
- Application Number
- CN202422645981.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2034-10-30
AI Technical Summary
Existing test devices for superconducting quantum computing room temperature control chassis system boards suffer from problems such as low testing efficiency, high labor costs, poor connection reliability, and large testing errors.
A board test device based on a superconducting quantum computing room temperature control chassis system was designed. It adopts a matrix switch array and a USB adapter to realize continuous access of multiple test channels, reduce the number of cable replacements, and ensure consistent locking.
It improves testing efficiency, ensures the reliability and consistency of test results, saves labor costs, and reduces testing errors.
Smart Images
Figure CN223513305U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic board testing, specifically to a board testing device based on a superconducting quantum computing room temperature control chassis system. Background Technology
[0002] After the superconducting quantum computing room temperature control chassis system is assembled, it needs to undergo a series of tests before being installed and used. To ensure its electronic performance, the radio frequency signals and digital circuits need to be debugged and verified. Currently, the operators connect individual channels of the board under test to individual test instruments via SMA cables, configure parameters in the test cases, and check whether the graphs or values on the instrument meet expectations. Once they do, the next channel is tested, and so on. Because quantum computing boards have many channels, a single AWG (Arbitrary Waveform Generator) control board has 32 channels. The instruments used include power meters, spectrum analyzers, multimeters, and phase noise meters. Testing a single board requires changing cable connections and setting parameters more than a hundred times.
[0003] Existing testing technologies and methods have the following drawbacks: 1. They consume a lot of manpower to replace cables, resulting in low testing efficiency; 2. Frequent cable replacements lead to decreased reliability of board connectors; 3. Inconsistent tightening of channel connections each time can cause testing errors. Utility Model Content
[0004] The technical problem to be solved in this application is how to improve the testing efficiency of the board test device based on the superconducting quantum computing room temperature control chassis system and improve the reliability and consistency of the test results.
[0005] This application solves the above-mentioned technical problems through the following technical means: a board test device based on a superconducting quantum computing room temperature control chassis system, including a chassis base plate (101), a cover plate (102), a front panel (103), a rear panel (104), and a matrix switch combination array inside the test device. The front panel (103) is provided with multiple test input terminals and multiple test output terminals. The rear panel (104) is equipped with a power switch (6) and a USB adapter (7). The USB adapter (7) is connected to the matrix switch combination array. The power socket (5) is connected to the power switch (6). The matrix switch combination array and the power socket (5) are fixed on the base plate (101). The cover plate (102), the front panel (103), and the rear panel (104) are respectively installed on the base plate (101) to form the test device chassis shell.
[0006] As a further optimized technical solution, the matrix switch combination array includes six matrix switches, which are divided into three layers. The first layer contains four eight-input, one-output matrix switches SP8T_1-SP8T_4, which have 32 input terminals IN_1 to IN_32 externally. The four common terminals are connected to the four input terminals of the four-input, one-output matrix switch SP4T_1 in the second layer. The common terminal of the second layer is connected to the common terminal of the one-input, four-output matrix switch SP4T_2 in the third layer. The third layer has four output terminals OUT_1 to OUT_4, forming a matrix switch combination array with 32 inputs and 4 outputs.
[0007] Alternatively, the matrix switch array may include six matrix switches, which are divided into three layers. The first layer contains three eight-input, one-output matrix switches SP8T_1-SP8T_3 and one four-input, one-output matrix switch SP4T_2, which has 28 input terminals IN_1 to IN_28 externally. The four common terminals are connected to the four input terminals of the four-input, one-output matrix switch SP4T_1 in the second layer. The common terminal of the second layer is connected to the common terminal of the one-input, eight-output matrix switch SP8T_4 in the third layer. The third layer has eight output terminals OUT_1 to OUT_8, forming a matrix switch array with 28 inputs and 8 outputs.
[0008] As a further optimized technical solution, there are six USB adapters (7), and the six USB adapters (7) are respectively connected to the USB interfaces USB_1-USB_6 of the six matrix switches.
[0009] As a further optimized technical solution, the board test device based on the superconducting quantum computing room temperature control chassis system also includes a power adapter. Each power adapter is connected to one of the matrix switches in the matrix switch combination array and is plugged into a power socket (5).
[0010] As a further optimized technical solution, the power adapter is a DC 12V power adapter.
[0011] As a further optimized technical solution, the cover plate (102) is provided with an opening above the matrix switch combination array, and a transparent acrylic panel (8) is installed on the opening.
[0012] As a further optimized technical solution, the board test device based on the superconducting quantum computing room temperature control chassis system also includes a front panel film (9), which is attached to the front panel (103) with its own adhesive backing.
[0013] As a further optimized technical solution, the power switch (6) is a rocker-type power switch.
[0014] As a further optimized technical solution, the cover plate (102) adopts an integrated cover plate, and the cover plate (102) has a grid on its side.
[0015] The advantages of this invention are as follows: It designs a board testing device based on a superconducting quantum computing room temperature control chassis system that enables continuous testing. Multiple test channels of the board to be tested are connected to the corresponding input terminals of the testing device through cables, and the output terminals are connected to the testing instrument. Multiple cables only need to be connected once, without the need to replace cables in the middle, ensuring that the locking degree of each channel is consistent, improving testing efficiency, and ensuring the reliability and consistency of test results. Attached Figure Description
[0016] Figure 1 This is an exploded view of the test apparatus according to an embodiment of this application;
[0017] Figure 2 This is an overall structural diagram of the testing device according to an embodiment of this application;
[0018] Figure 3 This is a matrix switch combination array diagram in the test device of this application embodiment;
[0019] Figure 4 This is another matrix switch combination array diagram of the test device according to an embodiment of this application;
[0020] Figure 5 This is a schematic diagram of the connection relationship of the test system according to an embodiment of this application;
[0021] Figure 6 This is a flowchart of a test method according to an embodiment of this application. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0023] It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. Furthermore, the illustrations provided in the following embodiments are merely schematic representations of the basic concept of this application. The illustrations only show components relevant to this application and are not drawn according to the actual number, shape, and size of components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex.
[0024] It should be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.
[0025] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.
[0026] Example 1
[0027] The board testing device proposed in this application is for testing the boards of a superconducting quantum computing room temperature controlled chassis system. The testing device is as follows: Figure 1 As shown, the system includes a chassis base plate 101, a cover plate 102, four 8-in-1-out matrix switches 2 (hereinafter referred to as matrix switches SP8T_1-SP8T_4 respectively), a 4-in-1-out matrix switch 3 (hereinafter referred to as matrix switch SP4T_1), a 1-in-4-out matrix switch 4 (hereinafter referred to as matrix switch SP4T_2), a power adapter (not shown), a power socket 5, a front panel 103, and a rear panel 104.
[0028] The cover plate 102 has a mesh design on both sides for ventilation and heat dissipation. As an optimized technical solution, a rectangular opening is provided on the top of the integrated cover plate 102, and a transparent acrylic panel 8 is installed on the rectangular opening, so that the situation below the cover plate 102 can be observed through the transparent acrylic panel 8. As an optimized technical solution, the cover plate 102 adopts an integrated cover plate, which improves the overall structural strength.
[0029] The four matrix switches SP8T_1-SP8T_4, the two matrix switches SP4T_1 and SP4T_2, and the power socket 5 are fixed to the screw holes reserved on the base plate 101 by bottom screws. The six matrix switches are fixed side by side at the front end of the base plate 101, and the power socket 5 is located at the rear end of the base plate 101.
[0030] The USB adapter 7 and the power switch 6 are installed on the rear panel 104 through the reserved screw holes. Six power adapters are plugged into the power socket 5, and the six power adapters supply power to the six matrix switches respectively. The input line of the power socket 5 is connected to the power switch 6 through the terminal wire. The power switch 6 is a rocker switch.
[0031] The front panel 103 has six circular outlets for the matrix switches to the outside, and the rear panel 104 has holes for installing power switches 6 and six USB adapters 7. The six USB adapters 7 are respectively connected to the USB interfaces USB_1-USB_6 of the six matrix switches.
[0032] The cover plate 102, front panel 103, and rear panel 104 are respectively installed onto the base plate 101 through the pre-drilled screw holes, thus forming a test device with a 32-input, 4-output control matrix. Figure 2 The diagram shown is an overall structural diagram of the testing device.
[0033] As a further optimization, the front panel film 9 is attached to the front panel 103 with its own adhesive backing. Correspondingly, the front panel film 9 also has six circular outlets for the matrix switches to the outside. The transparent acrylic panel 8 is attached to the reserved holes above the integrated cover plate 102 with adhesive backing, which is used to observe the indicator light status of the internal matrix switches SP8T_1-SP8T_4 and matrix switches SP4T_1 and SP4T_2 during operation.
[0034] It should be noted that the core component of this testing device is the six internal matrix switches, which are connected via SMA cables and arranged in three layers. The first layer contains four matrix switches SP8T_1-SP8T_4, with 32 input terminals (IN_1~IN_32) external to the testing device. The four common terminals are connected to the four input terminals of the second-layer matrix switch SP4T_1, and the common terminal of the second layer is connected to the common terminal of the third-layer matrix switch SP4T_2. The output terminals (OUT_1~OUT_4) of the third layer are connected to external devices and different testing instruments to achieve different performance tests. The 32 input terminals and 4 output terminals are connected to different channel signals via a circular outlet on the front panel 103 of the testing device. The six matrix switches are powered by DC 12V, and all six 12V power adapters are plugged into the internal power socket 5 of the testing device. Power socket 5 is connected to the power switch 6 on the rear panel 104. When power switch 6 is powered, the six matrix switches achieve DC power supply. Powered by 12V, each of the six matrix switches has a USB interface for connecting to the matrix switch MCU. These USB interfaces are then connected to the USB adapter 7 on the rear panel (104). This completes the formation of a matrix switch array with 32 inputs and 4 outputs within the test device. Figure 3 As shown.
[0035] This design implements a 32-input, 4-output test device to meet the board testing requirements of a room temperature controlled chassis system based on superconducting quantum computing. It mainly considers the advantages of single-pole multi-throw (8-input, 1-input, 4-input, and 4-input, 1-output) matrix switches, such as low cost, simple control, high flexibility in modification, and high testing accuracy.
[0036] Furthermore, based on the use of single-pole multi-throw matrix switches, a three-layer design is adopted as the smallest unit to achieve continuous testing of multiple channels (more than 8 channels) and multiple test items. The design principle is as follows: by designing four 8-input 1-output matrix switches 2 (SP8T_1-SP8T_4), 32 channels can be connected at once. The four common terminals of matrix switches 2 (SP8T_1-SP8T_4) are respectively connected to the four input terminals 2IN_1 to 2IN_4 of matrix switch 3 (SP4T_1). By selecting any channel from IN_1 to IN_32 and connecting it to the common terminal of matrix switch 3 (SP4T_1), a 32-channel single-test-item test scheme is achieved. A matrix switch 4 (SP4T_2) is further added. The common terminal of matrix switch 3 (SP4T_1) is connected to the common terminal of matrix switch 4 (SP4T_2), and the output terminals (OUT_1 to OUT_4) are connected to various test instruments to achieve a 32-channel multi-test-item test scheme.
[0037] As can be seen from the design principles above, if only the first layer is retained and the common terminals of the four matrix switches 2 (SP8T_1-SP8T_4) are connected to four different test instruments, only one test item for every eight channels can be achieved. At least 12 cable replacements would be required, connecting the common terminals of the four matrix switches 2 (SP8T_1-SP8T_4) to the remaining three test instruments. If both the first and second layers are retained, the second layer only has one output connected to a test instrument, allowing only one test item for 32 channels. At least three more cable replacements would be needed, connecting the common terminal of matrix switch 3 (SP4T_1) to the remaining three test instruments. Therefore, to meet the requirement of simultaneous access testing for multiple channel inputs and multiple test items, this solution designs a cascaded configuration of three matrix switches to ensure consistent locking levels across all channels and reduce testing errors.
[0038] With product updates and iterations, especially with the increasing integration of control boards for quantum computing, the number of test channels on a single board will increase (i.e., the number of input channels), and the use of test instruments will also increase (i.e., the number of output channels). By measuring the loss of cables between multiple layers and calculating compensation, the combination of matrix switches can be appropriately changed.
[0039] Optionally, the test device designed based on this scheme can realize longitudinal output comparison tests of multi-channel input and single-channel output, such as opening the input channels IN1-IN32 and the output OUT1 respectively; it can also realize lateral comparison tests of single-channel input and multi-channel output, such as opening the input channel IN1 and the output channels OUT1-OUT4 respectively; it can also realize inter-channel crosstalk tests, such as setting the output of the test board's 1 / 2 / 3 channels to output 5GHz frequency signals, opening only the input channel IN2 and the output channel OUT2 (connected to an external spectrum analyzer), and observing the fluctuation value of the output of the output channel OUT2 after the 5GHz frequency signal of the test board's 1 / 3 channels is turned off, etc. These are all commonly used test methods for superconducting quantum computing room temperature control chassis system boards, and different test scenarios can be realized by combining the test device of this scheme according to actual application requirements.
[0040] Of course, those skilled in the art will know that with the development of technology, when more or fewer inputs and outputs are required for the test device, the number and type of matrix switches in each layer can be adjusted accordingly to adapt to different input and output test scenarios.
[0041] The testing apparatus of this embodiment is used to test the circuit boards of a room-temperature controlled chassis system for superconducting quantum computing. It can perform multiple performance tests across all test channels and allows for continuous testing over extended periods (such as evenings or holidays) without human intervention, saving labor costs. To help those skilled in the art better understand the use of this testing apparatus, a connection diagram is provided. Figure 5 As shown, the test device is connected to the test computer via a USB cable. The test computer sends control commands to the MCU modules of each matrix switch. The test device is then connected to each test instrument via SMA cables, thus forming a test system. This system controls the connection of input and output terminals, enabling path selection and parameter testing. This solution further elaborates on a clear and complete description of the comparative test of multi-channel input and single-channel output. The test environment connection relationships are as follows: Figure 5 As shown.
[0042] The testing method of the board testing device in this embodiment includes the following steps:
[0043] Step 1: Setting up the test environment
[0044] according to Figure 1 The assembled test apparatus is shown in the figure, referring to Figure 5 Connect the network port of the test instrument (such as power meter, spectrum analyzer, multimeter, phase noise meter) to the test computer via a network cable; insert the board under test into the chassis of the superconducting quantum room temperature control system and power it on; after the board under test is connected to the test computer via the superconducting quantum room temperature control system chassis adapter, use a network cable.
[0045] Step 2: Connect the test device
[0046] Refer to Figure 5 , connect multiple channels of the board to be tested to the input end of the test device through SMA cable successively, such as input ends IN_1 to IN_32, connect the output ends of the test device, such as output ends OUT_1 to OUT_4 to the power meter, spectrum analyzer, multimeter and phase noise meter respectively, connect the USB adapters 7 connected to the USB interfaces of 6 matrix switches on the test device to the USB interfaces of the test computer through USB cables respectively, and externally provide power input to the test device;
[0047] Step 3: Select the path of the test device
[0048] Combined with Figure 3 and Figure 5 as shown, the test computer is connected to the USB_1 of the test device through the USB interface and issues corresponding instructions. The MCU_1 module of the matrix switch SP8T_1 controls the input end IN_1 and the common end to open, issues corresponding instructions to the MCU_5 module of the matrix switch SP4T_1 through USB_5 to control the input end 2IN_1 and the common end to open, issues corresponding instructions to the MCU_6 module of the matrix switch SP4T_2 through USB_6 to control the common end and the output end OUT_1 to open. Thus, a path is formed between the input end IN_1 and the output end OUT_1 of the test device. Similarly, referring to the above operations, 32×4 = 128 channels can be selected;
[0049] Step 4: Output power test
[0050] The test computer sets the output of channel 1 of the board to be tested to a fixed power A1 (such as 0 dBm) through the network port, and the test computer opens the path between the input end IN_1 and the output end OUT_1 through the USB interface; the test computer reads the measured value A2 of the power meter connected to the output end OUT_1 through the network cable; calculates the difference between the set value A1 and the read value A2 through the test computer software. If the error requirement is met, it is judged that the test is qualified, and the path formed by the input end IN_1 and the output end OUT_1 is closed. If the error requirement is not met, the path is reopened for retest. Similarly, open the paths between the input ends IN_2 to IN_32 and the output end OUT_1 respectively to complete the output power test of each channel of the board to be tested;
[0051] Step 5: Remaining test items
[0052] Similar to step four, the test computer opens the input terminals IN_1 to IN_32 and the output terminal OUT_2 via the USB interface to complete the spurious-free dynamic range (SFDR) test for each channel; opens the input terminals IN_1 to IN_32 and the output terminal OUT_3 to complete the output static voltage calibration test for each channel; opens the input terminals IN_1 to IN_32 and the output terminal OUT_4 to complete the phase noise test for each channel of the board under test, until all performance tests of the board under test are completed.
[0053] Example 2
[0054] Based on the solution in Example 1, and according to existing testing requirements, the number of input and output channels can be quickly recombined without changing the hardware. For example, the matrix switch SP4T_2 on the third layer can be swapped with the matrix switch SP8T_4 on the first layer. In this case, matrix switch SP4T_2 acts as a 4-input, 1-output switch, while SP8T_4 acts as a 1-input, 8-output switch, thus realizing a 28-input, 8-output testing device. Figure 4 As shown.
[0055] Similarly, the test device designed based on this scheme can realize longitudinal output comparison tests of multi-channel input and single-channel output, such as opening the input channels IN1-IN28 and the output OUT1 respectively; it can also realize lateral comparison tests of single-channel input and multi-channel output, such as opening the input channel IN1 and the output channels OUT1-OUT8 respectively; it can also realize inter-channel crosstalk tests, such as setting the output of the test board's 1 / 2 / 3 channels to output 5GHz frequency signals, opening only the input channel IN2 and the output channel OUT2 (connected to an external spectrum analyzer), and observing the fluctuation value of the output of the output channel OUT2 after the 5GHz frequency signal of the test board's 1 / 3 channels is turned off, etc. These are all commonly used test methods for superconducting quantum computing room temperature control chassis system boards, and different test scenarios can be realized by combining the test device of this scheme according to actual application needs.
Claims
1. A board testing device for a room-temperature controlled chassis system based on superconducting quantum computing, characterized in that, The test device includes a chassis base plate (101), a cover plate (102), a front panel (103), a rear panel (104), and a matrix switch array inside the test device. The front panel (103) is provided with multiple test input terminals and multiple test output terminals. The rear panel (104) is equipped with a power switch (6) and a USB adapter (7). The USB adapter (7) is connected to the matrix switch array. The power socket (5) is connected to the power switch (6). The matrix switch array and the power socket (5) are fixed on the base plate (101). The cover plate (102), the front panel (103), and the rear panel (104) are respectively installed on the base plate (101) to form the test device chassis shell.
2. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 1, characterized in that, The matrix switch array includes six matrix switches, which are divided into three layers. The first layer contains four eight-input, one-output matrix switches SP8T_1-SP8T_4, which have 32 input terminals IN_1 to IN_32. The four common terminals are connected to the four input terminals of the four-input, one-output matrix switch SP4T_1 in the second layer. The common terminal of the second layer is connected to the common terminal of the one-input, four-output matrix switch SP4T_2 in the third layer. The third layer has four output terminals OUT_1 to OUT_4, forming a matrix switch array with 32 inputs and 4 outputs.
3. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 1, characterized in that, The matrix switch array comprises six matrix switches, which are arranged in three layers. The first layer contains three eight-input, one-output matrix switches SP8T_1-SP8T_3 and one four-input, one-output matrix switch SP4T_2, which has 28 input terminals IN_1 to IN_28 externally. The four common terminals are connected to the four input terminals of the four-input, one-output matrix switch SP4T_1 in the second layer. The common terminal of the second layer is connected to the common terminal of the one-input, eight-output matrix switch SP8T_4 in the third layer. The third layer has eight output terminals OUT_1 to OUT_8, forming a matrix switch array with 28 inputs and 8 outputs.
4. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 2 or 3, characterized in that, There are six USB adapters (7), and the six USB adapters (7) are respectively connected to the USB interfaces USB_1-USB_6 of the six matrix switches.
5. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 1, characterized in that, It also includes power adapters, each power adapter being connected to one of the matrix switches in the matrix switch combination array, and the power adapters being plugged into a power socket (5).
6. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 5, characterized in that, The power adapter is a DC 12V power adapter.
7. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 1, characterized in that, The cover plate (102) has an opening above the matrix switch array, and a transparent acrylic panel (8) is installed on the opening.
8. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 7, characterized in that, It also includes a front panel film (9), which is attached to the front panel (103) by its own adhesive backing.
9. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 1, characterized in that, The power switch (6) is a rocker switch.
10. The board testing device for a superconducting quantum computing room temperature controlled chassis system as described in claim 1, characterized in that, The cover plate (102) is an integrated cover plate, and the cover plate (102) has a grid on its side.