Display device

Abstract

The display device includes a substrate and a bank layer disposed on the substrate and defining a first emission region, a second emission region, and a third emission region. Each of the first emission region, the second emission region, and the third emission region includes a first electrode and a second electrode extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and a plurality of light emitting elements disposed between the first electrode and the second electrode, the first emission region and the second emission region are adjacent to each other in a first direction, the third emission region is spaced apart from the first emission region or the second emission region in a second direction, and the first emission region, the second emission region, and the third emission region emit light of different colors.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display apparatus. BACKGROUND

[0002] With the development of multimedia technology, the importance of display apparatuses is increasing. With this trend, various types of display apparatuses such as organic light emitting displays (OLED), liquid crystal displays (LCD), etc. have been used.

[0003] As an apparatus for displaying an image of a display apparatus, there are self-emissive display apparatuses including light emitting elements. The self-emissive display apparatuses include an organic light emitting display apparatus using an organic material as a light emitting material as a light emitting element, an inorganic light emitting display apparatus using an inorganic material as a light emitting material, etc. SUMMARY

[0004] Aspects of the disclosure provide a high-resolution display apparatus by reducing the number of electrodes aligned with light emitting elements.

[0005] However, aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent by reference to the detailed description of the disclosure given below.

[0006] According to an embodiment of the disclosure, a display apparatus can include a substrate, and a bank layer disposed on the substrate and defining a first emission area, a second emission area, and a third emission area. Each of the first emission area, the second emission area, and the third emission area can include first electrodes and second electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and a plurality of light emitting elements disposed between the first electrodes and the second electrodes. The first emission area and the second emission area can be adjacent to each other in the first direction, the third emission area can be spaced apart from the first emission area or the second emission area in the second direction, and the first emission area, the second emission area, and the third emission area can emit different colors of light.

[0007] In an embodiment, an extension direction of the first electrodes of the first emission area can be aligned with an extension direction of the first electrodes of the second emission area, an extension direction of the second electrodes of the first emission area can be aligned with an extension direction of the second electrodes of the second emission area, the first electrodes of the third emission area can be spaced apart from the first electrodes of the first emission area in the second direction, and the second electrodes of the third emission area can be spaced apart from the second electrodes of the first emission area in the second direction.

[0008] In an embodiment, the first emission area can emit red light, the second emission area can emit blue light, and the third emission area can emit green light.

[0009] In an embodiment, in a plan view, a size of the third emission area can be greater than a size of the first emission area or a size of the second emission area, and the size of the first emission area can be equal to the size of the second emission area.

[0010] In an embodiment, the bank layer can further define a fourth emission area and a fifth emission area spaced apart in the first direction, and the third emission area can be interposed between the fourth emission area and the fifth emission area. Each of the fourth emission area and the fifth emission area can include the first electrode, the second electrode, and the plurality of light emitting elements, the fourth emission area and the first emission area can emit the same color of light, and the fifth emission area and the second emission area can emit the same color of light.

[0011] According to an embodiment of the disclosure, a display apparatus can include a substrate and a bank layer disposed on the substrate and defining a first emission area, a second emission area, a third emission area, and a fourth emission area. Each of the first emission area, the second emission area, the third emission area, and the fourth emission area can include first electrodes and second electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and a plurality of light emitting elements disposed between the first electrodes and the second electrodes. The first emission area and the second emission area can be adjacent to each other in the first direction, the third emission area and the fourth emission area can be adjacent to each other in the first direction, the third emission area and the fourth emission area can be spaced apart from the first emission area or the second emission area in the second direction, the first emission area, the second emission area, and the third emission area can emit different colors of light, and the third emission area and the fourth emission area can emit the same color of light.

[0012] In an embodiment, an extension direction of the first electrode of the first emission area can be aligned with an extension direction of the first electrode of the second emission area, an extension direction of the first electrode of the third emission area can be aligned with an extension direction of the first electrode of the fourth emission area, the first electrode of the third emission area and the first electrode of the fourth emission area can be spaced apart from the first electrode of the first emission area in the second direction, and the second electrode of the third emission area and the second electrode of the fourth emission area can be spaced apart from the second electrode of the first emission area in the second direction.

[0013] In an embodiment, the first emission area can emit red light, the second emission area can emit blue light, and the third emission area and the fourth emission area can emit green light.

[0014] In an embodiment, in a plan view, the sizes of the first emission area, the second emission area, the third emission area, and the fourth emission area can be equal, and wherein, in the first direction, the lengths of the first electrode of the first emission area, the first electrode of the second emission area, the first electrode of the third emission area, and the first electrode of the fourth emission area can be equal.

[0015] In an embodiment, the bank layer can further define a fifth emission area and a sixth emission area spaced apart in the first direction, and the third emission area is interposed between the fifth emission area and the sixth emission area. Each of the fifth emission area and the sixth emission area can include a first electrode, a second electrode, and a plurality of light emitting elements, and the fifth emission area and the second emission area can emit the same color of light, and the sixth emission area and the first emission area can emit the same color of light.

[0016] In the display apparatus according to an embodiment, since the emission areas adjacent to each other in the first direction or the second direction are disposed to emit different colors of light, the number of electrodes can be reduced, and thus more emission areas can be formed, thereby implementing a high-resolution display apparatus.

[0017] However, effects according to embodiments of the disclosure are not limited to those of the above examples, and various other effects are incorporated herein. BRIEF DESCRIPTION OF DRAWINGS

[0018] Embodiments of the disclosure will be described in detail with reference to the accompanying drawings, in which:

[0019] Figure 1 is a schematic plan view of a display apparatus according to an embodiment;

[0020] Figure 2 is a plan view illustrating an arrangement of a plurality of wiring lines included in a display apparatus according to an embodiment;

[0021] Figure 3 is a schematic view of an equivalent circuit of a sub-pixel according to an embodiment;

[0022] Figure 4 is a plan view illustrating one sub-pixel of a display apparatus according to an embodiment;

[0023] Figure 5 is a cross-sectional view taken along line E1-E1' of Figure 4 ;

[0024] Figure 6 is a cross-sectional view taken along line E2-E2' of Figure 4 ;

[0025] Figure 7 is a schematic perspective view of a light emitting element according to one embodiment;

[0026] Figure 8 is a schematic cross-sectional view of a display device according to one embodiment;

[0027] Figure 9 is a plan view showing a plurality of pixels of a display device according to one embodiment;

[0028] Figure 10 is a plan view showing a plurality of pixels of a display device according to another embodiment;

[0029] Figure 11 is a plan view showing a plurality of pixels of a display device according to still another embodiment;

[0030] Figure 12 is a plan view showing a plurality of pixels of a display device according to still another embodiment;

[0031] Figure 13 is a plan view showing a plurality of pixels of a display device according to still another embodiment;

[0032] Figure 14 is a plan view showing a plurality of pixels of a display device according to still another embodiment;

[0033] Figure 15 is a plan view showing a plurality of pixels of a display device according to still another embodiment;

[0034] Figure 16 is a plan view showing a plurality of pixels of a display device according to still another embodiment;

[0035] Figure 17 is a plan view showing a plurality of pixels of a display device according to still another embodiment; and

[0036] Figure 18 is a plan view showing a plurality of pixels of a display device according to still another embodiment. DETAILED DESCRIPTION

[0037] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0038] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” can refer to physical, electrical, and / or fluidic connections that are made or are not made with intervening elements. Furthermore, elements can be “in contact” with or “in contact” another element, or the like, which can mean that the elements are “in electrical contact” or “in physical contact”, or are “indirectly in contact” or “directly in contact” with the other element. Identical reference numbers can indicate identical components throughout the specification.

[0039] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper", "on", "directly on" and the like can be used herein for description of one ( s ) element or features'relationship to another ( s ) element or feature s ) as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the drawings. For example, if a device in the drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and, accordingly, spatially relative terms utilized herein are to be interpreted accordingly.

[0040] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element could be termed a first element.

[0041] In the description and claims, the phrase "at least one of" is intended to include the meaning of "at least one of a group of items" for its intended meaning, for example, "at least one of A and B" is intended to include A, B, or A and B. In the description and claims, the term "and / or" is intended to include any combination of the terms "and" and "or", for its intended meaning, for example, "A and / or B" is intended to include A, B, or A and B. The terms "and" and "or" can be used in a conjunctive or disjunctive sense, and can be understood as equivalent to "and / or".

[0042] The terms used in the present description are used only for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises", "comprising", "includes", "including", "contains", "containing", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] Each of the features of various embodiments of the present disclosure can be partially or wholly combined or combined with each other, and various interlocking and driving in the art are possible. Each embodiment can be implemented independently of each other, or can be implemented in association with each other.

[0044] Unless otherwise defined or implied herein, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless specifically so defined in the specification.

[0045] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0046] Figure 1 is a schematic plan view of a display apparatus according to an embodiment.

[0047] Referring to Figure 1 The display apparatus 10 can display a moving image or a still image. The display apparatus 10 can be any electronic apparatus that provides a display screen. Examples of the display apparatus 10 can include a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet Personal Computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a Portable Multimedia Player (PMP), a navigation apparatus, a game machine, a digital camera, a camcorder, etc. that provide a display screen.

[0048] The display device 10 can include a display panel that provides a display screen. Examples of the display panel can include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, and a field emission display panel. In the following description, an embodiment in which an inorganic light emitting diode display panel is applied as the display panel will be described, but the present disclosure is not limited thereto, and other display panels can be applied within the same scope of the technical spirit.

[0049] The shape of the display device 10 can be variously modified. For example, the display device 10 can have a shape such as a rectangular shape elongated in a horizontal direction, a rectangular shape elongated in a vertical direction, a square shape, a quadrilateral shape having rounded corners (vertices), another polygonal shape, and a circular shape in a plan view. The shape of the display area DPA of the display device 10 can be similar to the overall shape of the display device 10. Figure 1 The display device 10 is schematically shown to have a rectangular shape elongated in the second direction DR2.

[0050] The display device 10 can include a display area DPA and a non-display area NDA. The display area DPA can be an area in which an image can be displayed, and the non-display area NDA can be an area in which an image is not displayed. The display area DPA can be referred to as an active area, and the non-display area NDA can be referred to as an inactive area. The display area DPA can substantially occupy the center of the display device 10.

[0051] The display area DPA can include a plurality of pixels PX. The pixels PX can be arranged in a matrix. In a plan view, the shape of each pixel PX can be a rectangular shape or a square shape. However, the present disclosure is not limited thereto, and the shape of each pixel PX can be a rhombic shape in which each side is inclined with respect to a direction. The pixels PX can be arranged in a stripe pattern or an island pattern. Each of the pixels PX can include one or more light emitting elements that emit light of a wavelength band to display a color.

[0052] The non-display area NDA can be disposed adjacent to the display area DPA. In a plan view, the non-display area NDA can completely or partially surround the display area DPA. The display area DPA can have a rectangular shape in a plan view, and the non-display area NDA can be disposed adjacent to the side portions of the display area DPA. The non-display area NDA can form a bezel of the display device 10. Wires or circuit drivers included in the display device 10 can be disposed in the non-display area NDA, or external devices can be mounted in the non-display area NDA.

[0053] Figure 2 is a plan view showing an arrangement of a plurality of wires included in a display device according to one embodiment.

[0054] Referring to Figure 2 The display device 10 can include a plurality of wirings. The display device 10 can include a plurality of scan lines SL (SL1, SL2, and SL3), a plurality of data lines DTL (DTL1, DTL2, and DTL3), an initialization voltage line VIL, and a plurality of voltage lines VL (VL1, VL2, VL3, and VL4). Although not shown in the drawings, other wirings can also be provided in the display device 10.

[0055] The first scan line SL1 and the second scan line SL2 can extend in the first direction DR1. The first scan line SL1 and the second scan line SL2 can be disposed adjacent to each other and can be spaced apart from another first scan line SL1 and another second scan line SL2 in the second direction DR2. The first scan line SL1 and the second scan line SL2 can be connected to a scan line pad WPD_SC connected to a scan driver (not shown). The first scan line SL1 and the second scan line SL2 can extend from a pad area PDA disposed in the non-display area NDA to the display area DPA.

[0056] The third scan line SL3 can extend in the second direction DR2 and can be spaced apart from another third scan line SL3 in the first direction DR1. The third scan line SL3 can be connected to one or more first scan lines SL1 or one or more second scan lines SL2. In one embodiment, the first scan line SL1 and the second scan line SL2 can be formed as conductive layers disposed in different layers from the third scan line SL3. The scan lines SL can have a grid structure in the entire surface of the display area DPA, but the present disclosure is not limited thereto.

[0057] The term "connected" as used herein can mean not only that a member is connected to another member by physical contact, but also that a member is connected to another member by a further member. This can also be understood as a member connected as one integral element with another part of the integral element via another element. Furthermore, if a member is connected to another member, this can be interpreted as meaning an electrical connection via a further element in addition to including a direct connection by physical contact.

[0058] The data lines DTL can extend in the first direction DR1. The data lines DTL can include first data lines DTL1, second data lines DTL2, and third data lines DTL3, and the first data lines DTL1, the second data lines DTL2, and the third data lines DTL3 can form a group and can be disposed adjacent to each other. Each of the data lines DTL1, DTL2, and DTL3 can extend from the pad area PDA disposed in the non-display area NDA to the display area DPA. However, the present disclosure is not limited thereto, and the data lines DTL can be spaced apart from each other at equal intervals between the first voltage lines VL1 and the second voltage lines VL2 to be described below.

[0059] The initialization voltage lines VIL can extend in the first direction DR1. The initialization voltage lines VIL can be disposed between the data lines DTL and the first scan lines SL1 and the second scan lines SL2. The initialization voltage lines VIL can extend from the pad area PDA disposed in the non-display area NDA to the display area DPA.

[0060] The first voltage lines VL1 and the second voltage lines VL2 can extend in the first direction DR1, and the third voltage lines VL3 and the fourth voltage lines VL4 can extend in the second direction DR2. The first voltage lines VL1 and the second voltage lines VL2 can be alternately disposed in the second direction DR2, and the third voltage lines VL3 and the fourth voltage lines VL4 can be alternately disposed in the first direction DR1. The first voltage lines VL1 and the second voltage lines VL2 can extend in the first direction DR1 across the display area DPA, some of the third voltage lines VL3 and the fourth voltage lines VL4 can be disposed in the display area DPA, and others of the third voltage lines VL3 and the fourth voltage lines VL4 can be disposed in the non-display area NDA located on a side of the display area DPA in the first direction DR1. The first voltage lines VL1 and the second voltage lines VL2 can be formed as conductive layers disposed in different layers from the third voltage lines VL3 and the fourth voltage lines VL4. The first voltage lines VL1 can be connected to at least one third voltage line VL3, the second voltage lines VL2 can be connected to at least one fourth voltage line VL4, and the voltage lines VL can have a mesh structure in the entire display area DPA. However, the present disclosure is not limited thereto.

[0061] The first scan line SL1, the second scan line SL2, the data line DTL, the initialization voltage line VIL, the first voltage line VL1, and the second voltage line VL2 can be electrically connected to at least one line pad WPD. Each line pad WPD can be provided in the non-display area NDA. In one embodiment, each of the line pads WPD can be provided in a pad area PDA on the lower side located on the other side of the display area DPA in the first direction DR1. The first scan line SL1 and the second scan line SL2 can be connected to a scan line pad WPD_SC provided in the pad area PDA, and the data line DTL can be connected to a respective data line pad WPD_DT. The initialization voltage line VIL can be connected to an initialization line pad WPD_Vint, the first voltage line VL1 can be connected to a first voltage line pad WPD_VL1, and the second voltage line VL2 can be connected to a second voltage line pad WPD_VL2. An external device can be mounted on the line pad WPD. The external device can be mounted on the line pad WPD by applying an anisotropic conductive film, ultrasonic bonding, or the like. The drawing shows that each of the line pads WPD is provided in the pad area PDA provided on the lower side of the display area DPA, but the present disclosure is not limited thereto. Some of the line pads WPD can be provided in an area on the upper side or on the left and right sides of the display area DPA.

[0062] Each pixel PX or sub-pixel SPXn (n is an integer of 1 to 3) of the display device 10 can include a pixel driving circuit. The above-described wiring can pass through each pixel PX or the vicinity of each pixel PX to apply a driving signal to each pixel driving circuit. The pixel driving circuit can include a transistor and a capacitor. The number of transistors and capacitors of each pixel driving circuit can be variously modified. According to one embodiment, in each sub-pixel SPXn of the display device 10, the pixel driving circuit can have a 3T1C structure including three transistors and one capacitor. Hereinafter, the pixel driving circuit of the 3T1C structure will be described according to an embodiment, but the present disclosure is not limited thereto, and various other modified structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure can be applied.

[0063] Figure 3 is a schematic view of an equivalent circuit of a sub-pixel according to one embodiment.

[0064] Reference Figure 3 Each sub-pixel SPXn of the display device 10 according to one embodiment can include three transistors T1, T2, and T3 and one storage capacitor Cst in addition to a light emitting diode EL.

[0065] The light emitting diode EL can emit light by a current supplied from the first transistor T1. The light emitting diode EL can include a first electrode, a second electrode, and at least one light emitting element disposed between the first electrode and the second electrode. The light emitting element can emit light of a wavelength band by an electrical signal emitted from the first electrode and the second electrode.

[0066] One end portion of the light emitting diode EL can be connected to the source electrode of the first transistor T1, and the other end portion of the light emitting diode EL can be connected to a second voltage line VL2 to which a low potential voltage (hereinafter referred to as a second power voltage) lower than a high potential voltage (hereinafter referred to as a first power voltage) of the first voltage line VL1 is supplied.

[0067] The first transistor T1 can adjust a current flowing from the first voltage line VL1 to which the first power voltage is supplied to the light emitting diode EL according to a voltage difference between the gate electrode and the source electrode. For example, the first transistor T1 can be a driving transistor for driving the light emitting diode EL. The gate electrode of the first transistor T1 can be connected to the source electrode of the second transistor T2, the source electrode of the first transistor T1 can be connected to the first electrode of the light emitting diode EL, and the drain electrode of the first transistor T1 can be connected to the first voltage line VL1 to which the first power voltage is applied.

[0068] The second transistor T2 can be turned on by a scan signal of the first scan line SL1 to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the first scan line SL1, the source electrode of the second transistor T2 can be connected to the gate electrode of the first transistor T1, and the drain electrode of the second transistor T2 can be connected to the data line DTL.

[0069] The third transistor T3 can be turned on by a scan signal of the second scan line SL2 to connect the initialization voltage line VIL to one end portion of the light emitting diode EL. The gate electrode of the third transistor T3 can be connected to the second scan line SL2, the drain electrode of the third transistor T3 can be connected to the initialization voltage line VIL, and the source electrode of the third transistor T3 can be connected to one end portion of the light emitting diode EL or to the source electrode of the first transistor T1.

[0070] However, the source electrode and the drain electrode of each of the transistors T1, T2, and T3 are not limited to the above-described source electrode and drain electrode. Each of the transistors T1, T2, and T3 can be formed of a thin film transistor. In this case, the source electrode and the drain electrode of each of the transistors T1, T2, and T3 can be connected to each other by a via hole. Figure 3In the embodiment, each of the transistors T1, T2, and T3 is described as being formed of an N-type metal oxide semiconductor field effect transistor (MOSFET), but the present disclosure is not limited thereto. In another embodiment, each of the transistors T1, T2, and T3 can be formed of a P-type MOSFET. In another embodiment, some of the transistors T1, T2, and T3 can be formed of an N-type MOSFET, and others of the transistors T1, T2, and T3 can be formed of a P-type MOSFET.

[0071] The storage capacitor Cst can be formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst can store a voltage difference between the gate voltage and the source voltage of the first transistor T1.

[0072] Hereinafter, the structure of the pixel PX of the display apparatus 10 according to an embodiment will be described in further detail with reference to other drawings.

[0073] Figure 4 is a plan view showing one sub-pixel of a display apparatus according to an embodiment. Figure 4 The planar arrangement of the electrodes RME (RME1 and RME2), the bank patterns BP1 and BP2, the bank layer BNL, the plurality of light emitting elements ED, and the connection electrodes CNE (CNE1 and CNE2) provided in one sub-pixel SPX of the display apparatus 10 is schematically shown.

[0074] Reference Figure 4 The display apparatus 10 can include a plurality of sub-pixels SPXn. The plurality of sub-pixels SPXn can constitute one pixel. Each sub-pixel SPXn of the display apparatus 10 can include an emission area EMA and a non-emission area. The emission area EMA can be an area in which a light emitting element ED is provided to emit light of a wavelength band. The non-emission area can be an area in which the light emitting element ED is not provided and an area that does not emit light since light emitted from the light emitting element ED does not reach the area.

[0075] The emission area EMA can include an area in which the light emitting element ED is provided and an area adjacent to the light emitting element ED in which light emitted from the light emitting element ED is emitted. For example, the emission area EMA can include an area in which light emitted from the light emitting element ED is reflected or refracted by another member and emitted. The light emitting element ED can be provided in each sub-pixel SPXn, and the emission area EMA can include an area in which the light emitting element ED is provided and an area adjacent to the area in which the light emitting element ED is provided.

[0076] The sub-pixel SPXn can further include a sub-area SA disposed in the non-emission area. The sub-area SA of the corresponding sub-pixel SPXn can be disposed on a lower side as the other side in the first direction DR1. The emission area EMA and the sub-area SA can be alternately arranged in the first direction DR1, and the sub-area SA can be disposed between the emission areas EMA of different sub-pixels SPXn spaced apart from each other in the first direction DR1. For example, the emission areas EMA and the sub-areas SA can be alternately arranged in the first direction DR1, and each of the emission areas EMA and the sub-areas SA can be repeatedly arranged in the second direction DR2.

[0077] Since the light emitting element ED is not disposed in the sub-area SA, light can not be emitted from the sub-area SA, but a portion of the electrode RME in the sub-pixel SPXn can be disposed in the sub-area SA. The electrodes RME disposed in different sub-pixels SPXn can be separated at the separate portion ROP of the sub-area SA.

[0078] The wiring and the circuit element of the circuit layer disposed in the sub-pixel SPXn can be connected to the light emitting element ED. However, the wiring and the circuit element can not be disposed to correspond to an area occupied by the sub-pixel SPXn or the emission area EMA, and can be disposed regardless of a position of the emission area EMA.

[0079] In a plan view, the bank layer BNL can surround the sub-pixel SPXn, the emission area EMA, and the sub-area SA. The bank layer BNL can be disposed at a boundary between the sub-pixels SPXn adjacent in the first direction DR1 and the second direction DR2 and at a boundary between the emission area EMA and the sub-area SA. The sub-pixel SPXn, the emission area EMA, and the sub-area SA of the display apparatus 10 can be areas defined by the arrangement of the bank layer BNL. A gap between the sub-pixel SPXn, the emission area EMA, and the sub-area SA can vary according to a width of the bank layer BNL.

[0080] The bank layer BNL can include a portion extending in the first direction DR1 and the second direction DR2 in a plan view to be arranged in a lattice pattern throughout an entire surface of the display area DPA. The bank layer BNL can be disposed along a boundary between the sub-pixels SPXn to define adjacent sub-pixels SPXn. The bank layer BNL can also surround the emission area EMA and the sub-area SA disposed for each sub-pixel SPXn to define the emission area EMA and the sub-area SA to be spaced apart from each other.

[0081] Figure 5 is a schematic cross-sectional view taken along the line E1-E1' of Figure 4 is a schematic cross-sectional view taken along the line E2-E2' of Figure 6 is a schematic cross-sectional view taken along the line E2-E2' of Figure 4 is a schematic cross-sectional view taken along the line E2-E2' ofFigure 5 A cross section across an end of the light emitting element ED and the electrode contact hole CTD and CTS provided in the sub-pixel SPXn is schematically shown, and Figure 6 A cross section across an end of the light emitting element ED and the contact portion CT1 and CT2 provided in the sub-pixel SPXn is schematically shown.

[0082] In conjunction with Figure 4 Referring to Figure 5 and Figure 6 The display device 10 can include a wiring substrate 101 including a first substrate SUB, and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers provided on the first substrate SUB. Further, the display device 10 can include electrodes RME (RME1 and RME2), a light emitting element ED, and connection electrodes CNE (CNE1 and CNE2) provided on the wiring substrate 101. The semiconductor layer, the conductive layers, and the insulating layers of the wiring substrate 101 can constitute a circuit layer of the display device 10.

[0083] The first substrate SUB can be an insulating substrate. The first substrate SUB can be made of an insulating material such as glass, quartz, or a polymer resin. Further, the first substrate SUB can be a rigid substrate, or can be a flexible substrate that is bendable, foldable, or rollable. The first substrate SUB can include a display area DPA and a non-display area NDA adjacent to the display area DPA, and the display area DPA can include an emission area EMA and a sub-area SA that is part of a non-emission area.

[0084] The first conductive layer can be provided on the first substrate SUB. The first conductive layer can include a bottom metal layer BML that overlaps the first active layer ACT1 of the first transistor T1 in a plan view. The bottom metal layer BML can prevent light from entering the first active layer ACT1 of the first transistor T1, or can be electrically connected to the first active layer ACT1 to stabilize the electrical characteristics of the first transistor T1. However, the present disclosure is not limited thereto, and in another embodiment, the bottom metal layer BML can be omitted.

[0085] The buffer layer BL can be provided on the bottom metal layer BML and the first substrate SUB. The buffer layer BL can be formed on the first substrate SUB to protect the transistors of the pixel PX from moisture penetration through the first substrate SUB that is susceptible to moisture penetration, and can perform a surface planarization function.

[0086] The semiconductor layer can be provided on the buffer layer BL. The semiconductor layer can include the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2. The first active layer ACT1 and the second active layer ACT2 can partially overlap the first gate electrode G1 and the second gate electrode G2, respectively, of the second conductive layer described below in a plan view.

[0087] The semiconductor layer can include at least one of polysilicon, single crystal silicon, an oxide semiconductor, and the like. For example, the semiconductor layer can include polysilicon. The oxide semiconductor can be an oxide semiconductor containing indium (In). For example, the oxide semiconductor can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0088] Although one first transistor T1 is shown to be disposed in the sub-pixel SPXn of the display apparatus 10 in the drawings, the disclosure is not limited thereto, and the display apparatus 10 can include a greater number of transistors.

[0089] The first gate insulating layer GI can be disposed on the semiconductor layer and the buffer layer BL in the display area DPA. The first gate insulating layer GI can not be disposed in the pad area PDA. The first gate insulating layer GI can function as a gate insulating film of each of the transistors T1 and T2. Although the first gate insulating layer GI is shown to be disposed on the entire buffer layer BL in the drawings, the disclosure is not limited thereto. In some embodiments, the first gate insulating layer GI can be patterned together with gate electrodes G1 and G2 (to be described below) of the second conductive layer to be partially disposed between the second conductive layer and the active layers ACT1 and ACT2 of the semiconductor layer.

[0090] The second conductive layer can be disposed on the first gate insulating layer GI. The second conductive layer can include a first gate electrode G1 of the first transistor T1 and a second gate electrode G2 of the second transistor T2. The first gate electrode G1 can overlap a channel region of the first active layer ACT1 in a third direction DR3 that is a thickness direction, and the second gate electrode G2 can overlap a channel region of the second active layer ACT2 in the third direction DR3 that is a thickness direction. Although not shown in the drawings, the second conductive layer can further include an electrode of a storage capacitor.

[0091] The first interlayer insulating layer IL1 can be disposed on the second conductive layer. The first interlayer insulating layer IL1 can function as an insulating film between the second conductive layer and other layers disposed on the first interlayer insulating layer IL1, and can protect the second conductive layer.

[0092] The third conductive layer can be disposed on the first interlayer insulating layer IL1. The third conductive layer can include the first and second voltage lines VL1 and VL2, the first conductive pattern CDP1, the source and drain electrodes S1 and D1 of the first transistor T1, and the source and drain electrodes S2 and D2 of the second transistor T2, which are disposed in the display area DPA. Although not shown in the drawings, the third conductive layer can further include another electrode of the storage capacitor.

[0093] The first voltage line VL1 can be applied with a high potential voltage (or a first power voltage) transmitted to the first electrode RME1, and the second voltage line VL2 can be applied with a low potential voltage (or a second power voltage) transmitted to the second electrode RME2. A portion of the first voltage line VL1 can contact the first active layer ACT1 of the first transistor T1 through a contact hole passing through the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first voltage line VL1 can function as the first drain electrode D1 of the first transistor T1. The second voltage line VL2 can be connected to (e.g., directly connected to) the second electrode RME2 to be described below.

[0094] The first conductive pattern CDP1 can contact the first active layer ACT1 of the first transistor T1 through a contact hole passing through the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first conductive pattern CDP1 can contact the lower metal layer BML through another contact hole. The first conductive pattern CDP1 can function as the first source electrode S1 of the first transistor T1. In addition, the first conductive pattern CDP1 can be connected to the first electrode RME1 or the first connection electrode CNE1 to be described below. The first transistor T1 can transmit the first power voltage applied from the first voltage line VL1 to the first electrode RME1 or the first connection electrode CNE1.

[0095] The second source and drain electrodes S2 and D2 can contact the second active layer ACT2 of the second transistor T2 through a contact hole passing through the first interlayer insulating layer IL1 and the first gate insulating layer GI. The second transistor T2 can be one of the switching transistors described above. Figure 3 The second transistor T2 can transmit a signal applied from the data line DTL of the first transistor T1 to the first transistor T1, or can transmit a signal applied from the initialization voltage line VIL of the second transistor T2 to the other electrode of the storage capacitor Cst (refer to FIG. 1). Figure 3 Figure 3 The second transistor T2 can transmit a signal applied from the data line DTL of the first transistor T1 to the first transistor T1, or can transmit a signal applied from the initialization voltage line VIL of the second transistor T2 to the other electrode of the storage capacitor Cst (refer to FIG. 1). Figure 3

[0096] The first passivation layer PV1 can be disposed on the third conductive layer. The first passivation layer PV1 can function as an insulating layer between the third conductive layer and other layers, and can protect the third conductive layer.

[0097] ​​The buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first passivation layer PV1 described above can be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first passivation layer PV1 can be formed as a bilayer formed by stacking inorganic layers including at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ), or a multilayer formed by alternately stacking inorganic layers including at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ). However, the present disclosure is not limited thereto, and in another embodiment, the buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first passivation layer PV1 can be formed as a single inorganic layer containing the insulating material described above. In another embodiment, the first interlayer insulating layer IL1 can be made of an organic insulating material such as polyimide (PI) or the like.

[0098] The via layer VIA can be provided on the third conductive layer in the display area DPA. The via layer VIA can contain an organic insulating material such as polyimide (PI), and can compensate for a stepped portion formed by the conductive layer provided under the via layer VIA to planarize the top surface. However, the present disclosure is not limited thereto, and in another embodiment, the via layer VIA can be omitted.

[0099] The display device 10 can include the bank patterns BP1 and BP2, the electrodes RME (RME1 and RME2), the bank layer BNL, the light emitting element ED, and the connection electrode CNE (CNE1 and CNE2) as a display element layer provided on the via layer VIA of the wiring substrate 101. Further, the display device 10 can include a plurality of insulating layers PAS1, PAS2, and PAS3 provided on the wiring substrate 101.

[0100] The bank patterns BP1 and BP2 can be provided in the emission area EMA of each sub-pixel SPXn. The bank patterns BP1 and BP2 can have a width in the second direction DR2, and can have a shape extending in the first direction DR1.

[0101] For example, the bank pattern BP1 and BP2 can include a first bank pattern BP1 and a second bank pattern BP2 spaced apart from each other in the second direction DR2 in the emission area EMA of each sub-pixel SPXn. The first bank pattern BP1 can be disposed on the left side (one side of the second direction DR2) with respect to the center of the emission area EMA, and the second bank pattern BP2 can be disposed on the right side (the other side of the second direction DR2) with respect to the center of the emission area EMA while being spaced apart from the first bank pattern BP1. The first bank pattern BP1 and the second bank pattern BP2 can be alternately disposed in the second direction DR2, and can be arranged in an island pattern in the display area DPA. The light emitting element ED can be disposed between the first bank pattern BP1 and the second bank pattern BP2.

[0102] The lengths of the first bank pattern BP1 and the second bank pattern BP2 in the first direction DR1 can be the same, and can be smaller than the length of the emission area EMA surrounded by the bank layer BNL in the first direction DR1. The first bank pattern BP1 and the second bank pattern BP2 can be spaced apart from the portion of the bank layer BNL extending in the second direction DR2. However, the present disclosure is not limited thereto, and the bank patterns BP1 and BP2 can be integrated with the bank layer BNL, or can partially overlap the portion of the bank layer BNL extending in the second direction DR2, and the lengths of the bank patterns BP1 and BP2 in the first direction DR1 can be greater than or equal to the length of the emission area EMA surrounded by the bank layer BNL in the first direction DR1.

[0103] The widths of the first bank pattern BP1 and the second bank pattern BP2 in the second direction DR2 can be the same. However, the present disclosure is not limited thereto, and in another embodiment, the first bank pattern BP1 and the second bank pattern BP2 can have different widths. For example, one bank pattern can have a greater width than the other bank pattern, and the bank pattern having the greater width can be disposed across the emission area EMA of another sub-pixel SPXn adjacent in the second direction DR2. In the bank pattern disposed across the emission area EMA, the portion of the bank layer BNL extending in the first direction DR1 can overlap the second bank pattern BP2 in the thickness direction. Although two bank patterns BP1 and BP2 having the same width are arranged for each sub-pixel SPXn in the drawings, the present disclosure is not limited thereto. The number and shape of the bank patterns BP1 and BP2 can vary depending on the number or arrangement structure of the electrode RME.

[0104] The bank patterns BP1 and BP2 can be provided on the via layer VIA. For example, each of the bank patterns BP1 and BP2 can be provided on (e.g., directly on) the via layer VIA, and can have a structure in which at least a portion thereof protrudes from a top surface of the via layer VIA. The protruding portion of the bank patterns BP1 and BP2 can have an inclined or curved side surface, and light emitted from the light emitting element ED can be reflected by the electrode RME provided on the bank patterns BP1 and BP2, and emitted in an upward direction of the via layer VIA. Unlike the embodiment shown in the drawing, the bank patterns BP1 and BP2 can have a semicircular shape or a semi-elliptical shape having an outer surface curved in a cross-sectional view. The bank patterns BP1 and BP2 can include an organic insulating material such as polyimide (PI), but the present disclosure is not limited thereto.

[0105] The electrodes RME (RME1 and RME2) can have a shape extending in one direction, and can be provided for each sub-pixel SPXn. The electrodes RME1 and RME2 can extend across the emission area EMA and the sub-area SA of the sub-pixel SPXn in the first direction DR1, and can be spaced apart from each other in the second direction DR2. The electrodes RME can be electrically connected to the light emitting element ED to be described below. However, the present disclosure is not limited thereto, and in another embodiment, the electrodes RME can not be electrically connected to the light emitting element ED.

[0106] The display apparatus 10 can include a first electrode RME1 and a second electrode RME2 arranged in each sub-pixel SPXn. The first electrode RME1 can be located on the left with respect to the center of the emission area EMA, and the second electrode RME2 can be located on the right with respect to the center of the emission area EMA while being spaced apart from the first electrode RME1 in the second direction DR2. The first electrode RME1 can be provided on the first bank pattern BP1, and the second electrode RME2 can be provided on the second bank pattern BP2. The first electrode RME1 and the second electrode RME2 can be partially arranged in the respective emission area EMA and sub-area SA above the bank layer BNL. The first electrode RME1 and the second electrode RME2 of adjacent sub-pixels SPXn can be separated at a separation portion ROP located in the sub-area SA of one sub-pixel SPXn.

[0107] Although two electrodes RME having a shape extending in the first direction DR1 are shown for each sub-pixel SPXn in the drawing, the present disclosure is not limited thereto. A greater number of electrodes RME can be provided, or the electrodes RME can be partially curved and have different widths according to the location.

[0108] The first and second electrodes RME1 and RME2 can be disposed at least on the inclined surfaces of the bank patterns BP1 and BP2. In one embodiment, the width of the electrodes RME measured in the second direction DR2 can be smaller than the width of the bank patterns BP1 and BP2 measured in the second direction DR2, and the gap between the first and second electrodes RME1 and RME2 in the second direction DR2 can be smaller than the gap between the bank patterns BP1 and BP2. At least a portion of the first and second electrodes RME1 and RME2 can be disposed (e.g., directly disposed) on the via layer VIA such that the first and second electrodes RME1 and RME2 can be disposed on the same plane.

[0109] The light emitting element ED disposed between the bank patterns BP1 and BP2 can emit light toward the end portion, and the emitted light can be directed toward the electrodes RME disposed on the bank patterns BP1 and BP2. The electrodes RME can have a structure in which the portions disposed on the bank patterns BP1 and BP2 can reflect the light emitted from the light emitting element ED. The first and second electrodes RME1 and RME2 can be disposed to cover at least one side surface of the bank patterns BP1 and BP2, and can reflect the light emitted from the light emitting element ED.

[0110] In a plan view, the electrodes RME can be in direct contact with the third conductive layer through the electrode contact holes CTD and CTS between the emission area EMA and the sub-area SA at a portion where the bank layer BNL overlaps in the plan view. The first electrode contact hole CTD can be formed in an area where the bank layer BNL and the first electrode RME1 overlap in the plan view, and the second electrode contact hole CTS can be formed in an area where the bank layer BNL and the second electrode RME2 overlap in the plan view. The first electrode RME1 can be in contact with the first conductive pattern CDP1 through the first electrode contact hole CTD that passes through the via layer VIA and the first passivation layer PV1. The second electrode RME2 can be in contact with the second voltage line VL2 through the second electrode contact hole CTS that passes through the via layer VIA and the first passivation layer PV1. The first electrode RME1 can be electrically connected to the first transistor T1 through the first conductive pattern CDP1 such that the first power voltage can be applied to the first electrode RME1, and the second electrode RME2 can be electrically connected to the second voltage line VL2 such that the second power voltage can be applied to the second electrode RME2. However, the present disclosure is not limited thereto. In another embodiment, the electrodes RME1 and RME2 can not be electrically connected to the voltage lines VL1 and VL2 of the third conductive layer, respectively, and the connection electrode CNE to be described below can be connected to (e.g., directly connected to) the third conductive layer.

[0111] The electrode RME can include an electrically conductive material having high reflectivity. For example, the electrode RME can include a metal such as silver (Ag), copper (Cu), or aluminum (Al), or can include an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc. In another embodiment, the electrode RME can have a structure in which metal layers including titanium (Ti), molybdenum (Mo), and niobium (Nb) and alloys are stacked with each other. In an embodiment, the electrode RME can be formed as a double layer or a multi-layer formed by stacking at least one metal layer made of an alloy including aluminum (Al), titanium (Ti), molybdenum (Mo), and niobium (Nb).

[0112] The present disclosure is not limited thereto, and each electrode RME can further include a transparent conductive material. For example, each electrode RME can include a material such as ITO, IZO, and ITZO. In some embodiments, each of the electrodes RME can have a structure in which at least one transparent conductive material and at least one metal layer having high reflectivity are stacked with each other, or can be formed as one layer including at least one transparent conductive material and at least one metal layer having high reflectivity. For example, each electrode RME can have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO, ITO / Ag / ITZO / IZO, etc. The electrode RME can be electrically connected to the light emitting element ED, and can reflect some of light emitted from the light emitting element ED in the upward direction of the first substrate SUB.

[0113] The first insulating layer PAS1 can be disposed in the entire display area DPA, and can be disposed on the via layer VIA and the electrode RME. The first insulating layer PAS1 can protect the electrode RME and insulate the electrode RME from each other. For example, the first insulating layer PAS1 can be formed to cover the electrode RME before the bank layer BNL is formed, so that it is possible to prevent the electrode RME from being damaged in a process of forming the bank layer BNL. The first insulating layer PAS1 can prevent the light emitting element ED from being damaged due to direct contact with other members.

[0114] In an embodiment, the first insulating layer PAS1 can have a stepped portion so that the top surface is partially recessed between the electrodes RME spaced apart in the second direction DR2. The light emitting element ED can be disposed on the top surface of the first insulating layer PAS1 forming the stepped portion, and thus a space can be formed between the light emitting element ED and the first insulating layer PAS1.

[0115] The bank layer BNL can be disposed on the first insulating layer PAS1. The bank layer BNL can include portions extending in the first direction DR1 and the second direction DR2, and can surround the sub-pixel SPXn in a plan view. The bank layer BNL can surround and define the emission area EMA and the sub-area SA of each sub-pixel SPXn, and can surround the outermost portion of the display area DPA and define the display area DPA and the non-display area NDA. The bank layer BNL can be disposed throughout the display area DPA to form a lattice pattern, and the area exposed by the bank layer BNL in the display area DPA can be the emission area EMA and the sub-area SA.

[0116] Similar to the bank patterns BP1 and BP2, the bank layer BNL can have a height. In some embodiments, the top surface of the bank layer BNL can be higher than the top surface of the bank patterns BP1 and BP2, and the thickness of the bank layer BNL can be equal to or greater than the thickness of the bank patterns BP1 and BP2. The bank layer BNL can prevent ink from overflowing to adjacent sub-pixels SPXn in an inkjet printing process during a manufacturing process of the display apparatus 10. Similar to the bank patterns BP1 and BP2, the bank layer BNL can include an organic insulating material such as polyimide.

[0117] The light emitting elements ED can be disposed in the emission area EMA. The light emitting elements ED can be disposed between the bank patterns BP1 and BP2, and can be arranged to be spaced apart from each other in the first direction DR1. In one embodiment, the light emitting elements ED can have a shape extending in one direction, and the end portions of the light emitting elements ED can be disposed on different electrodes RME. The length of the light emitting elements ED can be greater than the gap between the electrodes RME spaced apart from each other in the second direction DR2. The direction of extension of the light emitting elements ED can be substantially perpendicular to the first direction DR1 in which the electrodes RME extend. However, the disclosure is not limited thereto, and the light emitting elements ED can extend in the second direction DR2 or in a direction inclined with respect to the second direction DR2.

[0118] The light emitting elements ED can be disposed on the first insulating layer PAS1. The light emitting elements ED can have a shape extending in one direction, and can be disposed such that the direction in which the light emitting elements ED extend is parallel to the top surface of the first substrate SUB. As will be described below, the light emitting elements ED can include a plurality of semiconductor layers arranged along the direction in which the light emitting elements ED extend, and the semiconductor layers can be sequentially arranged in a direction parallel to the top surface of the first substrate SUB. However, the disclosure is not limited thereto, and in the case where the light emitting elements ED have another structure, the semiconductor layers can be arranged in a direction perpendicular to the first substrate SUB.

[0119] The light emitting element ED disposed in each sub-pixel SPXn can emit light of different wavelength bands according to the material constituting the semiconductor layer. However, the present disclosure is not limited thereto, and the light emitting element ED arranged in each sub-pixel SPXn can include a semiconductor layer of the same material and emit light of the same color.

[0120] The light emitting element ED can be electrically connected to the conductive layer under the electrode RME and the via layer VIA while being in contact with the connection electrode CNE (CNE1 and CNE2), and can emit light of a wavelength band by receiving an electrical signal.

[0121] The second insulating layer PAS2 can be disposed on the light emitting element ED, the first insulating layer PAS1, and the bank layer BNL. The second insulating layer PAS2 can include a pattern portion disposed on the light emitting element ED while extending in the first direction DR1 between the bank patterns BP1 and BP2. The pattern portion can partially surround the outer surface of the light emitting element ED, and can not cover the entire side or end of the light emitting element ED. The pattern portion can form a linear pattern or an island-shaped pattern in each sub-pixel SPXn in a plan view. The pattern portion of the second insulating layer PAS2 can protect and fix the light emitting element ED during a manufacturing process of the display device 10. In addition, the second insulating layer PAS2 can fill a space between the light emitting element ED and the first insulating layer PAS1. In addition, a portion of the second insulating layer PAS2 can be disposed on the bank layer BNL and in the sub-area SA.

[0122] The connection electrode CNE (CNE1 and CNE2) can be disposed on the electrode RME and the bank patterns BP1 and BP2. The connection electrode CNE can have a shape extending in a direction, and can be disposed to be spaced apart from each other. Each of the connection electrodes CNE can be in contact with the light emitting element ED, and can be electrically connected to the third conductive layer.

[0123] The connection electrode CNE can include a first connection electrode CNE1 and a second connection electrode CNE2 provided in each sub-pixel SPXn. The first connection electrode CNE1 can have a shape extending in the first direction DR1, and can be provided on the first electrode RME1 or the first bank pattern BP1. The first connection electrode CNE1 can partially overlap the first electrode RME1 in a plan view, and can be disposed across the emission region EMA and the sub-region SA over the bank layer BNL. The second connection electrode CNE2 can have a shape extending in the first direction DR1, and can be provided on the second electrode RME2 or the second bank pattern BP2. The second connection electrode CNE2 can partially overlap the second electrode RME2 in a plan view, and can be disposed across the emission region EMA and the sub-region SA over the bank layer BNL. Each of the first connection electrode CNE1 and the second connection electrode CNE2 can be in contact with the light emitting element ED, and can be electrically connected to the electrode RME or to the conductive layer provided under the first connection electrode CNE1 and the second connection electrode CNE2.

[0124] For example, the first connection electrode CNE1 and the second connection electrode CNE2 can be provided on side surfaces of the second insulating layer PAS2, and can be in contact with the light emitting element ED. The first connection electrode CNE1 can partially overlap the first electrode RME1 in a plan view, and can be in contact with an end portion of the light emitting element ED. The second connection electrode CNE2 can partially overlap the second electrode RME2 in a plan view, and can be in contact with another end portion of the light emitting element ED. The connection electrode CNE can be disposed across the emission region EMA and the sub-region SA. The connection electrode CNE can be in contact with the light emitting element ED at a portion disposed in the emission region EMA, and can be electrically connected to the third conductive layer at a portion disposed in the sub-region SA.

[0125] According to one embodiment, in the display device 10, the connection electrode CNE can be in contact with the electrode RME through the contact portions CT1 and CT2 provided in the sub-area SA. The first connection electrode CNE1 can be in contact with the first electrode RME1 through the first contact portion CT1 passing through the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 in the sub-area SA. The second connection electrode CNE2 can be in contact with the second electrode RME2 through the second contact portion CT2 passing through the first insulating layer PAS1 and the second insulating layer PAS2 in the sub-area SA. Each of the connection electrodes CNE can be electrically connected to each of the electrodes RME through the third conductive layer. The first connection electrode CNE1 can be electrically connected to the first transistor T1 so that the first power voltage can be applied to the first connection electrode CNE1, and the second connection electrode CNE2 can be electrically connected to the second voltage line VL2 so that the second power voltage can be applied to the second connection electrode CNE2. Each of the connection electrodes CNE can be in contact with the light emitting element ED in the emission area EMA to transmit the power voltage to the light emitting element ED.

[0126] However, the present disclosure is not limited thereto. In some embodiments, the connection electrode CNE can be in direct contact with the third conductive layer, and can be electrically connected to the third conductive layer through a pattern other than the electrode RME.

[0127] The connection electrode CNE can include a conductive material. For example, the connection electrode CNE can include ITO, IZO, ITZO, aluminum (Al), or the like. For example, the connection electrode CNE can include a transparent conductive material, and light emitted from the light emitting element ED can pass through the connection electrode CNE to be emitted.

[0128] The third insulating layer PAS3 can be provided on the second connection electrode CNE2 and the second insulating layer PAS2. The third insulating layer PAS3 can be provided on the entire second insulating layer PAS2 to cover the second connection electrode CNE2, and the first connection electrode CNE1 can be provided on the third insulating layer PAS3. The third insulating layer PAS3 can be provided on the entire via layer VIA except for an area in which the second connection electrode CNE2 is provided. The third insulating layer PAS3 can insulate the first connection electrode CNE1 and the second connection electrode CNE2 to prevent direct contact between the first connection electrode CNE1 and the second connection electrode CNE2.

[0129] Although not shown in the drawings, another insulating layer can be further provided on the third insulating layer PAS3 and the first connection electrode CNE1. The insulating layer can be used to protect the members provided on the first substrate SUB from the external environment.

[0130] Each of the first, second, and third insulating layers PAS1, PAS2, and PAS3 described above can include an inorganic insulating material or an organic insulating material. For example, each of the first, second, and third insulating layers PAS1, PAS2, and PAS3 can include an inorganic insulating material, or the first and third insulating layers PAS1 and PAS3 can include an inorganic insulating material and the second insulating layer PAS2 can include an organic insulating material. Each or at least one of the first, second, and third insulating layers PAS1, PAS2, and PAS3 can have a structure in which a plurality of insulating layers are alternately stacked with each other or repeatedly stacked with each other. In an embodiment, each of the first, second, and third insulating layers PAS1, PAS2, and PAS3 can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ). The first, second, and third insulating layers PAS1, PAS2, and PAS3 can be made of the same material or different materials. In another embodiment, some of the first, second, and third insulating layers PAS1, PAS2, and PAS3 can be made of the same material, and some of the first, second, and third insulating layers PAS1, PAS2, and PAS3 can be made of different materials.

[0131] Figure 7 is a schematic perspective view of a light emitting element according to an embodiment.

[0132] Referring to Figure 7 , the light emitting element ED can be a light emitting diode. For example, the light emitting element ED can be an inorganic light emitting diode having a nano size or a micro size and made of an inorganic material. The light emitting element ED can be aligned between two electrodes having polarity in a case where an electric field is formed in a direction between the two electrodes facing each other.

[0133] The light emitting element ED according to an embodiment can have a shape elongated in one direction. The light emitting element ED can have a shape of a cylinder, a rod, a wire, a tube, or the like. However, the shape of the light emitting element ED is not limited thereto, and in another embodiment, the light emitting element ED can have a polygonal prismatic shape such as a cube, a cuboid, and a hexagonal prism, or can have various shapes such as a shape elongated in one direction and having a partially inclined outer surface.

[0134] The light emitting element ED can include a semiconductor layer doped with a conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer can emit light of a wavelength band by receiving an electrical signal applied from an external power source. The light emitting element ED can include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.

[0135] The first semiconductor layer 31 can be an n-type semiconductor. The first semiconductor layer 31 can include a semiconductor material having a chemical formula Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer 31 can include one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped into the first semiconductor layer 31 can be Si, Ge, Se, Sn, etc.

[0136] The second semiconductor layer 32 can be disposed on the first semiconductor layer 31, and the light emitting layer 36 is between the second semiconductor layer 32 and the first semiconductor layer 31. The second semiconductor layer 32 can be a p-type semiconductor, and the second semiconductor layer 32 can include a semiconductor material having a chemical formula Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer 32 can include one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped into the second semiconductor layer 32 can be Mg, Zn, Ca, Ba, etc.

[0137] Although the first semiconductor layer 31 and the second semiconductor layer 32 are illustrated as being configured as one layer in the drawings, the present disclosure is not limited thereto. The first semiconductor layer 31 and the second semiconductor layer 32 can further include a greater number of layers such as a cap layer or a tensile-strained barrier reduction (TSBR) layer, depending on the material of the light emitting layer 36. For example, the light emitting element ED can further include another semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36 or between the second semiconductor layer 32 and the light emitting layer 36. The semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36 can include one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN, and a superlattice doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer 32 and the light emitting layer 36 can include one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant.

[0138] The light emitting layer 36 can be disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 can include a material having a single quantum well structure or a multi quantum well structure. In the case where the light emitting layer 36 includes a material having a multi quantum well structure, a plurality of quantum layers and well layers can be alternately stacked with each other. The light emitting layer 36 can emit light by recombination of electron-hole pairs according to an electrical signal applied by the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 can include a material such as AlGaN, AlGaInN, or InGaN. For example, in the case where the light emitting layer 36 has a multi quantum well structure in which quantum layers and well layers are alternately stacked with each other, the quantum layers can include a material such as AlGaN or AlGaInN, and the well layers can include a material such as GaN or AlInN.

[0139] The light emitting layer 36 can have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked with each other, and can include Group III to Group V semiconductor materials according to a wavelength band of light emitted. The light emitted by the light emitting layer 36 is not limited to light of a blue wavelength band, and in another embodiment, the light emitting layer 36 can emit light of a red wavelength band or a green wavelength band.

[0140] The electrode layer 37 can be an ohmic connection electrode. However, the present disclosure is not limited thereto, and the electrode layer 37 can be a Schottky connection electrode. The light emitting element ED can include at least one electrode layer 37. The light emitting element ED can include one or more electrode layers 37, but the present disclosure is not limited thereto, and in another embodiment, the electrode layer 37 can be omitted.

[0141] In the display device 10, in the case where the light emitting element ED is electrically connected to an electrode or a connection electrode, the electrode layer 37 can reduce the electrical resistance between the light emitting element ED and the electrode or the connection electrode. The electrode layer 37 can include a conductive metal. For example, the electrode layer 37 can include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0142] The insulating film 38 can be disposed to surround the outer surfaces of the above-described semiconductor layers and electrode layers. For example, the insulating film 38 can surround at least the outer surface of the light emitting layer 36, and can be formed to expose the end portion of the light emitting element ED in the longitudinal direction. Further, in a cross-sectional view, the insulating film 38 can have a rounded top surface in a region adjacent to at least one end portion of the light emitting element ED.

[0143] The insulating film 38 can include, for example, silicon oxide (SiO x ), silicon nitride (SiN x), silicon oxynitride (SiO x N y ), aluminum nitride (AIN x ), aluminum oxide (AIO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x ) having insulating properties. The insulating film 38 is shown to be formed as a single layer in the drawings, but the present disclosure is not limited thereto. In some embodiments, the insulating film 38 can be formed as a multilayer structure having a plurality of layers stacked with each other.

[0144] The insulating film 38 can perform a function of protecting the semiconductor layer and the electrode layer of the light emitting element ED. The insulating film 38 can prevent a short circuit that can occur at the light emitting layer 36 in a case where the electrode to which an electrical signal is transmitted is in direct contact with the light emitting element ED. The insulating film 38 can prevent a decrease in light emitting efficiency of the light emitting element ED.

[0145] Further, the insulating film 38 can have a surface-treated outer surface. The light emitting element ED can be aligned by ejecting an ink in which the light emitting element ED is dispersed on an electrode. The surface of the insulating film 38 can be treated to have hydrophobicity or hydrophilicity to maintain the light emitting element ED in a dispersed state without being aggregated with other adjacent light emitting elements ED in the ink.

[0146] According to one embodiment, the display apparatus 10 can further include a color control layer (‘CCR’ in Figure 8 ) and a color filter layer (‘CFL’ in Figure 8 ) disposed on the light emitting element ED. Light emitted from the light emitting element ED can be emitted through the color control layer CCR and the color filter layer CFL. Even though the same type of light emitting element ED is disposed in the corresponding sub-pixel SPXn, the color of the emitted light can be different for each sub-pixel SPXn.

[0147] Figure 8 is a schematic cross-sectional view of a display apparatus according to one embodiment.

[0148] Referring to Figure 8 , the display apparatus 10 can include the light emitting element ED disposed on the substrate SUB, and the color control layer CCR and the color filter layer CFL can be disposed on the light emitting element ED. The display apparatus 10 can further include a plurality of layers disposed between the color control layer CCR and the color filter layer CFL. Hereinafter, layers disposed on the light emitting element ED of the display apparatus 10 will be described.

[0149] ​​A fourth insulating layer PAS4 can be provided on the third insulating layer PAS3, the connection electrodes CNE1 and CNE2, and the bank layer BNL. The fourth insulating layer PAS4 can protect the layers provided on the substrate SUB. However, the present disclosure is not limited thereto, and in another embodiment, the fourth insulating layer PAS4 can be omitted.

[0150] An upper bank layer UBN, a color control layer CCR, color patterns CP1, CP2, and CP3, and a color filter layer CFL can be provided on the fourth insulating layer PAS4. A plurality of capping layers CPL1 and CPL2, a low-refraction layer LRL, and a planarization layer PNL can be provided between the color control layer CCR and the color filter layer CFL. An overcoat layer OC can be provided on the color filter layer CFL.

[0151] The display apparatus 10 can include light transmission areas TA1, TA2, and TA3 in which the color filter layer CFL is provided to emit light, and light blocking areas BA provided between the light transmission areas TA1, TA2, and TA3 in which light is not emitted. The light transmission areas TA1, TA2, and TA3 can be positioned to correspond to portions of the emission area EMA of each sub-pixel SPXn, and the light blocking areas BA can be areas other than the light transmission areas TA1, TA2, and TA3.

[0152] The upper bank layer UBN can be provided on the fourth insulating layer PAS4 and overlap the bank layer BNL in a plan view. The upper bank layer UBN can include portions extending in the first direction DR1 and the second direction DR2, and can be provided in a lattice pattern. In a plan view, the upper bank layer UBN can surround the emission area EMA or a portion in which the light emitting element ED is disposed. The upper bank layer UBN can be formed in an area in which the color control layer CCR is provided.

[0153] The color control layer CCR can be provided in an area surrounded by the upper bank layer UBN on the fourth insulating layer PAS4. The color control layer CCR can be provided in the light transmission areas TA1, TA2, and TA3 surrounded by the upper bank layer UBN to form an island-shaped pattern in the display area DPA. However, the present disclosure is not limited thereto, and each of the color control layers CCR can extend in one direction and can be provided across the sub-pixel SPXn to form a linear pattern.

[0154] In an embodiment in which the light emitting element ED of each sub-pixel SPXn emits blue light of a third color, the color control layer CCR can include a first wavelength conversion layer WCL1 disposed in the first sub-pixel SPX1 to correspond to the first light transmission area TA1, a second wavelength conversion layer WCL2 disposed in the second sub-pixel SPX2 to correspond to the second light transmission area TA2, and a light transmission layer TPL disposed in the third sub-pixel SPX3 to correspond to the third light transmission area TA3.

[0155] The first wavelength conversion layer WCL1 can include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion layer WCL2 can include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 can convert blue light of a third color incident from the light emitting element ED. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 can further include a scatterer SCP included in the respective base resins, and the scatterer SCP can improve wavelength conversion efficiency.

[0156] The light transmission layer TPL can include a third base resin BRS3 and a scatterer SCP included in the third base resin BRS3. The light transmission layer TPL can transmit blue light of a third color incident from the light emitting element ED while maintaining a wavelength. The scatterer SCP of the light transmission layer TPL can be used to control an emission path of light emitted through the light transmission layer TPL. The light transmission layer TPL can not include a wavelength conversion material.

[0157] The scatterer SCP can be a metal oxide particle or an organic particle. Examples of the metal oxide can include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), etc. Examples of a material of the organic particle can include an acrylic resin, a urethane resin, etc.

[0158] The first base resin BRS1, the second base resin BRS2, and the third base resin BRS3 can include a light-transmissive organic material. For example, the first base resin BRS1, the second base resin BRS2, and the third base resin BRS3 can include an epoxy resin, an acrylic resin, a Cardo resin, an imide resin, etc. The first base resin BRS1, the second base resin BRS2, and the third base resin BRS3 can be formed of the same material, but the present disclosure is not limited thereto.

[0159] The first wavelength conversion material WCP1 can convert the third color of blue light into the first color of red light, and the second wavelength conversion material WCP2 can convert the third color of blue light into the second color of green light. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 can be quantum dots, quantum rods, phosphors, or the like. Examples of the quantum dots can include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, and combinations thereof.

[0160] In some embodiments, the color control layer CCR can be formed through an inkjet printing process or a photoresist process. The color control layer CCR can be formed through a drying or exposure and development process after materials constituting the color control layer CCR are jetted into or coated on the area surrounded by the upper bank layer UBN. For example, in an embodiment in which the color control layer CCR is formed through an inkjet printing process, the top surface of each color control layer CCR can be formed to be curved such that the edge portion of each color control layer CCR adjacent to the upper bank layer UBN can be lower than the center portion of each color control layer CCR. However, the present disclosure is not limited thereto. In an embodiment in which the color control layer CCR is formed through a photoresist process, the top surface of each color control layer CCR can be formed to be flat such that the edge portion adjacent to the upper bank layer UBN can be parallel to the top surface of the upper bank layer UBN. In another embodiment, unlike the drawing, the center portion of the color control layer CCR can be formed to be lower than the edge portion thereof.

[0161] The light emitting element ED of each sub-pixel SPXn can emit the same third color of blue light, and the sub-pixels SPXn can emit different colors of light. For example, light emitted from the light emitting element ED disposed in the first sub-pixel SPX1 can be incident on the first wavelength conversion layer WCL1, light emitted from the light emitting element ED disposed in the second sub-pixel SPX2 can be incident on the second wavelength conversion layer WCL2, and light emitted from the light emitting element ED disposed in the third sub-pixel SPX3 can be incident on the light transmission layer TPL.

[0162] The light incident on the first wavelength conversion layer WCL1 can be converted into red light, the light incident on the second wavelength conversion layer WCL2 can be converted into green light, and the light incident on the light transmission layer TPL can be transmitted as the same blue light without wavelength conversion. Although each sub-pixel SPXn includes a light emitting element ED emitting the same color of light, different colors of light can be emitted according to the arrangement of the color control layer CCR disposed above the light emitting element ED.

[0163] A first capping layer CPL1 can be disposed on the color control layer CCR and the upper bank layer UBN. The first capping layer CPL1 can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color control layer CCR. The first capping layer CPL1 can contain an inorganic insulating material.

[0164] A low-refraction layer LRL can be disposed on the first capping layer CPL1. The low-refraction layer LRL can improve light emission efficiency and color purity of the display apparatus 10 as an optical layer for recycling light that has passed through the color control layer CCR. The low-refraction layer LRL can be made of an organic material having a low refractive index, and can compensate for a stepped portion formed by the color control layer CCR and the upper bank layer UBN.

[0165] A second capping layer CPL2 can be disposed on the low-refraction layer LRL, and can prevent impurities such as moisture, air, etc. from penetrating from the outside and damaging or contaminating the low-refraction layer LRL. The second capping layer CPL2 can include an inorganic insulating material similarly to the first capping layer CPL1.

[0166] A planarization layer PNL can be disposed on the second capping layer CPL2 across the entire display area DPA and the entire non-display area NDA. The planarization layer PNL can overlap the color control layer CCR in a plan view in the display area DPA, and can overlap a bank to be described below in a plan view in the non-display area NDA.

[0167] In addition to protecting the capping layers CPL1 and CPL2 and the low-refraction layer LRL, the planarization layer PNL can also protect members disposed on the substrate SUB, and can partially compensate for a stepped portion formed under the planarization layer PNL. For example, the planarization layer PNL can compensate for a stepped portion formed by the color control layer CCR, the upper bank layer UBN, and the bank layer BNL under the planarization layer PNL in the display area DPA. Accordingly, a color filter layer CFL disposed on the planarization layer PNL can be formed on a flat surface.

[0168] A color filter layer CFL can be disposed on the planarization layer PNL. The color filter layer CFL can be disposed in the light transmission areas TA1, TA2, and TA3, and a portion of the color filter layer CFL can be disposed in the light blocking area BA. The portion of the color filter layer CFL can overlap another portion of the color filter layer CFL or the color patterns CP1, CP2, and CP3 in the light blocking area BA. The portions of the color filter layer CFL that do not overlap each other can be the light transmission areas TA1, TA2, or TA3. The areas of the color filter layer CFL that overlap each other or are provided with the color patterns CP1, CP2, and CP3 can be the light blocking area BA in which light is blocked.

[0169] The color filter layer CFL can include a first color filter CFL1 disposed in the first sub-pixel SPX1, a second color filter CFL2 disposed in the second sub-pixel SPX2, and a third color filter CFL3 disposed in the third sub-pixel SPX3. Each of the color filters CFL1, CFL2, and CFL3 can be formed in a linear pattern disposed in the light transmission areas TA1, TA2, and TA3 or the emission area EMA. However, the disclosure is not limited thereto. The color filters CFL1, CFL2, and CFL3 can be disposed to correspond to the light transmission areas TA1, TA2, and TA3, respectively, and can form an island-like pattern.

[0170] The color filter layer CFL can contain a colorant such as a dye or a pigment that absorbs light of a wavelength band other than a specific wavelength band. Each of the color filters CFL1, CFL2, and CFL3 can be provided for each sub-pixel SPXn, and can transmit only a portion of light incident on each of the color filters CFL1, CFL2, and CFL3 in the corresponding sub-pixel SPXn. In each sub-pixel SPXn of the display apparatus 10, only light transmitted through each of the color filters CFL1, CFL2, and CFL3 can be selectively displayed. In an embodiment, the first color filter CFL1 can be a red color filter layer, the second color filter CFL2 can be a green color filter layer, and the third color filter CFL3 can be a blue color filter layer. Light emitted from the light emitting element ED can be emitted through the color control layer CCR and the color filter layer CFL.

[0171] The color patterns CP1, CP2, and CP3 can be disposed on the planarization layer PNL or the color filter layer CFL. The color patterns CP1, CP2, and CP3 and the color filter layer CFL can be made of the same material, and the color patterns CP1, CP2, and CP3 can be disposed in the light blocking areas BA. In the light blocking areas BA, the color patterns CP1, CP2, CP3 and the different color filters CFL1, CFL2, and CFL3 can be stacked with each other, and can block light in the stacked areas.

[0172] The first color pattern CP1 and the first color filter CFL1 can be made of the same material, and the first color pattern CP1 can be disposed in the light blocking area BA. The first color pattern CP1 can be disposed (e.g., directly disposed) on the planarization layer PNL in the light blocking area BA, and can not be disposed in the light blocking area BA adjacent to the first light transmission area TA1 of the first sub-pixel SPX1. The first color pattern CP1 can be disposed in the light blocking area BA between the second sub-pixel SPX2 and the third sub-pixel SPX3. The first color filter CFL1 can be disposed in the light blocking area BA adjacent to the first sub-pixel SPX1.

[0173] The second color pattern CP2 and the second color filter CFL2 can be made of the same material, and the second color pattern CP2 can be disposed in the light-blocking area BA. The second color pattern CP2 can be disposed on (e.g., directly on) the planarization layer PNL in the light-blocking area BA, and can not be disposed in the light-blocking area BA adjacent to the second light-transmissive area TA2 of the second sub-pixel SPX2. The second color pattern CP2 can be disposed in the light-blocking area BA between the first sub-pixel SPX1 and the third sub-pixel SPX3, or on the boundary between the non-display area NDA and the outermost sub-pixel SPXn of the display area DPA. The second color filter CFL2 can be disposed in the light-blocking area BA adjacent to the second sub-pixel SPX2.

[0174] Similarly, the third color pattern CP3 and the third color filter CFL3 can be made of the same material, and the third color pattern CP3 can be disposed in the light-blocking area BA. The third color pattern CP3 can be disposed on (e.g., directly on) the planarization layer PNL in the light-blocking area BA, and can not be disposed in the light-blocking area BA adjacent to the third light-transmissive area TA3 of the third sub-pixel SPX3. The third color pattern CP3 can be disposed in the light-blocking area BA between the first sub-pixel SPX1 and the second sub-pixel SPX2. The third color filter CFL3 can be disposed in the light-blocking area BA adjacent to the third sub-pixel SPX3.

[0175] In the display device 10, the area in which the bank layer BNL and the upper bank layer UBN overlap each other can be the light-blocking area BA. In the light-blocking area BA, each of the first color pattern CP1, the second color pattern CP2, and the third color pattern CP3 can be disposed to overlap at least one of the color filters CFL1, CFL2, and CFL3 containing a material of a different color. For example, the first color pattern CP1 can overlap the second color filter CFL2 and the third color filter CFL3 in a plan view, the second color pattern CP2 can overlap the first color filter CFL1 and the third color filter CFL3 in a plan view, and the third color pattern CP3 can overlap the first color filter CFL1 and the second color filter CFL2 in a plan view. In the light-blocking area BA, the color patterns CP1, CP2, and CP3 containing a material of a different color and the color filters CFL1, CFL2, and CFL3 can overlap each other, thereby blocking light.

[0176] The color patterns CP1, CP2, and CP3, along with the color filters CFL1, CFL2, and CFL3, can form a stacked structure and include materials containing different colors, thereby preventing color mixing between adjacent areas. Since the color patterns CP1, CP2, and CP3, as well as the color filters CFL1, CFL2, and CFL3, comprise the same material, external light or reflected light that has passed through the light-blocking area BA can have a specific color wavelength band. Color sensitivity perceived by the user's eye can depend on the color of the light. For example, light in the blue wavelength band may be perceived less sensitively by the user than light in the green wavelength band and light in the red wavelength band. In the display device 10, since the color patterns CP1, CP2, and CP3 are disposed in the light-blocking area BA, light transmission can be blocked, and the user can perceive reflected light relatively insensitively. Furthermore, a portion of the light from outside the display device 10 can be absorbed, reducing reflected light caused by external light.

[0177] The outer coating OC can be applied to the color filter layer CFL and the color patterns CP1, CP2, and CP3. The outer coating OC can be applied throughout the display area DPA and can also be partially applied to the non-display area NDA. The outer coating OC provides external protection for components containing organic insulating material arranged within the display area DPA.

[0178] According to one embodiment, the display device 10 may include a color control layer CCR and a color filter layer CFL disposed above the light-emitting element ED. Therefore, even if the same type of light-emitting element ED is provided for each sub-pixel SPXn, the display device 10 can display different colors of light.

[0179] For example, the light-emitting element (ED) disposed in the first sub-pixel SPX1 can emit blue light of a third color, and this light can be incident on the first wavelength conversion layer WCL1 when passing through the fourth insulating layer PAS4. The first base resin BRS1 of the first wavelength conversion layer WCL1 can be made of a transparent material, and a portion of the light can pass through the first base resin BRS1 and be incident on the first capping layer CPL1 disposed on the first base resin BRS1. However, at least a portion of the light can be incident on the scatterer SCP and the first wavelength conversion material WCP1 disposed in the first base resin BRS1. The light can be scattered and subjected to wavelength conversion, and can be incident on the first capping layer CPL1 as red light. The light incident on the first capping layer CPL1 can be incident on the first color filter CFL1 when passing through the low refractive layer LRL, the second capping layer CPL2, and the planarization layer PNL, and the transmission of light other than red light can be blocked by the first color filter CFL1. Therefore, the first sub-pixel SPX1 can emit red light.

[0180] Similarly, light emitted from the light emitting element ED provided in the second sub-pixel SPX2 can be emitted as green light when passing through the fourth insulating layer PAS4, the second wavelength conversion layer WCL2, the first cap layer CPL1, the low-refraction layer LRL, the second cap layer CPL2, the planarization layer PNL, and the second color filter CFL2.

[0181] The light emitting element ED provided in the third sub-pixel SPX3 can emit blue light of a third color, and the blue light can be incident on the light transmission layer TPL when passing through the fourth insulating layer PAS4. The third base resin BRS3 of the light transmission layer TPL can be made of a transparent material, and a portion of the light can be transmitted through the third base resin BRS3 and be incident on the first cap layer CPL1 provided on the third base resin BRS3. The light incident on the first cap layer CPL1 can be incident on the third color filter CFL3 when passing through the low-refraction layer LRL, the second cap layer CPL2, and the planarization layer PNL, and the transmission of light other than the blue light can be blocked by the third color filter CFL3. Accordingly, the third sub-pixel SPX3 can emit blue light.

[0182] The display apparatus 10 can align the light emitting elements ED by applying an alignment signal to the first and second electrodes RME1 and RME2, and separate the first and second electrodes RME1 and RME2 on the basis of the sub-pixels SPXn. Since the sub-pixels SPXn emitting light of the same color are provided in the first direction DR1, and the first and second electrodes RME1 and RME2 extend in the first direction DR1, and at least the sub-pixels SPXn emitting light of three colors need to be provided, a large number of the first and second electrodes RME1 and RME2 are required. Hereinafter, a display apparatus 10 capable of reducing the number of the first and second electrodes RME1 and RME2 by arranging sub-pixels SPXn emitting light of two or more colors with the first and second electrodes RME1 and RME2 according to an embodiment will be described. In the following description, the reference numeral of the first electrode RME1 will be denoted as "FRM", and the reference numeral of the second electrode RME2 will be denoted as "SRM".

[0183] Figure 9 FIG. 1 is a plan view illustrating a plurality of pixels of a display apparatus according to one embodiment. Figure 9 A planar arrangement of the electrodes FRM and SRM, the bank layer BNL, the light emitting element ED, and the emission areas EMA1, EMA2, and EMA3 provided in the pixel PX of the display apparatus 10 is illustrated.

[0184] Reference Figure 9Each of the pixels PX of the display apparatus 10 can include a plurality of sub-pixels SPXn. For example, the pixel PX can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. For example, the first color can be red, the second color can be blue, and the third color can be green. However, the present disclosure is not limited thereto.

[0185] Each of the sub-pixels SPX1, SPX2, and SPX3 in the display apparatus 10 can include an emission area EMA and a non-emission area. The emission area EMA can be an area in which a light emitting element ED is disposed to emit light of a wavelength band. The non-emission area can be an area in which the light emitting element ED is not disposed and an area that does not emit light due to the light emitted from the light emitting element ED not reaching the area.

[0186] The bank layer BNL can surround the emission areas EMA in a plan view, thereby separating and defining the emission areas EMA of the respective sub-pixels SPX1, SPX2, and SPX3. For example, the bank layer BNL can define a first emission area EMA1, a second emission area EMA2, and a third emission area EMA3. The first emission area EMA1 and the second emission area EMA2 can be disposed adjacent to each other in the first direction DR1. The first emission area EMA1 and the second emission area EMA2 can be alternately disposed in the first direction DR1. The third emission area EMA3 can be disposed to be spaced apart from the first emission area EMA1 and the second emission area EMA2 in the second direction DR2. The third emission area EMA3 can be repeatedly arranged in the first direction DR1.

[0187] The first electrode FRM and the second electrode SRM can have a shape extending in a direction, and can be provided for the respective sub-pixels SPXn. The first electrode FRM and the second electrode SRM can be disposed in the emission area EMA of the respective sub-pixel SPXn while extending in the first direction DR1, and can be disposed to be spaced apart from each other in the second direction DR2.

[0188] Each sub-pixel SPXn can include the first electrode FRM and the second electrode SRM disposed in the respective emission area EMA. The first electrode FRM can be disposed on the left side with respect to the center of the emission area EMA, and the second electrode SRM can be spaced apart from the first electrode FRM in the second direction DR2 and disposed on the right side with respect to the center of the emission area EMA. The first electrode FRM and the second electrode SRM disposed in the emission areas EMA of different sub-pixels SPXn can be spaced apart from each other between the emission areas EMA.

[0189] The first sub-pixel SPX1 can include a first emission area EMA1 and a first electrode FRM1 and a second electrode SRM1 disposed in the first emission area EMA1. The second sub-pixel SPX2 can include a second emission area EMA2 and a first electrode FRM2 and a second electrode SRM2 disposed in the second emission area EMA2. The third sub-pixel SPX3 can include a third emission area EMA3 and a first electrode FRM3 and a second electrode SRM3 disposed in the third emission area EMA3.

[0190] The first electrode FRM1 and the second electrode SRM1 of the first emission area EMA1 can extend in the first direction DR1. The first electrode FRM2 and the second electrode SRM2 of the second emission area EMA2 can extend in the first direction DR1. The first electrode FRM3 and the second electrode SRM3 of the third emission area EMA3 can extend in the first direction DR1. In one embodiment, the extension direction of the first electrode FRM1 of the first emission area EMA1 can be aligned with the extension direction of the first electrode FRM2 of the second emission area EMA2. The extension direction of the second electrode SRM1 of the first emission area EMA1 can be aligned with the extension direction of the second electrode SRM2 of the second emission area EMA2. The first electrode FRM3 of the third emission area EMA3 can be spaced apart from the first electrode FRM1 of the first emission area EMA1 in the second direction DR2. The second electrode SRM3 of the third emission area EMA3 can be spaced apart from the second electrode SRM1 of the first emission area EMA1 in the second direction DR2.

[0191] The first emission area EMA1 and the second emission area EMA2 adjacent to each other in the first direction DR1 can emit different colors of light. For example, the first emission area EMA1 can emit red light, and the second emission area EMA2 can emit blue light. In one embodiment, the light emitting elements ED provided in the first emission area EMA1 and the second emission area EMA2 can be aligned by an alignment signal of the first electrode FRM and the second electrode SRM. As described above, the first electrode FRM and the second electrode SRM can be separated after the alignment process of the light emitting elements ED. Accordingly, in the alignment process of the light emitting elements ED, the light emitting elements ED of the first emission area EMA1 and the light emitting elements ED of the second emission area EMA2 can be aligned by the same alignment signal. In the case where emission areas EMA emitting the same color of light are provided in the first direction DR1, three pairs of first electrodes FRM and second electrodes SRM spaced apart in the second direction DR2 can be required. However, according to the embodiment, since the first emission area EMA1 and the second emission area EMA2 adjacent to each other in the first direction DR1 emit different colors of light, one pair of first electrodes FRM and second electrodes SRM can be omitted. Accordingly, the number of first electrodes FRM and second electrodes SRM can be reduced to form more emission areas EMA, thereby implementing a high-resolution display apparatus 10.

[0192] In a plan view, the sizes of the emission areas EMA can be the same or different. For example, the size of the first emission area EMA1 and the size of the second emission area EMA2 can be the same, and the size of the third emission area EMA3 can be greater than the size of the first emission area EMA1 or the size of the second emission area EMA2. However, the disclosure is not limited thereto, and the size of the emission area EMA can be adjusted according to the color of light emitted by each emission area EMA.

[0193] According to the size of each emission area EMA, the extension length of the first electrode FRM can be different from the extension length of the second electrode SRM. For example, the length of the first electrode FRM1 of the first emission area EMA1 and the length of the first electrode FRM2 of the second emission area EMA2 can be the same in the first direction DR1. In the first direction DR1, the length of the first electrode FRM3 of the third emission area EMA3 can be greater than the length of the first electrode FRM1 of the first emission area EMA1.

[0194] The light emitting elements ED provided in each emission area EMA can be disposed between the first electrode FRM and the second electrode SRM. An end portion of the light emitting element ED can overlap the first electrode FRM in a plan view, and the other end portion of the light emitting element ED can overlap the second electrode SRM in a plan view.

[0195] Figure 10is a plan view showing a plurality of pixels of a display device according to another embodiment.

[0196] Reference Figure 10 The present embodiment is different from the above-described Figure 9 embodiment in that each emission area EMA of each sub-pixel SPXn of the display device 10 further includes a third electrode TRM. In the following description, redundant descriptions of the above-described embodiment will be omitted while focusing on the differences.

[0197] Each sub-pixel SPXn can further include a third electrode TRM. The third electrode TRM can have a shape extending in a direction, and can be provided for each sub-pixel SPXn. The third electrode TRM can be provided in the emission area EMA of each sub-pixel SPXn while extending in the first direction DR1, and can be provided between the first electrode FRM and the second electrode SRM.

[0198] The first sub-pixel SPX1 can include a first emission area EMA1 and a first electrode FRM1, a second electrode SRM1, and a third electrode TRM1 provided in the first emission area EMA1. The second sub-pixel SPX2 can include a second emission area EMA2 and a first electrode FRM2, a second electrode SRM2, and a third electrode TRM2 provided in the second emission area EMA2. The third sub-pixel SPX3 can include a third emission area EMA3 and a first electrode FRM3, a second electrode SRM3, and a third electrode TRM3 provided in the third emission area EMA3.

[0199] The third electrode TRM1 of the first emission area EMA1, the third electrode TRM2 of the second emission area EMA2, and the third electrode TRM3 of the third emission area EMA3 can extend in the first direction DR1, respectively. In one embodiment, the extension direction of the third electrode TRM1 of the first emission area EMA1 can be aligned with the extension direction of the third electrode TRM2 of the second emission area EMA2. The third electrode TRM3 of the third emission area EMA3 can be spaced apart from the third electrode TRM1 of the first emission area EMA1 in the second direction DR2.

[0200] The light emitting element ED provided in each emission area EMA can include a first light emitting element ED1 and a second light emitting element ED2. The first light emitting element ED1 can be provided between the first electrode FRM and the third electrode TRM, and the second light emitting element ED2 can be provided between the second electrode SRM and the third electrode TRM. An end portion of the first light emitting element ED1 can overlap the first electrode FRM in a plan view, and another end portion of the first light emitting element ED1 can overlap the third electrode TRM in the plan view. An end portion of the second light emitting element ED2 can overlap the third electrode TRM in the plan view, and another end portion of the second light emitting element ED2 can overlap the second electrode SRM in the plan view.

[0201] In one embodiment, the third electrode TRM of the corresponding sub-pixel SPXn can extend in the first direction DR1, and the first emission area EMA1 and the second emission area EMA2 adjacent to each other in the first direction DR1 can emit light of different colors. Accordingly, the number of each of the electrodes FRM, SRM, and TRM can be reduced to form more emission areas EMA, thereby realizing a high-resolution display apparatus 10.

[0202] Figure 11 is a plan view illustrating a plurality of pixels of a display apparatus according to still another embodiment.

[0203] Reference Figure 11 This embodiment is different from the embodiment of Figure 9 in that the pixel PX of the display apparatus 10 further includes a fourth sub-pixel SPX4.

[0204] The pixel PX of the display apparatus 10 can further include a fourth sub-pixel SPX4. For example, the pixel PX can include a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4. The fourth sub-pixel SPX4 can be disposed to be spaced apart from the second sub-pixel SPX2 in the second direction DR2 and spaced apart from the third sub-pixel SPX3 in the first direction DR1. The first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 and the fourth sub-pixel SPX4 can emit light of a third color. For example, the first color can be red, the second color can be blue, and the third color can be green. However, the present disclosure is not limited thereto.

[0205] The fourth sub-pixel SPX4 can include a fourth emission area EMA4, a first electrode FRM4, a second electrode SRM4, and a light emitting element ED. The fourth emission area EMA4 can be disposed to be spaced apart from the third emission area EMA3 in the first direction DR1 and spaced apart from the second emission area EMA2 in the second direction DR2.

[0206] The first electrode FRM4 and the second electrode SRM4 of the fourth emission area EMA4 can extend in the first direction DR1 and can be disposed to be spaced apart from each other in the second direction DR2. In one embodiment, the extension direction of the first electrode FRM3 of the third emission area EMA3 can be aligned with the extension direction of the first electrode FRM4 of the fourth emission area EMA4. The extension direction of the second electrode SRM3 of the third emission area EMA3 can be aligned with the extension direction of the second electrode SRM4 of the fourth emission area EMA4. The first electrode FRM4 of the fourth emission area EMA4 can be spaced apart from the first electrode FRM2 of the second emission area EMA2 in the second direction DR2. The second electrode SRM4 of the fourth emission area EMA4 can be spaced apart from the second electrode SRM2 of the second emission area EMA2 in the second direction DR2.

[0207] The third emission area EMA3 and the fourth emission area EMA4 adjacent to each other in the first direction DR1 can emit the same color of light. For example, the third emission area EMA3 and the fourth emission area EMA4 can emit green light. In one embodiment, the light emitting elements ED disposed in the third emission area EMA3 and the fourth emission area EMA4 can be aligned by the same alignment signal of the first electrode FRM and the second electrode SRM.

[0208] In a plan view, the sizes of the emission areas EMA can be the same. For example, the size of the first emission area EMA1, the size of the second emission area EMA2, the size of the third emission area EMA3, and the size of the fourth emission area EMA4 can be the same. However, the disclosure is not limited thereto, and the sizes of the emission areas EMA can be adjusted according to the color of light emitted by each emission area EMA.

[0209] According to the size of each emission area EMA, the extension length of the first electrode FRM and the extension length of the second electrode SRM can be the same. For example, the length of the first electrode FRM1 of the first emission area EMA1, the length of the first electrode FRM2 of the second emission area EMA2, the length of the first electrode FRM3 of the third emission area EMA3, and the length of the first electrode FRM4 of the fourth emission area EMA4 can be the same in the first direction DR1.

[0210] In an embodiment, the first emission area EMA1 and the second emission area EMA2 adjacent to each other in the first direction DR1 can emit different colors of light, and the third emission area EMA3 and the fourth emission area EMA4 adjacent to each other in the first direction DR1 can emit the same color of light. Accordingly, the number of each of the electrodes FRM and SRM can be reduced to form more emission areas EMA, thereby implementing a high-resolution display apparatus 10.

[0211] Figure 12 is a plan view illustrating a plurality of pixels of a display apparatus according to still another embodiment.

[0212] Referring to Figure 12 This embodiment is different from the above-described Figure 11 embodiment of the display apparatus 10 in that each emission area EMA of each sub-pixel SPXn further includes a third electrode TRM.

[0213] Each sub-pixel SPXn can further include a third electrode TRM. The third electrode TRM can have a shape extending in a direction, and can be provided for each sub-pixel SPXn. The third electrode TRM can be provided in the emission area EMA of each sub-pixel SPXn while extending in the first direction DR1, and can be provided between the first electrode FRM and the second electrode SRM.

[0214] The first sub-pixel SPX1 can include a first emission area EMA1 and a first electrode FRM1, a second electrode SRM1, and a third electrode TRM1 provided in the first emission area EMA1. The second sub-pixel SPX2 can include a second emission area EMA2 and a first electrode FRM2, a second electrode SRM2, and a third electrode TRM2 provided in the second emission area EMA2. The third sub-pixel SPX3 can include a third emission area EMA3 and a first electrode FRM3, a second electrode SRM3, and a third electrode TRM3 provided in the third emission area EMA3. The fourth sub-pixel SPX4 can include a fourth emission area EMA4 and a first electrode FRM4, a second electrode SRM4, and a third electrode TRM4 provided in the fourth emission area EMA4.

[0215] The third electrode TRM1 of the first emission area EMA1, the third electrode TRM2 of the second emission area EMA2, the third electrode TRM3 of the third emission area EMA3, and the third electrode TRM4 of the fourth emission area EMA4 can each extend in the first direction DR1. In one embodiment, the direction of extension of the third electrode TRM3 of the third emission area EMA3 can be aligned with the direction of extension of the third electrode TRM4 of the fourth emission area EMA4. The third electrode TRM3 of the third emission area EMA3 can be spaced apart from the third electrode TRM1 of the first emission area EMA1 in the second direction DR2. The third electrode TRM4 of the fourth emission area EMA4 can be spaced apart from the third electrode TRM2 of the second emission area EMA2 in the second direction DR2.

[0216] The light emitting element ED provided in each emission area EMA can include a first light emitting element ED1 and a second light emitting element ED2. The first light emitting element ED1 can be provided between the first electrode FRM and the third electrode TRM, and the second light emitting element ED2 can be provided between the second electrode SRM and the third electrode TRM. An end portion of the first light emitting element ED1 can overlap the first electrode FRM in a plan view, and another end portion of the first light emitting element ED1 can overlap the third electrode TRM in a plan view. An end portion of the second light emitting element ED2 can overlap the third electrode TRM in a plan view, and another end portion of the second light emitting element ED2 can overlap the second electrode SRM in a plan view.

[0217] Figure 13 and Figure 14 is a plan view showing a plurality of pixels of a display apparatus according to still another embodiment.

[0218] Referring to Figure 13 and Figure 14 This embodiment differs from the above-described embodiments of Figure 11 and Figure 12 in that the first electrode FRM and the second electrode SRM of each sub-pixel SPXn extend in the second direction DR2 while being spaced apart from each other in the first direction DR1.

[0219] Referring to Figure 13 and Figure 14The first emission area EMA1 and the second emission area EMA2 can be disposed adjacent to each other in the second direction DR2. The third emission area EMA3 and the fourth emission area EMA4 can be disposed adjacent to each other in the second direction DR2. The first emission area EMA1 and the second emission area EMA2 can be alternately disposed in the second direction DR2. The third emission area EMA3 and the fourth emission area EMA4 can be alternately disposed in the second direction DR2. The third emission area EMA3 can be disposed spaced apart from the first emission area EMA1 in the first direction DR1. The fourth emission area EMA4 can be disposed spaced apart from the second emission area EMA2 in the first direction DR1.

[0220] The first electrode FRM and the second electrode SRM can have a shape extending in one direction, and can be provided for the respective sub-pixels SPXn.

[0221] As shown in FIG. 1A, the first electrode FRM and the second electrode SRM can be disposed in the emission area EMA of each sub-pixel SPXn while extending in the second direction DR2, and can be disposed spaced apart from each other in the first direction DR1. The first electrode FRM can be located on a lower side with respect to the center of the emission area EMA, and the second electrode SRM can be located on an upper side with respect to the center of each emission area EMA while being spaced apart from the first electrode FRM in the first direction DR1. Figure 13

[0222] ​For example, the first electrode FRM1 and the second electrode SRM1 of the first emitting region EMA1 can extend in the second direction DR2. The first electrode FRM2 and the second electrode SRM2 of the second emitting region EMA2 can extend in the second direction DR2. The first electrode FRM3 and the second electrode SRM3 of the third emitting region EMA3 can extend in the second direction DR2. The first electrode FRM4 and the second electrode SRM4 of the fourth emitting region EMA4 can extend in the second direction DR2. In one embodiment, the extension direction of the first electrode FRM1 of the first emitting region EMA1 can be aligned with the extension direction of the first electrode FRM2 of the second emitting region EMA2. The extension direction of the second electrode SRM1 of the first emitting region EMA1 can be aligned with the extension direction of the second electrode SRM2 of the second emitting region EMA2. The extension direction of the first electrode FRM3 of the third emitting region EMA3 can be aligned with the extension direction of the first electrode FRM4 of the fourth emitting region EMA4. The extension direction of the second electrode SRM3 of the third emitting region EMA3 can be aligned with the extension direction of the second electrode SRM4 of the fourth emitting region EMA4. The first electrode FRM3 of the third emission region EMA3 may be spaced apart from the first electrode FRM1 of the first emission region EMA1 in the first direction DR1. The second electrode SRM3 of the third emission region EMA3 may be spaced apart from the second electrode SRM1 of the first emission region EMA1 in the first direction DR1.

[0223] The first emitting region EMA1 and the second emitting region EMA2, which are adjacent to each other on the second direction DR2, can emit light of different colors. For example, the first emitting region EMA1 can emit red light, and the second emitting region EMA2 can emit blue light. The third emitting region EMA3 and the fourth emitting region EMA4, which are adjacent to each other on the second direction DR2, can emit light of the same color. For example, the third emitting region EMA3 and the fourth emitting region EMA4 can emit green light.

[0224] In one implementation, such as Figure 14 As shown, the third electrode TRM can extend along the second direction DR2 and be disposed in the emission region EMA of each sub-pixel SPXn, and the first electrode FRM, the second electrode SRM, and the third electrode TRM can be spaced apart from each other along the first direction DR1. The third electrode TRM can be disposed between the first electrode FRM and the second electrode SRM.

[0225] For example, the third electrode TRM1 of the first emission area EMA1 can extend in the second direction DR2. The third electrode TRM2 of the second emission area EMA2 can extend in the second direction DR2. The third electrode TRM3 and the second electrode SRM3 of the third emission area EMA3 can extend in the second direction DR2. The third electrode TRM4 of the fourth emission area EMA4 can extend in the second direction DR2. In one embodiment, the extension direction of the third electrode TRM1 of the first emission area EMA1 can be aligned with the extension direction of the third electrode TRM2 of the second emission area EMA2. The extension direction of the first electrode FRM3 of the third emission area EMA3 can be aligned with the extension direction of the first electrode FRM4 of the fourth emission area EMA4.

[0226] In one embodiment, the electrodes FRM, SRM, and TRM of each sub-pixel SPXn can extend in the second direction DR2, the first emission area EMA1 and the second emission area EMA2 adjacent to each other in the second direction DR2 can emit different colors of light, and the third emission area EMA3 and the fourth emission area EMA4 can emit the same color of light. Accordingly, the number of each of the electrodes FRM, SRM, and TRM can be reduced to form more emission areas EMA, thereby implementing a high-resolution display apparatus 10.

[0227] Figure 15 is a plan view illustrating a plurality of pixels of a display apparatus according to still another embodiment.

[0228] Referring to Figure 15 This embodiment is different from the above-described Figure 9 embodiment in that the second electrode SRM1 of the first emission area EMA1 can be connected to the first electrode FRM3 of the third emission area EMA3, and the second electrode SRM2 of the second emission area EMA2 can be connected to the first electrode FRM3 of the third emission area EMA3.

[0229] The pixel PX of the display apparatus 10 can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The pixel PX can be repeatedly disposed in the first direction DR1 and the second direction DR2. For example, the first sub-pixel SPX1 and the second sub-pixel SPX2 of the pixel PX can be repeatedly disposed in the first direction DR1, and the third sub-pixel SPX3 of the pixel PX can be disposed to be spaced apart from the first sub-pixel SPX1 in the second direction DR2. In the second direction DR2 of the third sub-pixel SPX3, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 of another pixel PX can be disposed.

[0230] In the following description, the emission areas EMA of the first and second sub-pixels SPX1 and SPX2 of another adjacent pixel PX will be referred to as a fourth emission area EMA4 and a fifth emission area EMA5, respectively. The bank BNL can define the fourth and fifth emission areas EMA4 and EMA5. For example, the fourth emission area EMA4 can emit the same color of light as the first emission area EMA1, and the fifth emission area EMA5 can emit the same color of light as the second emission area EMA2. The fourth and fifth emission areas EMA4 and EMA5 can be spaced apart in the first direction DR1.

[0231] A first electrode FRM and a second electrode SRM that extend in the first direction DR1 and are spaced apart from each other in the second direction DR2 can be disposed in each emission area EMA. For example, the fourth emission area EMA4 can include a first electrode FRM4 and a second electrode SRM4, and the fifth emission area EMA5 can include a first electrode FRM5 and a second electrode SRM5.

[0232] In one embodiment, the second electrode SRM1 of the first emission area EMA1 and the second electrode SRM2 of the second emission area EMA2 can be connected to the first electrode FRM3 of the third emission area EMA3. The first electrode FRM4 of the fourth emission area EMA4 and the first electrode FRM5 of the fifth emission area EMA5 can be connected to the second electrode SRM3 of the third emission area EMA3.

[0233] A first connection electrode CRM1 can be disposed between the second electrode SRM1 of the first emission area EMA1 and the first electrode FRM3 of the third emission area EMA3 to connect the second electrode SRM1 of the first emission area EMA1 to the first electrode FRM3 of the third emission area EMA3. A second connection electrode CRM2 can be disposed between the second electrode SRM2 of the second emission area EMA2 and the first electrode FRM3 of the third emission area EMA3 to connect the second electrode SRM2 of the second emission area EMA2 to the first electrode FRM3 of the third emission area EMA3. A third connection electrode CRM3 can be disposed between the second electrode SRM3 of the third emission area EMA3 and the first electrode FRM4 of the fourth emission area EMA4 to connect the second electrode SRM3 of the third emission area EMA3 to the first electrode FRM4 of the fourth emission area EMA4. A fourth connection electrode CRM4 can be disposed between the second electrode SRM3 of the third emission area EMA3 and the first electrode FRM5 of the fifth emission area EMA5 to connect the second electrode SRM3 of the third emission area EMA3 to the first electrode FRM5 of the fifth emission area EMA5.

[0234] The first connection electrode CRM1, the second connection electrode CRM2, the third connection electrode CRM3, and the fourth connection electrode CRM4 can extend in the second direction DR2 and can be disposed to be spaced apart from each other in the first direction DR1. The second electrode SRM1 of the first emission area EMA1, the first connection electrode CRM1, the second connection electrode CRM2, the second electrode SRM2 of the second emission area EMA2, and the first electrode FRM3 of the third emission area EMA3 can be integrated with each other. The first electrode FRM4 of the fourth emission area EMA4, the third connection electrode CRM3, the fourth connection electrode CRM4, the first electrode FRM5 of the fifth emission area EMA5, and the second electrode SRM3 of the third emission area EMA3 can be integrated with each other.

[0235] In an embodiment, the second electrode SRM1 of the first emission area EMA1, the second electrode SRM2 of the second emission area EMA2, and the first electrode FRM3 of the third emission area EMA3 can be connected, and the first electrode FRM4 of the fourth emission area EMA4, the first electrode FRM5 of the fifth emission area EMA5, and the second electrode SRM3 of the third emission area EMA3 can be connected, such that alignment signals of adjacent emission areas EMA can be shared to facilitate alignment of the light emitting element ED.

[0236] Figure 16 is a plan view illustrating a plurality of pixels of a display apparatus according to still another embodiment.

[0237] Referring to Figure 16 , this embodiment differs from the above-described Figure 9 to Figure 15 embodiment in that each pixel PX can include first, second, third, and fourth sub-pixels SPX1, SPX2, SPX3, and SPX4 formed as or Diamond .

[0238] The pixel PX of the display apparatus 10 can include first, second, third, and fourth sub-pixels SPX1, SPX2, SPX3, and SPX4. The first sub-pixel SPX1 and the second sub-pixel SPX2 can be disposed adjacent to each other in the first direction DR1. The third sub-pixel SPX3 can be disposed adjacent to the first sub-pixel SPX1 in the fourth direction DR4, and the fourth sub-pixel SPX4 can be disposed adjacent to the first sub-pixel SPX1 in the fifth direction DR5. The first sub-pixel SPX1 and the second sub-pixel SPX2 can be alternately disposed in the first direction DR1. The third sub-pixel SPX3 and the fourth sub-pixel SPX4 can be repeatedly disposed in the first direction DR1, respectively.

[0239] The first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 and the fourth sub-pixel SPX4 can emit light of a third color. For example, the first color can be red, the second color can be blue, and the third color can be green. However, the present disclosure is not limited thereto.

[0240] Each sub-pixel SPXn can include an emission area EMA. For example, the first sub-pixel SPX1 can include a first emission area EMA1, the second sub-pixel SPX2 can include a second emission area EMA2, the third sub-pixel SPX3 can include a third emission area EMA3, and the fourth sub-pixel SPX4 can include a fourth emission area EMA4. In a plan view, each emission area EMA can have a quadrilateral shape in which two sides extending in a fourth direction DR4 intersect with two sides extending in a fifth direction DR5.

[0241] Each emission area EMA can include a first electrode FRM and a second electrode SRM extending in the first direction DR1 and spaced apart from each other in the second direction DR2. In one embodiment, the extension direction of the first electrode FRM1 of the first emission area EMA1 can be aligned with the extension direction of the first electrode FRM2 of the second emission area EMA2. The extension direction of the second electrode SRM1 of the first emission area EMA1 can be aligned with the extension direction of the second electrode SRM2 of the second emission area EMA2.

[0242] The first emission area EMA1 and the second emission area EMA2 adjacent to each other in the first direction DR1 can emit light of different colors. In addition, the third emission area EMA3 and the fourth emission area EMA4 adjacent to each other in the second direction DR2 can emit light of the same color.

[0243] In a plan view, the sizes of the emission areas EMA can be the same or different. For example, the size of the second emission area EMA2 can be greater than the size of the first emission area EMA1, and the size of the first emission area EMA1 can be greater than the size of the third emission area EMA3 or the size of the fourth emission area EMA4. The size of the third emission area EMA3 and the size of the fourth emission area EMA4 can be the same. However, the present disclosure is not limited thereto, and the sizes of the emission areas EMA can be adjusted according to the colors of light emitted by each emission area EMA.

[0244] In an embodiment, the first emission area EMA1 and the second emission area EMA2 adjacent to each other in the first direction DR1 can emit different colors of light, and the third emission area EMA3 and the fourth emission area EMA4 adjacent to each other in the second direction DR2 can emit the same color of light. Accordingly, the number of each of the electrodes FRM and SRM can be reduced to form more emission areas EMA, thereby implementing a high-resolution display apparatus 10.

[0245] Figure 17 is a plan view illustrating a plurality of pixels of a display apparatus according to still another embodiment.

[0246] Referring to Figure 17 , this embodiment is different from the above-described Figure 16 embodiment of the display apparatus 10 in that each emission area EMA of each sub-pixel SPXn can further include a third electrode TRM.

[0247] Each sub-pixel SPXn can further include a third electrode TRM. The third electrode TRM can have a shape extending in a direction, and can be provided for each sub-pixel SPXn. The third electrode TRM can be provided in the emission area EMA of each sub-pixel SPXn while extending in the first direction DR1, and can be provided between the first electrode FRM and the second electrode SRM.

[0248] The first sub-pixel SPX1 can include a first emission area EMA1 and a first electrode FRM1, a second electrode SRM1, and a third electrode TRM1 provided in the first emission area EMA1. The second sub-pixel SPX2 can include a second emission area EMA2 and a first electrode FRM2, a second electrode SRM2, and a third electrode TRM2 provided in the second emission area EMA2. The third sub-pixel SPX3 can include a third emission area EMA3 and a first electrode FRM3, a second electrode SRM3, and a third electrode TRM3 provided in the third emission area EMA3. The fourth sub-pixel SPX4 can include a fourth emission area EMA4 and a first electrode FRM4, a second electrode SRM4, and a third electrode TRM4 provided in the fourth emission area EMA4.

[0249] The third electrode TRM1 of the first emission area EMA1, the third electrode TRM2 of the second emission area EMA2, the third electrode TRM3 of the third emission area EMA3, and the third electrode TRM4 of the fourth emission area EMA4 can each extend in the first direction DR1. In one embodiment, the third electrode TRM3 of the third emission area EMA3 can extend in a direction parallel to the third electrode TRM4 of the fourth emission area EMA4. The third electrode TRM3 of the third emission area EMA3 can be spaced apart from the third electrode TRM1 of the first emission area EMA1 in the second direction DR2. The third electrode TRM4 of the fourth emission area EMA4 can be spaced apart from the third electrode TRM2 of the second emission area EMA2 in the second direction DR2.

[0250] The light emitting element ED provided in each emission area EMA can include a first light emitting element ED1 and a second light emitting element ED2. The first light emitting element ED1 can be provided between the first electrode FRM and the third electrode TRM, and the second light emitting element ED2 can be provided between the second electrode SRM and the third electrode TRM. An end portion of the first light emitting element ED1 can overlap the first electrode FRM in a plan view, and another end portion of the first light emitting element ED1 can overlap the third electrode TRM in a plan view. An end portion of the second light emitting element ED2 can overlap the third electrode TRM in a plan view, and another end portion of the second light emitting element ED2 can overlap the second electrode SRM in a plan view.

[0251] Figure 18 is a plan view illustrating a plurality of pixels of a display apparatus according to still another embodiment.

[0252] Referring to Figure 18 This embodiment is different from the above-described Figure 16 embodiment in that the second electrode SRM1 of the first emission area EMA1 can be connected to the first electrode FRM3 of the third emission area EMA3, and the second electrode SRM2 of the second emission area EMA2 can be connected to the first electrode FRM3 of the third emission area EMA3.

[0253] The pixel PX of the display apparatus 10 can include a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4. The pixel PX can be repeatedly disposed in the first direction DR1 and the second direction DR2. For example, the first sub-pixel SPX1 and the second sub-pixel SPX2 of the pixel PX can be repeatedly disposed in the first direction DR1. The third sub-pixel SPX3 can be disposed to be spaced apart from the first sub-pixel SPX1 in the second direction DR2. The fourth sub-pixel SPX4 can be disposed to be spaced apart from the third sub-pixel SPX3 in the second direction DR2. In the second direction DR2 of the third sub-pixel SPX3, the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 of another pixel PX can be disposed. The fourth sub-pixel SPX4 of the another pixel PX can be the third sub-pixel SPX3 of the adjacent pixel PX.

[0254] In the following description, the emission areas EMA of the first sub-pixel SPX1 and the second sub-pixel SPX2 of the another adjacent pixel PX can be referred to as a sixth emission area EMA6 and a fifth emission area EMA5, respectively. The fifth emission area EMA5 and the sixth emission area EMA6 can be spaced apart in the first direction DR1.

[0255] The first electrode FRM and the second electrode SRM extending in the first direction DR1 and spaced apart from each other in the second direction DR2 can be disposed in each emission area EMA. For example, the fifth emission area EMA5 can include a first electrode FRM5 and a second electrode SRM5, and the sixth emission area EMA6 can include a first electrode FRM6 and a second electrode SRM6.

[0256] In one embodiment, the second electrode SRM1 of the first emission area EMA1 and the second electrode SRM2 of the second emission area EMA2 can be connected to the first electrode FRM3 of the third emission area EMA3. The first electrode FRM5 of the fifth emission area EMA5 and the first electrode FRM6 of the sixth emission area EMA6 can be connected to the second electrode SRM3 of the third emission area EMA3.

[0257] The first connection electrode CRM1 can be disposed between the second electrode SRM1 of the first emission area EMA1 and the first electrode FRM3 of the third emission area EMA3 to connect the second electrode SRM1 of the first emission area EMA1 to the first electrode FRM3 of the third emission area EMA3. The second connection electrode CRM2 can be disposed between the second electrode SRM2 of the second emission area EMA2 and the first electrode FRM3 of the third emission area EMA3 to connect the second electrode SRM2 of the second emission area EMA2 to the first electrode FRM3 of the third emission area EMA3. The third connection electrode CRM3 can be disposed between the second electrode SRM3 of the third emission area EMA3 and the first electrode FRM5 of the fifth emission area EMA5 to connect the second electrode SRM3 of the third emission area EMA3 to the first electrode FRM5 of the fifth emission area EMA5. The fourth connection electrode CRM4 can be disposed between the second electrode SRM3 of the third emission area EMA3 and the first electrode FRM6 of the sixth emission area EMA6 to connect the second electrode SRM3 of the third emission area EMA3 to the first electrode FRM6 of the sixth emission area EMA6.

[0258] The first connection electrode CRM1, the second connection electrode CRM2, the third connection electrode CRM3, and the fourth connection electrode CRM4 can extend in the second direction DR2 and can be disposed to be spaced apart from each other in the first direction DR1. The second electrode SRM1 of the first emission area EMA1, the first connection electrode CRM1, the second connection electrode CRM2, the second electrode SRM2 of the second emission area EMA2, and the first electrode FRM3 of the third emission area EMA3 can be integrated with each other. The first electrode FRM5 of the fifth emission area EMA5, the third connection electrode CRM3, the fourth connection electrode CRM4, the first electrode FRM6 of the sixth emission area EMA6, and the second electrode SRM3 of the third emission area EMA3 can be integrated with each other.

[0259] In an embodiment, the second electrode SRM1 of the first emission area EMA1, the second electrode SRM2 of the second emission area EMA2, and the first electrode FRM3 of the third emission area EMA3 can be connected, and the first electrode FRM5 of the fifth emission area EMA5, the first electrode FRM6 of the sixth emission area EMA6, and the second electrode SRM3 of the third emission area EMA3 can be connected, such that alignment signals of adjacent emission areas EMA can be shared to facilitate alignment of the light emitting element ED.

[0260] As described above, in the display apparatus 10 according to one embodiment, the emission areas EMA adjacent to each other in the first direction DR1 or the second direction DR2 can emit different colors of light. Accordingly, the number of each of the electrodes FRM, SRM, and TRM can be reduced to form more emission areas EMA, thereby realizing a high-resolution display apparatus 10.

[0261] The above description is an example of technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented alone or in combination with each other.

[0262] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are intended to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized by including: a substrate; and a bank layer disposed on the substrate and defining a first emission region, a second emission region, and a third emission region, wherein each of the first emission region, the second emission region, and the third emission region includes: a first electrode and a second electrode extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of light emitting elements disposed between the first electrode and the second electrode, the first emission region and the second emission region being adjacent to each other in the first direction, the third emission region being spaced apart from the first emission region or the second emission region in the second direction, and the first emission region, the second emission region, and the third emission region emit different colors of light.

2. The display device of claim 1, wherein an extension direction of the first electrode of the first emission region is aligned with an extension direction of the first electrode of the second emission region, an extension direction of the second electrode of the first emission region is aligned with an extension direction of the second electrode of the second emission region, the first electrode of the third emission region is spaced apart from the first electrode of the first emission region in the second direction, and the second electrode of the third emission region is spaced apart from the second electrode of the first emission region in the second direction.

3. The display device of claim 1, wherein the first emission region emits red light, the second emission region emits blue light, and the third emission region emits green light.

4. The display device of claim 1, wherein, in a plan view, a size of the third emission region is greater than a size of the first emission region or a size of the second emission region, and wherein the size of the first emission region is equal to the size of the second emission region.

5. The display device of claim 1, wherein, the bank layer further defines: a fourth emission region and a fifth emission region spaced apart in the first direction, and the third emission region being interposed between the fourth emission region and the fifth emission region, wherein each of the fourth emission region and the fifth emission region includes the first electrode, the second electrode, and the plurality of light emitting elements, wherein the fourth emission region and the first emission region emit the same color of light, and the fifth emission region and the second emission region emit the same color of light.

6. A display device, characterized by including: a substrate; and a bank layer disposed on the substrate and defining a first emission region, a second emission region, a third emission region, and a fourth emission region, wherein each of the first emission region, the second emission region, the third emission region, and the fourth emission region includes: a first electrode and a second electrode extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of light emitting elements disposed between the first electrode and the second electrode, the first emission region and the second emission region being adjacent to each other in the first direction, the third emission region and the fourth emission region being adjacent to each other in the first direction, the third emission region and the fourth emission region are spaced apart from the first emission region or the second emission region in the second direction, the first emission region, the second emission region, and the third emission region emit different colors of light, and the third emission region and the fourth emission region emit the same color of light.

7. The display device of claim 6, an extension direction of the first electrode of the first emission region is aligned with an extension direction of the first electrode of the second emission region, an extension direction of the first electrode of the third emission region is aligned with an extension direction of the first electrode of the fourth emission region, the first electrode of the third emission region and the first electrode of the fourth emission region are spaced apart from the first electrode of the first emission region in the second direction, and the second electrode of the third emission region and the second electrode of the fourth emission region are spaced apart from the second electrode of the first emission region in the second direction.

8. The display device of claim 6, the first emission region emits red light, the second emission region emits blue light, and the third emission region and the fourth emission region emit green light.

9. The display device of claim 6, wherein, in a plan view, the first emission region, the second emission region, the third emission region, and the fourth emission region are equal in size, and wherein, in the first direction, lengths of the first electrode of the first emission region, the first electrode of the second emission region, the first electrode of the third emission region, and the first electrode of the fourth emission region are equal.

10. The display device of claim 6, wherein, the bank further defines: a fifth emission region and a sixth emission region spaced apart in the first direction, and the third emission region is interposed between the fifth emission region and the sixth emission region, wherein each of the fifth emission region and the sixth emission region includes the first electrode, the second electrode, and the plurality of light emitting elements, wherein the fifth emission region and the second emission region emit the same color of light, and the sixth emission region and the first emission region emit the same color of light.

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