Wheel speed signal simulation device and semi-physical simulation test system

Abstract

The utility model relates to the technical field of simulation, and discloses a wheel speed signal simulation device and a semi-physical simulation test system, the wheel speed signal simulation device comprises an FPGA processor and at least one signal channel connected to the FPGA processor, and each signal channel comprises a signal processing module, a signal output module and a signal conversion module. The signal processing module and the signal output module of each signal channel are respectively connected with the FPGA processor, and the signal output module selects an output mode according to a mode selection signal output by the FPGA processor. The wheel speed signal simulation device can simulate the signal output of a vehicle wheel speed sensor, supports the simultaneous output of a plurality of channels, can respectively simulate different types of sensors through the plurality of channels, supports the fault simulation of the wheel speed sensor, and cooperates with the fault diagnosis function of a verification controller.

Description

TECHNICAL FIELD

[0001] The utility model relates to simulation technical field especially, and it is a wheel speed signal simulation device and semi -physical simulation test system. BACKGROUND

[0002] For vehicles, it is essential to obtain the wheel speed information of the vehicle. Wheel speed sensors are used to measure the rotational speed of vehicle wheels, and commonly used wheel speed sensors include magneto-electric wheel speed sensors, Hall wheel speed sensors, and magnetoresistive wheel speed sensors. Through logical calculation of the wheel speed signal sent by the wheel speed sensor by the vehicle ECU (Electronic Control Unit, also known as controller), the speed of the vehicle is estimated, and therefore, verifying the analysis capability of the ECU for the wheel speed signal is one of the key links in vehicle development testing.

[0003] Semi-physical simulation testing is a test method that saves manpower and resources in the vehicle industry, without obtaining the wheel speed signal from a real wheel speed sensor, but simulating the wheel speed signal through a specific simulation device, using the simulated wheel speed signal to verify the function of the ECU, such as verifying the analysis capability and fault handling capability of the ECU for regular wheel speed signals and abnormal wheel speed signals. However, the existing simulation device is still immature, and although the existing simulation device can simulate the wheel speed signal, it has a complex circuit structure and requires a large area of circuit board, making the simulation device expensive and bulky. SUMMARY

[0004] The utility model aims to solve at least one of the technical problems in the related art to some extent. To this end, the first purpose of the utility model is to propose a wheel speed signal simulation device that can simulate the signal output of a vehicle wheel speed sensor, support simultaneous output of multiple channels, and simulate different types of sensors in multiple channels. The wheel speed sensor fault simulation supports the fault diagnosis function of the controller.

[0005] The second purpose of the utility model is to propose a semi-physical simulation test system.

[0006] To achieve the above object, the utility model discloses a first aspect proposes a wheel speed signal simulation device, including FPGA treater and at least one signal channel connected to FPGA treater, and each signal channel includes: signal processing module, signal output module, signal conversion module. The signal processing module and signal output module of each signal channel are connected with FPGA treater respectively, and the signal output module selects the output mode according to the mode selection signal of FPGA treater, and the signal processing module converts the digital voltage of FPGA treater output into target analog voltage, wherein, digital voltage and mode selection signal are generated according to the configuration parameter of the target simulation signal of the configuration of FPGA treater, and the output mode includes at least: current mode and voltage mode. When the output mode is voltage mode, the signal processing module exports target analog voltage to the first end of controller through signal output module, and target analog voltage represents target simulation signal. When the output mode is current mode, the signal processing module exports target analog voltage to signal conversion module through signal output module, makes signal conversion module generate target current, and exports target current to the second end of controller, and target current represents target simulation signal.

[0007] As a possible implementation, the signal processing module includes: digital-to-analog converter, first operational amplifier, first resistance, second resistance. Digital-to-analog converter is connected with FPGA treater, and the first input end of first operational amplifier is connected with digital-to-analog converter, and the second input end is connected with the first end of first resistance and the first end of second resistance respectively, and the output end is connected with the second end of first resistance and signal output module respectively, and the second end of second resistance is grounded. Digital-to-analog converter is configured to convert digital voltage into analog voltage, and first operational amplifier is configured to amplify analog voltage based on the resistance of first resistance and second resistance to obtain target analog voltage.

[0008] As a possible implementation, FPGA treater is connected with host computer, for receiving the configuration data of target simulation signal configured by host computer for multiple signal channels respectively, and FPGA treater generates multiple digital voltages based on multiple configuration data, and outputs multiple digital voltages to the signal processing module of each signal channel respectively, and outputs multiple mode selection signals to the signal output module of each signal channel respectively.

[0009] As a possible implementation, the signal processing module further includes: isolation module. Isolation module is connected between FPGA treater and digital-to-analog converter. Isolation module is configured to isolate the digital voltage transmitted in multiple signal channels and output.

[0010] As a possible implementation, the signal output module comprises: a relay and a relay controller. The first end of the relay is connected with the output end of the first operational amplifier, the second end is connected with the first end of the controller, and the third end is connected with the relay controller, and the relay controller is further connected with the FPGA processor. The relay controller is configured to receive the mode selection signal and change the output mode of the relay based on the mode selection signal. When the output mode is the voltage mode, the first end and the second end of the relay are turned on, so that the signal processing module outputs the target analog voltage to the first end of the controller. When the output mode is the current mode, the first end and the second end of the relay are respectively connected with the signal conversion module, so that the signal processing module outputs the target analog voltage to the signal conversion module, and the signal conversion module outputs the generated target current to the second end of the controller.

[0011] As a possible implementation, the relay controller comprises: a second switch tube and a third resistor. The first end of the third resistor is connected with the FPGA processor, and the second end is connected with the control end of the second switch tube. The first end of the second switch tube is connected with the third end of the relay, and the second end is grounded. Under the action of the mode selection signal, if the second switch tube is turned on, the output mode is the voltage mode, and if the second switch tube is cut off, the output mode is the current mode.

[0012] As a possible implementation, the signal conversion module comprises: a second operational amplifier, a first switch tube and a fourth resistor. The second operational amplifier is configured to control the turn-on or cut-off of the first switch tube based on the target analog voltage. When the output mode is the current mode, the first input end of the second operational amplifier is connected with the first end of the relay, the second input end is respectively connected with the first end of the first switch tube and the first end of the fourth resistor, and the output end is connected with the control end of the first switch tube. The second end of the first switch tube is connected with the first end of the controller, and the second end of the fourth resistor is grounded. The second operational amplifier is configured to control the turn-on or cut-off of the first switch tube based on the target analog voltage.

[0013] As a possible implementation, the second end of the fourth resistor is further connected with the second end of the controller. When the output mode is the current mode, the first switch tube is turned on, and the first switch tube and the fourth resistor form a current loop of the target current with the controller, so that the controller takes the target current as the target simulation signal.

[0014] As a possible implementation, the signal conversion module further comprises: a first diode, a fifth resistor and a sixth resistor. The first end of the first diode is connected with the first end of the controller, and the second end is connected with the second end of the first switch tube. The second end of the fifth resistor is connected with the first input end of the second operational amplifier. The first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end is grounded. When the output mode is the current mode, the first end of the fifth resistor is connected with the first end of the relay.

[0015] To achieve the above object, the utility model discloses a second aspect proposes a kind of semi-physical simulation test system, comprising: host computer, controller, as any one described in the wheel speed signal simulation device.

[0016] The wheel speed signal simulation device of the embodiment of the utility model realizes the simulation of multiple types of wheel speed signals by the output mode selection function of signal output module.Specifically, when the type of target simulation signal required is magneto signal, signal output module connects signal processing module to controller, so that signal processing module can output target analog voltage as target simulation signal to controller.When the type of target simulation signal required is Hall current type, signal output module connects signal processing module to signal conversion module, so that target analog voltage drives signal conversion module to generate target current representing target simulation signal, and the target current enters controller through the loop between signal conversion module and controller, thereby realizing the simulation of target simulation signal.The wheel speed signal simulation device of the embodiment of the utility model can include multiple signal channels, support multiple signal channels to output different types of target simulation signals simultaneously, and due to the existence of isolation module, the degree of interference of multiple target simulation signals in the output process is reduced.In addition, the wheel speed signal simulation device of the embodiment of the utility model also supports fault simulation to cooperate with the fault diagnosis function of controller.

[0017] Additional aspects and advantages of the utility model will be partially given in the following description, some will become apparent from the following description, or be understood by the practice of the utility model. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The structure schematic diagram of the semi-physical simulation test system of some embodiments of the utility model.

[0019] Figure 2 The structure schematic diagram of the wheel speed signal simulation device of some embodiments of the utility model.

[0020] Figure 3 The structure schematic diagram of the wheel speed signal simulation device and the structure schematic diagram of some signal channels of some embodiments of the utility model.

[0021] Figure 4 A kind of structure schematic diagram of the signal processing module of some embodiments of the utility model.

[0022] Figure 5 Another structure schematic diagram of the signal processing module of some embodiments of the utility model.

[0023] Figure 6 A kind of structure schematic diagram of the signal output module of some embodiments of the utility model.

[0024] Figure 7 A structure schematic view of a relay controller of some embodiments of the utility model.

[0025] Figure 8 A structure schematic view of a signal conversion module of some embodiments of the utility model.

[0026] Figure 9 Another structure schematic view of a signal conversion module of some embodiments of the utility model.

[0027] Explanation of reference signs

[0028] 1000 - semi-physical simulation test system, 100 - wheel speed signal simulation device, 200 - upper computer, 300 - controller, CH+ - first end of the controller, CH- - second end of the controller, 10 - FPGA processor, 40 - signal processing module, 41 - isolation module, 42 - digital-to-analog converter, OP1 - first operational amplifier, R1 - first resistor, R2 - second resistor, 30 - signal output module, K1 - relay, 31 - relay controller, Q2 - second switch tube, R3 - third resistor, 50 - signal conversion module, Q1 - first switch tube, D1 - first diode, OP2 - second operational amplifier, R4 - fourth resistor, R5 - fifth resistor, R6 - sixth resistor. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the utility model more clear and intelligible, the following will be combined with specific embodiments, and referring to the drawings, the utility model is further explained in detail.

[0030] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the utility model should be understood as the usual meaning by the person skilled in the art in the field to which the utility model belongs. The "first", "second" and similar words used in the embodiments of the utility model do not represent any order, quantity or importance, but are only used to distinguish different components. "Include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, and other elements or objects are not excluded. "Connect" or "connected" and similar words are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent relative positional relationship, when the absolute position of the described object changes, the relative positional relationship can also change accordingly.

[0031] As in the background section, for vehicles, it is essential to obtain the wheel speed information of the vehicle. Wheel speed sensors are used to measure the rotational speed of the vehicle wheels, and commonly used wheel speed sensors include magneto-electric wheel speed sensors, Hall wheel speed sensors, and magneto-resistive wheel speed sensors. Through logical calculation of the wheel speed signal sent by the wheel speed sensor by the vehicle ECU, the speed of the vehicle is estimated, and therefore, verifying the analysis ability of the ECU for the wheel speed signal is one of the key links in the development and testing of vehicles.

[0032] The applicant found in the process of implementing the present application that semi-physical simulation testing is a testing method that saves manpower and resources in the vehicle industry, without the need to deploy real wheel speed sensors to obtain wheel speed signals, but to simulate wheel speed signals through a wheel speed signal simulation device, and to use the simulated signals to verify the analysis ability and fault handling ability of the ECU for regular or abnormal wheel speed signals.

[0033] The current wheel speed signal simulation device can simulate wheel speed signals, but the circuit structure is complex, a large area of circuit board is needed, the overall volume of the wheel speed signal simulation device is large, and the cost is high.

[0034] Based on the above, the present application embodiment provides a wheel speed signal simulation device and a semi-physical simulation testing system, which can improve the problem of complex circuit structure and high cost of the existing simulation device, to meet the actual needs of verifying the vehicle controller at present.

[0035] Please refer to Figure 1 The present application embodiment exemplarily shows a structure schematic diagram of a semi-physical simulation testing system. As Figure 1 Indicated, the semi-physical simulation testing system 1000 comprises: a controller 300, a wheel speed signal simulation device 100, and an upper computer 200 connected in sequence.

[0036] In the testing system, the wheel speed signal simulation device 100 is connected with the controller 300 through a bus, and is used for simulating the wheel speed signal detected by the real wheel speed sensor installed on the vehicle. When multiple wheel speed signals need to be simulated, multiple wheel speed signal simulation devices 100 can be arranged between the upper computer 200 and the controller 300, or the simulation of multiple sensors can be realized through multiple signal channels included in the wheel speed signal simulation device 100 itself, which is more helpful to reduce the complexity and cost of the semi-physical simulation testing system 1000.

[0037] As Figure 2As shown, each wheel speed signal simulation device 100 comprises: an FPGA processor 10 and at least one signal channel connected to the FPGA processor 10, the number of signal channels in each wheel speed signal simulation device 100 can be set according to actual simulation requirements, and a plurality of signal channels can be respectively denoted as signal channel 1 to signal channel n. Exemplarily, as shown in the figure, Figure 3 As shown in the embodiment of the wheel speed signal simulation device of the utility model, each signal channel can comprise: a signal processing module 40, a signal output module 30, and a signal conversion module 50, wherein the signal output module 30 and the signal processing module 40 are connected with the FPGA processor 10, and the signal output module 30 is also connected with the signal processing module 40 and the first end CH+ of the controller 300 respectively. In addition, in some cases, the signal output module 30 will also be connected with the signal conversion module 50, which will be fully explained hereinafter.

[0038] In the embodiment of the utility model, the FPGA processor 10 is configured to be connected with the upper computer 200, which is mainly used for receiving the configuration data of the target simulation signal configured by the upper computer 200. The FPGA processor 10 can output digital voltage to the signal processing module 40 based on these configuration data, and determine the type of the target simulation signal, and then output the mode selection signal to the signal output module 30 according to the type of the target simulation signal. In the case that multiple real sensors need to be simulated, the FPGA processor 10 will receive the configuration data of multiple target simulation signals configured by the upper computer 200. At this time, the FPGA processor 10 will generate multiple digital voltages based on these configuration data, and output the multiple digital voltages to the signal processing module 40 of each signal channel respectively, and output multiple mode selection signals to the signal output module 30 of each signal channel respectively.

[0039] Based on the above, in the embodiment of the utility model, the signal processing module 40 is mainly used for converting the digital voltage output by the FPGA processor 10 into a target analog voltage, and the signal output module 30 is mainly used for selecting the output mode according to the mode selection signal output by the FPGA processor 10, wherein the output mode at least includes: current mode and voltage mode. This is because in actual application, commonly used wheel speed sensors are mainly divided into two categories: magneto electric wheel speed sensor and Hall wheel speed sensor, therefore, the wheel speed signal simulation device of the utility model mainly simulates magneto electric wheel speed signal and Hall current wheel speed signal.

[0040] Exemplarily, when the type of the target simulation signal is a magneto electric wheel speed signal, the configuration data sent by the host computer 200 can include the frequency, amplitude, tooth number, etc. of the target simulation signal, and in addition, in order to realize fault simulation, the configuration data can also include a missing tooth number parameter for testing the ability of the controller 300 to analyze the fault wheel speed signal. When the type of the target simulation signal is a Hall current wheel speed signal, in addition to the frequency, amplitude, tooth number, missing tooth number, etc. parameters, the configuration data sent by the host computer 200 can also include the duty cycle, low current value, intermediate current value, high current value, rotation direction, pulse width, etc. of the target simulation signal, and in terms of fault simulation, it can also support simulation of fault types such as current value overrun.

[0041] Based on the above, in the wheel speed signal simulation device 100 of the embodiment of the utility model, when the type of the target simulation signal is magneto electric, the output mode of the signal output module 30 should be voltage mode, in this mode, the signal processing module 40 can form a connection with the controller 300 through the signal output module 30, transmit the target simulation voltage to the controller 300 through the first end CH+ of the controller 300, and the target simulation voltage at this time represents the target simulation signal. When the type of the target simulation signal is Hall current, the output mode should be current mode, in this mode, the signal conversion module 50 is connected with the signal output module 30, so that the signal processing module 40 can output the target simulation voltage to the signal conversion module 50 through the signal output module 30, drive the signal conversion module 50 to generate the target current, and transmit the target current to the controller 300 through the second end CH- of the controller 300, and the target current at this time represents the target simulation signal.

[0042] It can be seen that the wheel speed signal simulation device 100 of the embodiment of the utility model includes a signal output module 30, and the type of the simulated signal is controlled by the mode selection function of the signal output module 30, so that the simulation device 100 can simulate at least two types of wheel speed signals, namely magneto electric wheel speed signal and Hall current wheel speed signal. Obviously, the above design greatly simplifies the circuit structure of the wheel speed signal simulation device 100, which helps to reduce the manufacturing cost of the simulation device 100.

[0043] Please refer to Figure 4In some embodiments of the wheel speed signal simulation device 100 of the utility model, the signal processing module 40 comprises: a digital-to-analog converter 42 (DAC), a first operational amplifier OP1, a first resistor R1, and a second resistor R2. The input end of the digital-to-analog converter 42 is connected to the output end of the FPGA processor 10, and the output end of the digital-to-analog converter 42 is connected to the first input end of the first operational amplifier OP1. The second input end of the first operational amplifier OP1 is connected to the first end of the first resistor R1 and the first end of the second resistor R2, respectively, and the output end of the first operational amplifier OP1 is connected to the signal output module 30. The second end of the first resistor R1 is connected to the output end of the first operational amplifier OP1. The second end of the second resistor R2 is grounded.

[0044] Specifically, the digital-to-analog converter 42 is configured to convert the digital voltage generated by the FPGA processor 10 into an analog voltage. The first operational amplifier OP1 is configured to amplify the analog voltage output by the digital-to-analog converter 42 to obtain a target analog voltage, wherein the amplification factor is determined according to the resistance values of the first resistor R1 and the second resistor R2.

[0045] In the case where the wheel speed signal simulation device 100 needs to output multiple wheel speed signals simultaneously, as shown in Figure 5 the signal processing module 40 of the wheel speed signal simulation device 100 of the utility model embodiment can also include an isolation module 41. The input end of the isolation module 41 is connected to the output end of the FPGA processor 10, and the output end of the isolation module 41 is connected to the input end of the digital-to-analog converter 42. The isolation module 41 is used to isolate the digital voltage transmitted in each signal channel when receiving the multiple digital voltages, so that the multiple signal channels can output the target simulation signals simultaneously without being disturbed by other signal channels. At the same time, the isolation module 41 also plays a role in simplifying the circuit structure in the wheel speed signal simulation device with multiple signal channel structures.

[0046] Please refer to Figure 6 In some embodiments of the wheel speed signal simulation device 100 of the utility model, the signal output module 30 comprises a relay K1 and a relay controller 31.

[0047] The first end of the relay K1 is connected to the output end of the first operational amplifier OP1, the second end is connected to the first end CH+ of the controller 300, and the third end is connected to the relay controller 31. The relay controller 31 is also connected to the FPGA processor 10.

[0048] The relay controller 31 is used to receive a mode selection signal and change the output mode of the relay K1 based on the mode selection signal.

[0049] When the output mode is the voltage mode, the first end and the second end of the relay K1 are turned on, so that the signal processing module 40 outputs the target analog voltage to the first end CH+ of the controller 300. When the output mode is the current mode, the first end and the second end of the relay K1 are connected with the signal conversion module 50 respectively, so that the signal processing module 40 outputs the target analog voltage to the signal conversion module 50, and the signal conversion module 50 outputs the generated target current to the second end CH- of the controller 300.

[0050] Further, referring to Figure 7 The relay controller 31 comprises a second switch tube Q2 and a third resistor R3.

[0051] The first end of the third resistor R3 is connected with the FPGA processor 10, and the second end is connected with the control end of the second switch tube Q2. The first end of the second switch tube Q2 is connected with the third end of the relay K1, and the second end is grounded.

[0052] Under the action of the mode selection signal, if the second switch tube Q2 is turned on, the output mode is the voltage mode, and if the second switch tube Q2 is cut off, the output mode is the current mode.

[0053] Figure 6 And Figure 7 Exemplarily, the structure of the relay K1 and the relay controller 31 is given, and it can be seen that the Q2 is an NPN triode, the relay K1 has a double-pole double-throw structure, and the relay K1 comprises a magnetic core and two metal contacts for controlling the output path. One end of the magnetic core is connected with an external power supply, and the other end (the third end of the K1) of the magnetic core is connected with the collector of the Q2 (the first end of the Q2). The mode selection signal output by the FPGA processor 10 acts on the base of the Q2, and the R3 is used for providing the base current of the Q2. When the Q2 is in the turned-on state under the control of the mode selection signal, the magnetic core of the K1 is electrified to generate magnetism, and under the action of the magnetic field, the two metal contacts (the first end and the second end of the K1) of the K1 are connected, so that the output mode of the signal output module 30 is the voltage output mode. When the Q2 is in the cut-off state under the control of the mode selection signal, the two metal contacts of the K1 are disconnected and connected to the signal conversion module 50 respectively, so that the output mode of the signal output module 30 is the current output mode. In other embodiments of the utility model, the Q2 can also adopt other types of switch tubes, such as MOS tubes. The MOS tube is helpful to improve the circuit precision.

[0054] Referring to Figure 8The signal conversion module 50 comprises a second operational amplifier OP2, a first switch tube Q1, and a fourth resistor R4. When the output mode of the signal output module 30 is the current mode, the first input end of the second operational amplifier OP2 is connected with the first end of the relay K1, the second input end is connected with the first end of the first switch tube Q1 and the first end of the fourth resistor R4 respectively, and the output end is connected with the control end of the first switch tube Q1. The second end of the first switch tube Q1 is connected with the first end CH+ of the controller 300, and the second end of the fourth resistor R4 is grounded. The second end of the fourth resistor R4 is also connected with the second end CH- of the controller 300. The second operational amplifier OP2 is configured to control the conduction or cut-off of the first switch tube Q1 based on the target analog voltage, and the fourth resistor R4 is a sampling resistor.

[0055] It can be seen that the signal conversion module 50 is a voltage-to-current circuit. If the type of the target simulation signal is the Hall current signal, the signal conversion module 50 will output the current representing the target simulation signal to the controller 300 under the control of the target analog voltage.

[0056] Taking Q1 as an NPN triode as an example, when the output mode of the signal output module 30 is the current mode, Q2 is cut off under the control of the mode selection signal, and the target analog voltage generated by the signal processing module 40 is applied to the first input end of OP2. The first input end of OP2 inputs the target analog voltage. Assuming that Q1 has not been turned on at this time, the second input end of OP2 is equivalent to input zero, and the output end of OP1 generates an in-phase output voltage. The voltage difference between the base and the emitter of Q1 reaches the turn-on voltage of Q1 to turn on Q1. The controller 300 forms a current loop of the target current through its CH+ end and CH- end and Q1 and R4. The target current flows into the controller 300 through the CH- end of the controller 300 and is received by the controller 300 as the target simulation signal. In addition, the target current flowing through R4 changes the voltage of R4, and the sampling resistor R4 feeds back the change of the voltage of R4 to the second input end of OP2 in real time. The voltage difference between the first input end of OP2 and the second input end of OP2 determines the output voltage of OP2, which affects the voltage difference between the base and the emitter of Q1, and further affects the size of the target current flowing into the controller 300 in the loop.

[0057] Please refer to Figure 9 As an improvement of the signal conversion module 50 in the above embodiment, the signal conversion module 50 further comprises a first diode D1, a fifth resistor R5, and a sixth resistor R6.

[0058] The first end of the first diode D1 is connected with the first end CH+ of the controller 300, the second end is connected with the second end of the first switch tube Q1, the second end of the fifth resistor R5 is connected with the first input end of the second operational amplifier OP2, the first end of the fifth resistor R5 is connected with the first end of the relay K1 when the output mode is the current mode. When the controller 300 and Q1 form a current loop, the first diode D1 mainly plays a role of anti-reverse connection.

[0059] In summary, the wheel speed signal simulation device of the embodiment of the utility model realizes the simulation of multiple types of signals through the function of output mode selection of the signal output module. Specifically, when the type of the target simulation signal required is a magneto-electric signal, the signal output module connects the signal processing module to the controller, so that the signal processing module can output the target analog voltage as the target simulation signal to the controller. When the type of the target simulation signal required is a Hall current type, the signal output module connects the signal processing module to the signal conversion module, so that the target analog voltage drives the signal conversion module to generate a target current representing the target simulation signal, and the target current enters the controller through the loop between the signal conversion module and the controller, thereby realizing the simulation of the target simulation signal. The wheel speed signal simulation device of the embodiment of the utility model can include multiple signal channels, support multiple signal channels to output target simulation signals at the same time, and due to the existence of the isolation module, the degree of interference of multiple target simulation signals in the output process is reduced. In addition, the wheel speed signal simulation device of the embodiment of the utility model supports fault simulation to cooperate with the fault diagnosis function of the controller.

[0060] In addition, although the circuit structure features of the utility model are described in a specific combination manner in the drawings, this does not require or imply that the structure of the utility model must be constructed in this combination manner, or that all the shown modules must be applied to achieve the desired results.

[0061] It should be understood that various parts of the utility model can be realized by hardware, software, firmware or their combination. In the above-mentioned embodiments, multiple steps or methods can be realized by software or firmware stored in the memory and executed by a suitable instruction execution system. For example, if realized by hardware, and as in another embodiment, it can be realized by any one or their combination of the following technologies known in the art: discrete logic circuit with logic gate circuit for realizing logic function on data signal, application specific integrated circuit with suitable combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) and the like.

[0062] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present application shall have the common meaning understood by one of ordinary skill in the art to which the embodiments of the present application belong. The terms "first", "second", and similar terms used in the embodiments of the present application do not represent any order, number, or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0063] Although the spirit and principles of the present application have been described with reference to several specific embodiments, it should be understood that the present application is not limited to the disclosed specific embodiments, and the division of aspects does not mean that the features in these aspects cannot be combined to benefit. This division is only for the convenience of expression. The present application is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended claims. The scope of the appended claims is the broadest interpretation, so as to include all such modifications and equivalent structures and functions.

Claims

1. A wheel speed signal simulation device, characterized by, The application relates to a signal processing device, which comprises an FPGA processor (10) and at least one signal channel connected to the FPGA processor (10), wherein each signal channel comprises a signal processing module (40), a signal output module (30) and a signal conversion module (50); the signal processing module (40) and the signal output module (30) of each signal channel are connected to the FPGA processor (10) respectively, the signal processing module (40) converts a digital voltage output by the FPGA processor (10) into a target analog voltage, and the signal output module (30) selects an output mode according to a mode selection signal output by the FPGA processor (10), wherein the digital voltage and the mode selection signal are generated by the FPGA processor (10) according to configuration parameters of a target simulation signal configured, and the output mode at least comprises a current mode and a voltage mode; when the output mode is the voltage mode, the signal processing module (40) outputs the target analog voltage to a first end (CH+) of a controller (300) through the signal output module (30), and the target analog voltage represents the target simulation signal; when the output mode is the current mode, the signal processing module (40) outputs the target analog voltage to the signal conversion module (50) through the signal output module (30), so that the signal conversion module (50) generates a target current, and the target current is output to a second end (CH-) of the controller (300), and the target current represents the target simulation signal.

2. The wheel speed signal simulation device of claim 1, wherein, The signal processing module (40) comprises a digital-to-analog converter (42), a first operational amplifier (OP1), a first resistor (R1) and a second resistor (R2); the digital-to-analog converter (42) is connected to the FPGA processor (10), a first input end of the first operational amplifier (OP1) is connected to the digital-to-analog converter (42), a second input end of the first operational amplifier (OP1) is connected to a first end of the first resistor (R1) and a first end of the second resistor (R2) respectively, an output end of the first operational amplifier (OP1) is connected to a second end of the first resistor (R1) and the signal output module (30) respectively, and a second end of the second resistor (R2) is grounded; the digital-to-analog converter (42) is configured to convert the digital voltage into an analog voltage, and the first operational amplifier (OP1) is configured to amplify the analog voltage based on resistance values of the first resistor (R1) and the second resistor (R2) to obtain the target analog voltage.

3. The wheel speed signal simulation apparatus of claim 2, wherein, The FPGA processor (10) is connected with the upper computer (200), and is used for receiving configuration data of the target simulation signal configured by the upper computer (200) for a plurality of signal channels; the FPGA processor (10) generates a plurality of digital voltages and a plurality of mode selection signals based on a plurality of the configuration data, and outputs the plurality of digital voltages to the signal processing module (40) of each signal channel and outputs the plurality of mode selection signals to the signal output module (30) of each signal channel respectively.

4. The wheel speed signal simulation apparatus of claim 3, wherein, The signal processing module (40) further comprises an isolation module (41); the isolation module (41) is connected between the FPGA processor (10) and the digital-to-analog converter (42); the isolation module (41) is configured to isolate and output the digital voltage transmitted in a plurality of signal channels.

5. The wheel speed signal simulation apparatus of claim 3, wherein, The signal output module (30) comprises a relay (K1) and a relay controller (31); a first end of the relay (K1) is connected with an output end of the first operational amplifier (OP1), a second end is connected with a first end (CH+) of the controller (300), and a third end is connected with the relay controller (31); the relay controller (31) is further connected with the FPGA processor (10); the relay controller (31) is used for receiving the mode selection signal and changing the output mode of the relay (K1) based on the mode selection signal; when the output mode is the voltage mode, the first end and the second end of the relay (K1) are turned on, so that the signal processing module (40) outputs the target analog voltage to the first end (CH+) of the controller (300); when the output mode is the current mode, the first end and the second end of the relay (K1) are connected with the signal conversion module (50) respectively, so that the signal processing module (40) outputs the target analog voltage to the signal conversion module (50), and the signal conversion module (50) outputs the generated target current to the second end (CH-) of the controller (300).

6. The wheel speed signal simulation apparatus of claim 5, wherein, The relay controller (31) comprises a second switch tube (Q2) and a third resistor (R3); a first end of the third resistor (R3) is connected with the FPGA processor (10), and a second end is connected with a control end of the second switch tube (Q2); a first end of the second switch tube (Q2) is connected with a third end of the relay (K1), and a second end is grounded; under the action of the mode selection signal, if the second switch tube (Q2) is turned on, the output mode is the voltage mode, and if the second switch tube (Q2) is cut off, the output mode is the current mode.

7. The wheel speed signal simulation apparatus of claim 6, wherein, The signal conversion module (50) comprises a second operational amplifier (OP2), a first switch tube (Q1), and a fourth resistor (R4); the second operational amplifier (OP2) is configured to control the conduction or cut-off of the first switch tube (Q1) based on the target analog voltage; when the output mode is the current mode, a first input end of the second operational amplifier (OP2) is connected with a first end of the relay (K1), a second input end is respectively connected with a first end of the first switch tube (Q1) and a first end of the fourth resistor (R4), and an output end is connected with a control end of the first switch tube (Q1); a second end of the first switch tube (Q1) is connected with a first end (CH+) of the controller (300), and a second end of the fourth resistor (R4) is grounded; the second operational amplifier (OP2) is configured to control the conduction or cut-off of the first switch tube (Q1) based on the target analog voltage.

8. The wheel speed signal simulation device of claim 7, wherein, A second end of the fourth resistor (R4) is also connected with a second end (CH-) of the controller (300); when the output mode is the current mode, the first switch tube (Q1) is conducted, and the first switch tube (Q1) and the fourth resistor (R4) form a current loop of the target current with the controller (300), so that the controller (300) takes the target current as the target simulation signal.

9. The wheel speed signal simulation apparatus of claim 7, wherein, The signal conversion module (50) further comprises a first diode (D1), a fifth resistor (R5), and a sixth resistor (R6); a first end of the first diode (D1) is connected with the first end (CH+) of the controller (300), and a second end is connected with a second end of the first switch tube (Q1); a second end of the fifth resistor (R5) is connected with a first input end of the second operational amplifier (OP2); a first end of the sixth resistor (R6) is connected with a second end of the fifth resistor (R5), and a second end is grounded; when the output mode is the current mode, a first end of the fifth resistor (R5) is connected with a first end of the relay (K1).

10. A semi-physical simulation test system, characterized in that, The wheel speed signal simulation device comprises: a host computer (200), a controller (300), and the wheel speed signal simulation device according to any one of claims 1 to 9.

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