Current mode band-gap reference circuit with starting circuit

Abstract

The utility model relates to the field of power electronics, in particular to a current mode band-gap reference circuit with a starting circuit. The current mode band-gap reference circuit with the starting circuit comprises a band-gap reference unit which is configured to output reference voltage according to driving current; and the starting unit is connected with the band-gap reference unit and is configured to control the band-gap reference unit to generate the driving current until the reference voltage is output when the band-gap reference unit does not output the reference voltage. According to the current mode band-gap reference circuit with the starting circuit, the starting circuit is simple, the power supply ripple suppression performance is good, and reference voltage output is stable.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, in particular to a current mode bandgap reference circuit with a starting circuit. BACKGROUND

[0002] In integrated circuit design, the bandgap reference as the most important basic module in analog circuit system, whether it can work properly is particularly important. In order to avoid the current mode bandgap reference circuit into the degenerate state of zero current during power on, generally need to add starting circuit. The starting time of bandgap reference greatly affects the response speed of the whole chip system, so the starting circuit should make the bandgap reference quickly establish.

[0003] The current mode bandgap reference circuit in the prior art has complex structure, and the working state of the matched starting circuit is complex, which is inconvenient to start. On the other hand, there is usually a deviation voltage in the current mode bandgap reference circuit, which affects the reference voltage, resulting in unstable reference voltage. SUMMARY

[0004] In order to solve the problems in the prior art, the purpose of the present application is to provide a current mode bandgap reference circuit with a starting circuit, which has simple starting circuit, good power ripple suppression performance and stable reference voltage output.

[0005] To achieve the above purpose, the present application provides a current mode bandgap reference circuit with a starting circuit, comprising:

[0006] A bandgap reference unit configured to output a reference voltage according to a driving current;

[0007] A starting unit connected with the bandgap reference unit and configured to control the bandgap reference unit to generate a driving current until the reference voltage is output when the bandgap reference unit has no reference voltage output, comprising:

[0008] An inverter, the input end of which is connected with the reference voltage output end of the bandgap reference unit, and the output end of which is connected with the gate of the first N-type transistor;

[0009] A first P-type transistor, the gate of which is connected with the input end of the inverter, the source of which is connected with the first power voltage end, and the drain of which is connected with the drain of the first N-type transistor through the fifth resistor, and the drain is configured as an output end;

[0010] A first N-type transistor, the source of which is connected with the second power voltage end.

[0011] Further, the bandgap reference unit comprises:

[0012] An operational amplifier unit, the output end of which is connected with the drain of the first P-type transistor, and the two input ends of which are connected with the bandgap reference source core unit,

[0013] A bandgap reference source core unit is connected to the output terminal of the operational amplifier unit, and is configured to generate a driving current according to the voltage at the output terminal of the operational amplifier unit, and output a reference voltage.

[0014] Further, the bandgap reference source core unit comprises a common-source common-gate current mirror structure connected to the output terminal of the operational amplifier unit, and is configured to generate and copy the driving current according to the voltage at the output terminal of the operational amplifier unit.

[0015] Further, the bandgap reference unit further comprises:

[0016] A bias unit configured to provide bias for the common-source common-gate current mirror structure.

[0017] Further, the bandgap reference source core unit comprises:

[0018] A second P-type transistor, the source of which is connected to the first power supply voltage terminal, the gate of which is connected to the gate of the third P-type transistor and the output terminal of the operational amplifier unit, and the drain of which is connected to the source of the fourth P-type transistor;

[0019] A third P-type transistor, the source of which is connected to the first power supply voltage terminal, the gate of which is connected to the output terminal of the operational amplifier unit, and the drain of which is connected to the source of the fifth P-type transistor;

[0020] A fourth P-type transistor, the gate of which is connected to the gate of the fifth P-type transistor, and the drain of which is connected to the emitter of the first transistor and the inverting input terminal of the operational amplifier unit;

[0021] A fifth P-type transistor, the drain of which is connected to the non-inverting input terminal of the operational amplifier unit;

[0022] A sixth P-type transistor, the source of which is connected to the first power supply voltage terminal, the gate of which is connected to the gate of the third P-type transistor, and the drain of which is connected to the source of the seventh P-type transistor;

[0023] A seventh P-type transistor, the gate of which is connected to the gate of the fifth P-type transistor, and the drain of which is connected to the second power supply voltage terminal through a fourth resistor and configured as a reference voltage output terminal;

[0024] A first transistor, the collector and base of which are connected to the second power supply voltage terminal;

[0025] A first resistor is arranged between the emitter of the first transistor and the second power supply voltage terminal;

[0026] A second transistor, the collector and base of which are connected to the second power supply voltage terminal;

[0027] A second resistor is arranged between the drain of the fourth P-type transistor and the second power supply voltage terminal;

[0028] The second P-type transistor, the third P-type transistor, the fourth P-type transistor, the fifth P-type transistor, the sixth P-type transistor and the seventh P-type transistor constitute the current mirror structure of the common source and the common gate.

[0029] Further, the biasing unit comprises:

[0030] The eighth P-type transistor has a source connected to the first power supply voltage terminal, a gate connected to the gate of the seventh P-type transistor, and a drain connected to the gate.

[0031] The ninth P-type transistor has a source connected to the first power supply voltage terminal, a gate connected to the gate of the sixth P-type transistor, and a drain connected to the drain of the third N-type transistor.

[0032] The second N-type transistor has a drain connected to the drain of the eighth P-type transistor, a source connected to the second power supply voltage terminal, and a gate connected to the gate of the third N-type transistor.

[0033] The third N-type transistor has a drain connected to the gate, and a source connected to the second power supply voltage terminal.

[0034] Further, the operational amplifier unit comprises:

[0035] The tenth P-type transistor has a source connected to the first power supply voltage terminal, a gate connected to the gate of the eleventh P-type transistor, and a drain connected to the gate and configured as an output terminal of the operational amplifier unit.

[0036] The eleventh P-type transistor has a source connected to the first power supply voltage terminal, and a drain connected to the source of the twelfth P-type transistor.

[0037] The twelfth P-type transistor has a source connected to the source of the thirteenth P-type transistor, a drain connected to the drain of the eighth N-type transistor, and a gate configured as a non-inverting input terminal of the operational amplifier unit.

[0038] The thirteenth P-type transistor has a drain connected to the drain of the ninth N-type transistor, and a gate configured as an inverting input terminal of the operational amplifier unit.

[0039] The fourteenth P-type transistor has a source connected to the first power supply voltage terminal, a gate connected to the gate of the fifteenth P-type transistor, and a drain connected to the gate.

[0040] The fifteenth P-type transistor has a source connected to the first power supply voltage terminal, a drain connected to the drain of the seventh N-type transistor and the drain of the tenth P-type transistor.

[0041] The fourth N-type transistor has a drain connected to the drain of the tenth P-type transistor, a gate connected to the drain and the gate of the seventh N-type transistor, and a source connected to the drain of the fifth N-type transistor.

[0042] The fifth N-type transistor has a drain connected to a gate, a gate connected to a gate of the eighth N-type transistor, and a source connected to the second power voltage terminal;

[0043] The sixth N-type transistor has a drain connected to a drain of the fourteenth P-type transistor, a source connected to a drain of the eighth N-type transistor, and a gate connected to a gate of the seventh N-type transistor;

[0044] The seventh N-type transistor has a source connected to a drain of the ninth N-type transistor;

[0045] The eighth N-type transistor has a source connected to the second power voltage terminal, and a gate connected to a gate of the ninth N-type transistor;

[0046] The ninth N-type transistor has a source connected to the second power voltage terminal

[0047] Compared with the prior art, the current mode bandgap reference circuit with a starting circuit according to the present application has the following beneficial effects:

[0048] The current mode bandgap reference circuit with a starting circuit according to the present application takes whether the reference voltage exists or not as a starting signal of the starting circuit, and then controls the bandgap reference unit to generate a driving current, and then outputs a stable reference voltage. After the starting is completed, the starting circuit can be automatically turned off, and the starting process is convenient, efficient and energy-saving.

[0049] The current mode bandgap reference circuit with a starting circuit according to the present application uses a common-source common-gate structure in the bandgap reference source core unit, effectively improves the power ripple suppression performance of the reference voltage, and makes the reference voltage output more stable.

[0050] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0051] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, and together with the embodiments of the present application, serve to explain the present application, and do not constitute a limitation of the present application. In the drawings:

[0052] Figure 1 FIG. 1 is a structure schematic diagram of the current mode bandgap reference circuit with a starting circuit according to Embodiment 1 of the present application; DETAILED DESCRIPTION

[0053] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be carried out in various forms and should not be construed as limited to the embodiments set forth herein, provided that the essence of the present application is maintained. It is understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.

[0054] It is understood that each of the steps recited in the method embodiments of the present application can be performed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit performing the steps shown. The scope of the present application is not limited in this respect.

[0055] The term "comprising" and variations thereof as used herein are open-ended, that is, "comprising but not limited to." The term "based on" is "based, at least in part, on." The term "one embodiment" means "at least one embodiment." The term "another embodiment" means "at least one additional embodiment." The term "some embodiments" means "at least some embodiments." Related terms are defined below in the description of the application.

[0056] It is noted that the terms "a" or "an", as used herein, are defined as "one or more" and can be used interchangeably with the phrase "one or more." The term "or" as used herein is defined as "and / or", unless otherwise indicated.

[0057] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be carried out in various forms and should not be construed as limited to the embodiments set forth herein, provided that the essence of the present application is maintained. It is understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.

[0058] Embodiment 1

[0059] In one embodiment of the present application, a current mode bandgap reference circuit with start-up circuit is provided to conveniently and efficiently generate a stable reference voltage.

[0060] Figure 1 A structural schematic diagram of the current mode bandgap reference circuit with start-up circuit of Embodiment 1 of the present application is shown in Figure 1 The current mode bandgap reference circuit with start-up circuit of the present application includes:

[0061] The bandgap reference unit 200 is configured to output a reference voltage according to a driving current;

[0062] The start-up unit 100 is connected with the bandgap reference unit 200 and is configured to control the bandgap reference unit 200 to generate a driving current until the reference voltage is output when the bandgap reference unit 200 has no reference voltage output.

[0063] In the present embodiment, the start-up unit 100 includes:

[0064] a first P-type transistor MP1, a gate of which is connected with the input terminal of the inverter D1, a source of which is connected with the first power voltage terminal vdda, and a drain of which is connected with the drain of the first N-type transistor MN1 through the fifth resistor R5, and the drain is configured as an output terminal;

[0065] a first P-type transistor MP1, a gate of which is connected with the input terminal of the inverter D1, a source of which is connected with the first power voltage terminal vdda, and a drain of which is connected with the drain of the first N-type transistor MN1 through the fifth resistor R5, and the drain is configured as an output terminal;

[0066] a first N-type transistor MN1, a source of which is connected with the second power voltage terminal vssa.

[0067] In the embodiment, the bandgap reference unit 200 comprises:

[0068] an operational amplifier unit 202, an output terminal Vc of which is connected with the drain of the first P-type transistor MP1, and two input terminals of which are connected with the bandgap reference source core unit 201,

[0069] a bandgap reference source core unit 201, which is connected with the output terminal Vc of the operational amplifier unit 202, is configured to generate a driving current according to the voltage of the output terminal of the operational amplifier unit 202, and output a reference voltage, and comprises a common-source common-gate current mirror structure, which is connected with the output terminal Vc of the operational amplifier unit 202, is configured to generate and copy the driving current according to the voltage of the output terminal Vc of the operational amplifier unit 202;

[0070] a bias unit 203, which is configured to provide a bias for the common-source common-gate current mirror structure.

[0071] In the embodiment, the bandgap reference source core unit 201 comprises:

[0072] a second P-type transistor MP2, a source of which is connected with the first power voltage terminal vdda, a gate of which is connected with a gate of a third P-type transistor MP3, and a drain of which is connected with a source of a fourth P-type transistor MP4;

[0073] a third P-type transistor MP3, a source of which is connected with the first power voltage terminal vdda, a gate of which is connected with the output terminal Vc of the operational amplifier unit 202, and a drain of which is connected with a source of a fifth P-type transistor MP5;

[0074] a fourth P-type transistor MP4, a gate of which is connected with a gate of a fifth P-type transistor MP5, and a drain of which is connected with an emitter of a first transistor Q1;

[0075] a fifth P-type transistor MP5, a drain of which is connected with a positive input terminal Vp of the operational amplifier unit 202;

[0076] The sixth P-type transistor MP6 has a source connected to the first power supply voltage terminal vdda, a gate connected to the gate of the third P-type transistor MP3, and a drain connected to the source of the seventh P-type transistor MP7;

[0077] The seventh P-type transistor MP7 has a gate connected to the gate of the fifth P-type transistor MP5, and a drain connected to the second power supply voltage terminal vssa via the fourth resistor R4 and configured as a reference voltage output terminal vout.

[0078] The first transistor Q1 has a collector and a base connected to the second power supply voltage terminal vssa.

[0079] The first resistor R1 is arranged between the emitter of the first transistor Q1 and the second power supply voltage terminal vssa.

[0080] The second transistor Q2 has a collector and a base connected to the second power supply voltage terminal vssa.

[0081] The second resistor R2 is arranged between the drain of the fourth P-type transistor MP4 and the second power supply voltage terminal vssa.

[0082] It can be understood that the second P-type transistor MP2, the third P-type transistor MP3, the fourth P-type transistor MP4, the fifth P-type transistor MP5, the sixth P-type transistor MP6 and the seventh P-type transistor MP7 constitute a current mirror structure of common source and common gate.

[0083] In the embodiment, the biasing unit 203 comprises:

[0084] The eighth P-type transistor MP8 has a source connected to the first power supply voltage terminal vdda, a gate connected to the gate of the seventh P-type transistor MP7, and a drain connected to the gate.

[0085] The ninth P-type transistor MP9 has a source connected to the first power supply voltage terminal vdda, a gate connected to the gate of the sixth P-type transistor MP6, and a drain connected to the drain of the third N-type transistor MN3.

[0086] The second N-type transistor MN2 has a drain connected to the drain of the eighth P-type transistor MP8, a source connected to the second power supply voltage terminal vssa, and a gate connected to the gate of the third N-type transistor MN3.

[0087] The third N-type transistor MN3 has a drain connected to the gate, and a source connected to the second power supply voltage terminal vssa.

[0088] In some other embodiments, the biasing unit can also be implemented by other circuits capable of providing biasing for the above-mentioned current mirror.

[0089] In the embodiment, the current mirror circuit of the bandgap reference source core unit 201 is a cascode structure current mirror, which has the effect of improving the power supply ripple rejection of the bandgap reference circuit. The bias circuit of the cascode structure is generated by the bias unit 203 inside the bandgap reference unit 200, without the need for an external structure to generate bias.

[0090] In the embodiment, the operational amplifier unit 202 includes:

[0091] The tenth P-type transistor MP10 has a source connected to the first power supply voltage terminal vdda, a gate connected to the gate of the eleventh P-type transistor MP11, and a drain connected to the gate and configured as an output terminal Vc of the operational amplifier unit 202.

[0092] The eleventh P-type transistor MP11 has a source connected to the first power supply voltage terminal vdda and a drain connected to the source of the twelfth P-type transistor MP12.

[0093] The twelfth P-type transistor MP12 has a source connected to the source of the thirteenth P-type transistor MP13, a drain connected to the drain of the eighth N-type transistor M8, and a gate configured as a non-inverting input terminal Vp of the operational amplifier unit 202.

[0094] The thirteenth P-type transistor MP13 has a drain connected to the drain of the ninth N-type transistor MN9 and a gate configured as an inverting input terminal Vn of the operational amplifier unit 202.

[0095] The fourteenth P-type transistor MP14 has a source connected to the first power supply voltage terminal vdda, a gate connected to the gate of the fifteenth P-type transistor MP15, and a drain connected to the gate.

[0096] The fifteenth P-type transistor MP15 has a source connected to the first power supply voltage terminal vdda, a drain connected to the drain of the seventh N-type transistor MN7 and the drain of the tenth P-type transistor MP10.

[0097] The fourth N-type transistor MN4 has a drain connected to the drain of the tenth P-type transistor MP10, a gate connected to the drain and the gate of the seventh N-type transistor MN7, and a source connected to the drain of the fifth N-type transistor MN5.

[0098] The fifth N-type transistor MN5 has a drain connected to the gate, a gate connected to the gate of the eighth N-type transistor MN8, and a source connected to the second power supply voltage terminal vssa.

[0099] The sixth N-type transistor MN6 has a drain connected to the drain of the fourteenth P-type transistor MP14, a source connected to the drain of the eighth N-type transistor MN8, and a gate connected to the gate of the seventh N-type transistor MN7.

[0100] The seventh N-type transistor MN7 has a source connected to a drain of the ninth N-type transistor MN9.

[0101] The eighth N-type transistor MN8 has a source connected to the second power voltage terminal vssa and a gate connected to a gate of the ninth N-type transistor MN8.

[0102] The ninth N-type transistor MN9 has a source connected to the second power voltage terminal vssa.

[0103] In some other embodiments, the operational amplifier unit 202 can also be implemented in other structures.

[0104] In the embodiment, the current-mode bandgap reference circuit with start-up circuit can provide an output reference voltage of 800 mV when operating at a low power voltage of 1.2 V, and can be integrated in a receiver operating at a 1.2 V power supply, while having a low static power consumption.

[0105] The working process of the embodiment is as follows: when powered on, the reference voltage output terminal vout is 0 V, which means that there is no reference voltage output, at this time, the input of the inverter D1 of the start-up unit 100 is 0 V, and then the first P-type transistor MP1 and the first N-type transistor MN1 are opened, so that the output terminal Vc of the operational amplifier unit 300 is pulled to the same potential as the drain of the first P-type transistor MP1, and then the second P-type transistor MP2 and the third P-type transistor MP3 start to generate a driving current, until the first transistor Q1 and the second transistor Q2 are completely opened, and the reference voltage output terminal vout outputs a reference voltage, at this time, the voltage of the reference voltage output terminal vout is pulled up to the voltage of the drain of the seventh P-type transistor MP7, so that the inverter outputs a low potential, the first P-type transistor MP1 and the first N-type transistor MN1 are closed, and the start-up unit 100 stops.

[0106] The above description is only some embodiments of the present application and the explanation of the technical principles applied. Those skilled in the art should understand that the disclosure range involved in the present application is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features disclosed in the present application (but not limited to) having similar functions to form technical solutions.

[0107] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0108] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A current-mode bandgap reference circuit with start-up circuit, characterized by The application relates to a bandgap reference unit, comprising: a bandgap reference unit configured to output a reference voltage according to a driving current; a starting unit connected with the bandgap reference unit and configured to control the bandgap reference unit to generate the driving current until the reference voltage is output when the bandgap reference unit has no reference voltage output, comprising: an inverter, an input end of which is connected with a reference voltage output end of the bandgap reference unit, and an output end of which is connected with a gate of a first N-type transistor; a first P-type transistor, a gate of which is connected with an input end of the inverter, a source of which is connected with a first power voltage end, and a drain of which is connected with a drain of the first N-type transistor through a fifth resistor and is configured as an output end; a first N-type transistor, a source of which is connected with a second power voltage end.

2. The current-mode bandgap reference circuit with start-up circuit of claim 1, wherein, The bandgap reference unit comprises: an operational amplifier unit, an output end of which is connected with the drain of the first P-type transistor, and two input ends of which are connected with a bandgap reference source core unit, the bandgap reference source core unit, which is connected with the output end of the operational amplifier unit, is used for generating the driving current according to the voltage of the output end of the operational amplifier unit and outputting the reference voltage.

3. The current-mode bandgap reference circuit with start-up circuit of claim 2, wherein, The bandgap reference source core unit comprises a common-source common-gate current mirror structure, which is connected with the output end of the operational amplifier unit and is used for generating and copying the driving current according to the voltage of the output end of the operational amplifier unit.

4. The current-mode bandgap reference circuit with start-up circuit of claim 3, wherein, The bandgap reference unit further comprises: a bias unit used for providing bias for the common-source common-gate current mirror structure.

5. The current-mode bandgap reference circuit with start-up circuit of claim 3, wherein, The bandgap reference source core unit comprises: a second P-type transistor, a source of which is connected with the first power voltage end, a gate of which is connected with a gate of a third P-type transistor and an output end of the operational amplifier unit, and a drain of which is connected with a source of a fourth P-type transistor; the third P-type transistor, a source of which is connected with the first power voltage end, a gate of which is connected with the output end of the operational amplifier unit, and a drain of which is connected with a source of a fifth P-type transistor; the fourth P-type transistor, a gate of which is connected with a gate of the fifth P-type transistor, a drain of which is connected with an emitter of a first transistor and an inverting input end of the operational amplifier unit; the fifth P-type transistor, a drain of which is connected with a non-inverting input end of the operational amplifier unit; the sixth P-type transistor, a source of which is connected with the first power voltage end, a gate of which is connected with the gate of the third P-type transistor, and a drain of which is connected with a source of a seventh P-type transistor; the seventh P-type transistor, a gate of which is connected with the gate of the fifth P-type transistor, and a drain of which is connected with the second power voltage end through a fourth resistor and is configured as the reference voltage output end; the first transistor, a collector and a base of which are connected with the second power voltage end; the first resistor, which is arranged between the emitter of the first transistor and the second power voltage end; the second transistor, a collector and a base of which are connected with the second power voltage end; the second resistor, which is arranged between the drain of the fourth P-type transistor and the second power voltage end; wherein the second P-type transistor, the third P-type transistor, the fourth P-type transistor, the fifth P-type transistor, the sixth P-type transistor and the seventh P-type transistor constitute the common-source common-gate current mirror structure.

6. The current-mode bandgap reference circuit with start-up circuit of claim 4, wherein, The bias unit comprises: an eighth P-type transistor, a source of which is connected with the first power voltage end, a gate of which is connected with the gate of the seventh P-type transistor, and a drain of which is connected with the gate. a ninth P-type transistor, a source connected to the first power supply voltage terminal, a gate connected to a gate of the sixth P-type transistor, and a drain connected to a drain of the third N-type transistor; a second N-type transistor, a drain connected to a drain of the eighth P-type transistor, a source connected to the second power supply voltage terminal, and a gate connected to a gate of the third N-type transistor; a third N-type transistor, a drain connected to a gate, a source connected to the second power supply voltage terminal.

7. The current-mode bandgap reference circuit with start-up circuit of claim 2, wherein, The operational amplifier unit comprises: a tenth P-type transistor, a source connected to the first power supply voltage terminal, a gate connected to a gate of the eleventh P-type transistor, and a drain connected to the gate and configured as an output terminal of the operational amplifier unit; an eleventh P-type transistor, a source connected to the first power supply voltage terminal, and a drain connected to a source of the twelfth P-type transistor; a twelfth P-type transistor, a source connected to a source of the thirteenth P-type transistor, a drain connected to a drain of the eighth N-type transistor, and a gate configured as a non-inverting input terminal of the operational amplifier unit; a thirteenth P-type transistor, a drain connected to a drain of the ninth N-type transistor, and a gate configured as an inverting input terminal of the operational amplifier unit; a fourteenth P-type transistor, a source connected to the first power supply voltage terminal, a gate connected to a gate of the fifteenth P-type transistor, and a drain connected to the gate; a fifteenth P-type transistor, a source connected to the first power supply voltage terminal, a drain connected to a drain of the seventh N-type transistor and a drain of the tenth P-type transistor; a fourth N-type transistor, a drain connected to the drain of the tenth P-type transistor, a gate connected to the drain and to a gate of the seventh N-type transistor, and a source connected to a drain of the fifth N-type transistor; a fifth N-type transistor, a drain connected to a gate, a gate connected to a gate of the eighth N-type transistor, and a source connected to the second power supply voltage terminal; a sixth N-type transistor, a drain connected to a drain of the fourteenth P-type transistor, a source connected to a drain of the eighth N-type transistor, and a gate connected to a gate of the seventh N-type transistor; a seventh N-type transistor, a source connected to a drain of the ninth N-type transistor; an eighth N-type transistor, a source connected to the second power supply voltage terminal, a gate connected to a gate of the ninth N-type transistor; a ninth N-type transistor, a source connected to the second power supply voltage terminal.

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