Signal processing circuit and electronic equipment

Abstract

The utility model discloses a signal processing circuit and electronic equipment. The signal processing circuit comprises a signal receiving branch, a signal synthesis and amplification branch, a frequency division branch, a first signal processing branch, a second signal processing branch and a signal transmission branch. The signal receiving branch is used for receiving satellite signals. The signal synthesis and amplification branch is used for combining and amplifying a plurality of satellite signals received by the plurality of receiving antennas, and outputting a first signal. The frequency division branch is used for dividing the first signal into a second signal and a third signal and outputting the second signal and the third signal. The first signal processing branch is used for amplifying and filtering the second signal and outputting a fourth signal. And the second signal processing branch is used for amplifying and outputting the third signal and outputting a fifth signal. And the signal transmission branch is used for generating a sixth signal based on the combination of the fourth signal and the fifth signal and outputting the sixth signal to an external circuit. In this way, high-precision positioning can be achieved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronic circuit, in particular to a signal processing circuit and electronic equipment. BACKGROUND

[0002] In recent years, vehicle-mounted multimedia host and T-BOX (Telematics Box) are widely popularized in automobiles. Among them, a receiving antenna is also arranged on the automobile, which receives satellite signals and inputs them to the vehicle-mounted multimedia host and T-BOX (Telematics Box) after amplification and other processing, so as to realize positioning and other functions.

[0003] However, the current road network is becoming more and more complex, and the safety requirements of automobile driving are becoming higher and higher, that is, the requirements of automobile for high-precision positioning are also becoming higher and higher. However, the frequency range of the satellite signals received and processed by the receiving antenna is relatively small at present, resulting in low positioning accuracy. CONTENT OF THE UTILITY MODEL

[0004] Embodiments of the present application provide a signal processing circuit and electronic equipment, which can realize high-precision positioning.

[0005] In a first aspect, the embodiments of the present application provide a signal processing circuit, comprising: a signal receiving branch comprising a plurality of receiving antennas, configured to receive satellite signals; a signal synthesis and amplification branch connected with the signal receiving branch, configured to amplify the plurality of satellite signals received by the plurality of receiving antennas after being combined, and output a first signal; a frequency division branch connected with the signal synthesis and amplification branch, configured to divide the first signal into a second signal and a third signal and output, wherein the frequency band of the second signal is different from the frequency band of the third signal, and the sum of the frequency band of the second signal and the frequency band of the third signal is the frequency band of the first signal; a first signal processing branch connected with the frequency division branch, configured to amplify and filter the second signal, and output a fourth signal; a second signal processing branch connected with the frequency division branch, configured to amplify and output the third signal, and output a fifth signal; and a signal transmission branch connected with an external circuit, the first signal processing branch and the second signal processing branch respectively, configured to generate a sixth signal based on the combination of the fourth signal and the fifth signal, and output to the external circuit.

[0006] In one or more embodiments, the signal processing circuit further comprises a voltage conversion branch; the voltage conversion branch is connected with the external signal, the signal synthesis and amplification branch, the first signal processing branch and the second signal processing branch respectively, configured to receive a voltage signal output by the external circuit, and output a power supply voltage based on the voltage signal, so as to supply power for the signal synthesis and amplification branch, the first signal processing branch and the second signal processing branch.

[0007] In one or more embodiments, the plurality of receiving antennas comprises a first receiving antenna, a second receiving antenna, a third receiving antenna, a fourth receiving antenna, a fifth receiving antenna, a sixth receiving antenna, a seventh receiving antenna and an eighth receiving antenna, the receiving antennas are FPC antennas, the signal receiving branch further comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor; the first receiving antenna is connected with a first end of the first capacitor, the second receiving antenna, a first end of the second capacitor and the signal synthesis and amplification branch respectively, the third receiving antenna is connected with a first end of the third capacitor, the fourth receiving antenna, a first end of the fourth capacitor and the signal synthesis and amplification branch respectively, the fifth receiving antenna is connected with a first end of the fifth capacitor, the sixth receiving antenna, a first end of the sixth capacitor and the signal synthesis and amplification branch respectively, the seventh receiving antenna is connected with a first end of the seventh capacitor, the eighth receiving antenna, a first end of the eighth capacitor and the signal synthesis and amplification branch respectively, and second ends of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor and the eighth capacitor are grounded.

[0008] In one or more embodiments, the signal synthesis and amplification branch comprises a first hybrid coupler, a second hybrid coupler, a third hybrid coupler, a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a first inductor and a second inductor; first and second input ends of the first hybrid coupler and first and second input ends of the second hybrid coupler are connected with the signal receiving branch, the first input end of the first hybrid coupler is connected with the first input end of the third hybrid coupler, the first input end of the second hybrid coupler is connected with the second input end of the third hybrid coupler, the second output end of the first hybrid coupler is grounded through the first resistor, the second input end of the second hybrid coupler is grounded through the second resistor, the second output end of the third hybrid coupler is grounded through the third resistor, the first output end of the third hybrid coupler is connected with an input end of the first amplifier in sequence through the ninth capacitor and the first inductor, an output end of the first amplifier is connected with a first end of the second inductor, a first end of the eleventh capacitor and the frequency division branch respectively, a second end of the second inductor is connected with a first end of the fourth resistor and a first end of the tenth capacitor respectively, second ends of the tenth capacitor and the eleventh capacitor are grounded, and a second end of the fourth resistor is connected with the voltage conversion branch.

[0009] In one or more embodiments, the frequency dividing branch includes a twelfth capacitor, a thirteenth capacitor, a third inductor, and a fifth resistor; a first end of the twelfth capacitor is connected with the signal synthesizing and amplifying branch, a second end of the twelfth capacitor is connected with a first end of the thirteenth capacitor and a first end of the third inductor respectively, a second end of the third inductor is connected with the second signal processing branch through the fifth resistor, and a second end of the thirteenth capacitor is connected with the first signal processing branch.

[0010] In one or more embodiments, the first signal processing branch includes a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a sixth resistor, a second amplifier, and a first filter; a first end of the fourth inductor is connected with a first end of the fifteenth capacitor and the frequency dividing branch respectively, a second end of the fourth inductor is grounded through the fourteenth capacitor, a second end of the fifteenth capacitor is connected with an output end of the second amplifier through the fifth inductor, power supply ends of the second amplifier are connected with a first end of the sixth inductor and a first end of the sixteenth capacitor respectively, a second end of the sixteenth capacitor is grounded, a second end of the sixth inductor is connected with the voltage converting branch, the output end of the second amplifier is connected with an input end of the first filter through the seventeenth capacitor, the eighteenth capacitor is connected between the input end of the first filter and ground, an output end of the first filter is connected with a first end of the seventh inductor and a first end of the eighth inductor respectively, a second end of the seventh inductor is grounded through the sixth resistor, and a second end of the eighth inductor is connected with the second signal processing branch and the signal transmission branch respectively.

[0011] In one or more embodiments, the second signal processing branch includes a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a ninth inductor, a tenth inductor, an eleventh inductor, a twelfth inductor, a seventh resistor, a third amplifier, and a second filter; a first end of the ninth inductor is connected to a first end of the twentieth capacitor and the frequency division branch, respectively, a second end of the ninth inductor is grounded through the nineteenth capacitor, a second end of the twentieth capacitor is connected to an input end of the third amplifier through the tenth inductor, a power supply end of the third amplifier is connected to the voltage conversion branch through the eleventh inductor, the twenty-third capacitor is connected between the power supply end of the third amplifier and the ground, an output end of the third amplifier is connected to an input end of the second filter through the twenty-first capacitor, the twenty-second capacitor is connected between the input end of the second filter and the ground, an output end of the second filter is connected to a first end of the twenty-fourth capacitor and a first end of the twelfth inductor, respectively, a second end of the twelfth inductor is grounded through the seventh resistor, and a second end of the twenty-fourth capacitor is connected to the first signal processing branch and the signal transmission branch, respectively.

[0012] In one or more embodiments, the signal transmission branch includes a twenty-fifth capacitor, a twenty-sixth capacitor, a thirteenth inductor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and an electrostatic protection diode; a first end of the twenty-fifth capacitor is connected to the first signal processing branch and the second signal processing branch, respectively, a second end of the twenty-fifth capacitor is connected to a first end of the thirteenth inductor, a first end of the ninth resistor, and a first end of the tenth resistor, respectively, a second end of the tenth resistor is connected to a first end of the eleventh resistor and a first end of the twenty-sixth capacitor, respectively, a second end of the twenty-sixth capacitor is connected to a first end of the electrostatic protection diode, the voltage conversion branch, and the external circuit, respectively, and a second end of the thirteenth inductor, a second end of the ninth resistor, a second end of the eleventh resistor, and a second end of the electrostatic protection diode are all grounded.

[0013] In one or more embodiments, the voltage conversion branch comprises a fourteenth inductor, a twenty-seventh capacitor, a twenty-eighth capacitor, a twenty-ninth capacitor, a thirtieth capacitor, a twelfth resistor and a linear voltage regulator; a first end of the fourteenth inductor is connected with the signal transmission branch and the external circuit respectively, a second end of the fourteenth inductor is connected with an input end of the linear voltage regulator through the twelfth resistor, the twenty-seventh capacitor is connected between the input end of the linear voltage regulator and the ground, the twenty-seventh capacitor is connected with the twenty-eighth capacitor in parallel, the twenty-ninth capacitor is connected between an output end of the linear voltage regulator and the ground, the thirtieth capacitor is connected with the twenty-ninth capacitor in parallel, and the output end of the linear voltage regulator is connected with the signal synthesis and amplification branch, the first signal processing branch and the second signal processing branch respectively.

[0014] In a second aspect, the embodiments of the present application provide an electronic device comprising the signal processing circuit as described above.

[0015] The signal processing circuit of the embodiments of the present application comprises a signal receiving branch, a signal synthesis and amplification branch, a frequency division branch, a first signal processing branch, a second signal processing branch and a signal transmission branch. The signal receiving branch comprises a plurality of receiving antennas, and is configured to receive satellite signals. The signal synthesis and amplification branch is connected with the signal receiving branch, and is configured to amplify the plurality of satellite signals received by the plurality of receiving antennas after the plurality of satellite signals are combined, and output a first signal. The frequency division branch is connected with the signal synthesis and amplification branch, and is configured to divide the first signal into a second signal and a third signal and output the second signal and the third signal, wherein the frequency band of the second signal is different from the frequency band of the third signal, and the sum of the frequency band of the second signal and the frequency band of the third signal is the frequency band of the first signal. The first signal processing branch is connected with the frequency division branch, and is configured to amplify and filter the second signal, and output a fourth signal. The second signal processing branch is connected with the frequency division branch, and is configured to amplify and output the third signal, and output a fifth signal. The signal transmission branch is connected with an external circuit, the first signal processing branch and the second signal processing branch respectively, and is configured to generate a sixth signal based on the combination of the fourth signal and the fifth signal, and output the sixth signal to the external circuit. Through the above process, a plurality of frequency bands of satellite signals are received according to the plurality of receiving antennas, and subsequent signal processing is performed, so that the plurality of frequency bands of satellite signals can be used simultaneously, errors caused by atmospheric effects and the like can be significantly reduced, and positioning accuracy can be effectively improved, that is, high-precision positioning is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the embodiments described. These embodiments are described in connection with their respective figures to provide an understanding of the embodiments. The appearances of the reference numerals in the figures indicate the presence of these elements in the embodiments and variations understood to be within the scope of the embodiments as described herein.

[0017] Figure 1 is a schematic diagram of a composition block diagram of a signal processing circuit provided by an embodiment of the present application Figure 1 ;

[0018] Figure 2 is a schematic diagram of a composition block diagram of a signal processing circuit provided by an embodiment of the present application Figure 2 ;

[0019] Figure 3 is a schematic diagram of a circuit structure of a signal receiving branch and a signal synthesis and amplification branch provided by an embodiment of the present application

[0020] Figure 4 is a schematic diagram of a circuit structure of a frequency dividing branch, a first signal processing branch and a second signal processing branch provided by an embodiment of the present application

[0021] Figure 5 is a schematic diagram of a circuit structure of a signal transmission branch and a voltage conversion branch provided by an embodiment of the present application DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and in detail below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0023] It should be noted that when an element is described as "connected to" another element, it can be directly connected to the other element or one or more intermediate elements can be present between them.

[0024] In addition, the technical features involved in each of the embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0025] Reference will be made to Figure 1 , Figure 1 is a schematic diagram of a composition block diagram of a signal processing circuit provided by an embodiment of the present application. As shown in Figure 1 , the signal processing circuit 100 includes a signal receiving branch 10, a signal synthesis and amplification branch 20, a frequency dividing branch 30, a first signal processing branch 40, a second signal processing branch 50 and a signal transmission branch 60.

[0026] The signal receiving branch 10 includes a plurality of receiving antennas, including a first receiving antenna P1, a second receiving antenna P2, and an Nth receiving antenna PN, where N is an integer greater than 1. The signal synthesizing and amplifying branch 20 is connected to the signal receiving branch 10. The frequency dividing branch 30 is connected to the signal synthesizing and amplifying branch 20. The first signal processing branch 40 is connected to the frequency dividing branch 30. The second signal processing branch 50 is connected to the frequency dividing branch 30. The signal transmission branch 60 is connected to the external circuit 200, the first signal processing branch 40, and the second signal processing branch 50, respectively.

[0027] Specifically, the signal receiving branch 10 is configured to receive satellite signals. The signal synthesizing and amplifying branch 20 is configured to combine and amplify the plurality of satellite signals received by the plurality of receiving antennas and output a first signal. The frequency dividing branch 30 is configured to divide the first signal into a second signal and a third signal and output the second signal and the third signal, where the frequency band of the second signal is different from the frequency band of the third signal, and the sum of the frequency band of the second signal and the frequency band of the third signal is the frequency band of the first signal. The first signal processing branch 40 is configured to amplify and filter the second signal and output a fourth signal. The second signal processing branch 50 is configured to amplify and output the third signal and output a fifth signal. The signal transmission branch 60 is configured to generate a sixth signal based on the combination of the fourth signal and the fifth signal and output the sixth signal to the external circuit 200.

[0028] In summary, according to the plurality of receiving antennas receiving a plurality of frequency bands of satellite signals, and through subsequent signal processing, the simultaneous use of a plurality of frequency bands of satellite signals is achieved, which can significantly reduce errors caused by atmospheric effects and the like, thereby effectively improving the positioning accuracy, i.e., achieving high-precision positioning.

[0029] As is known, GPS and Beidou (BDS) are two different global navigation satellite systems (GNSS), each of which uses a specific frequency band to transmit signals, where the frequency range of the L1 frequency band of the GPS frequency band is 1565.19 MHz to 1585.65 MHz; the frequency range of the L5 frequency band of the GPS frequency band is 1163.95 MHz to 1188.95 MHz; the frequency range of the B1 frequency band of the Beidou frequency band is 1550.868 MHz to 1571.328 MHz; and the frequency range of the B2 frequency band of the Beidou frequency band is 1186.68 MHz to 1227.60 MHz. In a specific embodiment, the plurality of receiving antennas receive satellite signals of the L1 frequency band of the GPS frequency band, the L5 frequency band of the GPS frequency band, the B1 frequency band of the Beidou frequency band, and the B2 frequency band of the Beidou frequency band, the frequency band of the second signal is 1164 MHz to 1228 MHz, and the frequency band of the third signal is 1550 MHz to 1586 MHz. Thus, the simultaneous use of a plurality of frequency bands of satellite signals is achieved, which is conducive to achieving high-precision positioning.

[0030] In some embodiments, the external circuit 200 is a vehicle-mounted multimedia host and a T-BOX, wherein the vehicle-mounted multimedia host generally refers to a multimedia entertainment system installed in a car, which integrates functions such as audio playback, video playback, navigation, Bluetooth connection, telephone connection, etc.; the T-BOX, i.e. the telematics box, is a data acquisition and transmission device specially designed for vehicles, and its main functions include but are not limited to: real-time monitoring of the location, speed, driving state, etc. of the vehicle; supporting remote diagnosis of vehicle faults; providing emergency rescue services; managing fleets, etc.

[0031] In some embodiments, as shown in Figure 2 , the signal processing circuit 100 further includes a voltage conversion branch 70.

[0032] The voltage conversion branch 70 is connected with the external circuit 200, the signal synthesis and amplification branch 20, the first signal processing branch 40 and the second signal processing branch 50, respectively. The voltage conversion branch 70 is used to receive the voltage signal output by the external circuit 200, and output a supply voltage based on the voltage signal, so as to supply power to the signal synthesis and amplification branch 20, the first signal processing branch 40 and the second signal processing branch 50.

[0033] Please refer to Figure 3 , Figure 3 The circuit structure schematic diagram of the signal receiving branch and the signal synthesis and amplification branch is exemplarily shown. As shown in Figure 3 , the plurality of receiving antennas include a first receiving antenna P1, a second receiving antenna P2, a third receiving antenna P3, a fourth receiving antenna P4, a fifth receiving antenna P5, a sixth receiving antenna P6, a seventh receiving antenna P7 and an eighth receiving antenna P8 (in this embodiment, N is taken as 8 as an example), and the receiving antennas are FPC antennas. The signal receiving branch 10 further includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8.

[0034] The first receiving antenna P1 is connected with the first end of the first capacitor C1, the second receiving antenna P2, the first end of the second capacitor C2 and the signal synthesis and amplification branch 20 respectively, the third receiving antenna P3 is connected with the first end of the third capacitor C3, the fourth receiving antenna P4, the first end of the fourth capacitor C4 and the signal synthesis and amplification branch 20 respectively, the fifth receiving antenna P5 is connected with the first end of the fifth capacitor C5, the sixth receiving antenna P6, the first end of the sixth capacitor C6 and the signal synthesis and amplification branch 20 respectively, the seventh receiving antenna P7 is connected with the first end of the seventh capacitor C7, the eighth receiving antenna P8, the first end of the eighth capacitor C8 and the signal synthesis and amplification branch 20 respectively, the second end of the first capacitor C1, the second end of the second capacitor C2, the second end of the third capacitor C3, the second end of the fourth capacitor C4, the second end of the fifth capacitor C5, the second end of the sixth capacitor C6, the second end of the seventh capacitor C7 and the second end of the eighth capacitor C8 are all grounded GND.

[0035] Specifically, by adopting the FPC antenna, the cost can be saved. And by the eight receiving antennas, the satellite signals of the full frequency band (the frequency range is 1164MHz to 1615MHz) can be received.

[0036] In some embodiments, the signal synthesis and amplification branch 20 includes a first hybrid coupler U1, a second hybrid coupler U2, a third hybrid coupler U3, a first amplifier U4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a first inductor L1 and a second inductor L2.

[0037] The first input end IN1 and the second input end IN2 of the first hybrid coupler U1, the first input end IN1 and the second input end IN2 of the second hybrid coupler U2 are connected with the signal receiving branch 10, the first input end IN1 of the first hybrid coupler U1 is connected with the first input end IN1 of the third hybrid coupler U3, the first input end IN1 of the second hybrid coupler U2 is connected with the second input end IN2 of the third hybrid coupler U3, the second output end IN2 of the first hybrid coupler U1 is grounded GND through the first resistor R1, the second input end IN2 of the second hybrid coupler U2 is grounded GND through the second resistor R2, the second output end IN2 of the third hybrid coupler U3 is grounded GND through the third resistor R3, the first output end IN1 of the third hybrid coupler U3 is connected with the input end RF-IN of the first amplifier U4 in turn through the ninth capacitor C9 and the first inductor L1, the output end RF-OUT of the first amplifier U4 is connected with the first end of the second inductor L2, the first end of the eleventh capacitor C11 and the frequency dividing branch 30 respectively, the second end of the second inductor L2 is connected with the first end of the fourth resistor R4 and the first end of the tenth capacitor C10 respectively, the second end of the tenth capacitor C10 and the second end of the eleventh capacitor C11 are grounded GND, and the second end of the fourth resistor R4 is connected with the voltage conversion branch 70.

[0038] Specifically, the first hybrid coupler U1 can combine the satellite signals received by the first receiving antenna P1, the second receiving antenna P2, the third receiving antenna P3 and the fourth receiving antenna P4; the second hybrid coupler U2 can combine the satellite signals received by the fifth receiving antenna P5, the sixth receiving antenna P6, the seventh receiving antenna P7 and the eighth receiving antenna P8; the third hybrid coupler U3 combines the signals output by the first hybrid coupler U1 and the signals output by the second hybrid coupler U2; the signals output by the third hybrid coupler U3 are amplified by the first amplifier U4 and output the first signal.

[0039] Please refer to Figure 4 , Figure 4 The circuit structure schematic diagrams of the frequency dividing branch 30, the first signal processing branch 40 and the second signal processing branch 50 are exemplarily shown. Figure 4 As shown in the drawings, the frequency dividing branch 30 includes the twelfth capacitor C12, the thirteenth capacitor C13, the third inductor L3 and the fifth resistor R5.

[0040] The first end of the twelfth capacitor C12 is connected with the signal combining and amplifying branch 20, i.e. the first end of the twelfth capacitor C12 is connected with the second output end IN2 of the third hybrid coupler U3, the second end of the twelfth capacitor C12 is connected with the first end of the third inductor L3, the second end of the third inductor L3 is connected with the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected with the first end of the second inductor L2. Figure 3The output end of the first amplifier U4 in the first signal processing branch 40 is connected with the output end of the first amplifier U4 in the second signal processing branch 50. The second end of the twelfth capacitor C12 is connected with the first end of the thirteenth capacitor C13 and the first end of the third inductor L3 respectively, the second end of the third inductor L3 is connected with the second signal processing branch 50 through the fifth resistor R5, and the second end of the thirteenth capacitor C13 is connected with the first signal processing branch 40.

[0041] Specifically, in some embodiments, the frequency band of the first signal is 1164MHz to 1615MHz, and the second signal after passing through the thirteenth capacitor C13 is 1164MHz to 1228MHz; the third signal after passing through the fifth resistor R5 is 1550MHz to 1586MHz.

[0042] In some embodiments, the first signal processing branch 40 includes a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, a sixth resistor R6, a second amplifier U5 and a first filter U6.

[0043] The first end of the fourth inductor L4 is connected with the first end of the fifteenth capacitor C15 and the frequency division branch 30 respectively, the second end of the fourth inductor L4 is grounded through the fourteenth capacitor C14, the second end of the fifteenth capacitor C15 is connected with the output end of the second amplifier U5 through the fifth inductor L5, the power supply end of the second amplifier U5 is connected with the first end of the sixth inductor L6 and the first end of the sixteenth capacitor C16 respectively, the second end of the sixteenth capacitor C16 is grounded, the second end of the sixth inductor L6 is connected with the voltage conversion branch 70, the output end of the second amplifier U5 is connected with the input end of the first filter U6 through the seventeenth capacitor C17, the eighteenth capacitor C18 is connected between the input end of the first filter U6 and the ground GND, the output end of the first filter U6 is connected with the first end of the seventh inductor L7 and the first end of the eighth inductor L8 respectively, the second end of the seventh inductor L7 is grounded through the sixth resistor R6, and the second end of the eighth inductor L8 is connected with the second signal processing branch 50 and the signal transmission branch 60 respectively.

[0044] Specifically, the second amplifier U5 is used to amplify the second signal, the first filter U6 is used to filter the signal output by the second amplifier U5, and the voltage conversion branch 70 supplies power to the second amplifier U5 through the sixth inductor L6.

[0045] In some embodiments, the second signal processing branch 50 comprises a nineteenth capacitor C19, a twentieth capacitor C20, a twenty-first capacitor C21, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a ninth inductor L9, a tenth inductor L10, an eleventh inductor L11, a twelfth inductor L12, a seventh resistor R7, a third amplifier U7, and a second filter U8.

[0046] The first end of the ninth inductor L9 is connected with the first end of the twentieth capacitor C20 and the frequency division branch 30, the second end of the ninth inductor L9 is grounded through the nineteenth capacitor C19, the second end of the twentieth capacitor C20 is connected with the input end of the third amplifier U7 through the tenth inductor L10, the power supply end of the third amplifier U7 is connected with the voltage conversion branch 70 through the eleventh inductor L11, the twenty-third capacitor C23 is connected between the power supply end of the third amplifier U7 and the ground GND, the output end of the third amplifier U7 is connected with the input end of the second filter U8 through the twenty-first capacitor C21, the twenty-second capacitor C22 is connected between the input end of the second filter U8 and the ground GND, the output end of the second filter U8 is connected with the first end of the twenty-fourth capacitor C24 and the first end of the twelfth inductor L12, the second end of the twelfth inductor L12 is grounded through the seventh resistor R7, and the second end of the twenty-fourth capacitor C24 is connected with the first signal processing branch 40 and the signal transmission branch 60.

[0047] Specifically, the third amplifier U7 is configured to amplify the third signal, the second filter U8 is configured to filter the signal output by the third amplifier U7, and the voltage conversion branch 70 supplies power to the third amplifier U7 through the eleventh inductor L11.

[0048] Please refer to Figure 5 , Figure 5 The signal transmission branch and the voltage conversion branch provided by the embodiments of the present application are shown in the circuit structure schematic diagram. Figure 5 As shown in the figure, the signal transmission branch 60 comprises a twenty-fifth capacitor C25, a twenty-sixth capacitor C26, a thirteenth inductor L13, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and an electrostatic protection diode D1.

[0049] Specifically, the first terminal of the 25th capacitor C25 is connected to the 8th inductor L8 in the first signal processing branch 40 and the 24th capacitor C24 in the second signal processing branch 50. The second terminal of the 25th capacitor C25 is connected to the first terminal of the 13th inductor L13, the first terminal of the 9th resistor R9, and the first terminal of the 10th resistor R10. The second terminal of the 10th resistor R10 is connected to the first terminal of the 11th resistor R11 and the first terminal of the 26th capacitor C26. The second terminal of the 26th capacitor C26 is connected to the first terminal of the electrostatic protection diode D1, the voltage conversion branch 70, and the external circuit 200. The second terminals of the 13th inductor L13, the 9th resistor R9, the 11th resistor R11, and the electrostatic protection diode D1 are all grounded to GND.

[0050] Specifically, the fourth signal output from the first signal processing branch 40 and the fifth signal output from the second signal processing branch 50 are superimposed and then pass through the signal transmission branch 60 to become the sixth signal, which is then input to the external circuit 200.

[0051] In some embodiments, the voltage conversion branch 70 includes a fourteenth inductor L14, a twenty-seventh capacitor C27, a twenty-eighth capacitor C28, a twenty-ninth capacitor C29, a thirtieth capacitor C30, a twelfth resistor R12, and a linear regulator U9.

[0052] The fourteenth inductor L14 is connected to the signal transmission branch 60 and the external circuit 200. The second end of the fourteenth inductor L14 is connected to the input of the linear regulator U9 through the twelfth resistor R12. The twenty-seventh capacitor C27 is connected between the input of the linear regulator U9 and ground GND. The twenty-seventh capacitor C27 and the twenty-eighth capacitor C28 are connected in parallel. The twenty-ninth capacitor C29 is connected between the output of the linear regulator U9 and ground GND. The thirtieth capacitor C30 is connected in parallel with the twenty-ninth capacitor C29. The output of the linear regulator U9 is connected to the signal synthesis and amplification branch 20, the first signal processing branch 40, and the second signal processing branch 50.

[0053] Specifically, the supply voltage output from the output terminal of the linear regulator U9 is obtained through, as follows: Figure 3 The fourth resistor R4 and the second inductor L2 shown power the first amplifier U4; the supply voltage output from the output terminal of the linear regulator U9 is supplied through... Figure 4 The sixth inductor L6 shown supplies power to the second amplifier U5; the supply voltage output from the output terminal of the linear regulator U9 is supplied through... Figure 4 The eleventh inductor L11 shown supplies power to the third amplifier U7.

[0054] This application also provides an electronic device, which includes the signal processing circuit 100 in any embodiment of this application.

[0055] The above merely describes the embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, which is made by using the content of the present application specification and drawings, is also included in the patent protection scope of the present application.

[0056] The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; the technical features between the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal processing circuit, characterized by comprising: The application relates to a signal processing circuit. The signal processing circuit comprises: a signal receiving branch comprising a plurality of receiving antennas for receiving satellite signals; a signal synthesizing and amplifying branch connected with the signal receiving branch, for synthesizing and amplifying the satellite signals received by the plurality of receiving antennas, and outputting a first signal; a frequency dividing branch connected with the signal synthesizing and amplifying branch, for dividing the first signal into a second signal and a third signal and outputting the second signal and the third signal, wherein the frequency band of the second signal is different from the frequency band of the third signal, and the sum of the frequency band of the second signal and the frequency band of the third signal is the frequency band of the first signal; a first signal processing branch connected with the frequency dividing branch, for amplifying and filtering the second signal, and outputting a fourth signal; a second signal processing branch connected with the frequency dividing branch, for amplifying and outputting the third signal, and outputting a fifth signal; 2. The signal processing circuit of claim 1, wherein, a signal transmission branch connected with an external circuit, the first signal processing branch and the second signal processing branch, for generating a sixth signal based on the combination of the fourth signal and the fifth signal, and outputting the sixth signal to the external circuit. The signal processing circuit further comprises a voltage converting branch; 3. The signal processing circuit of claim 2, wherein, the voltage converting branch is connected with the external signal, the signal synthesizing and amplifying branch, the first signal processing branch and the second signal processing branch, for receiving a voltage signal output by the external circuit, and outputting a power supply voltage based on the voltage signal, so as to supply power to the signal synthesizing and amplifying branch, the first signal processing branch and the second signal processing branch. The plurality of receiving antennas comprises a first receiving antenna, a second receiving antenna, a third receiving antenna, a fourth receiving antenna, a fifth receiving antenna, a sixth receiving antenna, a seventh receiving antenna and an eighth receiving antenna, the receiving antennas are FPC antennas, and the signal receiving branch further comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor; the first receiving antenna is connected with a first end of the first capacitor, the second receiving antenna, a first end of the second capacitor and the signal synthesizing and amplifying branch, the third receiving antenna is connected with a first end of the third capacitor, the fourth receiving antenna, a first end of the fourth capacitor and the signal synthesizing and amplifying branch, the fifth receiving antenna is connected with a first end of the fifth capacitor, the sixth receiving antenna, a first end of the sixth capacitor and the signal synthesizing and amplifying branch, the seventh receiving antenna is connected with a first end of the seventh capacitor, the eighth receiving antenna, a first end of the eighth capacitor and the signal synthesizing and amplifying branch, and the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor, the second end of the fourth capacitor, the second end of the fifth capacitor, the second end of the sixth capacitor, the second end of the seventh capacitor and the second end of the eighth capacitor are grounded.

4. The signal processing circuit of claim 3, wherein The signal synthesis and amplification branch comprises a first hybrid coupler, a second hybrid coupler, a third hybrid coupler, a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a first inductor and a second inductor; The first input end and the second input end of the first hybrid coupler, the first input end and the second input end of the second hybrid coupler are connected with the signal receiving branch, the first input end of the first hybrid coupler is connected with the first input end of the third hybrid coupler, the first input end of the second hybrid coupler is connected with the second input end of the third hybrid coupler, the second output end of the first hybrid coupler is grounded through the first resistor, the second input end of the second hybrid coupler is grounded through the second resistor, the second output end of the third hybrid coupler is grounded through the third resistor, the first output end of the third hybrid coupler is connected with the input end of the first amplifier through the ninth capacitor and the first inductor in sequence, the output end of the first amplifier is connected with the first end of the second inductor, the first end of the eleventh capacitor and the frequency dividing branch respectively, the second end of the second inductor is connected with the first end of the fourth resistor and the first end of the tenth capacitor respectively, the second end of the tenth capacitor and the second end of the eleventh capacitor are grounded, and the second end of the fourth resistor is connected with the voltage conversion branch.

5. The signal processing circuit according to claim 1 or 2, characterized by The frequency dividing branch comprises a twelfth capacitor, a thirteenth capacitor, a third inductor and a fifth resistor; The first end of the twelfth capacitor is connected with the signal synthesis and amplification branch, the second end of the twelfth capacitor is connected with the first end of the thirteenth capacitor and the first end of the third inductor respectively, the second end of the third inductor is connected with the second signal processing branch through the fifth resistor, and the second end of the thirteenth capacitor is connected with the first signal processing branch.

6. The signal processing circuit of claim 2, wherein, The first signal processing branch comprises a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a sixth resistor, a second amplifier and a first filter; A first end of the fourth inductor is connected with a first end of the fifteenth capacitor and the frequency division branch respectively, a second end of the fourth inductor is grounded through the fourteenth capacitor, a second end of the fifteenth capacitor is connected with the output end of the second amplifier through the fifth inductor, a power supply end of the second amplifier is connected with a first end of the sixth inductor and a first end of the sixteenth capacitor respectively, a second end of the sixteenth capacitor is grounded, a second end of the sixth inductor is connected with the voltage conversion branch, the output end of the second amplifier is connected with the input end of the first filter through the seventeenth capacitor, an eighteenth capacitor is connected between the input end of the first filter and the ground, an output end of the first filter is connected with a first end of the seventh inductor and a first end of the eighth inductor respectively, a second end of the seventh inductor is grounded through the sixth resistor, a second end of the eighth inductor is connected with the second signal processing branch and the signal transmission branch respectively.

7. The signal processing circuit of claim 2, wherein, The second signal processing branch comprises a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a ninth inductor, a tenth inductor, an eleventh inductor, a twelfth inductor, a seventh resistor, a third amplifier and a second filter; A first end of the ninth inductor is connected with a first end of the twentieth capacitor and the frequency division branch respectively, a second end of the ninth inductor is grounded through the nineteenth capacitor, a second end of the twentieth capacitor is connected with the input end of the third amplifier through the tenth inductor, a power supply end of the third amplifier is connected with the voltage conversion branch through the eleventh inductor, the twenty-third capacitor is connected between the power supply end of the third amplifier and the ground, an output end of the third amplifier is connected with the input end of the second filter through the twenty-first capacitor, the twenty-second capacitor is connected between the input end of the second filter and the ground, an output end of the second filter is connected with a first end of the twenty-fourth capacitor and a first end of the twelfth inductor respectively, a second end of the twelfth inductor is grounded through the seventh resistor, a second end of the twenty-fourth capacitor is connected with the first signal processing branch and the signal transmission branch respectively.

8. The signal processing circuit of claim 2, wherein, The signal transmission branch comprises a twenty-fifth capacitor, a twenty-sixth capacitor, a thirteenth inductor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and an electrostatic protection diode; A first end of the twenty-fifth capacitor is connected with the first signal processing branch and the second signal processing branch respectively, a second end of the twenty-fifth capacitor is connected with a first end of the thirteenth inductor, a first end of the ninth resistor and a first end of the tenth resistor respectively, a second end of the tenth resistor is connected with a first end of the eleventh resistor and a first end of the twenty-sixth capacitor respectively, a second end of the twenty-sixth capacitor is connected with a first end of the electrostatic protection diode, the voltage conversion branch and the external circuit respectively, a second end of the thirteenth inductor, the ninth resistor, the eleventh resistor and the electrostatic protection diode are grounded.

9. The signal processing circuit of claim 2, wherein, The voltage conversion branch comprises a fourteenth inductor, a twenty-seventh capacitor, a twenty-eighth capacitor, a twenty-ninth capacitor, a thirtieth capacitor, a twelfth resistor and a linear voltage regulator; A first end of the fourteenth inductor is connected with the signal transmission branch and the external circuit respectively, a second end of the fourteenth inductor is connected with an input end of the linear voltage regulator through the twelfth resistor, the twenty-seventh capacitor is connected between the input end of the linear voltage regulator and the ground, the twenty-seventh capacitor is connected with the twenty-eighth capacitor in parallel, the twenty-ninth capacitor is connected between an output end of the linear voltage regulator and the ground, the thirtieth capacitor is connected with the twenty-ninth capacitor in parallel, the output end of the linear voltage regulator is connected with the signal synthesis and amplification branch, the first signal processing branch and the second signal processing branch respectively.

10. An electronic device, comprising: The signal processing circuit comprises the signal processing circuit according to any one of claims 1-9.

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