Hybrid counter capable of shielding clock metastable state

Abstract

The utility model discloses a hybrid counter capable of shielding a clock metastable state. The hybrid counter structurally comprises an n-bit asynchronous clock counter, a metastable state shielding circuit and an m-bit synchronous clock counter. A first input clock signal passes through the n-bit asynchronous clock counter to generate an asynchronous clock signal, the asynchronous clock signal Q [n-3] and a data signal Qdata [n] pass through the metastable state shielding circuit to generate a second input clock, and the clock signal passes through the m-bit synchronous clock counter to output a count value. The shielding signal generated by the metastable state shielding circuit can shield the rising edge and the falling edge of the clock received by the synchronous clock counter during the metastable state, so that the problem of overflow counting caused by burrs generated by the metastable state is solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to counter technical field, concretely relates to a mixed type counter of clock metastability shielding. BACKGROUND

[0002] Generally mixed type counter is composed of n asynchronous clock counter and m synchronous clock counter, the signal transmission of asynchronous clock counter output to synchronous clock counter, and its data processing principle is, the output data Q_data[n:0] of asynchronous clock counter and the output data Q_data[n+m:n+1] of synchronous clock counter, after integration, the final output data is Q_data[n+m:0]. The frequency of asynchronous clock counter output signal is 1 / 2 of the frequency of asynchronous clock counter input clock signal n , and this frequency as the reference frequency of synchronous clock counter can effectively reduce the power consumption of counter.

[0003] In asynchronous processing digital circuit, the transmission delay of control signal is inevitable, and this delay will lead to insufficient setup time and hold time of signal, and produce metastability. When metastability occurs, the output level is indeterminate, and presents the oscillation between 0-1, and this unstable signal output to logic circuit, and it is easy to produce glitch or phase reversal and other misoperation.

[0004] Therefore, when the output signal of asynchronous clock counter appears metastability, it will lead to misoperation of synchronous clock counter, and finally make the counter miscount. When clock signal appears metastability, at the same time, if the output signal of comparator also inverts, then the latch will latch this metastability, and the output signal of latch can produce glitch. When this glitch is transmitted to the clock of synchronous counter, the clock signal of synchronous clock counter also appears glitch, and when this glitch exceeds threshold voltage, it is locked by latch, and this miscarry will lead to counter miscount. SUMMARY

[0005] TECHNICAL PROBLEM

[0006] For mixed type counter, when the output signal of asynchronous clock counter appears metastability, it will lead to misoperation of synchronous clock counter, and the output of counter appears miscount.

[0007] The utility model discloses a kind of mixed type counter structures of clock metastability shielding, when the output signal of asynchronous clock counter generates shielding signal after metastability shielding circuit, this signal can control input clock signal of synchronous counter, shielding metastability, solve the glitch of clock signal of synchronous counter when comparator inverts, lead to overflow count problem.

[0008] Solution to technical problem

[0009] In a first aspect, the utility model provides a hybrid counter capable of shielding clock metastability, the counter includes n asynchronous clock counter, metastability shielding circuit and m synchronous clock counter, first input clock signal generates asynchronous clock signal after n asynchronous clock counter, asynchronous clock signal Q [n-3] and data signal Q_data [n] generate second input clock after metastability shielding circuit, the clock signal is outputted after m synchronous clock counter count value.

[0010] Further, the metastability shielding circuit includes differential signal generating unit 201, frequency division unit 202 and latch 203, differential signal generating unit (201) generates differential signal CK1 and XCK1 by asynchronous clock signal Q [n-3], frequency division unit (202) is used to generate frequency division signal, and latch (203) shields the metastable state of data signal Q_data [n] by shielding signal and generates second input clock.

[0011] Further, in the differential signal generating unit 201, the first inverter INV1 is connected in series with the second inverter INV2, and the common end of the two inverters is connected to the transmission gate TG, the clock signal Q [n-3] is continuously outputted after passing through the first inverter INV1 and the second inverter INV2, and the output signal CK1 is outputted after passing through the transmission gate TG, and the output signal XCK1 is outputted.

[0012] Further, the frequency division unit 202 includes a first frequency division unit, a second frequency division unit, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7 and an eighth inverter INV8, wherein the first frequency division unit generates a one-to-one frequency division signal from the differential signal CK1 and CK2, and generates a signal Q1 and a signal XQ1 after passing through the third inverter INV3 and the fourth inverter INV4 respectively, the second frequency division unit generates a one-to-two frequency division signal from the signal Q1 and the signal XQ1, and generates Q2 and XQ2 after passing through the fifth inverter INV5 and the sixth inverter INV6 respectively, and generates CK2 and XCK2 after passing through the seventh inverter INV7 and the eighth inverter INV8 respectively.

[0013] Further, the first frequency dividing unit comprises a transistor MP1, a transistor MP2, a transistor MP3, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MP4, a transistor MP5, a transistor MN4, a transistor MN5, a transistor MN6, wherein the drain of the transistor MP1 is connected to the common terminal of the source of the transistor MP2 and the source of the transistor MP3, the drain of the transistor MP2 is connected to the drain of the transistor MN1, the drain of the transistor MP3 is connected to the drain of the transistor MN2, the common terminal of the source of the transistor MN1 and the source of the transistor MN2 is connected to the drain of the transistor MN3;

[0014] the drain of the transistor MP4 is connected to the drain of the transistor MN4, the drain of the transistor MP5 is connected to the drain of the transistor MN5, and the common terminal of the source of the transistor MN4 and the source of the transistor MN5 is connected to the drain of the transistor MN6;

[0015] the gate of the transistor MP1 is connected to a signal CK1, the gate of the transistor MN3 is connected to a signal XCK1, the common terminal of the gates of the transistor MP2 and the transistor MN1 is connected to a signal XCK2, the common terminal of the gates of the transistor MP3 and the transistor MN2 is connected to a signal CK2, the common terminal of the drain of the transistor MP2 and the drain of the transistor MN1 is connected to the common terminal of the drain of the transistor MP4 and the drain of the transistor MN4, and the common terminal of the drain of the transistor MP3 and the drain of the transistor MN2 is connected to the common terminal of the drain of the transistor MP5 and the drain of the transistor MN5;

[0016] the gate of the transistor MP4 and the gate of the transistor MN4 are respectively connected to the common terminal of the drain of the transistor MP5 and the drain of the transistor MN5, the gate of the transistor MP5 and the gate of the transistor MN5 are respectively connected to the common terminal of the drain of the transistor MP4 and the drain of the transistor MN4, and the common terminal of the source of the transistor MP4 and the source of the transistor MN5 is connected to the source of the transistor MP1;

[0017] the common terminal of the drain of the transistor MP4 and the drain of the transistor MN4 is connected to a third inverter INV3, and the common terminal of the drain of the transistor MP5 and the drain of the transistor MN5 is connected to a fourth inverter INV4;

[0018] The second frequency dividing unit has the same structure as the first frequency dividing unit.

[0019] Further, the output end of the AND gate is connected with the input end IN of the ninth inverter INV9 in the latch 203, the output end OUT of the ninth inverter INV9 is connected with the CKN end of the first inverter with selection EINV1 and the CKP end of the second inverter with selection EINV2 at the same time, the CKP end of the first inverter with selection EINV1 is connected with the output end of the AND gate, the input end IN of the first inverter with selection EINV1 is connected with the output end OUT of the tenth inverter INV10, the output end of the first inverter with selection EINV1 is connected with the input end of the eleventh inverter INV11, the output end of the eleventh inverter INV11 is connected with the input end IN of the second inverter with selection EINV2, the CKN end of the second inverter with selection EINV2 is connected with the output end of the AND gate, the output end OUT of the second inverter with selection EINV2 is connected with the input end of the eleventh inverter INV11, the output end of the eleventh inverter INV11 outputs the second input clock, and the input end of the tenth inverter INV10 inputs the data signal Q_data[n].

[0020] Advantageous effects

[0021] Compared with the existing hybrid counter structure, the counter structure provided by the utility model can realize the clock signal stability of the synchronous counter, shield the influence brought by the metastable state of the clock signal of the asynchronous counter, and finally guarantee the accuracy of the counter counting. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings provided herein are used to further illustrate the embodiments of the utility model, so as to facilitate understanding, and do not constitute a limitation on the embodiments of the utility model.

[0023] Figure 1 It is the structural schematic diagram of the hybrid counter of the utility model;

[0024] Figure 2 It is the structural schematic diagram of the metastable state shielding circuit of the utility model;

[0025] Figure 3 It is the structural schematic diagram of the inverter, the inverter with selection and the transmission gate of the prior art;

[0026] Figure 4 It is the action timing diagram of the metastable state shielding circuit of the utility model;

[0027] Figure 5 It is the principle diagram of shielding the clock metastable state of the utility model;

[0028] Figure 6 It is the schematic diagram of the utility model capable of realizing the clock signal stability of the synchronous counter. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of this utility model clearer, the following detailed description is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this utility model are for explanation only and are not intended to limit the scope of the utility model. For the sake of brevity, this document will not describe technologies known in the art; any processes not specifically described in detail are implementations that can be carried out by those skilled in the art with reference to existing technology.

[0030] For hybrid counters, when the output clock signal Q[n] of the asynchronous clock counter exhibits metastability, it can cause miscounting in the synchronous clock counter. Specifically, when the high-order bit Q[n] of the asynchronous clock counter is used as its clock, the transition from high to low or from low to high takes a certain amount of time. During this period, the clock signal will oscillate between 0 and 1 or between 1 and 0. This state is called metastability, so both the rising and falling edges of the asynchronous counter's clock signal Q[n] exhibit metastability. If the comparator's output signal flips at this time, the counter value will revert to its previous value. The latch will latch this metastability, potentially generating glitches in the latch's output data signal Q_data[n]. These glitches are transmitted to the clock of the next-stage synchronous clock counter, causing glitches in the synchronous clock counter's clock signal as well. When these glitches exceed the threshold voltage, they are latched by the latch, causing a false carry and resulting in miscounting.

[0031] To address the aforementioned problems, this invention provides a hybrid counter capable of shielding clock metastability, such as... Figure 1 As shown, the counter includes an n-bit asynchronous clock counter, a metastable shielding circuit, and an m-bit synchronous clock counter. The first input clock signal is converted into an asynchronous clock signal by the n-bit asynchronous clock counter. The asynchronous clock signal Q[n-3] and the data signal Q_data[n] are converted into a second input clock signal by the metastable shielding circuit. This clock signal is converted into a count value by the m-bit synchronous clock counter.

[0032] It should be noted that Q[n] and Q[n-3] are the clock signals of the asynchronous counter. The clock signal Q[n] is the output signal after being latched by the latch.

[0033] The main difference between the hybrid counter provided by this invention and the prior art is that by introducing a metastable shielding circuit, the metastable period of the asynchronous clock signal Q[n] is shielded. In this way, even if there are large glitches in the asynchronous clock signal when the comparator flips, it will not affect the second input clock, thus ensuring the stability of the synchronous clock counter.

[0034] Figure 2The utility model discloses a metastable shielding circuit's structure is shown, as shown in the drawing, this metastable shielding circuit includes differential signal generation unit 201, frequency division unit 202 and latch 203,

[0035] In differential signal generation unit 201, the first inverter INV1 is connected with the second inverter INV2 in series, and the common end of the two is connected with the transmission gate TG, the clock signal Q [n-3] is continuously outputted signal CK1 after passing through the first inverter INV1 and the second inverter INV2, and the output signal XCK1 is outputted after passing through the transmission gate TG.

[0036] The frequency division unit 202 includes the first frequency division unit, the second frequency division unit, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8, wherein the first frequency division unit generates a one-to-one frequency division signal from the differential signal CK1 and CK2, generates signal Q1 and signal XQ1 after passing through the third inverter INV3 and the fourth inverter INV4 respectively, the second frequency division unit generates a one-to-two frequency division signal from signal Q1 and signal XQ1, generates Q2 and XQ2 after passing through the fifth inverter INV5 and the sixth inverter INV6 respectively, and generates CK2 and XCK2 after passing through the seventh inverter INV7 and the eighth inverter INV8 respectively.

[0037] The first frequency division unit includes transistors MP1, MP2, MP3, MN1, MN2, MN3, MP4, MP5, MN4, MN5 and MN6, wherein the drain of transistor MP1 is connected to the common end of the source of MP2 and the source of MP3, the drain of MP2 is connected to the drain of MN1, the drain of MP3 is connected to the drain of MN2, and the common end of the source of MN1 and the source of MN2 is connected to the drain of MN3;

[0038] The drain of MP4 is connected to the drain of MN4, the drain of MP5 is connected to the drain of MN5, and the common end of the source of MN4 and the source of MN5 is connected to the drain of MN6;

[0039] The gate of MP1 is connected to signal CK1, the gate of MN3 is connected to signal XCK1, the common end of the gates of MP2 and MN1 is connected to signal XCK2, the common end of the gates of MP3 and MN2 is connected to signal CK2, the common end of the drain of MP2 and the drain of MN1 is connected to the common end of the drain of MP4 and the drain of MN4, and the common end of the drain of MP3 and the drain of MN2 is connected to the common end of the drain of MP5 and the drain of MN5;

[0040] The gates of MP4 and MN4 are respectively connected to the common end of the drain of MP5 and the drain of MN5, the gates of MP5 and MN5 are respectively connected to the common end of the drain of MP4 and the drain of MN4, and the common end of the source of MP4 and the source of MN5 is connected to the source of MP1.

[0041] The common end of the drain of MP4 and the drain of MN4 is connected to a third inverter INV3, and the common end of the drain of MP5 and the drain of MN5 is connected to a fourth inverter INV4.

[0042] The structure of the second frequency dividing unit is the same as that of the first frequency dividing unit, and includes transistors MP6, MP7, MP8, MN7, MN8, MN9, MP9, MP10, MN10, MN11, MN12, wherein the common end of the drain of MP6, the source of MP7 and the source of MP8 is connected to the drain of MP7, the drain of MP8 is connected to the drain of MN8, and the common end of the source of MN7 and the source of MN8 is connected to the drain of MN9;

[0043] The drain of MP9 is connected to the drain of MN10, the drain of MP10 is connected to the drain of MN11, and the common end of the source of MN10 and the source of MN11 is connected to the drain of MN12;

[0044] The gate of MP6 is connected to a signal XCK1, the common end of the gate of MP7 and the gate of MN7 is connected to a signal Q1, the common end of the gate of MP8 and the gate of MN8 is connected to a signal XQ1, the gate of MN9 is connected to a signal CK1, and the gate of MN12 is connected to a signal XCK1; the common end of the source of MP6, the source of MP9 and the source of MP10 is connected to a signal XCK1;

[0045] The common end of the gate of MP9 and the gate of MN10 is connected to the drain of MP10 and the drain of MN11, and the common end of the gate of MP10 and the gate of MN11 is connected to the drain of MP9 and the drain of MN10;

[0046] The common end of the drain of MP9 and the drain of MN10 is connected to a fifth inverter INV5, and the common end of the drain of MP10 and the drain of MN11 is connected to a sixth inverter INV6.

[0047] The frequency dividing signal CK2 and the signal CK1 in the latch 203 are connected to an AND gate to generate a shielding signal, and the shielding signal and the data signal Q_data[n] are processed to generate a second input clock;

[0048] Specifically, the output end of the AND gate is connected with the input end IN of the inverter INV9, the output end OUT of the inverter INV9 is connected with the CKN end of the inverter EINV1 with selection, the CKP end of the inverter EINV2 with selection, the CKP end of the inverter EINV1 with selection is connected with the output end of the AND gate, the input end IN of EINV1 is connected with the output end OUT of the inverter INV10, the output end of EIVN1 is connected with the input end of the inverter INV11, the output end of INV11 is connected with the input end IN of the inverter EINV2 with selection, the CKN end of EINV2 is connected with the output end of the AND gate, the output end OUT of EINV2 is connected with the input end of the inverter INV11, the output end of the inverter INV11 outputs the second input clock, and the input end of the inverter INV10 inputs the data signal Q_data[n].

[0049] It should be noted that the inverters, inverters with selection, transmission gates, NMOS transistors and PMOS transistors in the present application are all common knowledge in the art, MN refers to an NMOS transistor, MP refers to a PMOS transistor structure as shown in Figure 3 , which will not be repeated here.

[0050] Figure 4 The action timing of the metastability shielding circuit is shown as follows: at t0, when the signal Q[n-3] is high (H), the signals in the shielding circuit are all in the initial state, i.e., Q1=H, XQ1=L, Q2=L, XQ2=H, CK2=L, XCK2=H;

[0051] At t1, CK1 becomes H and XCK1 becomes L, the transistor MP1 is closed, the transistor MN3 is closed, and the transistor MN6 is opened, Q1 and XQ1 maintain the previous state, Q1=H, XQ1=L; the transistor MP6 is opened, the transistor MN9 is opened, and the transistor MN12 is closed, Q2 and XQ2 are updated to Q1 and XQ1, Q2=H, XQ2=L; CK2 and XCK2 are updated to Q2 and XQ2, CK2=H, XCK2=L; at this time, CK2 is H and Q[n-3] is H, so the shielding signal is H, and the second input clock is updated to the value of Q[n] from L to H;

[0052] At time t2, CK1 changes to L, XCK1 changes to H, transistor MP1 turns on, transistor MN3 turns on, transistor MN6 turns off, Q1 updates to XCK2, XQ1 updates to CK2, Q1=L, XQ1=H; transistor MP6 turns off, transistor MN9 turns off, transistor MN12 turns on, Q2 and XQ2 maintain the previous state, Q2=H, XQ2=L; CK2 and XCK2 maintain the previous state, CK2=H, XCK2=L; at this time, CK2 is H, Q[n-3] changes from H to L, the shielding signal changes from H to L, the second input clock maintains the previous state of H;

[0053] At time t3, CK1 changes to H, XCK1 changes to L, transistor MP1 turns off, transistor MN3 turns off, transistor MN6 turns on, Q1 and XQ1 maintain the previous state, Q1=L, XQ1=H; transistor MP6 turns on, transistor MN9 turns on, transistor MN12 turns off, Q2 and XQ2 update to Q1 and XQ1, Q2=L, XQ2=H; CK2 and XCK2 update to Q2 and XQ2, CK2=L, XCK2=H; at this time, CK2 is L, Q[n-3] changes from L to H, the shielding signal is L, the second input clock maintains the previous state of H;

[0054] At time t4, CK changes to L, XCK changes to H, transistor MP1 turns on, transistor MN3 turns on, transistor MN6 turns off, Q1 updates to XCK2, XQ1 updates to CK2, Q1=H, XQ1=L; transistor MP6 turns off, transistor MN9 turns off, transistor MN12 turns on, Q2 and XQ2 maintain the previous state, Q2=L, XQ2=H; CK2 and XCK2 maintain the previous state, CK2=L, XCK2=H; at this time, CK2 is L, Q[n-3] changes from H to L, the shielding signal is L, the second input clock maintains the previous state of H;

[0055] At time t5, CK1 changes to H, XCK1 changes to L, transistor MP1 turns off, transistor MN3 turns off, transistor MN6 turns on, Q1 and XQ1 maintain the previous state, Q1=H, XQ1=L; transistor MP6 turns on, transistor MN9 turns on, transistor MN12 turns off, Q2 and XQ2 update to Q1 and XQ1, Q2=H, XQ2=L; CK2 and XCK2 update to Q2 and XQ2, CK2=H, XCK2=L; at this time, CK2 is H, Q[n-3] is H, the shielding signal is H, the second input clock updates to the value of Q[n] from H to L;

[0056] The above actions are repeated in turn to obtain the shielding signal.

[0057] The principle that the shielding circuit can realize clock metastable state shielding is that the output clock Q[n-3] of the asynchronous clock counter generates a set of differential signals CK1 and XCK1, when CK=L and XCK=H, the internal latching state is updated as the feedback signals CK2 and XCK2, when CK=H and XCK=L, the output CK2 and XCK2 maintain the state of the internal latching, realizing the frequency division of the Q[n-3] signal. The shielding signal is obtained by the operation of the signals CK2 and CK, when the shielding signal is H, the latch is opened, and the second input clock is Q_data[n]; when the shielding signal is L, the latch is closed, the last state is latched and output, and the state of the second input clock is maintained.

[0058] Figure 5 The waveform diagram of the second input clock controlled by the shielding signal is shown, when the shielding signal is generated by the metastable state shielding circuit provided by the utility model, when the shielding signal is low, the rising edge and the falling edge of the second input clock received by the synchronous clock counter are shielded, thereby solving the problem that the overflow counting is caused by the glitch of the second input clock when the comparator flips.

[0059] Figure 6 The effect that the clock of the synchronous counter can be in a stable state is shown, as shown in the figure, when the clock signal Q[n] of the asynchronous counter is in a metastable state, the output data signal Q_data[n] of the asynchronous counter generates a glitch due to the metastable state, when the shielding signal is introduced, the rising edge and the falling edge of the data signal Q_data[n] in the metastable state period are shielded, the second clock signal is generated, and the glitch on the clock signal is eliminated, so that the stability of the clock signal of the synchronous counter is ensured, and the normal counting of the counter is not affected.

[0060] The above specific embodiments are used to further explain the purpose, technical scheme and beneficial effects of the utility model, and it should be understood that the above description is only the specific embodiments of the utility model, and is not used to limit the protection scope of the utility model, any modification, equivalent replacement, improvement, etc. within the spirit and principle of the utility model should be included in the protection scope of the utility model.

Claims

1. A hybrid counter capable of shielding clock metastability, characterized by, The counter comprises an n-bit asynchronous clock counter, a metastable shielding circuit and an m-bit synchronous clock counter; an asynchronous clock signal is generated after a first input clock signal passes through the n-bit asynchronous clock counter, and a second input clock is generated after the asynchronous clock signal Q[n-3] and a data signal Q_data[n] pass through the metastable shielding circuit; and a count value is output after the clock signal passes through the m-bit synchronous clock counter.

2. The hybrid counter of claim 1, wherein, The metastable shielding circuit comprises: a differential signal generating unit (201) for generating differential signals CK1 and XCK1 from the asynchronous clock signal Q[n-3]; a frequency dividing unit (202) for generating a frequency-divided signal; and a latch (203) for shielding the metastable state of the data signal Q_data[n] by a shielding signal to generate the second input clock.

3. The hybrid counter of claim 2, wherein, In the differential signal generating unit (201), a first inverter INV1 and a second inverter INV2 are connected in series, and a transmission gate TG is connected to the common end of the first inverter INV1 and the second inverter INV2; the clock signal Q[n-3] passes through the first inverter INV1 and the second inverter INV2 in sequence to output the signal CK1, and passes through the transmission gate TG to output the signal XCK1.

4. The hybrid counter of claim 2, wherein, The frequency dividing unit (202) comprises a first frequency dividing unit, a second frequency dividing unit, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7 and an eighth inverter INV8; the first frequency dividing unit generates a one-to-one frequency-divided signal from the differential signals CK1 and CK2, and generates the signal Q1 and the signal XQ1 after passing through the third inverter INV3 and the fourth inverter INV4, respectively; the second frequency dividing unit generates a one-to-two frequency-divided signal from the signals Q1 and XQ1, and generates the signal Q2 and the signal XQ2 after passing through the fifth inverter INV5 and the sixth inverter INV6, respectively; and the signals CK2 and XCK2 are generated after passing through the seventh inverter INV7 and the eighth inverter INV8, respectively.

5. The hybrid counter of claim 4, wherein, The first frequency dividing unit comprises a transistor MP1, a transistor MP2, a transistor MP3, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MP4, a transistor MP5, a transistor MN4, a transistor MN5 and a transistor MN6; the drain of the transistor MP1 is connected to the common end of the source of the transistor MP2 and the source of the transistor MP3, the drain of the transistor MP2 is connected to the drain of the transistor MN1, the drain of the transistor MP3 is connected to the drain of the transistor MN2, and the common end of the source of the transistor MN1 and the source of the transistor MN2 is connected to the drain of the transistor MN3; the drain of the transistor MP4 is connected to the drain of the transistor MN4, the drain of the transistor MP5 is connected to the drain of the transistor MN5, and the common end of the source of the transistor MN4 and the source of the transistor MN5 is connected to the drain of the transistor MN6. The gate of the transistor MP1 is connected to the signal CK1, the gate of the transistor MN3 is connected to the signal XCK1, the common terminal of the gates of the transistor MP2 and the transistor MN1 is connected to the signal XCK2, the common terminal of the gates of the transistor MP3 and the transistor MN2 is connected to the signal CK2, the common terminal of the drain of the transistor MP2 and the drain of the transistor MN1 is connected to the drain of the transistor MP4 and the drain of the transistor MN4, the common terminal of the drain of the transistor MP3 and the drain of the transistor MN2 is connected to the drain of the transistor MP5 and the drain of the transistor MN5; The gate of the transistor MP4 and the gate of the transistor MN4 are respectively connected to the common terminal of the drain of the transistor MP5 and the drain of the transistor MN5, the gate of the transistor MP5 and the gate of the transistor MN5 are respectively connected to the common terminal of the drain of the transistor MP4 and the drain of the transistor MN4; the common terminal of the source of the transistor MP4 and the source of the transistor MN5 is connected to the source of the transistor MP1; The common terminal of the drain of the transistor MP4 and the drain of the transistor MN4 is connected to the third inverter INV3, and the common terminal of the drain of the transistor MP5 and the drain of the transistor MN5 is connected to the fourth inverter INV4. The second frequency dividing unit has the same structure as the first frequency dividing unit.

6. The hybrid counter of claim 2, wherein, The output of the AND gate is connected to the input IN of the ninth inverter INV9, and the output OUT of the ninth inverter INV9 is connected to the CKN terminal of the first selectable inverter EINV1 and the CKP terminal of the second selectable inverter EINV2, the CKP terminal of the first selectable inverter EINV1 is connected to the output of the AND gate, the input IN of the first selectable inverter EINV1 is connected to the output OUT of the tenth inverter INV10, the output of the first selectable inverter EINV1 is connected to the input IN of the eleventh inverter INV11, the output of the eleventh inverter INV11 is connected to the input IN of the second selectable inverter EINV2, the CKN terminal of the second selectable inverter EINV2 is connected to the output of the AND gate, the output OUT of the second selectable inverter EINV2 is connected to the input IN of the eleventh inverter INV11, the output of the eleventh inverter INV11 outputs the second input clock, and the input of the tenth inverter INV10 inputs the data signal Q_data[n].

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