Groove Schottky barrier diode

Abstract

The utility model discloses a groove Schottky barrier diode, which is characterized in that a groove in an epitaxial layer of the diode forms a step shape by a small upper cylindrical opening and a large lower cylindrical opening, conductive polycrystalline silicon is arranged in the groove, and a dielectric layer isolates the conductive polycrystalline silicon from the epitaxial layer on the inner wall of the groove. The thickness of the dielectric layer on the inner wall of the upper cylindrical opening is smaller than that of the dielectric layer on the inner wall of the lower cylindrical opening. According to the trench and the upper cylindrical small opening, the conductive area during forward conduction is increased, and forward conduction voltage drop is reduced; the lower cylindrical opening is large, so that the point discharge effect during reverse bias of the device is avoided; furthermore, the dielectric layer covered on the inner wall of the lower cylindrical opening of the groove is thicker, and the pressure drop borne by the dielectric layer is increased during reverse bias; and the thin dielectric layer on the side wall of the upper cylindrical opening is beneficial to forming depletion pinch-off in the mesa structure epitaxial layer during reverse bias, so that the reverse blocking performance of the device is further improved, the reliability of the device is improved, and the service life of the device is prolonged.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor device, especially to a Schottky barrier diode of a semiconductor discrete device and a manufacturing method thereof. BACKGROUND

[0002] Rectifier devices are required to have unidirectional conduction characteristics, i.e. low forward voltage and low on-resistance when forward biased, and high blocking voltage and low reverse leakage when reverse biased. Schottky barrier diodes have been used as rectifier devices for decades in power supply applications. Because of their low forward voltage and fast switching speed, they are very suitable for use in switching power supplies and high frequency applications.

[0003] Schottky barrier diodes are made using the principle of metal-semiconductor junctions formed by the contact of metal and semiconductor. Conventional planar Schottky barrier diode devices are usually formed by a low doped N-epitaxial layer and a metal layer deposited on the top surface to form a Schottky barrier contact. The difference in work function between the metal and the N-type single crystal silicon forms a barrier, and the height of the barrier determines the characteristics of the Schottky barrier diode. A lower barrier can reduce the forward conduction opening voltage, but will increase the reverse leakage and reduce the reverse blocking voltage. Conversely, a higher barrier will increase the forward conduction opening voltage, while reducing the reverse leakage and enhancing the reverse blocking capability. However, conventional planar Schottky barrier diodes generally have high reverse leakage and low reverse blocking voltage. In view of the above problems, trench Schottky barrier diodes have been invented, which have low forward conduction opening voltage and overcome the shortcomings of the above-mentioned planar Schottky diodes.

[0004] A significant feature of the trench Schottky barrier diode is that there are several trenches extending into the N-epitaxial layer in the N-epitaxial layer, an oxide layer covering the surface of the trench, and a conductive material filling therein. For example, US Patent No. 5,365,102 discloses a trench Schottky barrier diode, in which the device structure of one embodiment is shown in the attached figure. Figure 1The shown is a trench Schottky barrier diode structure commonly used in the prior art. As can be seen from the figure, the silicon wafer for manufacturing the diode is composed of a highly doped N+ substrate 301 and a lower doped N- epitaxial layer 302, a series of trenches 303 are prepared in the N- epitaxial layer 302, the N-type single crystal silicon mesa structure 304 is between the trenches 303, the silicon dioxide layer 305 is grown on the sidewall of the trench 303, the metal layer 306 is covered on the upper surface of the entire structure and contacts the top surface of the single crystal silicon mesa structure 304 to form a Schottky barrier contact; the cathode metal layer 307 is deposited on the bottom surface of the N+ substrate 301. Due to the existence of the composite structure composed of the trench 303, the silicon dioxide layer 305 and the conductive material 306 in the trench, the electric field distribution changes when the device is reversely biased, the electric field intensity at the bottom of the trench appears a peak value, the free carriers in the mesa structure 304 are completely depleted, and the electric field intensity reaching the Schottky barrier is reduced, thereby the voltage reverse blocking capability of the device is enhanced, and the reverse leakage current is reduced.

[0005] However, the trench Schottky barrier diode structure in the prior art still has some problems, and the main problems exposed include: 1) when forward conducting, the area occupied by the trench structure cannot conduct current, causing current crowding in the semiconductor of the mesa, so that the forward conduction voltage drop of the trench Schottky diode becomes large; 2) when reversely biased, the electric field intensity at the bottom of the trench is the largest, the curvature radius of the bottom structure is small, or the thickness of the oxide layer at the bottom of the trench is thin or uneven due to the limitation of the step coverage capability, which can all cause uneven distribution of the electric field intensity and too high local electric field intensity; the reverse voltage drop blocking capability of the device is reduced, and the reliability and service life of the device are reduced; 3) when reversely biased, complete depletion in the mesa needs to be achieved to obtain the required reverse leakage current and the reliability and service life of the device.

[0006] As can be seen, the existing trench Schottky barrier diode structure still has some defects, and the performance needs to be further optimized, the reliability of the device needs to be improved, and the manufacturing method of the device needs to be simplified to reduce the cost. Content of the utility model

[0007] In view of the defects of the prior art, the purpose of the utility model is to provide a trench Schottky barrier diode and a manufacturing method thereof, so as to improve the above-mentioned defects of the existing trench Schottky barrier diode, further improve the performance and reliability of the device, and optimize the manufacturing cost.

[0008] In order to achieve the above-mentioned purpose, the utility model adopts the following technical scheme.

[0009] The utility model provides a trench Schottky barrier diode first, comprising:

[0010] The first conductive type heavily doped semiconductor substrate;

[0011] a lightly doped semiconductor epitaxial layer of a first conductivity type on the top surface of the substrate;

[0012] a series of periodically arranged trenches in the epitaxial layer, opening on the top surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent trenches forms a mesa structure;

[0013] a heavily doped conductive polysilicon of the first conductivity type filled in the trenches;

[0014] a first isolation dielectric layer on the inner wall of the trenches and used to isolate the conductive polysilicon and the epitaxial layer;

[0015] a Schottky barrier metal layer covering the top surface of the epitaxial layer in the mesa structure region;

[0016] an ohmic contact metal layer covering the top surface of the conductive polysilicon;

[0017] a second isolation dielectric layer formed by upward extension of the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer;

[0018] an anode metal layer covering the top surface of the Schottky barrier diode;

[0019] and a cathode metal layer on the bottom surface of the substrate, the bottom surface of the substrate forming an ohmic contact with the cathode metal layer;

[0020] wherein the trenches are composed of two columnar openings in communication with each other, and the lateral opening size of the upper columnar opening is smaller than that of the lower columnar opening, and a step is formed at the communication part of the two columnar openings;

[0021] wherein the first isolation dielectric layer is composed of a first upper isolation dielectric layer and a first lower isolation dielectric layer; the first upper isolation dielectric layer is on the inner wall of the upper columnar opening of the trench and used to isolate the epitaxial layer constituting the inner wall of the upper columnar opening and the conductive polysilicon; the first lower isolation dielectric layer is on the inner wall of the lower columnar opening of the trench and used to isolate the epitaxial layer constituting the inner wall of the lower columnar opening and the conductive polysilicon; and the thickness of the first upper isolation dielectric layer is smaller than that of the first lower isolation dielectric layer.

[0022] As a preferred solution, the thickness of the first upper isolation dielectric layer is 0.05 microns to 0.15 microns, the thickness of the first lower isolation dielectric layer is 0.1 microns to 0.6 microns, and the difference between the two is greater than or equal to 0.05 microns. 0.01 microns.

[0023] Further, there is a second conductivity type ion implantation region in the epitaxial layer region at the bottom of the trench.

[0024] The cross sections of the upper cylindrical opening and the lower cylindrical opening of the trench are circular. The upper small cylindrical opening structure maximizes the Schottky barrier area of the mesa structure. Meanwhile, in order to improve the tip discharge enhancement possibly caused by the upper opening, the lower cylindrical transverse opening of the trench is widened to form a structure with an enlarged curvature radius at the bottom of the trench, thereby avoiding the tip discharge enhancement.

[0025] Further, the transverse opening size of the upper cylindrical opening is 0.1-0.5 microns, and the transverse opening size of the lower cylindrical opening is 0.2-2 microns, and the difference between the transverse opening size of the lower cylindrical opening and the transverse opening size of the upper cylindrical opening is greater than or equal to 0.1 micron.

[0026] Further, the first upper isolation medium layer and the second isolation medium layer are synchronously grown to have the same thickness.

[0027] The Schottky barrier metal layer and the ohmic contact metal layer are the same metal formed by alloying after synchronous deposition.

[0028] Further, the first conductive type is N type, and the second conductive type is P type.

[0029] The utility model also provides a manufacturing method of the trench Schottky barrier diode, which comprises the following steps.

[0030] S1. Growing a first conductive type lightly doped semiconductor epitaxial layer on a first conductive type heavily doped semiconductor substrate.

[0031] S2. Forming a first medium layer on the upper surface of the epitaxial layer, performing photolithography on the first medium layer to define an upper cylindrical opening pattern, selectively removing the first medium layer not protected by the photoresist to expose the epitaxial layer corresponding to the upper cylindrical opening pattern, and then removing the photoresist on the first medium layer; using the first medium layer remaining after removing the photoresist as a first medium hard mask.

[0032] S3. Using the first medium hard mask as protection, selectively etching the exposed epitaxial layer by dry etching to form the upper cylindrical opening in the trench. Thus, the mesa structure with a certain width is formed between the upper cylindrical openings, and the upper surface of the mesa structure is still covered with the first medium hard mask at this time.

[0033] S4. Forming a second medium layer on the surface of the entire structure.

[0034] S5. Selectively etching the second dielectric layer by dry etching method, exposing the epitaxial layer at the bottom of the upper columnar opening, while the second dielectric layer above the first dielectric layer is also removed synchronously; at this time, the upper surface of the mesa structure is still covered with the first dielectric layer, i.e. the first dielectric hard mask, and at this time, the second dielectric layer covering the sidewall of the upper columnar opening is used as the second dielectric hard mask.

[0035] S6. Selectively etching the exposed epitaxial layer by dry etching method, with the first dielectric hard mask and the second dielectric hard mask as protection.

[0036] S7. Continuing to use the first dielectric hard mask and the second dielectric hard mask as protection, selectively etching the exposed epitaxial layer by XeF2 dry etching method, forming the lower columnar opening of the trench.

[0037] S8. Continuing to use the first dielectric hard mask and the second dielectric hard mask as protection, implanting second-conductivity-type dopant impurities into the exposed epitaxial layer by ion implantation method.

[0038] S9. Continuing to use the first dielectric hard mask and the second dielectric hard mask as protection, forming an oxide layer on the exposed epitaxial layer, at this time, the oxide layer formed on the inner wall of the lower columnar opening constitutes the first lower isolation dielectric layer; at the same time, the heat process of the oxide layer formation promotes the diffusion of the above-mentioned second-conductivity-type dopant impurities to form a preliminary ion implantation region.

[0039] S10. Removing the second dielectric layer and the first dielectric layer by wet etching method.

[0040] S11. Depositing an oxide layer on the surface of the entire structure formed after step S10, the oxide layer deposited on the sidewall of the upper columnar opening constitutes the first upper isolation dielectric layer; at this time, the final formation of the first lower isolation dielectric layer is also completed; at the same time, the heat process of the oxide layer formation further promotes the diffusion of the above-mentioned second-conductivity-type dopant impurities to complete the formation of the ion implantation region.

[0041] S12. Depositing conductive polysilicon on the surface of the entire structure formed after step S11; then selectively removing the conductive polysilicon outside the trench by dry etching method, and making the upper surface of the conductive polysilicon filled in the trench flush with the upper surface of the epitaxial layer of the mesa structure. Due to the large thickness of the oxide layer on the inner wall of the lower columnar opening, i.e. the first lower isolation dielectric layer, there is no longer a hollow inside the conductive polysilicon during the filling of the lower columnar opening.

[0042] S13. The oxidation layer on the mesa structure surface is selectively removed by dry etching or wet etching, and the oxidation layer extending upward and surrounding the upper surface opening of the trench of the first upper isolation medium layer is reserved, and the reserved oxidation layer constitutes the second isolation medium layer, which is used for isolating the Schottky barrier metal layer and the ohmic contact metal layer to be formed.

[0043] S14. A first metal layer is deposited on the entire structure surface after step S13 is completed, and after alloying, the first metal layer forms a Schottky barrier contact with the upper surface of the epitaxial layer of the mesa structure, that is, the Schottky barrier metal layer is formed, and forms an ohmic contact with the upper surface of the conductive polysilicon filled in the trench, that is, the ohmic contact metal layer is formed.

[0044] S15. An anode metal layer is deposited on the entire structure surface after step S14 is completed.

[0045] S16. The substrate is thinned by grinding and etching the lower surface of the substrate, and then a cathode metal layer is deposited on the lower surface of the substrate.

[0046] The beneficial effects of the utility model are as follows.

[0047] Due to the use of the above technical scheme, the utility model has the following advantages and effects compared with the prior art.

[0048] 1. The periodically arranged trenches present a stepped structure design with small upper opening and large lower opening, the horizontal size of the upper cylindrical opening of the trench is small, the chip area occupied by the non-conductive structure is reduced, the conductive semiconductor area during forward conduction is increased, the current density during forward conduction is reduced, the forward conduction voltage drop is reduced, and the junction temperature during forward conduction is reduced, thereby improving the forward conduction performance, reliability and service life of the device.

[0049] 2. The horizontal size of the upper cylindrical opening of the trench is small, and the horizontal size of the lower cylindrical opening is large, which avoids the possible deterioration of the sharp tip discharge effect of the trench bottom during reverse bias of the device, thereby improving the reverse blocking performance, reliability and service life of the device.

[0050] 3. The isolation medium layer covering the inner wall of the lower cylindrical opening of the trench is relatively thick, and the pressure drop borne by this part of the medium layer during reverse bias is increased, thereby improving the reverse blocking capability of the device.

[0051] 4) The isolation medium layer covering the sidewall of the upper cylindrical opening of the trench is relatively thin, which is beneficial to the formation of a depletion pinch in the epitaxial layer of the mesa structure during reverse bias, thereby improving the reverse blocking performance, reliability and service life of the device.

[0052] 5). The second conductive type injection region is arranged in the trench bottom epitaxial layer, the first conductive type doping concentration of the local region is reduced through compensation, the expansion of the electric field intensity distribution in the bottom epitaxial layer is assisted when the device is reversely biased, the electric field intensity of the local region is reduced, and therefore the reverse blocking performance, the device reliability and the service life of the device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 is a trench Schottky barrier diode disclosed in US 5,365,102, and is also a schematic structural diagram of a commonly used trench Schottky barrier diode in the prior art.

[0054] wherein, Figure 1 in which 301 is N + substrate, 302 is N － epitaxial layer, 303 is a trench, 304 is an N-type monocrystalline silicon mesa structure, 305 is a silicon dioxide layer, 306 is a metal layer, and 307 is a cathode metal layer.

[0055] Figure 2 is a top view structural schematic diagram of a Schottky barrier diode made by each embodiment of the utility model.

[0056] Figure 3 is a cross-sectional structural schematic diagram of the Schottky barrier diode of each embodiment of the utility model at A1-A2 position. Figure 2

[0057] Figure 4 is a cross-sectional schematic diagram of a device structure formed after step S4 in embodiment 1 of the utility model.

[0058] Figure 5 is a cross-sectional schematic diagram of a device structure formed after step S8 in embodiment 1 of the utility model.

[0059] Figure 6 is a cross-sectional schematic diagram of a device structure formed after step S9 in embodiment 1 of the utility model.

[0060] Figure 7 is a cross-sectional schematic diagram of a device structure formed after step S11 in embodiment 1 of the utility model.

[0061] Figure 8 is a cross-sectional schematic diagram of a device structure formed after step S12 in embodiment 1 of the utility model.

[0062] Figure 9 is a cross-sectional schematic diagram of a device structure formed after step S14 in embodiment 1 of the utility model.

[0063] wherein, Figures 2-8 ​In the figure, 10 is a cathode metal layer, 20 is a first conductive type heavily doped substrate, 30 is a first conductive type lightly doped epitaxial layer, 30a is a mesa structure, 31 is a step-shaped groove, 31a is an upper cylindrical opening, 31b is a lower cylindrical opening, 32 is a conductive polysilicon, 33a is a first upper isolation dielectric layer, 34 is a first lower isolation dielectric layer, 33b is a second isolation dielectric layer, 35 is an ion implantation region, 35a is a second conductive type doped impurity, 40 is a functional metal layer, 40a is a Schottky barrier metal layer, 40b is an ohmic contact metal layer, and 50 is an anode metal layer; 61 is a first dielectric layer, and 62 is a second dielectric layer. DETAILED DESCRIPTION

[0064] In order to more clearly illustrate the technical scheme of the utility model and the purpose of the application, the utility model will be further described in detail below in combination with the drawings and specific embodiments.

[0065] As Figure 2 is a top view structural schematic diagram of a Schottky barrier diode made by each embodiment of the utility model, Figure 3 is a cross-sectional structural schematic diagram of the Schottky barrier diode of each embodiment in Figure 2 From Figures 2-3 It can be seen that the Schottky barrier diode of the utility model comprises, from bottom to top, a cathode metal layer 10, a semiconductor first conductive type heavily doped substrate 20, a semiconductor first conductive type lightly doped epitaxial layer 30, a functional metal layer 40, and an anode metal layer 50 covering the top layer of the entire Schottky barrier diode structure; further comprising a series of step-shaped grooves 31 in the epitaxial layer 30, the step-shaped grooves 31 being opened on the upper surface of the epitaxial layer 30 and extending into the epitaxial layer 30; from Figure 2 , Figure 3It can be seen that the stepped trench in the figure is composed of two cylindrical openings in communication, the inner diameter (i.e. the lateral opening size) of the upper cylindrical opening 31a is smaller than that of the lower cylindrical opening 31b; the first conductive type heavily doped conductive polysilicon 32 is filled in the trench; the inner wall of the stepped trench 31 is covered with an isolation oxide layer as a first isolation medium layer, which is composed of a first upper isolation medium layer 33a covering the inner wall of the upper cylindrical opening and a first lower isolation medium layer 34 covering the inner wall of the lower cylindrical opening, the first isolation medium layer is used to isolate the conductive polysilicon 32 and the epitaxial layer constituting the inner wall of the trench; in the epitaxial layer close to the bottom of the stepped trench 31, there is a second conductive type ion implantation region 35. Among them, the epitaxial layer between adjacent trenches forms a mesa structure 30a, the functional metal layer 40 covering the upper surface of the epitaxial layer of the mesa structure 30a forms a Schottky barrier metal layer 40a in Schottky barrier contact with the epitaxial layer; while the functional metal layer 40 covering the upper surface of the conductive polysilicon 32 is an ohmic contact metal layer 40b forming ohmic contact with the heavily doped conductive polysilicon; the isolation oxide layer extending upward from the first upper isolation medium layer 33a between the Schottky barrier metal layer 40a and the ohmic contact metal layer 40b constitutes a second isolation medium layer 33b used to isolate the Schottky barrier metal layer and the ohmic contact metal layer.

[0066] The Schottky barrier diode and the specific manufacturing process of the present application will be described in more detail below through specific examples.

[0067] Example 1

[0068] In this embodiment, the heavily doped substrate is an N+ single crystal silicon wafer, the epitaxial layer is a lightly doped N- silicon epitaxial layer grown on the N+ single crystal silicon wafer, the ion implantation region is a P-type ion implantation region, and the silicon oxide layer is an isolation oxide layer. The inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped trench 31 is 0.25 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 0.5 microns. The thickness of the first upper isolation medium layer 33a covering the inner wall of the upper cylindrical opening is 0.1 microns, and the thickness of the first lower isolation medium layer 34 covering the inner wall of the lower cylindrical opening is 0.11 microns.

[0069] The process flow for manufacturing the trench Schottky barrier diode of this embodiment is as follows:

[0070] S1. Prepare a semiconductor first conductive type heavily doped substrate N+ single crystal silicon wafer, and grow a first conductive type lightly doped epitaxial layer N- silicon epitaxial layer 30 on the substrate 20.

[0071] S2. Form a first dielectric layer 61 on the surface of the epitaxial layer, perform photoetching on the first dielectric layer to define an upper cylindrical opening 31a pattern, selectively remove the first dielectric layer not protected by the photoresist to expose the epitaxial layer corresponding to the upper cylindrical opening pattern, and then remove the photoresist on the first dielectric layer; use the first dielectric layer remaining after the photoresist is removed as a first dielectric hard mask.

[0072] S3. Use the first dielectric hard mask as protection and selectively etch the exposed epitaxial layer 30 by dry etching to form the upper cylindrical opening 31a in the step-shaped trench 31 in the epitaxial layer, thereby forming a mesa structure 30a in the epitaxial layer between the upper cylindrical openings. At this time, the mesa structure 30a is still covered by the first dielectric hard mask on the upper surface.

[0073] S4. Form a second dielectric layer 62 on the surface of the entire structure formed after step S3, and obtain a structure cross-sectional view as shown in Figure 4 .

[0074] S5. Selectively etch the second dielectric layer 62 by dry etching to expose the epitaxial layer at the bottom of the upper cylindrical opening 31a, and at the same time, the second dielectric layer 62 above the first dielectric layer 61 is also removed synchronously; at this time, the mesa structure 30a is still covered by the first dielectric layer 61, i.e., the first dielectric hard mask on the upper surface, and at this time, the second dielectric layer 62 covering the sidewall of the upper cylindrical opening 31a is used as a second dielectric hard mask.

[0075] S6. Use the first dielectric hard mask and the second dielectric hard mask as protection and selectively etch the exposed epitaxial layer by dry etching.

[0076] S7. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection and selectively etch the exposed epitaxial layer by dry etching with xenon difluoride to form a lower cylindrical opening 31b of the step-shaped trench 31.

[0077] S8. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection and implant second-conductivity-type doping impurities 35a into the exposed epitaxial layer by ion implantation; at this time, obtain a structure cross-sectional view as shown in Figure 5 .

[0078] S9. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection and form an oxide layer on the exposed epitaxial layer; at this time, the oxide layer formed on the inner wall of the lower cylindrical opening 31b constitutes a preliminary first lower isolation dielectric layer 34; at the same time, the heat process formed on the oxide layer promotes the diffusion of the above-mentioned second-conductivity-type doping impurities to form a preliminary ion implantation region. At this time, obtain a device structure cross-sectional view as shown in Figure 6 .

[0079] S10. The second dielectric layer 62 and the first dielectric layer 61 are selectively removed by wet etching.

[0080] S11. An oxide layer is deposited on the surface of the entire structure formed after step S10, and the oxide layer deposited on the inner wall of the upper cylindrical opening 31a forms the first upper isolation dielectric layer 33a. At this time, the final formation of the first lower isolation dielectric layer 34 is also completed synchronously. The formation of the ion implantation region 35 is further promoted by the diffusion of the second-conductivity-type doped impurities 35a during the formation of the oxide layer. The cross-sectional view of the device structure at this time is shown in FIG. 3. Figure 7

[0081] S12. Conductive polysilicon 32 is deposited on the surface of the entire structure formed after step S11. The conductive polysilicon outside the trench is selectively removed by dry etching, and the upper surface of the conductive polysilicon 32 filled in the trench is leveled with the upper surface of the epitaxial layer of the mesa structure 30a. Due to the large thickness of the oxide layer, i.e., the first lower isolation dielectric layer, on the inner wall of the lower cylindrical opening, no cavity is left in the conductive polysilicon during the filling of the polysilicon in the lower cylindrical opening. The cross-sectional view of the structure at this time is shown in FIG. 4. Figure 8

[0082] S13. The isolation oxide layer on the surface of the mesa structure 30a is selectively removed by dry etching, and the oxide layer extending upward from the first isolation dielectric layer and surrounding the upper surface opening of the trench is retained. The retained oxide layer forms the second isolation dielectric layer 33b, which is used to isolate the Schottky barrier metal layer and the ohmic contact metal layer to be formed in the subsequent steps.

[0083] S14. A metal layer is deposited on the surface of the entire structure formed after step S13. After alloying, the metal layer forms the functional metal layer 40. The part of the functional metal layer in contact with the upper surface of the epitaxial layer of the mesa structure 30a forms the Schottky barrier contact, i.e., the Schottky barrier metal layer 40a. The part of the functional metal layer in contact with the upper surface of the conductive polysilicon filled in the trench forms the ohmic contact, i.e., the ohmic contact metal layer 40b. The cross-sectional view of the structure at this time is shown in FIG. 5. Figure 9

[0084] S15. An anode metal layer 50 is deposited on the surface of the entire structure formed after step S13.

[0085] S16. The substrate is thinned by grinding and etching the lower surface of the substrate, and a cathode metal layer 10 is deposited on the lower surface of the substrate. The fabrication of the trench Schottky barrier diode of the embodiment is completed, and the overall structure of the diode is shown in the cross-sectional view of FIG. 6. Figure 3

[0086] ​​​​Example 2

[0087] The difference from Example 1 is that the inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped trench 31 is 0.5 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 1.0 microns. The thickness of the first upper isolation medium layer 33a covering the inner wall of the upper cylindrical opening is 0.1 microns, and the thickness of the first lower isolation medium layer 34 covering the inner wall of the lower cylindrical opening is 0.4 microns.

[0088] Other process steps, parameters, etc. are the same as in Example 1.

[0089] Example 3

[0090] The difference from Example 1 is that the inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped trench 31 is 0.15 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 0.25 microns. The thickness of the first upper isolation medium layer 33a covering the inner wall of the upper cylindrical opening is 0.05 microns, and the thickness of the first lower isolation medium layer 34 covering the inner wall of the lower cylindrical opening is 0.1 microns.

[0091] Other process steps, parameters, etc. are the same as in Example 1.

[0092] Example 4

[0093] The difference from Example 1 is that the inner diameter (lateral opening size) of the upper cylindrical opening 31a in the stepped trench 31 is 0.5 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening 31b is 2.0 microns. The thickness of the first upper isolation medium layer 33a covering the inner wall of the upper cylindrical opening is 0.15 microns, and the thickness of the first lower isolation medium layer 34 covering the inner wall of the lower cylindrical opening is 0.6 microns.

[0094] Other process steps, parameters, etc. are the same as in Example 1.

[0095] The above description is only a preferred embodiment of the present application, and is not intended to limit the present application in any form. Any skilled person in the art, without departing from the technical solution of the present application, can make many possible changes and modifications to the technical solution of the present application by using the disclosed methods and technical contents, or modify equivalent embodiments with equivalent changes, to achieve the above effects. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, all within the scope of the technical solution of the present application.

Claims

1. A trench Schottky barrier diode, characterized by, The semiconductor device comprises: a first conductive type heavily doped semiconductor substrate; a first conductive type lightly doped semiconductor epitaxial layer on the top surface of the substrate; a series of periodically arranged trenches in the epitaxial layer, opening on the top surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent trenches forms a mesa structure; a first conductive type heavily doped conductive polysilicon filled in the trenches; a first isolation dielectric layer on the inner wall of the trenches and used to isolate the conductive polysilicon and the epitaxial layer; a Schottky barrier metal layer covering the top surface of the mesa structure region of the epitaxial layer; an ohmic contact metal layer covering the top surface of the conductive polysilicon; a second isolation dielectric layer formed by upward extension of the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer; an anode metal layer covering the top surface of the Schottky barrier diode; and a cathode metal layer on the bottom surface of the substrate, which forms an ohmic contact with the bottom surface of the substrate; wherein the trenches are composed of two cylindrical openings in communication with each other, and the lateral opening size of the upper cylindrical opening is smaller than that of the lower cylindrical opening, and a step is formed at the communication part of the two openings; wherein the first isolation dielectric layer is composed of a first upper isolation dielectric layer and a first lower isolation dielectric layer; the first upper isolation dielectric layer is on the inner wall of the upper cylindrical opening of the trench and is used to isolate the epitaxial layer constituting the inner wall of the upper cylindrical opening and the conductive polysilicon; the first lower isolation dielectric layer is on the inner wall of the lower cylindrical opening of the trench and is used to isolate the epitaxial layer constituting the inner wall of the lower cylindrical opening and the conductive polysilicon; and the thickness of the first upper isolation dielectric layer is smaller than that of the first lower isolation dielectric layer.

2. The trench Schottky barrier diode of claim 1, wherein: The lateral opening size of the upper cylindrical opening is 0.1-0.5 microns.

3. The trench Schottky barrier diode of claim 2, wherein: The lateral opening size of the lower cylindrical opening is 0.2-2 microns, and the difference between the lateral opening size of the lower cylindrical opening and that of the upper cylindrical opening is greater than or equal to 0.1 micron.

4. The trench Schottky barrier diode of claim 3, wherein: The thickness of the first upper isolation dielectric layer is 0.05-0.15 microns.

5. The trench Schottky barrier diode of claim 4, wherein: The thickness of the first lower isolation dielectric layer is 0.1-0.6 microns, and the difference between the two is greater than or equal to 0.01 micron.

6. The trench Schottky barrier diode of claim 1, wherein: The thickness of the first upper isolation dielectric layer and the second isolation dielectric layer is consistent.

7. The trench Schottky barrier diode of claim 1, wherein: There is a second conductive type ion implantation region in the epitaxial layer region at the bottom of the trench.

8. The trench Schottky barrier diode of claim 1, wherein: The upper cylindrical opening and the lower cylindrical opening of the trench are both cylindrical openings.

Images