Step-shaped groove Schottky barrier diode

Abstract

The diode comprises a cathode metal layer, a substrate, an epitaxial layer, a functional metal layer and an anode metal layer from bottom to top, step-shaped grooves are distributed in the epitaxial layer, each groove is composed of an upper cylindrical opening and a lower cylindrical opening, the upper cylindrical opening is small, the lower cylindrical opening is large, and the functional metal layer and the anode metal layer are arranged on the substrate. Conductive polycrystalline silicon is arranged in the groove, the dielectric layer isolates the conductive polycrystalline silicon from the epitaxial layer, the Schottky barrier region and the anode electrode region, and the epitaxial layer at the bottom of the groove further comprises an ion implantation region. According to the utility model, the grooves and the upper cylindrical small openings increase the conductive area during forward conduction, reduce the forward conduction current density, reduce the forward conduction voltage drop, and improve the forward conduction performance; the lower cylindrical opening is large, so that the point discharge effect during reverse bias of the device is avoided, the reverse blocking performance of the device is improved, and the reliability and the service life of the device are improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor device, especially to a Schottky barrier diode of semiconductor discrete device. BACKGROUND

[0002] Rectifier devices are required to have unidirectional conduction characteristics, i.e. low forward voltage and low on-resistance in forward conduction, and high blocking voltage and low reverse leakage in reverse bias. Schottky barrier diodes have been used as rectifier devices for decades in power supply applications. Because of their low forward voltage and fast switching speed, they are very suitable for use in switching power supplies and high frequency applications.

[0003] Schottky barrier diodes are made by using the principle of metal-semiconductor junction formed by the contact of metal and semiconductor. Conventional planar Schottky barrier diode devices are usually formed by low doped N-epitaxial layer and metal layer deposited on the top surface to form Schottky barrier contact. The difference between the work function of metal and N-type single crystal silicon forms the barrier, and the height of the barrier determines the characteristics of the Schottky barrier diode. Lower barrier can reduce the forward conduction opening voltage, but will increase the reverse leakage and reduce the reverse blocking voltage. On the contrary, higher barrier will increase the forward conduction opening voltage, and at the same time, reduce the reverse leakage and enhance the reverse blocking capability. However, the conventional planar Schottky barrier diode has high reverse leakage and low reverse blocking voltage in general. In view of the above problems, trench Schottky barrier diode is invented, which has low forward conduction opening voltage and overcomes the shortcomings of the above-mentioned planar Schottky diode.

[0004] The significant feature of the trench Schottky barrier diode is that there are several trenches extending into the N-epitaxial layer in the N-epitaxial layer, an oxide layer covering the surface of the trench, and a conductive material filling therein. For example, US 5,365,102 discloses a trench Schottky barrier diode, in which the device structure of one embodiment is shown in the attached figure. Figure 1The shown is a trench Schottky barrier diode structure commonly used in the prior art. As can be seen from the figure, the silicon wafer for manufacturing the diode is composed of a highly doped N+ substrate 301 and a lower doped N- epitaxial layer 302, a series of trenches 303 are prepared in the N- epitaxial layer 302, the N-type single crystal silicon mesa structure 304 is between the trenches 303, the silicon dioxide layer 305 is grown on the sidewall of the trench 303, the metal layer 306 is covered on the upper surface of the entire structure and contacts the top surface of the single crystal silicon mesa structure 304 to form a Schottky barrier contact; the cathode metal layer 307 is deposited on the bottom surface of the N+ substrate 301. Due to the existence of the composite structure composed of the trench 303, the silicon dioxide layer 305 and the conductive material 306 in the trench, the electric field distribution changes when the device is reversely biased, the electric field intensity at the bottom of the trench appears a peak value, the free carriers in the mesa structure 304 are completely depleted, and the electric field intensity reaching the Schottky barrier is reduced, thereby the voltage reverse blocking capability of the device is enhanced, and the reverse leakage current is reduced.

[0005] However, the trench Schottky barrier diode structure in the prior art still has some problems, and the main problems exposed include: 1) when forward conducting, the area occupied by the trench structure cannot conduct current, causing current crowding in the semiconductor of the mesa, so that the forward conducting voltage drop of the trench Schottky diode becomes large; 2) when reversely biased, the electric field intensity at the bottom of the trench is the largest, the curvature radius of the bottom structure is small, or the thickness of the oxide layer at the bottom of the trench is thin or uneven due to the limitation of the step coverage capability, which can all cause uneven distribution of the electric field intensity and too high local electric field intensity; the reverse voltage drop blocking capability of the device is reduced, and the reliability and service life of the device are reduced; 3) when reversely biased, complete depletion in the mesa needs to be achieved to obtain the required reverse leakage current and the reliability and service life of the device.

[0006] As can be seen, the existing trench Schottky barrier diode structure still has some defects, and the performance needs to be further optimized, the reliability of the device needs to be improved, and the manufacturing method of the device needs to be simplified to reduce the cost. Content of the utility model

[0007] In view of the defects of the prior art, the purpose of the utility model is to provide a Schottky barrier diode, which aims to improve the above-mentioned defects of the existing trench Schottky barrier diode, further improve the performance and reliability of the device, and optimize the manufacturing cost.

[0008] In order to achieve the above-mentioned purpose, the utility model adopts the following technical scheme.

[0009] The utility model provides a step-shaped trench Schottky barrier diode first, which comprises:

[0010] The first conductive type heavily doped semiconductor substrate;

[0011] a lightly doped semiconductor epitaxial layer of a first conductivity type on the upper surface of the substrate;

[0012] a series of periodically arranged stepped trenches in the epitaxial layer, opening on the upper surface of the epitaxial layer and extending into the epitaxial layer, wherein the epitaxial layer between adjacent trenches forms a mesa structure;

[0013] a heavily doped conductive polysilicon of the first conductivity type filled in the trenches;

[0014] a first isolation dielectric layer on the inner walls of the trenches and used to isolate the conductive polysilicon and the epitaxial layer;

[0015] a Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region;

[0016] an ohmic contact metal layer covering the upper surface of the conductive polysilicon;

[0017] a second isolation dielectric layer formed by upward extension of the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer;

[0018] an anode metal layer covering the upper surface of the Schottky barrier diode;

[0019] and a cathode metal layer on the lower surface of the substrate, the lower surface of the substrate and the cathode metal layer forming an ohmic contact.

[0020] Further, the trenches are composed of two cylindrical openings in communication with each other, and the lateral opening size of the upper cylindrical opening is smaller than that of the lower cylindrical opening, and a step is formed at the communication part.

[0021] Further, there is a second conductivity type ion implantation region in the epitaxial layer region at the bottom of the trench.

[0022] The cross sections of the upper and lower cylindrical openings of the trench are circular. The opening structure of the upper small cylindrical shape maximizes the area of the Schottky barrier region of the mesa structure; at the same time, in order to improve the enhancement of sharp discharge possibly formed by the reduction of the upper opening, the lower cylindrical lateral opening of the trench is widened to form a structure with an enlarged curvature radius at the bottom of the trench, thereby avoiding the enhancement of sharp discharge.

[0023] Further, the lateral opening size of the upper cylindrical opening is 0.1-0.5 microns, and the lateral opening size of the lower cylindrical opening is 0.2-2 microns, and the difference between the lateral opening size of the lower cylindrical opening and that of the upper cylindrical opening is greater than or equal to 0.1 micron.

[0024] Further, the isolation medium layer is an oxide layer.

[0025] Further, the first isolation medium layer has a uniform thickness on the inner wall of the upper columnar opening and the inner wall of the lower columnar opening.

[0026] Further, the first isolation medium layer has a thickness of 0.05-0.25 microns.

[0027] Further, a cavity exists in the conductive polysilicon in the lower columnar opening of the trench, and the cavity is formed during deposition of the conductive polysilicon.

[0028] The Schottky barrier metal layer and the ohmic contact metal layer are formed by alloying of the same metal deposited synchronously.

[0029] Further, the first conductive type is N type, and the second conductive type is P type.

[0030] The utility model also provides a manufacturing method of the step-shaped trench Schottky barrier diode.

[0031] S1. growing a first conductive type lightly doped semiconductor epitaxial layer on a first conductive type heavily doped semiconductor substrate.

[0032] S2. forming a first medium layer on the upper surface of the epitaxial layer, performing photoetching on the first medium layer to define an upper columnar opening pattern, selectively removing the first medium layer not protected by the photoresist to expose the epitaxial layer corresponding to the upper columnar opening pattern, and then removing the photoresist on the first medium layer; the first medium layer remaining after removal of the photoresist is used as a first medium hard mask.

[0033] S3. using the first medium hard mask as protection, selectively etching the exposed epitaxial layer by dry etching to form the upper columnar opening in the trench in the epitaxial layer. Thus, the mesa structure with a certain width is formed between the upper columnar openings, and the upper surface of the mesa structure is still covered by the first medium hard mask.

[0034] S4. forming a second medium layer on the surface of the entire structure.

[0035] S5. Selectively etching the second dielectric layer by dry etching method to expose the epitaxial layer at the bottom of the upper columnar opening, while the second dielectric layer above the first dielectric layer is also removed synchronously; at this time, the upper surface of the mesa structure is still covered with the first dielectric layer, i.e. the first dielectric hard mask, and the second dielectric layer covering the sidewall of the upper columnar opening is used as the second dielectric hard mask.

[0036] S6. Selectively etching the exposed epitaxial layer by dry etching method with the protection of the first dielectric hard mask and the second dielectric hard mask.

[0037] S7. Continuously etching the exposed epitaxial layer by XeF2 dry etching method with the protection of the first dielectric hard mask and the second dielectric hard mask to form the lower columnar opening of the trench.

[0038] S8. Continuously implanting the second conductive type impurity into the exposed epitaxial layer by ion implantation method with the protection of the first dielectric hard mask and the second dielectric hard mask.

[0039] S9. Removing the second dielectric layer and the first dielectric layer by wet etching method.

[0040] S10. Growing an oxide layer on the surface of the entire structure formed after step S9, at this time, the oxide layer grown on the inner wall of the trench constitutes the first isolation dielectric layer; at the same time, the second conductive type impurity is diffused to form the ion implantation region during the heat process of oxide layer growth.

[0041] S11. Depositing conductive polysilicon on the surface of the entire structure formed after step S10; then selectively removing the conductive polysilicon outside the trench by dry etching method, and making the upper surface of the conductive polysilicon filled in the trench flush with the upper surface of the epitaxial layer of the mesa structure; due to the larger lateral opening size of the lower columnar opening than that of the upper columnar opening, a hollow will be formed in the conductive polysilicon inside the lower columnar opening during the polysilicon deposition process.

[0042] S12. Selectively removing the oxide layer on the surface of the mesa structure by dry etching or wet etching method, and retaining the oxide layer extending upwards and surrounding the upper surface opening of the trench, which constitutes the second isolation dielectric layer to isolate the Schottky barrier metal layer and the ohmic contact metal layer to be formed.

[0043] S13. After the step S12, a first metal layer is deposited on the whole structure surface, which forms a Schottky barrier contact with the upper surface of the mesa structure after alloying, i.e. the Schottky barrier metal layer, and forms an ohmic contact with the upper surface of the conductive polysilicon filled in the trench, i.e. the ohmic contact metal layer.

[0044] S14. After the step S13, an anode metal layer is deposited on the whole structure surface.

[0045] S15. The substrate is thinned by grinding and etching the lower surface of the substrate, and then a cathode metal layer is deposited on the lower surface of the substrate.

[0046] The beneficial effects of the present application are as follows.

[0047] Thanks to the above technical solution, the present application has the following advantages and effects compared with the prior art.

[0048] 1. The periodically arranged trenches present a stepped structure design with small upper opening and large lower opening, the horizontal size of the upper cylindrical opening of the trench is small, the chip area occupied by the non-conductive structure is reduced, the conductive semiconductor area during forward conduction is increased, the current density during forward conduction is reduced, the forward conduction voltage drop is reduced, the junction temperature during forward conduction is reduced, and thus the forward conduction performance, reliability and service life of the device are improved.

[0049] 2. The horizontal size of the upper cylindrical opening of the trench is small, and the horizontal size of the lower cylindrical opening is large, which avoids the possible deterioration of the sharp tip discharge effect of the trench bottom curvature radius during reverse bias of the device, and thus the reverse blocking performance, reliability and service life of the device are improved.

[0050] 3. The second conductive type injection region is arranged in the trench bottom epitaxial layer, which reduces the first conductive type doping concentration in the local area through compensation, assists the widening of the electric field intensity distribution in the bottom epitaxial layer during reverse bias of the device, and reduces the local area electric field intensity, and thus the reverse blocking performance, reliability and service life of the device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 is a trench Schottky barrier diode disclosed in US 5,365,102, which is also a schematic diagram of the structure of the trench Schottky barrier diode commonly used in the prior art.

[0052] wherein, Figure 1 in which 301 is N + substrate, 302 is N － epitaxial layer, 303 is a trench, 304 is an N-type monocrystalline silicon mesa structure, 305 is a silicon dioxide layer, 306 is a metal layer, and 307 is a cathode metal layer.

[0053] Figure 2 This is a top view schematic diagram of a Schottky barrier diode manufactured according to various embodiments of this utility model.

[0054] Figure 3 The Schottky barrier diodes in various embodiments of this utility model are Figure 2 A schematic diagram of the cross-sectional structure at positions A1-A2.

[0055] Figure 4 This is a cross-sectional schematic diagram of the device structure formed after step S4 in Embodiment 1 of this utility model.

[0056] Figure 5 This is a cross-sectional schematic diagram of the device structure formed after step S8 in Embodiment 1 of this utility model.

[0057] Figure 6 This is a cross-sectional schematic diagram of the device structure formed after step S11 in Embodiment 1 of this utility model.

[0058] Figure 7 This is a cross-sectional schematic diagram of the device structure formed after step S13 in Embodiment 1 of this utility model.

[0059] in, Figures 2-7 In the middle: 10 is the cathode metal layer, 20 is the first conductivity type heavily doped substrate, 30 is the first conductivity type lightly doped epitaxial layer, 30a is the mesa structure, 31 is the stepped trench, 31a is the upper cylindrical opening, 31b is the lower cylindrical opening, 32 is the conductive polycrystalline silicon, 33 is the isolation oxide layer, 34 is the void, 35 is the ion implantation region, 35a is the second conductivity type doped impurity, 40 is the functional metal layer, 40a is the Schottky barrier metal layer, 40b is the ohmic contact metal layer, 50 is the anode metal layer; 61 is the first dielectric layer, 62 is the second dielectric layer. Detailed Implementation

[0060] To more clearly illustrate the technical solution and purpose of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] like Figure 2 This is a top view schematic diagram of the stepped trench Schottky barrier diode fabricated according to various embodiments of this utility model. Figure 3 For the Schottky barrier diodes in each embodiment Figure 2 A schematic diagram of the cross-sectional structure at positions A1-A2. From... Figures 2-3It can be seen that the Schottky barrier diode of the utility model comprises cathode metal layer 10, semiconductor first conductive type heavily doped substrate 20, semiconductor first conductive type lightly doped epitaxial layer 30, functional metal layer 40 and anode metal layer 50 from bottom to top, which covers the top layer of the Schottky barrier diode structure; further comprising a series of step-shaped grooves 31 in the epitaxial layer 30, the step-shaped grooves 31 are opened on the upper surface of the epitaxial layer 30 and extend into the epitaxial layer 30; from Figure 2 、 Figure 3 It can be seen that the step-shaped groove in the figure is composed of two cylindrical openings in communication from top to bottom, the inner diameter (i.e. the lateral opening size) of the upper cylindrical opening 31a is smaller than the inner diameter (i.e. the lateral opening size) of the lower cylindrical opening 31b; the first conductive type heavily doped conductive polysilicon 32 is filled in the groove, a layer of isolation oxide layer 33 is covered on the inner wall of the step-shaped groove 31 as the first isolation medium layer, which is used to isolate the conductive polysilicon 32 and the epitaxial layer constituting the inner wall of the groove, and an unfilled cavity 34 is contained in the interior of the conductive polysilicon 32 located in the lower cylindrical opening; a second conductive type ion implantation region 35 is contained in the epitaxial layer close to the bottom of the step-shaped groove 31. Among them, the epitaxial layer between adjacent grooves forms a mesa structure 30a, the functional metal layer 40 covering the upper surface of the mesa structure 30a is the Schottky barrier metal layer 40a which forms a Schottky barrier contact with the epitaxial layer; and the functional metal layer 40 covering the upper surface of the conductive polysilicon 32 is the ohmic contact metal layer 40b which forms an ohmic contact with the heavily doped conductive polysilicon; the isolation oxide layer 33 extends upwardly between the Schottky barrier metal layer 40a and the ohmic contact metal layer 40b, constituting the second isolation medium layer used to isolate the two.

[0062] Next, the step-shaped groove Schottky barrier diode of the utility model and the specific manufacturing process thereof will be described in more detail through specific examples.

[0063] Example 1

[0064] In this embodiment, the heavily doped substrate is N+ monocrystalline silicon wafer, the epitaxial layer is lightly doped N- silicon epitaxial layer grown on the N+ monocrystalline silicon wafer, the ion implantation region is P-type ion implantation region, and the silicon oxide layer is isolation oxide layer. The inner diameter (lateral opening size) of the upper cylindrical opening in the step-shaped groove is 0.25 microns, and the inner diameter (lateral opening size) of the lower cylindrical opening is 0.5 microns. The thickness of the isolation oxide layer is 0.1 microns.

[0065] The process flow for specifically manufacturing the groove Schottky barrier diode of this embodiment is as follows:

[0066] S1. Prepare semiconductor first conductive type heavily doped substrate N+ monocrystalline silicon wafer, and grow first conductive type lightly doped epitaxial layer N- silicon epitaxial layer 30 on the substrate 20.

[0067] S2. Form a first dielectric layer 61 on the surface of the epitaxial layer, perform photoetching on the first dielectric layer, define an upper cylindrical opening 31a pattern, selectively remove the first dielectric layer not protected by the photoresist, expose the epitaxial layer corresponding to the upper cylindrical opening pattern, and then remove the photoresist on the first dielectric layer; use the first dielectric layer remaining after the photoresist is removed as a first dielectric hard mask.

[0068] S3. Use the first dielectric hard mask as protection, and selectively etch the exposed epitaxial layer 30 by dry etching to form an upper cylindrical opening 31a in the epitaxial layer in the stepped trench 31. Thus, a mesa structure 30a is formed in the epitaxial layer between the upper cylindrical openings. At this time, the mesa structure 30a is still covered by the first dielectric hard mask on the upper surface.

[0069] S4. Form a second dielectric layer 62 on the surface of the entire structure formed after step S3, and obtain a structure cross-sectional view as shown in Figure 4 .

[0070] S5. Selectively etch the second dielectric layer 62 by dry etching to expose the epitaxial layer at the bottom of the upper cylindrical opening 31a, and at the same time, the second dielectric layer 62 above the first dielectric layer 61 is also removed synchronously. At this time, the mesa structure 30a is still covered by the first dielectric layer 61, i.e., the first dielectric hard mask on the upper surface, and at this time, the second dielectric layer 62 covering the sidewall of the upper cylindrical opening 31a is used as a second dielectric hard mask.

[0071] S6. Use the first dielectric hard mask and the second dielectric hard mask as protection, and selectively etch the exposed epitaxial layer by dry etching.

[0072] S7. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and selectively etch the exposed epitaxial layer by dry etching with xenon difluoride to form a lower cylindrical opening 31b of the stepped trench 31.

[0073] S8. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and implant second-conductivity-type dopant 35a into the exposed epitaxial layer by ion implantation. At this time, obtain a structure cross-sectional view as shown in Figure 5 .

[0074] S9. Selectively remove the second dielectric layer 62 and the first dielectric layer 61 by wet etching.

[0075] S10. Growth of isolation oxide layer 33 on the surface of the whole structure formed after step S9, at this time the isolation oxide layer grown on the inner wall of the trench constitutes the first isolation medium layer; meanwhile the diffusion of the second conductive type doped impurities 35a mentioned above is formed into ion implantation region 35 during the thermal process of the growth of the isolation oxide layer.

[0076] S11. Deposition of conductive polysilicon 32 on the surface of the whole structure formed after step S10; then selective removal of the conductive polysilicon outside the trench by dry etching, and making the upper surface of the conductive polysilicon 32 filled in the trench flush with the upper surface of the epitaxial layer of mesa structure 30a; due to the lateral opening size of the lower cylindrical opening being larger than that of the upper cylindrical opening, a cavity 34 will be formed inside the conductive polysilicon in the lower cylindrical opening during the polysilicon deposition process. At this time the structure cross-sectional schematic diagram is as shown in Figure 6 .

[0077] S12. Selective removal of the isolation oxide layer on the surface of mesa structure 30a by dry etching, and retaining the isolation oxide layer extending upward from the first isolation medium layer and surrounding the upper surface opening of the trench, i.e. retaining the isolation oxide layer 33 constituting the second isolation medium layer, for isolating the Schottky barrier metal layer and the ohmic contact metal layer to be formed in the following steps.

[0078] S13. Deposition of a metal layer on the surface of the whole structure after step S12, after alloying process, the functional metal layer 40 is formed; wherein the part of functional metal layer 40 in contact with the upper surface of the epitaxial layer of mesa structure 30a forms the Schottky barrier contact, i.e. Schottky barrier metal layer 40a; the part of functional metal layer 40 in contact with the upper surface of the conductive polysilicon filled in the trench forms the ohmic contact, i.e. ohmic contact metal layer 40b. At this time the structure cross-sectional schematic diagram is as shown in Figure 7 .

[0079] S14. Deposition of anode metal layer 50 on the surface of the whole structure after step S13.

[0080] S15. Substrate thinning by grinding and etching the lower surface of the substrate, and then deposition of cathode metal layer 10 on the lower surface of the substrate. The fabrication of the Schottky barrier diode of the present embodiment is completed, and the overall structure of the diode is as shown in the cross-sectional schematic diagram Figure 3 .

[0081] Embodiment 2

[0082] The difference from Example 1 is that the inner diameter (lateral opening dimension) of the upper cylindrical opening in the stepped trench is 0.5 microns, and the inner diameter (lateral opening dimension) of the lower cylindrical opening is 1.0 microns. The isolation oxide layer thickness is 0.2 microns. Other process steps, parameters, etc. are the same as in Example 1.

[0083] Example 3

[0084] The difference from Example 1 is that the inner diameter (lateral opening dimension) of the upper cylindrical opening in the stepped trench is 0.15 microns, and the inner diameter (lateral opening dimension) of the lower cylindrical opening is 0.25 microns. The isolation oxide layer thickness is 0.05 microns. Other process steps, parameters, etc. are the same as in Example 1.

[0085] Example 4

[0086] The difference from Example 1 is that the inner diameter (lateral opening dimension) of the upper cylindrical opening in the stepped trench is 0.5 microns, and the inner diameter (lateral opening dimension) of the lower cylindrical opening is 2.0 microns. The isolation oxide layer thickness is 0.15 microns. Other process steps, parameters, etc. are the same as in Example 1.

[0087] The above only describes preferred embodiments of the present application and is not intended to limit the present application in any form. Any person skilled in the art, without departing from the technical scheme of the present application, can make many possible changes and modifications to the technical scheme of the present application, or modify equivalent embodiments of equivalent changes, to achieve the above effects. Therefore, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present application, all still belong to the scope of protection of the technical scheme of the present application.

Claims

1. A stepped trench Schottky barrier diode, characterized by, The Schottky barrier diode comprises: a first conductive type heavily doped semiconductor substrate; a first conductive type lightly doped semiconductor epitaxial layer on the upper surface of the substrate; a series of periodically arranged stepped trenches in the epitaxial layer, opening on the upper surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent trenches forms a mesa structure; a first conductive type heavily doped conductive polysilicon filled in the trenches; a first isolation dielectric layer on the inner wall of the trenches and used to isolate the conductive polysilicon and the epitaxial layer; a Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region; an ohmic contact metal layer covering the upper surface of the conductive polysilicon; a second isolation dielectric layer formed by upward extension of the first isolation dielectric layer, and isolating the Schottky barrier metal layer and the ohmic contact metal layer; an anode metal layer covering the upper surface of the Schottky barrier diode; and a cathode metal layer on the lower surface of the substrate, forming an ohmic contact with the lower surface of the substrate; wherein the stepped trenches are composed of two cylindrical openings in communication with each other, and the lateral opening size of the upper cylindrical opening is smaller than that of the lower cylindrical opening, and a step is formed at the communication part.

2. The stepped trench Schottky barrier diode of claim 1, wherein: There is a second conductive type ion implantation region in the epitaxial layer region at the bottom of the trench.

3. The stepped trench Schottky barrier diode of claim 1, wherein: The thickness of the first isolation dielectric layer on the inner wall of the upper cylindrical opening and the inner wall of the lower cylindrical opening is uniform.

4. The stepped trench Schottky barrier diode of claim 1, wherein: The lateral opening size of the upper cylindrical opening is 0.1-0.5 microns.

5. The stepped trench Schottky barrier diode of claim 4, wherein: The lateral opening size of the lower cylindrical opening is 0.2-2 microns, and the difference between the lateral opening size of the lower cylindrical opening and the lateral opening size of the upper cylindrical opening is greater than or equal to 0.1 micron.

6. The stepped trench Schottky barrier diode of claim 5, wherein: The thickness of the first isolation dielectric layer is 0.05-0.25 microns.

7. The stepped trench Schottky barrier diode of claim 1, wherein: the first and second Schottky regions are formed of a metal selected from the group consisting of aluminum, titanium, platinum, nickel, gold, silver, and combinations thereof. Both the upper cylindrical opening and the lower cylindrical opening of the trench are cylindrical openings.

Images