MEMS device and electronic device
By setting through holes and cavities in MEMS devices, the parasitic capacitance between the diaphragm and the substrate and backplane layers is reduced, solving the problem of interference with the signal-to-noise ratio of MEMS microphones and achieving an improvement in the signal-to-noise ratio.
Patent Information
- Application Number
- CN202423318474.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In existing MEMS microphones, the signal-to-noise ratio is affected by parasitic capacitance interference between the diaphragm and the substrate and backplate layer.
In MEMS devices, through-holes and cavities are formed by setting spaced wire regions on the outside of the diaphragm and backplane layers, thereby reducing parasitic capacitance. A wet etching process is used to release part of the sacrificial layer to form the cavity, further reducing capacitance.
This effectively reduces the parasitic capacitance of MEMS devices and improves the signal-to-noise ratio.
Smart Images
Figure CN223694004U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a MEMS device and electronic apparatus. Background Technology
[0002] MEMS microphones, fabricated using microelectromechanical systems (MEMS) technology, are widely used in voice communication, hearing aids, and noise control devices due to their advantages over traditional microphones, such as smaller size, lower cost, and more stable performance. Among these, capacitive MEMS microphones are frequently used because of their high signal-to-noise ratio and excellent stability.
[0003] However, as Figure 1 As shown, a MEMS microphone in the related technology generally includes a substrate 10, a diaphragm 11, a backplate layer 12, and a cavity 13. Among them, the diaphragm 11 located outside the cavity 13 generates capacitance between itself and the substrate 10, and the backplate layer 12 located outside the cavity 13 also generates parasitic capacitance between itself and the diaphragm 11 and between itself and the substrate 10, thereby interfering with the MEMS microphone and affecting the signal-to-noise ratio of the MEMS microphone. Utility Model Content
[0004] The utility model description section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To at least partially solve the above-mentioned technical problems, this application provides a MEMS device, comprising:
[0006] A substrate, the substrate comprising a first surface and a second surface opposite to the first surface;
[0007] A first sacrificial layer is located on a portion of the first surface of the substrate;
[0008] A diaphragm is located above the first surface, and a first sacrificial layer is disposed between a portion of the diaphragm and the substrate;
[0009] The second sacrificial layer is located partially on the diaphragm;
[0010] A backplate layer is partially located on the second sacrificial layer, and a cavity is formed between the backplate layer and the diaphragm;
[0011] The back cavity extends from the second surface of the substrate through the substrate and the first sacrificial layer, and exposes a portion of the surface of the diaphragm;
[0012] The MEMS device comprises a first conductive region and a second conductive region arranged at intervals outside the cavity. The vibrating diaphragm of the first conductive region is formed with at least one first through hole penetrating the vibrating diaphragm, and each first through hole is correspondingly formed with a first inner cavity in the first sacrificial layer below the first through hole. The backplate layer of the second conductive region is formed with at least one second through hole penetrating the backplate layer, and each second through hole is correspondingly formed with a second inner cavity in the second sacrificial layer below the second through hole.
[0013] Exemplarily, the first inner cavity penetrates the first sacrificial layer and exposes a partial first surface of the substrate.
[0014] The second inner cavity penetrates the second sacrificial layer and exposes a partial surface of the vibrating diaphragm.
[0015] Exemplarily, a partial second through hole and a partial second inner cavity are located outside the vibrating diaphragm and away from the cavity.
[0016] Exemplarily, the first through hole and the second through hole are cylindrical through holes.
[0017] The first inner cavity and the second inner cavity are inverted circular truncated cone-shaped inner cavities.
[0018] Exemplarily, a plurality of second through holes and a plurality of second inner cavities are arranged along a first direction and a second direction. Adjacent second inner cavities along the first direction are spaced apart or the side walls of adjacent second inner cavities along the first direction are in contact. Adjacent second inner cavities along the second direction are spaced apart or the side walls of adjacent second inner cavities along the second direction are in contact. The first direction is perpendicular to the second direction.
[0019] Exemplarily, the second conductive region is a rectangular region. The first direction is the length direction of the second conductive region, and the second direction is the width direction of the second conductive region.
[0020] Exemplarily, the backplate layer of the first conductive region is formed with an isolation hole penetrating the backplate layer, and the isolation hole electrically isolates the backplate layer of the first conductive region from the backplate layer of other regions. The isolation hole is in communication with the first through hole and the first inner cavity.
[0021] Exemplarily, the first conductive region is further formed with a first pad, the first pad is electrically connected to the vibrating diaphragm, and the first through hole is located between the first pad and the cavity.
[0022] A second pad is also formed in the second wire region, the second pad is electrically connected to the back plate layer, and the second via is located between the second pad and the cavity.
[0023] Exemplarily, the back plate layer comprises a first dielectric layer, a conductive layer and a second dielectric layer stacked from bottom to top, wherein a side of the first dielectric layer located above the cavity is formed with a plurality of protrusions, and the first dielectric layer further comprises an etching stop layer in contact with the surface of the diaphragm, the etching stop layer is located at the four peripheral edges of the cavity to define the boundary of the cavity.
[0024] Another aspect of the present application also provides an electronic device comprising the above-mentioned MEMS device.
[0025] The MEMS device and the electronic device of the present application, the diaphragm in the first wire region is formed with at least one first via penetrating the diaphragm, and a first inner cavity corresponding to each first via is formed in the first sacrificial layer below each first via, and / or the back plate layer in the second wire region is formed with at least one second via penetrating the back plate layer, and a second inner cavity corresponding to each second via is formed in the second sacrificial layer below each second via, compared with the related art in which the first inner cavity and the second inner cavity remain the sacrificial layer, the present application can reduce the parasitic capacitance of the MEMS device, thereby reducing the interference of the parasitic capacitance on the MEMS device and improving the signal-to-noise ratio. BRIEF DESCRIPTION OF DRAWINGS
[0026] The following drawings of the present application are hereby incorporated as a part of the present application for understanding the present application. The embodiments of the present application and the description thereof shown in the drawings are used to explain the principles of the present application.
[0027] In the drawings:
[0028] Figure 1 A cross-sectional schematic view of a MEMS device in the related art is shown;
[0029] Figures 2A-2C Cross-sectional schematic views of a MEMS device obtained by sequentially implementing a manufacturing method of the MEMS device of an exemplary embodiment of the present application are shown;
[0030] Figure 3 A top view schematic view of a MEMS device of an exemplary embodiment of the present application is shown.
[0031] Reference signs:
[0032] 10, substrate; 11, diaphragm; 12, back plate layer; 13, cavity;
[0033] 100, substrate; 101, first sacrificial layer; 102, diaphragm; 103, first via; 104, vent hole; 105, second sacrificial layer; 106, backplate layer; 1061, first dielectric layer; 1062, conductive layer; 1063, second dielectric layer; 1064, etch stop layer; 107, second via; 108, release hole; 109, isolation hole; 110, first pad; 111, second pad; 112, first inner cavity; 113, second inner cavity; 114, cavity; 115, back cavity. DETAILED DESCRIPTION
[0034] The present application will be described in more detail with reference to the drawings, in which embodiments of the application are shown. The application may, however, be embodied in different forms without departing from the spirit thereof. Rather, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the application. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. Like reference numbers signify like elements throughout.
[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature would then be oriented "above" and "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0037] The embodiments of the application will be described in the following description with reference to the schematic cross sectional views of the drawings accompanying the application. It is to be understood that the drawings are schematic and that the shape of the elements shown in the figures can vary due to, for example, manufacturing techniques and / or tolerances.
[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0039] For a thorough understanding of the application, a detailed description will be made in the following description with reference to the following detailed description. The preferred embodiments of the application are described in detail as follows, however, the application can have other embodiments in addition to these detailed descriptions.
[0040] Therefore, in view of the foregoing technical problems, the application proposes a MEMS device, comprising:
[0041] a substrate, the substrate comprising a first surface and a second surface opposite to the first surface;
[0042] a first sacrificial layer located on a part of the first surface of the substrate;
[0043] a diaphragm located above the first surface, and a part of the diaphragm is provided with the first sacrificial layer between the diaphragm and the substrate;
[0044] a second sacrificial layer partially located on the diaphragm;
[0045] a backplate layer partially located on the second sacrificial layer, and a cavity is formed between the backplate layer and the diaphragm;
[0046] a back cavity, penetrating the substrate and the first sacrificial layer from the second surface of the substrate and exposing a part of the surface of the diaphragm;
[0047] In the MEMS device, the first wire region is provided with at least one first through hole penetrating the diaphragm, and each first through hole is correspondingly provided with a first inner cavity in the first sacrificial layer below the first through hole; and / or the second wire region is provided with at least one second through hole penetrating the back plate layer, and each second through hole is correspondingly provided with a second inner cavity in the second sacrificial layer below the second through hole.
[0048] In the MEMS device, the first wire region is provided with at least one first through hole penetrating the diaphragm, and each first through hole is correspondingly provided with a first inner cavity in the first sacrificial layer below the first through hole; and / or the second wire region is provided with at least one second through hole penetrating the back plate layer, and each second through hole is correspondingly provided with a second inner cavity in the second sacrificial layer below the second through hole.
[0049] Embodiment One
[0050] Hereinafter, the MEMS device in the embodiments of the present application will be described with reference to the accompanying drawings. Figure 2C In the embodiments of the present application, the MEMS device is described. Figure 3 The MEMS device in the embodiments of the present application will be described.
[0051] In one example, as shown in FIG. 1, the MEMS device 100 includes a substrate 101, a diaphragm 102, a back plate layer 103, a first sacrificial layer 104, a second sacrificial layer 105, a first wire region 106 and a second wire region 107. Figure 2CAs shown, the MEMS device of the present application comprises a substrate 100, a first sacrificial layer 101, a diaphragm 102, a second sacrificial layer 105, a backplate layer 106 and a back cavity 115, wherein: the substrate 100 comprises a first surface and a second surface opposite to the first surface; the diaphragm 102 is located above the first surface of the substrate 100, and the first sacrificial layer 101 is arranged between part of the diaphragm 102 and the substrate 100; the second sacrificial layer 105 is partially located on the diaphragm 102; the backplate layer 106 is partially located on the second sacrificial layer 105, and a cavity 114 is formed between the backplate layer 106 and the diaphragm 102; the back cavity 115 penetrates the substrate 100 and the first sacrificial layer 101 from the second surface of the substrate 100 and exposes part of the surface of the diaphragm 102. The MEMS device further comprises a first wire region and a second wire region arranged at intervals outside the cavity 114, the diaphragm 102 of the first wire region is formed with at least one first through hole 103 penetrating the diaphragm 102, and a first inner cavity 112 in the first sacrificial layer 101 is formed below each first through hole 103, and / or the backplate layer 106 of the second wire region is formed with at least one second through hole 107 penetrating the backplate layer 106, and a second inner cavity 113 in the second sacrificial layer 105 is formed below each second through hole 107.
[0052] In one example, the substrate 100 is a bulk silicon substrate, which can comprise at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 100 can also comprise silicon-on-insulator (SOI), silicon-on-silicon stacked insulator (SSOI), silicon germanium-on-silicon stacked insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI) or germanium-on-insulator (GeOI) and the like. Although several examples of materials that can form the substrate 100 are described herein, any material that can be used as the substrate 100 falls within the spirit and scope of the present application.
[0053] In one example, the first sacrificial layer 101 and the second sacrificial layer 105 are selected from oxide layers, such as silicon oxide and carbon-doped silicon oxide (SiOC) and the like, but are not limited to the above examples.
[0054] In one example, the diaphragm 102 can be selected from polysilicon, SiGe and the like, and is not limited to a certain type. Exemplarily, the diaphragm 102 is wrapped by a dielectric layer (for example, a silicon nitride layer), which plays a role of protecting the diaphragm 102.
[0055] In one example, as shown in FIG. 1, the diaphragm 102 is formed with a plurality of first through holes 103, and the first sacrificial layer 101 is formed with a plurality of first inner cavities 112 corresponding to the first through holes 103. Figure 2CAs shown, the backplate layer 106 includes a first dielectric layer 1061, a conductive layer 1062, and a second dielectric layer 1063 stacked from bottom to top. The first dielectric layer 1061 located above the cavity 114 is formed with a plurality of protrusions on the side facing the cavity 114 to prevent the diaphragm 102 from sticking to the backplate layer 106 during vibration. The first dielectric layer 1061 further includes an etch stop layer 1064 in contact with the surface of the diaphragm 102, which is located around the edges of the cavity 114 to define the boundary of the cavity 114. The material of the conductive layer 1062 can be metal or N-type ion-doped polysilicon such as phosphorus-doped polysilicon or P-type ion-doped polysilicon such as boron-doped polysilicon, and is not limited to a specific type. In this embodiment, the material of the first dielectric layer 1061 and the second dielectric layer 1063 includes silicon nitride. In other embodiments, the material of the first dielectric layer 1061 and the second dielectric layer 1063 can also include inorganic insulating layers such as silicon oxide or silicon oxynitride, or organic insulating layers such as polyvinyl phenol, polyimide, or siloxane.
[0056] In one example, as shown in FIG. 1, the diaphragm 102 is formed with a vent hole 104 penetrating the diaphragm 102 corresponding to the portion of the cavity 114. The vent hole 104 can be used to balance the air pressure inside the MEMS device. Figure 2C Figure 2C As shown, the backplate layer 106 is formed with a release hole 108 penetrating the backplate layer 106 corresponding to the portion of the cavity 114. The release hole 108 is used to release the removed portion of the second sacrificial layer 105 to form the cavity 114.
[0057] In one example, the diaphragm 102 of the first conductive wire region and the substrate 100 can generate a parasitic capacitance, and the at least one first through hole 103 penetrating the diaphragm 102 of the first conductive wire region can reduce the area of the diaphragm 102 of the first conductive wire region and the substrate 100, and the parasitic capacitance is proportional to the area, so the first through hole 103 can reduce the parasitic capacitance generated between the diaphragm 102 of the first conductive wire region and the substrate 100; at the same time, a first inner cavity 112 in the first sacrificial layer 101 is formed below each first through hole 103, and the first inner cavity 112 is obtained by releasing part of the first sacrificial layer 101 through the corresponding first through hole 103, and the first inner cavity 112 can change the medium between the diaphragm 102 of the first conductive wire region and the substrate 100 to air, and the dielectric constant of air is close to 1, which is much smaller than the dielectric constant of the first sacrificial layer 101 (for example, the dielectric constant of silicon oxide is 3.9-4.5), and the parasitic capacitance generated between the diaphragm 102 of the first conductive wire region and the substrate 100 is proportional to the dielectric constant of the medium between the diaphragm 102 of the first conductive wire region and the substrate 100, so the first inner cavity 112 can reduce the parasitic capacitance generated between the diaphragm 102 of the first conductive wire region and the substrate 100. Therefore, the first through hole 103 and the first inner cavity 112 can both reduce the parasitic capacitance generated between the diaphragm 102 of the first conductive wire region and the substrate 100, thereby reducing the interference of the parasitic capacitance on the MEMS device and improving the signal-to-noise ratio.
[0058] In one example, the first inner cavity 112 penetrates the first sacrificial layer 101 and exposes part of the surface of the substrate 100, which can further reduce the parasitic capacitance generated between the diaphragm 102 of the first conductive wire region and the substrate 100.
[0059] In one example, as shown in Figure 2C , the first conductive wire region further forms a first pad 110, the first pad 110 is electrically connected to the diaphragm 102 to function as a lead-out of the diaphragm 102, and the first through hole 103 is located between the first pad 110 and the cavity 114.
[0060] In one example, parasitic capacitance is generated between the backplate layer 106 and the diaphragm 102 in the second conductor region. At least one second through-hole 107 penetrating the backplate layer 106 in the second conductor region can reduce the facing area between the backplate layer 106 and the diaphragm 102, thereby reducing the parasitic capacitance generated between the backplate layer 106 and the diaphragm 102 in the second conductor region. At the same time, a second inner cavity 113 is formed below each second through-hole 107 in the second sacrificial layer 105. The second inner cavity 113 is formed by... By releasing a portion of the second sacrificial layer 105 through the corresponding first through-hole 103, the second inner cavity 113 can convert the dielectric in a portion of the area between the backplate layer 106 and the diaphragm 102 in the second conductive region into air. The dielectric constant of air is close to 1, much smaller than that of the second sacrificial layer 105 (taking silicon oxide as an example, the dielectric constant of silicon oxide is 3.9-4.5). Therefore, the second inner cavity 113 can reduce the parasitic capacitance generated between the backplate layer 106 and the diaphragm 102 in the second conductive region. Thus, both the second through-hole 107 and the second inner cavity 113 can reduce the parasitic capacitance generated between the backplate layer 106 and the diaphragm 102 in the second conductive region, thereby reducing the interference of parasitic capacitance on MEMS devices and improving the signal-to-noise ratio.
[0061] In one example, the second inner cavity 113 penetrates the second sacrificial layer 105 and exposes part of the surface of the diaphragm 102, which can further reduce the parasitic capacitance generated between the backplate layer 106 and the diaphragm 102 in the second conductor region.
[0062] In one example, parasitic capacitance also occurs between the backplate layer 106 of the second conductor region and the portion of the substrate 100 located outside the diaphragm 102 and away from the cavity 114, such as Figure 2C As shown, a portion of the second through-hole 107 is located outside the diaphragm 102 and away from the cavity 114. This portion of the second through-hole 107 can reduce the parasitic capacitance generated between the backplate layer 106 of the second conductor region and the portion of the substrate 100 located outside the diaphragm 102 and away from the cavity 114. A portion of the second inner cavity 113 is located outside the diaphragm 102 and away from the cavity 114. This portion of the second inner cavity 113 can also reduce the parasitic capacitance generated between the backplate layer 106 of the second conductor region and the portion of the substrate 100 located outside the diaphragm 102 and away from the cavity 114. Exemplarily, the second inner cavity 113 located outside the diaphragm 102 and away from the cavity 114 can also penetrate the second sacrificial layer 105. Furthermore, the second inner cavity 113 located outside the diaphragm 102 and away from the cavity 114 can also partially extend into or even penetrate the first sacrificial layer 101.
[0063] In one example, such as Figure 2CAs shown, a second pad 111 is also formed in the second wire region, the second pad 111 is electrically connected to the back plate layer 106 to serve as a lead-out of the back plate layer 106, and the second via hole 107 is located between the second pad 111 and the cavity 114. Exemplarily, the second pad 111 is electrically connected to the conductive layer 1062.
[0064] In one example, the first via hole 103 and the second via hole 107 are cylindrical via holes, and the first inner cavity 112 and the second inner cavity 113 are inverted circular truncated cone-shaped inner cavities.
[0065] In one example, the first inner cavity 112 is obtained by releasing part of the first sacrificial layer 101 through the corresponding first via hole 103. In this case, a wet etching process can be used to remove part of the first sacrificial layer 101 to obtain the first inner cavity 112. Due to the isotropy of the wet etching process, side etching occurs when etching the first sacrificial layer 101, so that the first inner cavity 112 is in the shape of an inverted circular truncated cone. Similarly, a wet etching process can be used to remove part of the second sacrificial layer 105 to obtain the second inner cavity 113. The isotropy of the wet etching process also causes the second inner cavity 113 to be in the shape of an inverted circular truncated cone. Since side etching occurs when forming the first inner cavity 112 and the second inner cavity 113, the spacing between the first via holes 103 and the spacing between the second via holes 107 need to be reasonably set to retain part of the first sacrificial layer 101 and part of the second sacrificial layer 105 to ensure the structural stability of the MEMS device.
[0066] In one example, assuming that the side etching amount when forming the first inner cavity 112 and the second inner cavity 113 is 5-7um, in order to ensure that enough sacrificial layer is released, the spacing between the first via holes 103 and the spacing between the second via holes 107 can be set to 10-14um, and 2-10um of the sacrificial layer is retained to support the wire region. In this case, the size of the first via hole 103 and the second via hole 107 can be set to 0.5-5um.
[0067] In one example, as shown in FIG. 1, the first via hole 103 and the second via hole 107 are arranged in a staggered manner in the first wire region and the second wire region, respectively. Figure 2CAs shown, the plurality of second through holes 107 and the plurality of second inner cavities 113 are arranged along the first direction and the second direction, there is a gap between the second inner cavities 113 adjacent along the first direction or the side walls of the second inner cavities 113 adjacent along the first direction are in contact, there is a gap between the second inner cavities 113 adjacent along the second direction or the side walls of the second inner cavities 113 adjacent along the second direction are in contact, wherein the first direction is perpendicular to the second direction. For example, when the side walls of the second inner cavities 113 adjacent along the first direction are in contact and the side walls of the second inner cavities 113 adjacent along the second direction are in contact, more of the second sacrificial layer 105 is released, thereby further reducing the parasitic capacitance. For example, the plurality of second through holes 107 and the plurality of second inner cavities 113 can also be arranged in other manners, which are not limited in the present application.
[0068] In one example, the second wire region is a rectangular region, the first direction is the length direction of the second wire region, and the second direction is the width direction of the second wire region.
[0069] In one example, taking the length of the second wire region as 60um, the width of the second wire region as 14um, the first direction as the length direction of the second wire region, and the second direction as the width direction of the second wire region as an example, the interval of the second through holes 107 adjacent along the first direction and the interval of the second through holes 107 adjacent along the second direction are set as 14um, and the size of the second through holes 107 is 2um, then 4 columns of second through holes 107 can be arranged along the first direction, 5 second through holes 107 are arranged in each column, and a total of 20 second through holes 107 can be arranged. Assuming that the depth of the second inner cavity 113 is 2um (i.e., the depth of the second sacrificial layer 105 released is 2um), and assuming that the second inner cavity 113 is a circular truncated cone inner cavity with a top surface radius of 7um and a bottom surface radius of 5um, and assuming that the second inner cavity 113 is located above the diaphragm 102, the volume of the second sacrificial layer 105 released is the volume of the circular truncated cone, then the volume V1 of the second sacrificial layer 105 released can be calculated by the volume formula of the circular truncated cone as V1 = 7 2 * 3.14 * 7 / 3 - 5 2 * 3.14 * 5 / 3 = 230um 3 and the original volume V2 of the second sacrificial layer 105 is V2 = 14 * 14 * 2 = 392um 3 That is, about 60% of the second sacrificial layer 105 in the second wire region is released, and according to the capacitance formula, the parasitic capacitance between the back plate layer 106 of the second wire region and the diaphragm 102 can be reduced by at least 60%.
[0070] In one example, the plurality of first through holes 103 and the plurality of first inner cavities 112 are arranged along a third direction and a fourth direction, there is a gap between the first inner cavities 112 adjacent along the third direction or the side walls of the first inner cavities 112 adjacent along the third direction are in contact, there is a gap between the first inner cavities 112 adjacent along the fourth direction or the side walls of the first inner cavities 112 adjacent along the fourth direction are in contact, and the third direction is perpendicular to the fourth direction. Illustratively, when the side walls of the first inner cavities 112 adjacent along the third direction are in contact and the side walls of the first inner cavities 112 adjacent along the fourth direction are in contact, the first sacrificial layer 101 released is the most, thereby further reducing the parasitic capacitance. Illustratively, the plurality of first through holes 103 and the plurality of first inner cavities 112 can also be arranged in other manners, which are not limited in the present application.
[0071] In one example, the first wire region is a rectangular region, the third direction is the length direction of the first wire region, and the fourth direction is the width direction of the first wire region.
[0072] In one example, as shown in Figure 3 The back plate layer 106 of the first wire region is formed with an isolation hole 109 penetrating the back plate layer 106, the isolation hole 109 electrically isolates the back plate layer 106 of the first wire region from the back plate layer 106 of other regions (the first wire region and the region corresponding to the cavity 114), and the isolation hole 109 is in communication with the first through hole 103 and the first inner cavity 112.
[0073] The structure of the MEMS device of the embodiment of the present application has been introduced so far, and the complete MEMS device can also include other component structures, which are not described here
[0074] In summary, the MEMS device of the present application, the diaphragm of the first wire region is formed with at least one first through hole penetrating the diaphragm, and a first inner cavity corresponding to each first through hole is formed in the first sacrificial layer below each first through hole, and / or the back plate layer of the second wire region is formed with at least one second through hole penetrating the back plate layer, and a second inner cavity corresponding to each second through hole is formed in the second sacrificial layer below each second through hole. Compared with the related art in which the sacrificial layer is retained in the first inner cavity and the second inner cavity, the present application can reduce the parasitic capacitance of the MEMS device, thereby reducing the interference of the parasitic capacitance on the MEMS device and improving the signal-to-noise ratio.
[0075] Embodiment two
[0076] The manufacturing method of the MEMS device of the embodiment of the present application will be described below. Figure 2C
[0077] In one example, as shown in Figures 2A-2C As shown, a substrate 100 is provided, and a first sacrificial layer 101 and a diaphragm 102 are sequentially formed on the substrate 100, wherein the diaphragm 102 of the first conductive region is formed with at least one first through hole 103 penetrating the diaphragm 102, and the diaphragm 102 corresponding to the part of the cavity to be formed later is formed with a vent hole 104 penetrating the diaphragm 102. For example, the first sacrificial layer 101 and the diaphragm 102 can be formed by using a deposition process commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. For example, the diaphragm 102 can be etched to form the first through hole 103 and the vent hole 104 by using an etching process commonly used in the art, such as dry etching or wet etching.
[0078] Next, as shown in FIG. 1C, a second sacrificial layer 105 and a back plate layer 106 are sequentially formed, wherein the back plate layer 106 of the second conductive region is formed with at least one second through hole 107 penetrating the back plate layer 106, and the back plate layer 106 corresponding to the part of the cavity 114 to be formed later is formed with a release hole 108 penetrating the back plate layer 106. For example, the second sacrificial layer 105 and the back plate layer 106 can be formed by using a deposition process commonly used in the art. For example, the back plate layer 106 can be etched to form the second through hole 107 and the release hole 108 by using an etching process commonly used in the art, such as dry etching or wet etching. Figure 2A Figure 2B As shown in FIG. 1D, the back plate layer 106 of the first conductive region is also formed with an isolation hole 109 penetrating the back plate layer 106, which electrically isolates the back plate layer 106 of the first conductive region from the back plate layer 106 of other regions, and the isolation hole 109 exposes the second sacrificial layer 105 above the first through hole 103.
[0079] In one example, as shown in FIG. 1E, the steps of forming a first pad 110 electrically connected to the diaphragm 102 in the first conductive region, and forming a second pad 111 electrically connected to the back plate layer 106 in the second conductive region are further included. Figure 2B
[0080] Next, as shown in FIG. 1F, a first inner cavity 112 in the first sacrificial layer 101, a second inner cavity 113 in the second sacrificial layer 105, a cavity 114 between the back plate layer 106 and the diaphragm 102, and a back cavity 115 penetrating the substrate 100 from the back surface of the substrate 100 and exposing part of the surface of the diaphragm 102 are formed. Figure 2B Figure 2C
[0081] In one example, part of the first sacrificial layer 101 can be removed to form the first inner cavity 112 and part of the second sacrificial layer 105 can be removed to form the second inner cavity 113 by a wet etching process, for example, part of the first sacrificial layer 101 can be removed to form the first inner cavity 112 and part of the second sacrificial layer 105 can be removed to form the second inner cavity 113 by using a Buffer Oxide Etchant or gaseous hydrogen fluoride (VHF). Specifically, part of the first sacrificial layer 101 can be removed to form the first inner cavity 112 by releasing the second sacrificial layer 105 above the first via 103 through the isolation hole 109 to expose the first via 103, and part of the second sacrificial layer 105 can be removed to form the second inner cavity 113 by releasing the first via 103 through the second via 107.
[0082] So far, the key steps of the manufacturing method of the MEMS device of the present application have been described. Other steps can be included in the preparation of the complete MEMS device, which will not be described here. It is worth mentioning that the above-mentioned step sequence can be adjusted without conflict.
[0083] Embodiment Three
[0084] Another embodiment of the present application further provides an electronic device, which comprises the aforementioned MEMS device.
[0085] The electronic device of the present embodiment can be a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PSP, or any other electronic product or device, or any intermediate product comprising the aforementioned MEMS device. The electronic device of the present embodiment has better performance due to the use of the aforementioned MEMS device.
[0086] Although a number of embodiments have been described herein, it is understood that the skilled person would be able to devise further modifications and embodiments which would fall within the ambit of the inventive concept disclosed herein. More particularly, various modifications and changes can be made within the scope of the present disclosure, the drawings, and the appended claims, in the arrangement and / or composition of the subject matter. In addition to modifications and changes in the arrangement and / or composition of the subject matter, the use of alternative materials is also a selection which would be apparent to the skilled person.
Claims
1. A MEMS device, characterized by, The MEMS device comprises: a substrate comprising a first surface and a second surface opposite to the first surface; a first sacrificial layer on a part of the first surface of the substrate; a diaphragm above the first surface, and a part of the diaphragm is provided with the first sacrificial layer between the diaphragm and the substrate; a second sacrificial layer partially on the diaphragm; a backplate layer partially on the second sacrificial layer, and a cavity is formed between the backplate layer and the diaphragm; a back cavity penetrating through the substrate and the first sacrificial layer from the second surface of the substrate, and exposing a part of the surface of the diaphragm; wherein the MEMS device comprises a first wire region and a second wire region arranged apart outside the cavity, at least one first through hole penetrating through the diaphragm is formed in the diaphragm of the first wire region, and a first inner cavity corresponding to each first through hole is formed below each first through hole in the first sacrificial layer, and / or at least one second through hole penetrating through the backplate layer is formed in the backplate layer of the second wire region, and a second inner cavity corresponding to each second through hole is formed below each second through hole in the second sacrificial layer.
2. The MEMS device according to claim 1, wherein: the first inner cavity penetrates through the first sacrificial layer and exposes a part of the first surface of the substrate; the second inner cavity penetrates through the second sacrificial layer and exposes a part of the surface of the diaphragm.
3. The MEMS device of claim 1, wherein, A part of the second through hole and a part of the second inner cavity are located outside the diaphragm and away from the cavity.
4. The MEMS device according to claim 1, wherein: the first through hole and the second through hole are cylindrical through holes; the first inner cavity and the second inner cavity are inverted circular truncated cone-shaped inner cavities.
5. The MEMS device of claim 4, wherein, A plurality of second through holes and a plurality of second inner cavities are arranged along a first direction and a second direction, there is a gap between adjacent second inner cavities along the first direction or the side walls of adjacent second inner cavities along the first direction are in contact, there is a gap between adjacent second inner cavities along the second direction or the side walls of adjacent second inner cavities along the second direction are in contact, wherein the first direction is perpendicular to the second direction.
6. The MEMS device of claim 5, wherein, The second wire region is a rectangular region, the first direction is the length direction of the second wire region, and the second direction is the width direction of the second wire region.
7. The MEMS device of claim 1, wherein, The backplate layer of the first wire region is provided with an isolation hole penetrating through the backplate layer, and the isolation hole electrically isolates the backplate layer of the first wire region from the backplate layer of other regions, wherein the isolation hole is in communication with the first through hole and the first inner cavity.
8. The MEMS device according to claim 1, wherein: a first pad is further formed in the first wire region, the first pad is electrically connected to the diaphragm, and the first through hole is located between the first pad and the cavity; a second pad is further formed in the second wire region, the second pad is electrically connected to the backplate layer, and the second through hole is located between the second pad and the cavity.
9. The MEMS device of claim 1, wherein, The back plate layer comprises a first dielectric layer, a conductive layer and a second dielectric layer stacked from bottom to top, wherein a side of the first dielectric layer facing the cavity is formed with a plurality of protrusions, and the first dielectric layer further comprises an etching stop layer in contact with the surface of the diaphragm, the etching stop layer being located at the four peripheral edges of the cavity to define the boundary of the cavity.
10. An electronic device, comprising: The electronic device comprises the MEMS device of any one of claims 1-9.