Shift register, gate drive circuit and display device

Abstract

The utility model provides a shift register, a gate drive circuit and a display device, belongs to the technical field of display, and can solve the problem that an existing display product is likely to have poor horizontal black lines. The shifting register comprises an input sub-circuit which is configured to respond to an input signal input by a signal input end and write the input signal into a pull-up node so as to charge the pull-up node; the output sub-circuit is configured to respond to the potential of the pull-up node and output a clock signal input by a clock signal end through a signal output end; the pull-up reset sub-circuit is configured to respond to a pull-up reset signal input by a pull-up reset signal end and reset the potential of the pull-up node through a non-working level signal input by a non-working level signal end; and the channel width of the thin film transistor in the pull-up reset sub-circuit is greater than that of the thin film transistor in the output sub-circuit.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] In recent years, the development of displays has gradually shown a trend towards high integration and low cost. One very important technology is the mass production of Gate Driver on Array (GOA) technology. GOA technology integrates the gate driving circuit composed of thin-film transistors (TFTs) onto the array substrate of the display panel to form a scanning drive for the display panel. This eliminates the need for the gate driver integrated circuit, which not only reduces product costs in terms of both materials and manufacturing processes, but also allows for aesthetically pleasing designs with symmetrical sides and narrow bezels. Utility Model Content

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a shift register, a gate drive circuit, and a display device.

[0004] In a first aspect, embodiments of this disclosure provide a shift register, the shift register comprising: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit;

[0005] The input sub-circuit connects the signal input terminal and the pull-up node, and is configured to respond to the input signal input at the signal input terminal and write the input signal into the pull-up node to charge the pull-up node; the output sub-circuit connects the pull-up node, the clock signal input terminal, and the signal output terminal, and is configured to respond to the potential of the pull-up node and output the clock signal input at the clock signal terminal through the signal output terminal; the pull-up reset sub-circuit connects the pull-up node, the pull-up reset signal terminal, and the non-working level signal terminal, and is configured to respond to the pull-up reset signal input at the pull-up reset signal terminal and reset the potential of the pull-up node through the non-working level signal input at the non-working level signal terminal.

[0006] The channel width of the thin-film transistor in the pull-up reset sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0007] In some embodiments, the first electrode of the thin-film transistor in the output sub-circuit includes: a plurality of first extensions and at least one second extension; the second electrode of the thin-film transistor in the output sub-circuit includes: a plurality of first U-shaped portions;

[0008] The first extension and the second extension respectively extend into the opening of the corresponding first U-shaped portion; at least one second extension is located on at least one side of the plurality of first extensions;

[0009] The width of the second extension is greater than the width of the first extension.

[0010] In some embodiments, the first electrode of the thin-film transistor in the pull-up reset circuit includes: a plurality of third extensions and at least one fourth extension; the second electrode of the thin-film transistor in the pull-up reset circuit includes: a plurality of second U-shaped portions;

[0011] The third extension and the fourth extension respectively extend into the opening of the corresponding second U-shaped portion; at least one of the fourth extensions is located on at least one side of the plurality of third extensions;

[0012] The width of the fourth extension is greater than the width of the third extension.

[0013] In some embodiments, the input sub-circuit includes: a first transistor; the pull-up reset sub-circuit includes: a second transistor; and the output sub-circuit includes: a third transistor and a storage capacitor.

[0014] The control electrode and first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the control electrode of the second transistor is connected to the pull-up reset signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal; the control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal.

[0015] In some embodiments, the shift register further includes: a discharge circuit; the discharge circuit is connected to the frame enable signal terminal, the non-working level signal terminal and the pull-up node, and is configured to respond to a frame enable signal input at the frame enable signal terminal, and discharge the pull-up node through the non-working level signal input at the non-working level signal terminal;

[0016] The channel width of the thin-film transistor in the discharge circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0017] In some embodiments, the first electrode of the thin-film transistor in the discharge circuit includes: a plurality of fifth extensions and at least one sixth extension; the second electrode of the thin-film transistor in the discharge circuit includes: a plurality of third U-shaped portions;

[0018] The fifth extension and the sixth extension respectively extend into the opening of the corresponding third U-shaped portion; at least one of the sixth extensions is located on at least one side of the plurality of fifth extensions;

[0019] The width of the sixth extension is greater than the width of the fifth extension.

[0020] In some embodiments, the discharge circuit includes: a seventh transistor; the control electrode of the seventh transistor is connected to the frame-on signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal.

[0021] In some embodiments, the shift register further includes: a noise reduction sub-circuit; the noise reduction sub-circuit is connected to a pull-down node, a non-working level signal terminal, and a pull-up node, and is configured to reduce noise on the pull-up node in response to the potential of the pull-down node through a non-working level signal input from the non-working level signal terminal;

[0022] The channel width of the thin-film transistor in the noise reduction sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0023] In some embodiments, the first electrode of the thin-film transistor in the noise reduction sub-circuit includes: a plurality of seventh extensions and at least one eighth extension; the second electrode of the thin-film transistor in the noise reduction sub-circuit includes: a plurality of fourth U-shaped portions;

[0024] The seventh extension and the eighth extension respectively extend into the opening of the corresponding fourth U-shaped portion; at least one of the eighth extensions is located on at least one side of the plurality of seventh extensions;

[0025] The width of the eighth extension is greater than the width of the seventh extension.

[0026] In some embodiments, the noise reduction sub-circuit includes: a tenth transistor; the control electrode of the tenth transistor is connected to a pull-down node, the first electrode is connected to a pull-up node, and the second electrode is connected to a non-working level signal terminal.

[0027] In some embodiments, the channel width of the thin-film transistor in the input sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0028] Secondly, embodiments of this disclosure provide a gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers as provided in the first aspect.

[0029] Thirdly, embodiments of this disclosure provide a display device, the display device including the gate driving circuit as provided in the second aspect. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of an exemplary shift register.

[0031] Figure 2 for Figure 1 The diagram shows a partial structure of the thin-film transistor in the shift register.

[0032] Figure 3 This is a partial structural diagram of a thin-film transistor in a shift register provided in an embodiment of this disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. Without conflict, the various embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0035] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0036] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0037] It should be noted that the thin-film transistor (TFT) can be either an N-type TFT or a P-type TFT. An N-type TFT refers to a TFT with N-type ion doping in its active layer, while a P-type TFT refers to a TFT with P-type ion doping in its active layer. The operating voltage of an N-type TFT is a high-level voltage, meaning that when a high-level voltage is input to the gate of an N-type TFT, the source and drain are connected. The operating voltage of a P-type TFT is a low-level voltage, meaning that when a low-level voltage is input to the gate of a P-type TFT, the source and drain are connected. In this embodiment, an N-type TFT will be used as an example for explanation. It is understood that the implementation principle of a P-type TFT is similar and will not be described in detail here.

[0038] In this embodiment, since the transistor used is an N-type transistor, the working level signal in this embodiment refers to a high-level signal, and the non-working level signal refers to a low-level signal; the corresponding working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.

[0039] A typical display panel consists of multiple grid lines and multiple data lines. The grid lines and data lines intersect to define multiple pixel areas, each containing a pixel unit. The structure of the display panel is explained using the extension direction of the grid lines as the row direction and the extension direction of the data lines as the column direction as an example. When driving the display panel to display an image, scan signals are written to the grid lines row by row, and data voltage signals are simultaneously written to each data line, causing the pixel units in the display panel to light up row by row.

[0040] In this design, the scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit. In related technologies, the gate drive circuit can be integrated into a gate drive chip, and the source drive circuit into a source drive chip. Currently, to reduce the number of chips and achieve narrow or borderless bezels, a GOA (Grid-Oriented Array) technology is proposed, which integrates the gate drive circuit onto the array substrate. The gate drive circuit includes multiple cascaded shift registers integrated on the array substrate. Each shift register is connected to a gate line, providing a scan signal to the connected gate line.

[0041] In recent years, with the continuous development of display technology, the refresh rate of display products has also been increasing, especially for gaming displays, where refresh rates have evolved from 100 Hz to 144 Hz, 240 Hz, and 360 Hz. However, with the increase in refresh rate, the occurrence of horizontal black lines in the display screen has become more frequent. Furthermore, the width of these horizontal black lines is not fixed, and they are more noticeable in monochrome images. The problem worsens as the refresh rate decreases; for example, compared to a 60 Hz display, a 48 Hz display shows significantly more pronounced horizontal black line defects.

[0042] Figure 1 This is a schematic diagram of an exemplary shift register, such as... Figure 1 As shown, the shift register includes: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit. The input sub-circuit is connected to the signal input terminal INPUT and the pull-up node PU, and is configured to respond to the input signal input to the signal input terminal INPUT and write the input signal to the pull-up node PU to charge it. The output sub-circuit is connected to the pull-up node PU, the clock signal terminal CLK, and the signal output terminal OUTPUT, and is configured to respond to the potential of the pull-up node PU and output the clock signal input to the clock signal terminal CLK through the signal output terminal OUTPUT. The pull-up reset sub-circuit is connected to the pull-up node PU, the pull-up reset signal terminal RESET_PU, and the low-level signal terminal VGL, and is configured to respond to the pull-up reset signal input to the pull-up reset signal terminal RESET_PU and reset the potential of the pull-up node PU through the low-level signal input to the low-level signal terminal VGL.

[0043] Specifically, such as Figure 1As shown, the input sub-circuit includes a first transistor M1; the pull-up reset sub-circuit includes a second transistor M2; and the output sub-circuit includes a third transistor M3 and a storage capacitor C. The gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and its drain is connected to the pull-up node PU. The gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, its source is connected to the pull-up node PU, and its drain is connected to the low-level signal terminal VGL. The gate of the third transistor M3 is connected to the pull-up node PU, its source is connected to the clock signal terminal CLK, and its drain is connected to the signal output terminal OUTPUT. One end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the signal output terminal OUTPUT.

[0044] like Figure 1 As shown, the shift register also includes: a pull-down control subcircuit, a pull-down subcircuit, a noise reduction subcircuit, an electron discharge circuit, and a cascaded subcircuit; wherein, the pull-down control subcircuit includes: a first pull-down control subcircuit and a second pull-down control subcircuit; the pull-down subcircuit includes: a first pull-down subcircuit and a second pull-down subcircuit; the noise reduction subcircuit includes: a first noise reduction subcircuit and a second noise reduction subcircuit. The first pull-down control subcircuit and the second pull-down control subcircuit have the same structure and function, they only operate in a time-sharing manner; similarly, the first pull-down subcircuit and the second pull-down subcircuit have the same structure and function; the first noise reduction subcircuit and the second noise reduction subcircuit have the same structure and function.

[0045] The first pull-down control sub-circuit is connected to the first power supply voltage signal terminal VDDO and the first pull-down node PD1. It is configured to input the first power supply voltage input to the first power supply voltage signal terminal VDDO to the first pull-down node PD1 in response to the first power supply voltage input to the first power supply voltage signal terminal VDDO, thereby controlling the potential of the first pull-down node PD1. The second pull-down control sub-circuit is connected to the second power supply voltage signal terminal VDDE and the second pull-down node PD2. It is configured to input the second power supply voltage input to the second power supply voltage signal terminal VDDE to the second pull-down node PD2 in response to the second power supply voltage input to the second power supply voltage signal terminal VDDE, thereby controlling the potential of the second pull-down node PD2. The first pull-down sub-circuit is connected to the pull-up node PU, the low-level signal terminal VGL, the first pull-down node PD1, and the first pull-down control node PD_CN1. It is configured to respond to the potential of the pull-up node PU and pull down the potentials of the first pull-down node PD1 and the first pull-down control node PD_CN1 through the low-level signal input to the low-level signal terminal VGL. The second pull-down sub-circuit is connected to the pull-up node PU, the low-level signal terminal VGL, the first pull-down node PD1, and the first pull-down control node PD_CN1. The low-level signal terminal VGL, the second pull-down node PD2, and the second pull-down control node PD_CN2 are configured to respond to the potential of the pull-up node PU, and pull down the potential of the second pull-down node PD2 and the second pull-down control node PD_CN2 through a low-level signal input to the low-level signal terminal VGL; the first noise reduction sub-circuit is connected to the first pull-down node PD1, the low-level signal terminal VGL, the pull-up node PU, the signal output terminal OUTPUT, and the cascaded signal output terminal OUT_C, and is configured to respond to the potential of the first pull-down node PD1 through a low-level signal input to the low-level signal terminal VGL. The low-level signal input at terminal VGL performs noise reduction on the pull-up node PU, signal output terminal OUTPUT, and cascaded signal output terminal OUT_C. The second noise reduction sub-circuit is connected to the second pull-down node PD2, the low-level signal terminal VGL, the pull-up node PU, the signal output terminal OUTPUT, and the cascaded signal output terminal OUT_C. It is configured to respond to the potential of the second pull-down node PD2 and perform noise reduction on the pull-up node PU, signal output terminal OUTPUT, and cascaded signal output terminal OUT_C ​​through the low-level signal input at the low-level signal terminal VGL. The discharge circuit is connected to the frame start signal terminal STV, the low-level signal terminal VGL, and the pull-up node PU. It is configured to respond to the frame start signal input at the frame start signal terminal STV and discharge the pull-up node PU through the low-level signal input at the low-level signal terminal VGL. The cascaded sub-circuit connects the pull-up node PU, the clock signal terminal CLK, and the cascaded signal output terminal OUT_C. It is configured to respond to the potential of the pull-up node PU and output the clock signal input at the clock signal terminal CLK to other cascaded shift registers through the cascaded signal output terminal OUT_C.

[0046] It should be noted that the cascaded signal output terminal OUT_C ​​and the signal output terminal OUTPUT output the same signal. The only difference is that this shift register unit has two output terminals: one is the signal output terminal OUTPUT connected to the gate line, and the other is the cascaded signal output terminal OUT_C ​​used for cascading. The reason for setting up a separate cascaded sub-circuit is to reduce the load on the signal output terminal OUTPUT, thereby avoiding interference with the scan signal output by OUTPUT.

[0047] Specifically, such as Figure 1 As shown, both the first and second pull-down control sub-circuits include a fifth transistor and a ninth transistor; wherein the fifth transistor in the first and second control sub-circuits is represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. Both the first and second pull-down sub-circuits include a sixth transistor and an eighth transistor; wherein the sixth transistor in the first and second pull-down sub-circuits is represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. Both the first and second noise reduction sub-circuits include a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein the tenth transistor in the first and second noise reduction sub-circuits is represented by M10 and M10', respectively, the eleventh transistor is represented by M11 and M11', respectively, and the twelfth transistor is represented by M12 and M12', respectively; the discharge circuit includes a seventh transistor M7.

[0048] In this configuration, the gate and source of the fifth transistor M5 are both connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down control node PD_CN1; the gate of the ninth transistor M9 is connected to the first pull-down control node PD_CN1, the source is connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down node PD1; the gate and source of the fifth transistor M5' are both connected to the second power supply voltage terminal VDDE, and the drain is connected to the second pull-down control node PD_CN2; the gate of the ninth transistor M9' is connected to the second pull-down control node PD_CN2, the source is connected to the second power supply voltage terminal VDDE, and the drain is connected to the first pull-down node PD1; the gate of the sixth transistor M6 is connected to the pull-up node PU, the source is connected to the first pull-down node PD1, and the drain is connected to the low-level signal terminal VGL; the gate of the eighth transistor M8 is connected to the pull-up node PU, the source is connected to the first pull-down control node PD_CN1, and the drain is connected to the low-level signal terminal VGL; the gate of the sixth transistor M6' is connected to the pull-up node PU... The source of the eighth transistor M8' is connected to the second pull-down node PD2, and its drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11 is connected to the first pull-down node PD1, its source is connected to the pull-up node PU, and its drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11 is connected to the first pull-down node PD1, its source is connected to the signal output terminal OUTPUT, and its drain is connected to the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected to the second pull-down node PD2, its source is connected to the pull-up node PU, and its drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11' is connected to the second pull-down node PD2, its source is connected to the signal output terminal OUTPUT, and its drain is connected to the low-level signal terminal VGL; the gate of the seventh transistor M7 is connected to the frame enable signal terminal STV, its source is connected to the pull-up node PU, and its drain is connected to the low-level signal terminal VGL. The cascaded sub-circuit includes a thirteenth transistor M13. The gate of transistor M13 is connected to the pull-up node PU, its source is connected to the clock signal terminal CLK, and its drain is connected to the cascaded signal output terminal OUT_C. Simultaneously, a twelfth transistor, denoted as M12 and M12', is also provided in both the first and second noise reduction sub-circuits, used to reduce the noise of the signal output from the cascaded signal output terminal OUT_C. The gate of the twelfth transistor M12 is connected to the first pull-down node PD1, its source is connected to the cascaded signal output terminal OUT_C, and its drain is connected to the low-level signal terminal VGL. The gate of the twelfth transistor M12' is connected to the second pull-down node PD2, its source is connected to the cascaded signal output terminal OUT_C, and its drain is connected to the low-level signal terminal VGL.

[0049] In this circuit, the fifth transistor M5 and the ninth transistor M9 form the first pull-down control sub-circuit, and the fifth transistor M5' and the ninth transistor M9' form the second pull-down control sub-circuit, which operate in a time-sharing manner (i.e., alternately). Correspondingly, since the first noise reduction sub-circuit composed of the tenth transistor M10 and the eleventh transistor M11, and the second noise reduction sub-circuit composed of the tenth transistor M10' and the eleventh transistor M11', are controlled by the first and second pull-down control sub-circuits respectively, they also operate in a time-sharing manner. The first and second pull-down control sub-circuits operate on the same principle, as do the first and second noise reduction sub-circuits; therefore, the following explanation focuses on the operation of the shift register when the first pull-down control sub-circuit and the first noise reduction sub-circuit are in operation. It should be noted that... Figure 1 In the circuit structure shown, some low-level signal terminals can be represented by VGL or LVGL. The low-level signal terminal LVGL can provide a signal with a lower potential than the low-level signal terminal VGL, which can more fully pull down the potential of the corresponding point.

[0050] During the input phase, a high-level signal is written to the signal input terminal INPUT, the first transistor M1 is turned on, the potential of the pull-up node PU is pulled up by the high-level signal, and the storage capacitor C is charged.

[0051] During the output phase, the third transistor M3 turns on because the potential of the pull-up node PU is pulled high during the input phase. The high-level signal input at the clock signal terminal CLK is output through the signal output terminal OUTPUT to the gate line connected to the shift register.

[0052] During the shutdown phase, a high-level signal is input to the frame enable signal terminal STV, turning on the seventh transistor M7. The low-level signal input to the low-level signal terminal VGL discharges the pull-up node PU, preventing residual charge in the pull-up node PU from causing display abnormalities. A high-level signal is input to the pull-up reset signal terminal RESET_PU, turning on the second transistor M2. The low-level signal input to the low-level signal terminal VGL pulls down the potential of the pull-up node PU, resetting it. Since the pull-up node PU is pulled low, the third transistor M3 turns off, and both the signal output terminal OUTPUT and the cascaded signal output terminal OUT_C ​​no longer output high-level signals. Simultaneously, the first pull-down control node PD_CN1 and the pull-down node are both high-level signals, turning on the tenth transistor M10 and the eleventh transistor M11. These transistors reduce noise in the outputs of the pull-up node PU, the signal output terminal OUTPUT, and the cascaded signal output terminal OUT_C, respectively, until the pull-up node PU potential is pulled high at the start of the next frame scan.

[0053] In practical applications, monitoring the voltage of each node in the sample revealed that the voltage of the pull-up node PU in the defective sample (NG) was low during the output phase, with insufficient voltage retention, decreasing from 41.6V to 30.5V. In contrast, the voltage of the pull-up node PU in the normal sample (OK) decreased from 44.6V to 35.1V during the output phase. The delay time of the OUTPUT voltage at the signal output terminal of the normal sample during the shutdown phase was 2.9μs, while the delay time of the OUTPUT voltage at the signal output terminal of the defective sample during the shutdown phase was 11.5μs, indicating an increased delay time in the shutdown phase for the output voltage of the defective sample.

[0054] Research revealed that the input sub-circuit is responsible for inputting the signal and raising the voltage of the pull-up node PU. The pull-up reset sub-circuit, discharge circuit, and noise reduction sub-circuit are responsible for lowering the voltage of the pull-up node PU. In the defective sample, the channel size of the thin-film transistors (TFTs) in the input, pull-up reset, discharge, and noise reduction sub-circuits was too small. Smaller channel sizes lead to larger leakage currents. Analysis of the voltage results at each node showed that in the output stage, the excessive leakage current of the TFTs in these circuits caused a decrease in the voltage of the pull-up node PU, resulting in insufficient voltage retention. During clock signal output, the low voltage of the pull-up node PU reduced the output capability of the TFTs in the output sub-circuit, leading to an increased output voltage delay. This resulted in incorrect data signal charging, causing the appearance of a horizontal black line defect.

[0055] Figure 2 for Figure 1 The diagram shows a partial structure of the thin-film transistor in the shift register, as shown below. Figure 2 As shown, the source of the thin-film transistor includes multiple extensions 301; the drain includes multiple U-shaped portions 302. The extensions 301 extend into the openings of the corresponding U-shaped portions 302. The thin-film transistor also includes other structures such as a channel. Figure 2 (Not shown in the diagram). Because the channel size of the thin-film transistor in the shift register can cause defects in the horizontal black line, it is necessary to measure and control the channel size of the thin-film transistor. At the same time, in order to narrow the bezel and reduce the load, the width of the extension 301 of the thin-film transistor needs to be smaller and smaller. When measuring the channel width of the thin-film transistor, due to the influence of the extension 301, there are many mismeasurements when monitoring the channel width, and the channel width of the thin-film transistor cannot be accurately monitored.

[0056] To at least solve one of the aforementioned technical problems, this disclosure provides a shift register, a gate driving circuit, and a display device. The shift register, gate driving circuit, and display device provided in this disclosure will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0057] Firstly, embodiments of this disclosure provide a shift register whose circuit structure is similar to... Figure 1 The shift registers shown have the same structure, such as Figure 1 As shown, the shift register includes an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit. The input sub-circuit connects the signal input terminal INPUT and the pull-up node PU, and is configured to respond to the input signal input at the signal input terminal INPUT and write the input signal to the pull-up node PU to charge it. The output sub-circuit connects the pull-up node PU, the clock signal terminal CLK, and the signal output terminal OUTPUT, and is configured to respond to the potential of the pull-up node PU and output the clock signal input at the clock signal terminal CLK through the signal output terminal OUTPUT. The pull-up reset sub-circuit connects the pull-up node PU, the pull-up reset signal terminal RESET_PU, and the low-level signal terminal VGL, and is configured to respond to the pull-up reset signal input at the pull-up reset signal terminal RESET_PU and reset the potential of the pull-up node PU through the low-level signal input at the low-level signal terminal VGL. The channel width of the thin-film transistor in the pull-up reset sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0058] It should be noted that the working principle of the shift register provided in this embodiment is the same as that described above. Figure 1 The shift registers shown operate on the same principle, so they will not be described again here.

[0059] In the shift register provided in this embodiment, the input sub-circuit is responsible for inputting signals during the input phase and pulling up the voltage of the pull-up node PU. The pull-up reset sub-circuit is responsible for pulling down the voltage of the pull-up node PU during the output phase. The output sub-circuit is responsible for outputting the gate drive signal during the output phase. Since the channel width of the thin-film transistor in the pull-up reset sub-circuit is larger, for example, the channel width of the thin-film transistor in the pull-up reset sub-circuit is larger than the channel width of the thin-film transistor in the output sub-circuit, the leakage current of the thin-film transistor in the pull-up reset sub-circuit can be reduced, ensuring that the voltage of the pull-up node PU can be maintained sufficiently during the output phase, so that the voltage of the pull-up node PU is high enough during the off phase, avoiding the decrease in the output capability of the thin-film transistor in the output sub-circuit, thereby reducing the output voltage delay time. This can prevent data signal mischarging and the resulting horizontal black line defects, thereby improving the display effect and enhancing the user experience.

[0060] In some embodiments, Figure 3 This is a partial structural diagram of the thin-film transistor in the shift register provided in an embodiment of the present disclosure, as shown below. Figure 3As shown, the thin-film transistor can be a thin-film transistor in an output sub-circuit. The source of the thin-film transistor in the output sub-circuit includes: a plurality of first extensions 3011 and at least one second extension 3012 (e.g., three second extensions); the second electrode of the thin-film transistor in the output sub-circuit includes: a plurality of first U-shaped portions 3021; ​​the first extensions 3011 and the second extensions 3012 respectively extend into the openings of the corresponding first U-shaped portions 3021; ​​at least one second extension 3012 is located on at least one side of the plurality of first extensions 3011; the width of the second extension 3012 is greater than the width of the first extension 3011.

[0061] The channel size of the thin-film transistors (TFTs) in the output sub-circuit is critical, affecting the normal operation of the shift register. Furthermore, the TFTs in the output sub-circuit have a relatively large overall area, making them easy to identify. Therefore, the TFTs in the output sub-circuit can serve as monitoring units for the channel size of the TFTs in the shift register. Figure 3 In the output sub-circuit, the source of the thin-film transistor includes a plurality of first extensions 3011 and at least one second extension 3012; the second electrode of the thin-film transistor in the output sub-circuit includes a plurality of first U-shaped portions 3021; ​​the first extensions 3011 and the second extensions 3012 respectively extend into the openings of the corresponding first U-shaped portions 3021; ​​at least one second extension 3012 is located on at least one side of the plurality of first extensions 3011 (e.g., at the edge of the overall region where the thin-film transistor is located). Figure 3 The diagram only shows the case where the second extension 3012 is located to the right of the first extension 3011. Since the width of the second extension 3012 is greater than the width of the first extension 3011, the second extension 3012 is easily identified during the detection process. When monitoring the channel dimensions of the thin-film transistor, the second extension 3012 can be directly identified, avoiding any influence of the second extension 3012 on the measurement of the thin-film transistor's channel dimensions. This prevents mismeasurements when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the thin-film transistor and enhancing the stability of each thin-film transistor in the shift register.

[0062] In some embodiments, the source of the thin-film transistor in the pull-up reset circuit includes: a plurality of third extensions and at least one fourth extension; the second electrode of the thin-film transistor in the pull-up reset circuit includes: a plurality of second U-shaped portions; the third extensions and the fourth extensions extend into the openings of the corresponding second U-shaped portions; at least one fourth extension is located on at least one side of the plurality of third extensions; the width of the fourth extension is greater than the width of the third extension.

[0063] It should be noted here that the structure of the third extension is similar to... Figure 3The structure of the first extension 3011 is the same as that of the fourth extension. Figure 3 The structure of the second extension 3012 is the same as that of the second U-shaped part. Figure 3 The structure of the first U-shaped part 3021 is the same as that in the previous one, and its specific structure can be found in [reference]. Figure 3 .

[0064] The channel size of the thin-film transistor (TFT) in the pull-up reset circuit affects the horizontal black line defect. The TFT in the pull-up reset circuit can serve as a channel size monitoring unit to monitor the channel size of the TFT in the shift register. The source of the TFT in the pull-up reset circuit includes: multiple third extensions and at least one fourth extension; the drain of the TFT in the pull-up reset circuit includes: multiple second U-shaped portions; the third and fourth extensions extend into the openings of the corresponding second U-shaped portions; at least one fourth extension is located on at least one side of the multiple third extensions (e.g., the edge of the overall area where the TFT is located). Since the width of the fourth extension is greater than the width of the third extension, the fourth extension is easily identified during the detection process. When monitoring the channel size of the TFT, the fourth extension can be directly identified, avoiding the influence of the fourth extension on the channel size measurement of the TFT. This avoids false measurements when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the TFT and improving the stability of each TFT in the shift register.

[0065] Specifically, such as Figure 1 As shown, the output sub-circuit includes a first transistor M1; the pull-up reset sub-circuit includes a second transistor M2; the output sub-circuit includes a third transistor M3 and a storage capacitor C; wherein, the gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and the drain is connected to the pull-up node PU; the gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal OUTPUT; one end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the signal output terminal OUTPUT; the channel width of the second transistor M2 is greater than the channel width of the third transistor M3.

[0066] For example, the difference between the channel width of the second transistor M2 and the channel width of the third transistor M3 is 0.1 to 1.0 μm, specifically 0.5 μm.

[0067] For example, the width of the second extension 3012 in the third transistor M3 is greater than the width of the first extension 3011, and the difference between the width of the second extension 3012 and the width of the first extension 3011 is 0.5 to 2 μm, specifically 1.0 μm.

[0068] For example, the width of the fourth extension of the second transistor M2 is greater than the width of the third extension, and the difference between the width of the fourth extension and the width of the third extension is 0.5 to 2 μm, specifically 1.0 μm.

[0069] In some embodiments, such as Figure 1 As shown, the shift register also includes: a discharge circuit; the discharge circuit is connected to the frame enable signal terminal STV, the low level signal terminal VGL, and the pull-up node PU, and is configured to respond to the frame enable signal input to the frame enable signal terminal STV, and discharge the pull-up node PU through the low level signal input to the low level signal terminal VGL; the channel width of the thin film transistor in the discharge circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

[0070] The discharge circuit is responsible for pulling down the voltage of the pull-up node PU during the output phase. Because the channel width of the thin-film transistor in the discharge circuit is relatively large (for example, the channel width of the thin-film transistor in the discharge circuit is larger than that of the thin-film transistor in the output sub-circuit), the leakage current of the thin-film transistor in the discharge circuit can be reduced. This ensures that the voltage of the pull-up node PU can be maintained sufficiently during the output phase, so that the voltage of the pull-up node PU is high enough during the shutdown phase. This prevents the output capability of the thin-film transistor in the output sub-circuit from decreasing, thereby reducing the output voltage delay time. In turn, it can prevent data signal mischarging that could lead to horizontal black line defects, thus improving the display effect and enhancing the user experience.

[0071] In some embodiments, the source of the thin-film transistor in the discharge circuit includes: a plurality of fifth extensions and at least one sixth extension; the drain of the thin-film transistor in the discharge circuit includes: a plurality of third U-shaped portions; the fifth extensions and the sixth extensions respectively extend into the openings of the corresponding third U-shaped portions; at least one sixth extension is located on at least one side of the plurality of fifth extensions; the width of the sixth extension is greater than the width of the fifth extensions.

[0072] It should be noted that the structure of the fifth extension is similar to... Figure 3 The structure of the first extension 3011 is the same as that of the sixth extension. Figure 3 The structure of the second extension 3012 is the same as that of the third U-shaped part. Figure 3 The structure of the first U-shaped part 3021 is the same as that in the previous one, and its specific structure can be found in [reference]. Figure 3 .

[0073] The channel size of the thin-film transistor (TFT) in the discharge circuit affects the horizontal black line defect. The TFT in the discharge circuit can serve as a channel size monitoring unit to monitor the channel size of the TFT in the shift register. The source of the TFT in the discharge circuit includes: multiple fifth extensions and at least one sixth extension; the drain of the TFT in the discharge circuit includes: multiple third U-shaped portions; the fifth and sixth extensions extend into the openings of the corresponding third U-shaped portions; at least one sixth extension is located on at least one side of the multiple fifth extensions (e.g., the edge of the overall area where the TFT is located). Since the width of the sixth extension is greater than the width of the fifth extension, the sixth extension is easily identified during the detection process. When monitoring the channel size of the TFT, the sixth extension can be directly identified, avoiding the influence of the sixth extension on the channel size measurement of the TFT. This can avoid mismeasurement when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the TFT and improving the stability of each TFT in the shift register.

[0074] Specifically, the discharge circuit includes: a seventh transistor M7; the gate of the seventh transistor M7 is connected to the frame enable signal terminal STV, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the channel width of the seventh transistor M7 is greater than the channel width of the third transistor M3.

[0075] For example, the difference between the channel width of the seventh transistor M7 and the channel width of the third transistor M3 is 0.1 to 1.0 μm, specifically 0.5 μm.

[0076] For example, the width of the sixth extension in the seventh transistor M7 is greater than the width of the fifth extension, and the difference between the width of the sixth extension and the width of the fifth extension is 0.5 to 2 μm, specifically 1.0 μm.

[0077] In some embodiments, such as Figure 1 As shown, the shift register also includes: a noise reduction sub-circuit; the noise reduction sub-circuit is connected to the pull-down node PD (first pull-down node PD1 or second pull-down node PD2), the low-level signal terminal VGL, and the pull-up node PU, and is configured to respond to the potential of the pull-down node PD (first pull-down node PD1 or second pull-down node PD2), and to reduce noise on the pull-up node PU through the low-level signal input at the low-level signal terminal; the channel width of the thin-film transistor in the noise reduction sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0078] The noise reduction sub-circuit is responsible for pulling down the voltage of the pull-up node PU during the output phase. Because the channel width of the thin-film transistor in the noise reduction sub-circuit is larger (for example, the channel width of the thin-film transistor in the noise reduction sub-circuit is larger than that of the thin-film transistor in the output sub-circuit), the leakage current of the thin-film transistor in the noise reduction sub-circuit can be reduced, ensuring that the voltage of the pull-up node PU can be maintained sufficiently during the output phase. This ensures that the voltage of the pull-up node PU is high enough during the shutdown phase, preventing the output capability of the thin-film transistor in the output sub-circuit from decreasing, thereby reducing the output voltage delay time. This, in turn, can prevent data signal mischarging that could lead to horizontal black line defects, thus improving the display effect and enhancing the user experience.

[0079] In some embodiments, the source of the thin-film transistor in the noise reduction sub-circuit includes: a plurality of seventh extensions and at least one eighth extension; the drain of the thin-film transistor in the noise reduction sub-circuit includes: a plurality of fourth U-shaped portions; the seventh extensions and the eighth extensions extend into the openings of the corresponding fourth U-shaped portions; at least one eighth extension is located on at least one side of the plurality of seventh extensions; the width of the eighth extension is greater than the width of the seventh extension.

[0080] It should be noted here that the structure of the seventh extension is similar to... Figure 3 The structure of the first extension 3011 is the same as that of the eighth extension. Figure 3 The structure of the second extension 3012 is the same as that of the fourth U-shaped part. Figure 3 The structure of the first U-shaped part 3021 is the same as that in the previous one, and its specific structure can be found in [reference]. Figure 3 .

[0081] The channel size of the thin-film transistor (TFT) in the noise reduction sub-circuit affects the horizontal black line defect. The TFT in the noise reduction sub-circuit can serve as a channel size monitoring unit to monitor the channel size of the TFT in the shift register. The source of the TFT in the noise reduction sub-circuit includes: multiple seventh extensions and at least one eighth extension; the drain of the TFT in the noise reduction sub-circuit includes: multiple fourth U-shaped portions; the seventh and eighth extensions extend into the openings of the corresponding fourth U-shaped portions; at least one eighth extension is located on at least one side of the multiple seventh extensions (e.g., the edge of the overall area where the TFT is located). Since the width of the eighth extension is greater than the width of the seventh extension, the eighth extension is easily identified during the detection process. When monitoring the channel size of the TFT, the eighth extension can be directly identified, avoiding the influence of the eighth extension on the channel size measurement of the TFT. This avoids false measurements when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the TFT and improving the stability of each TFT in the shift register.

[0082] Specifically, the noise reduction sub-circuit includes: a tenth transistor, denoted by M10 and M10'; the gate of the tenth transistor M10 is connected to the first pull-down node PD1, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected to the second pull-down node PD2, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the channel width of the tenth transistors M10 / M10' is greater than the channel width of the third transistor M3.

[0083] For example, the difference between the channel width of the tenth transistor M10 / M10' and the channel width of the third transistor M3 is 0.1 to 1.0 μm, specifically 0.5 μm.

[0084] For example, the width of the eighth extension in the tenth transistor M10 / M10' is greater than the width of the seventh extension, and the difference between the width of the eighth extension and the width of the seventh extension is 0.5 to 2 μm, specifically 1.0 μm.

[0085] In some embodiments, the channel width of the thin-film transistor in the input sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

[0086] The input sub-circuit is responsible for inputting signals during the input phase and pulling up the voltage of the pull-up node PU. Because the channel width of the thin-film transistor in the input sub-circuit is larger (for example, the channel width of the thin-film transistor in the input sub-circuit is larger than that of the thin-film transistor in the output sub-circuit), the leakage current of the thin-film transistor in the input sub-circuit can be reduced. This ensures that the voltage of the pull-up node PU can be maintained sufficiently during the output phase, so that the voltage of the pull-up node PU is high enough during the shutdown phase. This prevents the output capability of the thin-film transistor in the output sub-circuit from decreasing, thereby reducing the output voltage delay time. In turn, it can prevent data signal mischarging that could lead to horizontal black lines, thus improving the display effect and enhancing the user experience.

[0087] For example, the difference between the channel width of the first transistor M1 and the channel width of the third transistor M3 is 0.1 to 1.0 μm, specifically 0.5 μm.

[0088] It should be noted that, in addition to the sub-circuits described above, the shift register provided in this embodiment also includes other sub-circuits, which can be specifically described as follows: Figure 1 As shown. Of course, the individual sub-circuits in the shift register can also be structured as in related technologies, which will not be elaborated here.

[0089] Secondly, embodiments of this disclosure provide a gate driving circuit, which includes a plurality of cascaded shift registers as provided in any of the above embodiments. For example, the number of shift registers can be N, wherein the signal input terminal INPUT of the first-stage shift register is connected to the frame enable signal terminal STV; the signal input terminal INPUT of the (i+1)th-stage shift register is connected to the cascaded signal output terminal OUT_C ​​of the ith-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0090] The gate driving circuit provided in this embodiment is configured to provide an on or off signal to the gate of the thin-film transistor in each pixel driving circuit, so that the pixel driving circuit controls the light-emitting device to emit light.

[0091] It should be noted that the light-emitting devices involved in the embodiments of this disclosure may include, but are not limited to, organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or micro light-emitting diodes (MicroLEDs). Optionally, the light-emitting device is an OLED device.

[0092] For a detailed explanation of the specific structure of a shift register, please refer to the detailed description of shift registers mentioned above. Repeated parts will not be repeated here.

[0093] Thirdly, embodiments of this disclosure provide a display device including the gate driving circuit of any of the above embodiments. This display device can be, for example, any product with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0094] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0095] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the positions of the components shown are only logical functional positions, and in actual implementation, they may be arranged in other positions.

[0096] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, characterized in that, The shift register includes: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; The input sub-circuit connects the signal input terminal and the pull-up node, and is configured to respond to the input signal input at the signal input terminal and write the input signal into the pull-up node to charge the pull-up node; the output sub-circuit connects the pull-up node, the clock signal input terminal, and the signal output terminal, and is configured to respond to the potential of the pull-up node and output the clock signal input at the clock signal terminal through the signal output terminal; the pull-up reset sub-circuit connects the pull-up node, the pull-up reset signal terminal, and the non-working level signal terminal, and is configured to respond to the pull-up reset signal input at the pull-up reset signal terminal and reset the potential of the pull-up node through the non-working level signal input at the non-working level signal terminal. The channel width of the thin-film transistor in the pull-up reset sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

2. The shift register according to claim 1, characterized in that, The first electrode of the thin-film transistor in the output sub-circuit includes: a plurality of first extensions and at least one second extension; the second electrode of the thin-film transistor in the output sub-circuit includes: a plurality of first U-shaped portions; The first extension and the second extension extend into the opening of the corresponding first U-shaped portion; at least one second extension is located on at least one side of the plurality of first extensions; The width of the second extension is greater than the width of the first extension.

3. The shift register according to claim 1, characterized in that, The first electrode of the thin-film transistor in the pull-up reset circuit includes: a plurality of third extensions and at least one fourth extension; the second electrode of the thin-film transistor in the pull-up reset circuit includes: a plurality of second U-shaped portions; The third extension and the fourth extension respectively extend into the opening of the corresponding second U-shaped portion; at least one of the fourth extensions is located on at least one side of the plurality of third extensions; The width of the fourth extension is greater than the width of the third extension.

4. The shift register according to claim 1, characterized in that, The input sub-circuit includes a first transistor; the pull-up reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a storage capacitor. The control electrode and first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the control electrode of the second transistor is connected to the pull-up reset signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal; the control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal.

5. The shift register according to claim 1, characterized in that, The shift register further includes a discharge circuit; the discharge circuit is connected to the frame enable signal terminal, the non-working level signal terminal and the pull-up node, and is configured to respond to the frame enable signal input at the frame enable signal terminal, and discharge the pull-up node through the non-working level signal input at the non-working level signal terminal; The channel width of the thin-film transistor in the discharge circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

6. The shift register according to claim 5, characterized in that, The first electrode of the thin-film transistor in the electron discharge circuit includes: a plurality of fifth extensions and at least one sixth extension; the second electrode of the thin-film transistor in the electron discharge circuit includes: a plurality of third U-shaped portions; The fifth extension and the sixth extension respectively extend into the opening of the corresponding third U-shaped portion; at least one of the sixth extensions is located on at least one side of the plurality of fifth extensions; The width of the sixth extension is greater than the width of the fifth extension.

7. The shift register according to claim 5, characterized in that, The discharge circuit includes: a seventh transistor; the control electrode of the seventh transistor is connected to the frame enable signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal.

8. The shift register according to claim 1 or 5, characterized in that, The shift register further includes a noise reduction sub-circuit; the noise reduction sub-circuit is connected to a pull-down node, a non-working level signal terminal, and a pull-up node, and is configured to respond to the potential of the pull-down node and reduce noise on the pull-up node through a non-working level signal input from the non-working level signal terminal; The channel width of the thin-film transistor in the noise reduction sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

9. The shift register according to claim 8, characterized in that, The first electrode of the thin-film transistor in the noise reduction sub-circuit includes: a plurality of seventh extensions and at least one eighth extension; the second electrode of the thin-film transistor in the noise reduction sub-circuit includes: a plurality of fourth U-shaped portions; The seventh extension and the eighth extension respectively extend into the opening of the corresponding fourth U-shaped portion; at least one of the eighth extensions is located on at least one side of the plurality of seventh extensions; The width of the eighth extension is greater than the width of the seventh extension.

10. The shift register according to claim 9, characterized in that, The noise reduction sub-circuit includes: a tenth transistor; the control electrode of the tenth transistor is connected to a pull-down node, the first electrode is connected to a pull-up node, and the second electrode is connected to a non-working level signal terminal.

11. The shift register according to claim 1, characterized in that, The channel width of the thin-film transistor in the input sub-circuit is greater than the channel width of the thin-film transistor in the output sub-circuit.

12. A gate driving circuit, characterized in that, The gate drive circuit includes a plurality of cascaded shift registers as described in any one of claims 1 to 11.

13. A display device, characterized in that, The display device includes the gate driving circuit as described in claim 12.

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