Image sensor and electronic device

Abstract

The utility model provides an image sensor and electronic equipment. The image sensor comprises the following steps: providing a semiconductor substrate, forming a first groove and a first filling layer on a second surface, forming a second groove on the first filling layer, and preparing a second filling layer comprising a first structure layer and a second structure layer. On the basis of the design, the first groove and the first filling layer are firstly formed, the second groove is prepared in the first filling layer, the second filling layer with the first structure layer and the second structure layer is formed on the basis of the second groove, a signal matching modulation structure and a crosstalk improvement structure can be formed on the basis of the second filling layer, and the crosstalk can be improved on the basis of the design of the second filling layer. The problem of matching difference between different pixels in the pixel array is solved while crosstalk is improved, and the imaging quality is improved.

Description

Technical Field

[0001] This utility model belongs to the field of image acquisition technology, and in particular relates to an image sensor and a corresponding electronic device. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on the different components, they can be divided into two main categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor).

[0003] With the continuous development of CMOS integrated circuit manufacturing processes, especially the design and manufacturing processes of CMOS image sensors (CIS), CMOS image sensors have gradually replaced CCD image sensors as the mainstream. Compared with CCD, CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application value in fields such as machine vision, consumer electronics, high-definition surveillance, and medical imaging.

[0004] However, crosstalk between imaging signals often exists during the imaging process of image sensors, affecting the final imaging effect. In some applications, such as high-resolution, low-pixel CIS products with 100-megapixel or 200-megapixel resolutions, there is often a need to fuse multiple high-resolution pixels into a low-resolution image to suit different application scenarios. A 4x4 color filter arrangement becomes one option. However, the 4x4 arrangement causes differences in the physical environment surrounding the same color. These differences in the physical environment lead to variations in signal crosstalk at different locations of the same color, resulting in color noise in the image and affecting the imaging effect. In addition, the fabrication processes for structures that mitigate crosstalk and differences in existing technologies are often quite complex.

[0005] Therefore, it is essential to provide an image sensor or electronic device that can effectively address the problems of crosstalk between imaging signals and the differences in crosstalk between different pixels in existing technologies. Utility Model Content

[0006] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide an image sensor and electronic device to solve the problems of crosstalk between imaging signals of pixels in pixel arrays, the difficulty in effectively solving the crosstalk differences between different pixels, and the complexity of the corresponding manufacturing process in the prior art.

[0007] To achieve the above object and other related objects, the utility model provides a kind of image sensor, the image sensor can be prepared using the preparation method described above, of course, it can also be prepared using other methods, the image sensor includes:

[0008] Semiconductor substrate, the semiconductor substrate has opposite first face and second face;

[0009] First groove, from the second face of the semiconductor substrate extends into the semiconductor substrate;

[0010] First filling layer, filled in the first groove;

[0011] Second groove, in the first filling layer, and the second groove extends into the corresponding first groove from the second face of the semiconductor substrate;

[0012] Second filling layer, at least in the second groove, wherein:

[0013] The second filling layer includes first structure layer and second structure layer, the first structure layer fills the second groove and covers the first filling layer surface exposed by the second groove to form signal matching modulation structure, and the second structure layer is located on the second face of the semiconductor substrate to form crosstalk improvement structure.

[0014] The utility model also provides an electronic equipment, including the image sensor of any scheme as described above.

[0015] As described above, the image sensor and electronic equipment of the application, in the preparation process, first groove and first filling layer are formed, second groove is prepared in the first filling layer, second filling layer with first structure layer and second structure layer is formed based on second groove, signal matching modulation structure and crosstalk improvement structure can be formed based on second filling layer, the problem of matching difference between different pixels in pixel array can be optimized while improving crosstalk based on the design of second filling layer, and the imaging quality is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0017] Figure 1 The basic structure block diagram of an image sensor system is shown.

[0018] Figure 2A schematic diagram of a pixel circuit of an image sensor.

[0019] Figure 3 A flow chart of the preparation of an image sensor in an embodiment of the present application.

[0020] Figure 4 A schematic diagram of providing a semiconductor substrate in the preparation of an image sensor in the present application.

[0021] Figure 5 A schematic diagram after a front side process in the preparation of an image sensor in the present application.

[0022] Figure 6 A schematic diagram after back side thinning in the preparation of an image sensor in the present application.

[0023] Figures 7-12 A schematic diagram of forming a first trench, a surface cover layer, a first fill layer, a structure after thinning the first fill layer, a second trench and a second fill material layer in the preparation of an image sensor in the present application.

[0024] Figures 13-16 A first example of forming a second fill layer in the preparation of an image sensor in the present application.

[0025] Figure 17 A diagram of forming a lens corresponding to the first example in the preparation of an image sensor in the present application.

[0026] Figures 18-22 A second example of forming a second fill layer in the preparation of an image sensor in the present application.

[0027] Figure 23 A diagram of forming a lens corresponding to the first example in the preparation of an image sensor in the present application.

[0028] Figure 24 And Figure 25 A structure corresponding to a second trench in the preparation of an image sensor in the present application.

[0029] Figure 26 And Figure 27 A schematic diagram of a pixel circuit and layout of a pixel unit in an image sensor in the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail with specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied in different specific embodiments, and the details in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0031] It should be emphasized that the term "comprises / comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0032] Features described and / or illustrated with respect to one implementation can be used in the same or similar manner in one or more other implementations, in combination with or in place of features in other implementations. As detailed in the description of the new embodiments, for ease of illustration, cross-sectional views of the device structures are sometimes shown on a larger scale than actual scale. The illustrations presented herein are examples only and should not limit the scope of the present disclosure. In actual fabrication, three-dimensional structures can be formed in the length, width, and depth dimensions.

[0033] For convenience in description, spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper" and the like can be used for describing one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. The device can be oriented in any direction, and terms such as "above" can be understood accordingly. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present. A structure described as "on" a first feature can include embodiments in which the first and second features are in direct contact, and embodiments in which one or more other features are interposed between the first and second features.

[0034] Figure 1 A basic structure block diagram of an image sensor system is shown. The image sensor includes a readout circuit connected to a pixel array and a control circuit, a functional logic unit connected to the readout circuit, and the readout circuit and the control circuit connected to a state register to implement control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx), and pixel signals output by the pixel array are output to the readout circuit via column lines. In a specific implementation, the readout circuit can include an analog-to-digital conversion circuit (ADC) and other circuits. In some applications, after the pixels acquire image data, the image data is read out using a readout mode specified by the state register and then transmitted to the functional logic unit.

[0035] In some applications, the status register can include a programmable selection system to determine whether the readout system is exposed and read out in a rolling shutter mode or a global shutter mode. The functional logic unit can store raw image data or image data after image processing. In some implementations, the readout circuit can read out one row of image data along the readout column line at a time, although other manners of reading out image data can also be used. The operation of the control circuit can be determined by the current settings of the status register, for example, the control circuit generates a shutter signal for controlling image acquisition, which in some applications can be a global shutter signal to cause all pixels of the pixel array to acquire their image data simultaneously through a single acquisition window, or in other applications, the shutter signal can be a rolling shutter signal to cause the pixels of each pixel row of the pixel array to perform exposure and readout operations consecutively through the acquisition window.

[0036] Figure 2 An example of a pixel cell in an image sensor is shown. As shown, each pixel cell includes a photoconversion element (e.g., a photodiode) and a pixel circuit (e.g., transistors shown in the dashed box). The photodiode can be a buried photodiode (PPD) as used in current image sensors. In one example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel select transistor (RS) connected to the transfer transistor (TX) and the photodiode as shown in Figure 2 In some examples, the pixel circuit is implemented in a stacked manner, including the reset transistor, the source follower transistor, and the pixel select transistor on a first circuit chip, and the transfer transistor on a second circuit chip, with the photodiode in the second circuit chip connected to the other transistors in the first circuit chip based on the transfer transistor. In further examples, the pixel circuit can also include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoconversion element generates photocharge in response to incident light during exposure, the transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer the accumulated charge in the photoconversion element to the floating diffusion region, the reset transistor is connected between a power supply voltage and the floating diffusion region and is responsive to a reset signal to reset the sensor pixel circuit (e.g., discharge or charge the floating diffusion region and the photodiode to a current voltage), the floating diffusion region is connected to the gate of the source follower transistor, the source follower transistor is connected between the power supply voltage and the pixel select transistor and is responsive to the potential of the floating diffusion region and outputs it, and the pixel select transistor is connected between the source follower transistor and a bit line and is responsive to a pixel select control signal to enable pixel selection readout and output it to a readout column.

[0037] However, in the imaging process of the image sensor, there is often crosstalk between the imaging signals, thereby affecting the final imaging effect. In some applications, such as in high-resolution small pixels, such as 1 billion, 2 billion pixel CIS products, multi-pixel high-resolution fusion into low-resolution is often required to adapt to different application scenarios, and 4*4 color arrangement becomes a choice. Due to the 4*4 arrangement, the physical environment around the same color will be different, and the difference caused by the physical environment will cause the signal crosstalk of the same color at different positions to be different, which will produce color noise on the image, thereby affecting the imaging effect. The preparation process of the existing technology to alleviate the crosstalk and difference structure is often also relatively complex. The present application can effectively improve the above-mentioned crosstalk and difference and process design problems by designing the structure and process of the image sensor.

[0038] The embodiments will be described in detail below.

[0039] Embodiment one:

[0040] Referring to Figure 3 The present embodiment provides a preparation method of an image sensor, Figure 3 is shown as a flowchart of the preparation method, wherein the preparation method comprises the following steps:

[0041] S1: providing a semiconductor substrate, the semiconductor substrate having opposite first and second surfaces;

[0042] S2: preparing a first trench in the semiconductor substrate from the second surface of the semiconductor substrate;

[0043] S3: preparing a first filling layer in the first trench, the first filling layer filling in the first trench and extending to cover the semiconductor substrate around the first trench;

[0044] S4: preparing a second trench in the first filling layer, the second trench corresponding to the first trench and the second trench extending from the second surface of the semiconductor substrate to the corresponding first trench;

[0045] S5: preparing a second filling layer in the second trench, wherein:

[0046] The second filling layer comprises a first structure layer and a second structure layer, the first structure layer filling the second trench and covering the surface of the first filling layer exposed by the second trench to form a signal matching modulation structure, and the second structure layer is located on the second surface of the semiconductor substrate to form a crosstalk improvement structure.

[0047] In the image sensor and the preparation thereof of the embodiment, the first trench and the first filling layer are first formed, then the second trench is prepared in the first filling layer, the second filling layer including the first structure layer and the second structure layer is formed based on the second trench, the signal matching modulation structure and the crosstalk improvement structure can be formed based on the second filling layer, the matching difference problem between different pixels in the pixel array can be optimized while improving the crosstalk through the design of the second filling layer, and the imaging quality is improved. It should be noted that the preparation sequence corresponding to the existing process in the above steps can be changed according to actual needs, as long as the realization of the beneficial effects of the present application is not affected.

[0048] The preparation of the image sensor of the present application will be described in detail below with reference to specific embodiments.

[0049] First, as shown in Figure 4 , step S1 is performed, and a semiconductor substrate 101 is provided, which has opposite first and second surfaces 101a (upper surface) and 101b (lower surface).

[0050] Specifically, the semiconductor substrate 101 can be a structure composed of a single material layer, including but not limited to a silicon substrate, which can be monocrystalline silicon, monocrystalline germanium, polycrystalline silicon, amorphous silicon, and also can be a silicon germanium compound, etc. Of course, the semiconductor substrate 101 can also be a silicon-on-insulator (SOI), etc. In addition, the semiconductor substrate 101 can also have an N-type doped or P-type doped region to meet actual needs.

[0051] In addition, the semiconductor substrate 101 as the substrate of the image sensor can also be a multi-layer structure, such as including a semiconductor substrate and an epitaxial layer formed on the surface of the semiconductor substrate, the epitaxial layer as a device functional layer, realizing the preparation of the device of the image sensor. In other embodiments, the semiconductor substrate 101 can be any structure used to prepare the functional area of the image sensor in the field of image sensors, and the photosensitive element, each transistor, and interconnection wiring of the CMOS image sensor can be prepared based on the semiconductor substrate 101.

[0052] In an example, the device functional layer can be a part of the semiconductor substrate 101, for example, an epitaxial layer (EPI) formed on a semiconductor substrate (such as a silicon substrate), the epitaxial layer as a device functional layer, the epitaxial layer can be a P-type silicon epitaxial layer, which can be formed directly by epitaxial process, or can be formed by other ways of existing process, at this time, the semiconductor substrate and the epitaxial layer constitute the semiconductor substrate 101. Among them, Figure 4 It can be considered that the first surface 101a is the upper surface of the epitaxial layer, and the second surface 101b is the lower surface of the epitaxial layer. In addition, Figure 6 the surface 101c in the above is obtained by flipping the back surface and thinning, which is still called the second surface.

[0053] In some applications, the functional regions (including semiconductor devices) of the image sensor are fabricated within the device functional layer. In other applications, the semiconductor substrate 101 can be considered as a doped substrate as a whole, including the device functional layer of the first doping type (P-type). In this case, the functional regions of the image sensor can be fabricated within the semiconductor substrate 101, including the photoelectric conversion doped regions of the second doping type (N-type). Of course, if needed, the required structure of the image sensor can also be fabricated within the semiconductor substrate or other material layers. A back-illuminated image sensor can be fabricated based on this semiconductor substrate and device functional layer.

[0054] Next, as Figures 5-7 As shown, in step S2, a first trench 108 is formed in the semiconductor substrate 101 from the second surface 101b.

[0055] Please see Figure 5 and Figure 6 As an example, before forming the first trench 108, the following steps are also included:

[0056] A shallow trench isolation structure 103 is formed on the first surface 101a side of the semiconductor substrate 101. The material includes, but is not limited to, silicon oxide. When forming the shallow trench isolation structure 103, a surface dielectric layer 102 is also prepared on the trench surface, which can be a silicon oxide layer formed by thermal oxidation. Furthermore, the method also includes the step of forming a photoelectric conversion doped region 104 and an isolation region 105 with different doping types from the first surface 101a side, such as the isolation region 105 having a first doping type P-type and the photoelectric conversion doped region 104 having a second doping type N-type.

[0057] The image sensor fabrication process also includes forming various semiconductor devices, such as transmission transistors 106, from the first surface layer. Furthermore, an interconnect layer 107 for electrical connection and routing of the transistors is formed, such as... Figure 5 As shown. In other examples, a support substrate may be further formed on the interconnect layer 107 to facilitate subsequent processes. Furthermore, before performing the second-side process, a process of flipping the aforementioned structure is included. After flipping, the structure can be further thinned to obtain the second surface 101c for subsequent processes, such as... Figure 6 As shown.

[0058] Specifically, the semiconductor device (not shown in the figure) may include photoelectric conversion elements and the corresponding transistors of the pixel circuit of the image sensor. The photoelectric conversion elements realize the conversion of photoelectricity, and the photoelectric conversion doped region is a component of the photoelectric conversion elements. Of course, it may also include other CIS pixel circuit devices in the prior art to realize the functions of image acquisition and subsequent imaging. For example, the pixel circuit may include transmission transistors TX, etc. See [reference needed]. Figure 26As shown, it may also include a reset transistor RST, an output transistor SF, a pixel selection transistor RS, and a gain adjustment transistor DCG, etc.

[0059] As an example, the isolation region 105 can be ion-doped to achieve isolation. In one example, the semiconductor substrate 101 includes a semiconductor substrate and an epitaxial layer, with the epitaxial layer serving as the device functional layer. The isolation region 105 can penetrate the device functional layer. Of course, in some implementations, the depth of the isolation region 105 can be set according to the location of the photoelectric conversion element or actual needs to achieve isolation. Figure 5 In the example shown, the bottom of the isolation region 105 is closer to the first surface 101a than the photoelectric conversion doped region 104.

[0060] In an optional example, the shallow trench isolation structure 103 and the subsequent first trench and second trench are all formed at positions corresponding to the isolation region 105, and the device isolation function can be achieved based on the structure formed by each part according to the requirements. For example, the position of the first trench 108 corresponding to the isolation region 105 can mean that the first trench 108 is completely located within the projection range of the isolation region 105, that is, the periphery of the first trench corresponds to the isolation region 105, or the edge of the first trench 108 is aligned with the edge of the isolation region 105.

[0061] Please see Figure 7 As shown, in one example, the method for forming the first trench 108 may be:

[0062] First, a first mask layer (not shown in the figure) is formed on the second surface 101c of the semiconductor substrate 101; then, the semiconductor substrate 101 is etched based on the first mask layer to form a first trench 108. Optionally, the first mask layer includes, but is not limited to, a hard mask layer, such as a silicon nitride mask layer.

[0063] In one example, this step involves fabricating a deep trench isolation structure on the back side (photosensitive surface) of a back-illuminated image sensor. First, the first isolation structure on the back side is patterned using a photolithography process, and then an etching process is performed to fabricate the trench structure in the area of ​​the first isolation structure on the back side defined by the photolithography process.

[0064] Optionally, the depth of the first trench 108 is greater than 0.5 μm and less than or equal to the thickness of the semiconductor substrate. Further, the depth of the first trench 108 is less than or equal to the thickness of the device functional layer (such as an epitaxial layer); wherein, the thickness of the semiconductor substrate (such as a silicon substrate) can be distributed between 1 μm and 15 μm.

[0065] Next, as Figures 8-10As shown, step S3 is performed to prepare the first filling layer 110 in the first trench 108, the first filling layer 110 fills in the first trench 108 and extends on the semiconductor substrate 101 around the first trench 108.

[0066] As shown, step S3 is performed to prepare the first filling layer 110 in the first trench 108, the first filling layer 110 fills in the first trench 108 and extends on the semiconductor substrate 101 around the first trench 108. Figure 8 As shown, as an example, before the first filling layer 110 is prepared in the first trench 108, a step of forming a surface covering layer 109 on the inner wall of the first trench 108 and the surface of the semiconductor substrate 101 around the first trench 108 is further included, and the first filling layer 110 is subsequently formed on the surface covering layer 109 and forms a stack barrier structure with the surface covering layer 109, and the stack barrier structure formed by the surface covering layer 109 and the first filling layer 110 forms the basis of the subsequent process, which improves the process stability. Details will be further described in the corresponding subsequent process.

[0067] As an example, the surface covering layer 109 includes at least one of an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, and a tantalum oxide layer, that is, the surface covering layer 109 material can be a common oxide or nitride material, including aluminum oxide, silicon oxide, silicon nitride, hafnium oxide, tantalum oxide, etc.

[0068] In addition, the surface covering layer 109 is at least one layer, that is, it can be a single layer or multiple layers, and when the surface covering layer 109 is multiple layers, it is a combination of the above-mentioned material layers, and the thickness of the single-layer surface covering layer 109 is between 1 nm and 200 nm, such as 2 nm, 10 nm, 50 nm, 100 nm, etc.

[0069] Specifically, to prepare the surface covering layer, one or a combination of ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition) techniques can be used.

[0070] As shown, step S3 is performed to prepare the first filling layer 110 in the first trench 108, the first filling layer 110 fills in the first trench 108 and extends on the semiconductor substrate 101 around the first trench 108. Figure 9 And Figure 10 As shown, after the surface covering layer 109 is formed, a step of forming a filling material layer in the first trench 108 is included to obtain the first filling layer 110.

[0071] The specific steps can be: depositing an initial material layer on the semiconductor substrate 101 in the first trench 108 and around the first trench 108, such as Figure 9 As shown, then the initial material layer is subjected to chemical mechanical polishing (CMP) to obtain the first filling layer 110, such as Figure 10 As shown, the same reference number 110 is used to represent the polishing before and after.

[0072] Specifically, the first filling layer 110 can be prepared using one or a combination of ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), and PVD (Physical Vapor Deposition) techniques. Furthermore, the material of the first filling layer 110 can be a transparent material with a refractive index different from that of the semiconductor substrate (such as silicon), which helps prevent crosstalk of optical signals. For example, the material of the first filling layer 110 can be a non-metallic material, such as silicon oxide, aluminum oxide, or silicon nitride.

[0073] Specifically, the first filler layer 110 completely or partially fills the first trench 108 on the back side, so that the entire surface of the first trench 108 on the back side is covered with the material of the first filler layer. The portion of the first filler layer on the silicon surface can be planarized by CMP process, so that the remaining material of the first filler layer on the silicon surface is planarized.

[0074] Next, as Figure 11 As shown, step S4 is performed: a second trench 111 is prepared in the first filling layer 110. The second trench 111 corresponds to the first trench 108 and extends from the second surface 101c of the semiconductor substrate 101 to the corresponding first trench 108 for subsequent preparation of the second filling layer.

[0075] Specifically, in this step, the fabrication of the second trench 111 on the back side can be achieved by first patterning the second trench 111 on the back side using a photolithography process, and then using an etching process to fabricate the trench structure in the area of ​​the second trench on the back side defined by the photolithography process.

[0076] As an example, the depth of the second trench 111 is greater than 0.1 μm and less than the depth of the first trench 108. For example, the depth of the second trench 111 can be set to 0.2 μm, 0.3 μm, 0.4 μm, etc.

[0077] Finally, as Figures 12-23 As shown, step S5 is performed: a second filling layer is prepared in the second trench 111, wherein: the second filling layer includes a first structural layer and a second structural layer, the first structural layer fills the second trench and covers the surface of the first filling layer 110 exposed in the second trench to form a signal matching modulation structure, and the second structural layer is located on the second surface 101c of the semiconductor substrate 101 to form a crosstalk improvement structure.

[0078] Please see Figures 12-17 As shown, in one implementation, the step of preparing the second filling layer includes:

[0079] First, a second filling material layer 112 is formed on the inner wall of the second trench 108 and the surface of the surrounding first filling layer 110, such as... Figure 12As shown; in this step, the preparation of the second filling material layer 112 can be carried out by one or more of the following techniques: ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition).

[0080] The second filling layer is made of a light-absorbing material (a material with low transmittance of visible light), such as a metallic material like tungsten, aluminum, or copper. The second filling layer can completely or partially fill the second trench 108, and the entire surface of the second trench 108 is covered by the first filling layer.

[0081] Next, the second filling material layer 112 is etched to obtain the second filling layer, wherein:

[0082] In one example, such as Figure 13 As shown, the second filling layer includes a first structure 113 and a second structure 114 in contact with each other, and a first modified structure group is formed based on the first structure and the second structure; wherein, in this example, the first structure 113 constitutes the first structural layer and the second structure 114 constitutes the second structural layer.

[0083] In another example, such as Figure 14 As shown, the second filling layer includes a first structure 113 and a second structure 114 in contact with each other, and the second filling layer also includes a third structure 115 located on the first filling layer. Based on the third structure 115 at this location, a second modified structure group is also formed, such as... Figure 14 As shown in the square dashed box, the first modified structure group is as follows: Figure 14 The elliptical dashed box is shown in the figure. In this example, the first structure 113 constitutes the first structural layer, and the second structure 114 and the third structure 115 constitute the second structural layer.

[0084] The first structure 13 and the second structure 14, which are in contact, are formed in the semiconductor substrate and extend into the material layer above the semiconductor substrate. This effectively reduces the mutual interference between signals. The first modified structure group can perform matched modulation to improve the inconsistency of signal interference between pixels and obtain uniform image information. In addition, the second modified structure group, formed on the semiconductor substrate, can serve as a grid structure above to prevent incident light crosstalk, thereby improving crosstalk. Furthermore, the first and second modified structure groups can be fabricated using the same process, simplifying the process and saving costs.

[0085] As an example, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench 108. When the second modified structure group is present, see [reference needed]. Figure 14 As shown, the number of combinations of the two corresponds to the first groove, that is, each first groove is provided with a first modified structure group or a second modified structure group.

[0086] Please see Figure 15 As shown, in one example, in the first modified structure group, the second filling layer includes the first structure 113 and the second structure 114 in contact with each other, and the width of the second structure 114 is greater than the width of the first structure 113. In this example, the second structure with the larger width is still indicated by the reference numeral 114.

[0087] In another example, the second filling layer also includes a third structure 115 located on the first filling layer. In this example, the width of the third structure 115 can be the same as the width of the first structure 113, such as... Figure 15 As shown; of course, in other further examples, the width of the third structure 115 can also be designed to be consistent with the width of the second structure 114, such as the third structure 115 and the second structure 114 having the same width, such as... Figure 16 As shown.

[0088] Please see Figure 16 As shown, as an example, at least the second structure 114 has an extension extending toward the center of the pixel array, and the widths of the extensions at different locations from the center of the pixel array may be the same or different. When the third structure 115 is present, the third structure may also have an extension extending toward the center of the pixel array.

[0089] Specifically, the extension refers to the area on the side facing the center of the pixel array where the second structure 114 extends beyond the first structure 113, such as... Figure 16 As shown in the elliptical dashed box, for ease of understanding, the width of the extension can be considered as the distance between the edge of the second structure 114 and the center line of the first groove on the side facing the center of the pixel array. Furthermore, the third structure 115 also has a corresponding extension, so that the second structure 114 and the third structure 115 constitute a structural group with extensions. They are designed as a whole. In this structural group, the widths of the extensions at different locations from the center of the pixel array may be the same or different. When the widths are different, the width of the extension at the corresponding position can be adjusted based on the principal ray angle CRA.

[0090] Please see Figure 12 and 18 As shown in Figure 22, in another implementation, the preparation of the second filling layer includes:

[0091] First, a second filling material 112 is formed on the inner wall of the second trench 111 and the surface of the surrounding first filling layer 110, such as... Figure 12 As shown, the preparation and structure of the second filler material 112 are described above.

[0092] Next, the second filler layer and the first filler layer are etched to obtain the first structure 121, such as... Figure 18As shown, in this example, the second filling layer material layer on the surface can be etched away by a direct etching process (without a photolithography process), and since part of the second filling layer material is located in the second groove, the surface etching process will cause part of the second filling layer material to remain in the second filling layer to form the first structure 121.

[0093] Next, an intermediate separation layer 122 is formed on the surface of the etched structure, as shown in Figure 19 As shown, the material of the intermediate separation layer 122 can be the same as that of the first filling layer 110, and in this step, the preparation of the first filling layer can be performed again. The thin film layer can be prepared by one or a combination of ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition) techniques. In addition, the intermediate separation layer 122 on the silicon surface can be further polished by a CMP (chemical mechanical polishing) process to make the intermediate separation layer material on the silicon surface flat.

[0094] Continuing, a third filling material layer 123 is formed on the surface of the intermediate separation layer 122, as shown in Figure 20 As shown, the material of the third filling material layer 123 is the same as that of the second filling material layer 112, and in this step, the preparation of the second filling layer can be performed again. The thin film layer can be prepared by one or a combination of ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition) techniques.

[0095] Finally, the third filling material 123 is etched to obtain a second structure layer 124, wherein:

[0096] As shown in Figure 21 In an example, the second filling layer includes the first structure 121 and the second structure 124 corresponding to the intermediate separation layer 122, and a third modified structure group is formed based on the first structure 121 and the second structure 124. The third modified structure group is shown in the oval dashed box in Figure 21 As shown, in this example, the first structure 121 constitutes a first structure layer, and the second structure 124 constitutes a second structure layer.

[0097] In another example, continuing to refer to Figure 21 As shown, the second filling layer includes the first structure 121 and the second structure 124 corresponding to the intermediate separation layer 122, and a third modified structure group is formed based on the first structure 121 and the second structure 124. The second filling layer further includes a third structure layer 125 on the intermediate separation layer 122, and a fourth modified structure group is formed based on the third structure 125. The third modified structure group is shown in the oval dashed box in Figure 21 As shown, the fourth modified structure group is shown in the oval dashed box in Figure 21The first structure 121 and the second structure 124 are shown in the square dashed box. In this example, the first structure 121 constitutes a first structure layer, and the second structure 124 and the third structure 125 constitute a second structure layer.

[0098] As an example, the second filling layer includes corresponding first structures 121 and second structures 124, and the width of the second structure 124 is greater than the width of the first structure 121; further, the second structure 124 can also be provided with an extension; in addition, when there is a third structure 125, the second structure 124 and the third structure 125 can be designed as a whole as a structure group. As an example, the combination of the first modified structure group and the second modified structure group corresponds to the first groove 108 one by one. The similar structure related description here in this embodiment can refer to the content in the above implementation manner, which will not be repeated here.

[0099] Please refer to Figure 22 As an example, at least the second structure 124 has an offset distance d relative to the corresponding first groove, and the offset distance d to different positions from the center of the pixel array is the same or different. When there is a third structure 125, the third structure 125 can also have an offset distance d relative to the first groove. Among them, the second structure 124 and the third structure 125 can constitute a structure group with an offset distance d, and they are designed as a whole. In this structure group, the width of the offset distance d to different positions from the center of the pixel array is the same or different, and when the width is different, the chief ray angle CRA can be adjusted.

[0100] As an example, the depth of the first groove 108 is greater than 0.5 μm; the thickness of the semiconductor substrate 101 is between 1 μm-15 μm; the depth of the second groove 111 is greater than 0.1 μm and less than the depth of the first groove.

[0101] As an example, the number of second grooves 111 is less than the number of first grooves 108.

[0102] Specifically, in this example, based on the second groove 111, a matching modulation structure can be formed, and based on the first groove 108, a crosstalk improvement structure can be obtained, and the design of the present application can be flexibly set.

[0103] As an example, the first filling layer 110 includes a light-transmitting material layer and has a different refractive index from the semiconductor substrate 101, and the second filling layer (such as including the first structure, the second structure and the third structure) includes a light-absorbing material layer.

[0104] As an example, the position of the second groove 111 is arranged based on a simulation manner.

[0105] Specifically, the second trench 111 can be set at the position where the simulation results show that the isolation strength needs to be enhanced. The pixels that receive inconsistent crosstalk can be obtained through simulation, and then a second communication can be prepared at the corresponding position. Matching modulation can be achieved through the second filling layer filled in the second trench to improve the uniformity of the interference.

[0106] Additionally, please see Figure 17 and Figures 24 to 27 As shown, after forming the second filling layer, the process also includes the steps of fabricating a color filter and microlens for the image sensor, both of which can be achieved using existing CIS processes and structures.

[0107] Please see Figure 24 As shown, as an example, the semiconductor substrate 101 includes a plurality of pixel blocks arranged in an array, wherein each pixel block is arranged periodically in a Bayer array and each pixel block corresponds to a color filter of the same color, and each pixel block has at least a first sub-pixel and a second sub-pixel with different environments.

[0108] Specifically, with Figure 24 Taking a 4x4 arrangement as an example, sub-pixels B1-4 and B4-4 are the first and second sub-pixels with different environments. Both sub-pixels B1-4 and B4-4 are blue, but their physical structures differ. Specifically, B1-4 is surrounded by blue material, while B4-4 is surrounded by blue, green (or yellow), and some red material. When light shines on the sensor surface, in addition to the light signals directly received by B1-4 and B4-4 themselves (assuming the amount of this light signal is the same), B1-4 will mainly receive crosstalk signals from B1-1, B1-2, B2-1, B2-3, B4-1, B3-2, B3-1, and B1-3, while B4-4 will mainly receive crosstalk signals from B4-1, B4-2, G3-1, G3-3, R1-1, G2-2, and G2-1. The crosstalk signal of B4-3 can be considered as follows: the physical environment of the same color is the same, so the amount of crosstalk signal generated is also the same. However, compared with B1-4, since G3-1, G3-3, R1-1, G2-2, and G2-1 are not blue, the main source of crosstalk in B4-4 is the signal of the four green (or yellow) colors (G3-1, G3-3, G2-2, and G2-1). Green (or yellow) colors have higher sensitivity and contribute more crosstalk signal, thus causing a difference in the signal amount between B1-4 and B4-4, affecting the imaging effect. That is, the 4*4 arrangement will cause the physical environment around the same color to be different. This difference in physical environment will cause the signal crosstalk of the same color at different positions to be different, which will be reflected in the image as color noise, thus affecting the imaging effect.

[0109] Specifically, the periodic arrangement of the Bayer matrix can be an arrangement of RGGB, or RYYB, or RGBW, RGBIR, or other color arrangement based on which a pixel block can obtain information of corresponding pixel points, that is, a periodic structure similar to the traditional Bayer matrix for obtaining image signal information.

[0110] As an example, as shown in Figure 25 The first groove 108 is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, and the second groove 111 is formed between adjacent pixel blocks and also between adjacent pixel units to correspond to the light collection center of the pixel unit.

[0111] Specifically, based on the example design, the second groove is arranged around the sub-pixel in different environments and corresponds to the second filling layer, that is, includes the first modified structure group or the third modified structure group, thereby facilitating matching adjustment, for example, the amount of crosstalk signal from the green (or yellow) color can be reduced in the above example, thereby improving the non-uniformity of the sub-pixel affected by the surrounding sub-pixels and improving the imaging quality. Further, in this example, the configuration position of the second groove corresponds to the center of the microlens, which is beneficial to optimize the low-light effect.

[0112] Further, in this example, one pixel block corresponds to four pixel units, and one pixel unit has four sub-pixels, and the first groove is formed between each sub-pixel, and the second groove is formed between the pixel blocks, and further, one microlens is arranged corresponding to one pixel unit.

[0113] In another example, as shown in Figures 24 to 27 The first groove 108 is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, and the second groove 111 is formed between adjacent pixel blocks.

[0114] Further, in this example, one pixel block corresponds to four pixel units, and one pixel unit has four sub-pixels, and the first groove is formed between each sub-pixel, and the second groove is formed between the pixel blocks, and further, one microlens is arranged corresponding to one pixel unit.

[0115] Please refer to Figure 26 As an example, each pixel block includes a plurality of pixel units to obtain focus information of different phases based on at least one pixel unit.

[0116] As an example, each pixel block includes four pixel units, and each pixel unit includes four sub-pixels, wherein the pixel unit and the microlens correspond one-to-one to form phase focus information corresponding to the microlens.

[0117] Specifically, different phase information of different phases can be obtained based on different sub-pixels under the same microlens, so as to realize phase focusing based on the calculation of the phase information of different phases. For example, the left two sub-pixels in a pixel unit under one microlens are combined to obtain left phase information, and the right two sub-pixels are combined to obtain right phase information. Based on the left phase information and the right phase information, phase focusing can be realized. Similarly, the upper and lower phase information can also be obtained based on the sub-pixels under one microlens. Based on the design of the above example, full-pixel phase focusing of the entire pixel array can be realized, and the focusing accuracy can be improved.

[0118] In actual operation, the signals of the sub-pixels in one pixel unit or one pixel block can also be combined and read to obtain the combined information, thereby improving the read frame rate. Of course, the information of each sub-pixel in the pixel array can also be read out respectively to form an image based on the sub-pixel information and improve the resolution.

[0119] As shown in Figure 27 and Figure 26 As an example, the pixel unit includes four photoelectric conversion doped regions (corresponding to PD1 to PD4) and four transfer control gates (corresponding to Tx1 to Tx4) corresponding to the photoelectric conversion doped regions, Figure 27 is shown as a pixel circuit diagram, Figures 13 to 17 is a corresponding layout structure, wherein,

[0120] The transfer control gates are arranged opposite to each other to form a central opening region, and the pixel unit further includes:

[0121] An output transistor SF is located at the center of the central opening region.

[0122] A floating diffusion region includes a first floating diffusion node FD1 and a second floating diffusion node FD2 located on both sides of the output transistor SF and connected to the corresponding transfer control gates TX1 to TX4; and

[0123] A device gate connected to at least one floating diffusion node; wherein the device gate can be the gate of other transistors in the pixel circuit, such as the gate of the reset transistor RST. In this example, the first floating diffusion point FD1 is connected. Of course, the gate of the gain control transistor DCG can also be connected according to the actual setting.

[0124] Specifically, the second groove 111 is arranged in the first groove in the periphery of the pixel unit, as shown by the square dashed box in the figure, that is, the first modified structure group or the third modified structure group is arranged in the periphery of the pixel unit. In this example, the center of the second groove is arranged corresponding to the center of each photoelectric conversion doped region in the pixel unit, so that the crosstalk between adjacent photoelectric conversion doped regions is effectively improved, thereby effectively improving the influence between the pixels at the corresponding position, facilitating mismatched modulation, and also improving the pixel sensitivity.

[0125] Embodiment two:

[0126] As shown in FIGS. 1-3, the present application also provides an image sensor, which is prepared by the preparation method of the image sensor in embodiment one, and the related structures and corresponding features can be referred to the description in the preparation method, which will not be repeated here. Of course, in other embodiments, the image sensor can also be obtained based on other preparation methods. The image sensor includes: Figures 21 to 27 Figure 25 A semiconductor substrate 101 having opposite first and second surfaces 101a and 101c;

[0127] A first trench 108 extending from the second surface 101c of the semiconductor substrate 101 into the semiconductor substrate 101;

[0128] A first filling layer 110 filled in the first trench 108, the first filling layer 110 also extending and covering the semiconductor substrate 101 around the first trench 108;

[0129] A second trench 111 located in the first filling layer 110, and the second trench 111 extending from the second surface 101c of the semiconductor substrate 101 into the corresponding first trench 108;

[0130] A second filling layer located at least in the second trench 111, wherein:

[0131] The second filling layer includes a first structure layer and a second structure layer, the first structure layer fills the second trench 111 and covers the surface of the first filling layer 110 exposed by the second trench 111 to form a signal matching modulation structure, and the second structure layer is located on the second surface 101c of the semiconductor substrate 101 to form a crosstalk improvement structure.

[0132] As an example, the image sensor further includes a surface covering layer 109 located in the inner wall of the first trench 108 and the surface of the semiconductor substrate 101 around the first trench 108, and the first filling layer 110 is formed on the surface covering layer 109 and constitutes a stacked barrier structure with the surface covering layer 109.

[0133] As an example, the image sensor further includes a surface covering layer 109 located in the inner wall of the first trench 108 and the surface of the semiconductor substrate 101 around the first trench 108, and the first filling layer 110 is formed on the surface covering layer 109 and constitutes a stacked barrier structure with the surface covering layer 109.

[0134] ​As an example, the second filling layer includes the first structure layer 113 and the second structure layer 114 in contact, and the first structure 113 and the second structure 114 in contact constitute the first modified structure group, or the second filling layer further includes the third structure 115 on the first filling layer 110, and the third structure 115 on the first filling layer 110 also constitutes the second modified structure group.

[0135] As an example, the image sensor further includes the intermediate interval layer 122 on the semiconductor substrate 101, the second filling layer includes the first structure 121 and the second structure 124 corresponding to the interval intermediate interval layer, and the third modified structure group is formed based on the first structure 121 and the second structure 124, or the second filling layer further includes the third structure 125 on the intermediate interval layer 122, and the fourth modified structure group is also formed based on the third structure layer 125.

[0136] As an example, the second filling layer includes the first structure 113 and the second structure 114 in contact, wherein: in the first modified structure group, the width of the second structure layer is greater than the width of the first structure layer; and / or, the combination of the first modified structure group and the second modified structure group corresponds to the first groove one by one; and / or, at least each second structure has an extension part extending towards the center of the pixel array, and the width of the extension part at different positions from the center of the pixel array is the same or different.

[0137] As an example, the second filling layer includes the first structure 121 and the second structure 124 corresponding to each other, wherein: in the third modified structure group, the width of the second structure layer is greater than the width of the first structure layer; and / or, the combination of the first modified structure group and the second modified structure group corresponds to the first groove one by one; and / or, at least the second structure has an offset distance relative to the corresponding first groove, and the size of the offset distance at different positions from the center of the pixel array is the same or different.

[0138] As an example, the semiconductor substrate includes a plurality of pixel blocks arranged in an array, each pixel block is arranged in a Bayer base structure, and each pixel block corresponds to the same color filter and has at least a first sub-pixel and a second sub-pixel with different environments.

[0139] As an example, the semiconductor substrate includes a plurality of pixel blocks arranged in an array, the pixel blocks are arranged in a Bayer base array, and the pixel blocks include a plurality of pixel units to obtain phase focus information based on at least the pixel units.

[0140] As an example, each pixel block includes four pixel units, and each pixel unit includes four sub-pixels, wherein the pixel unit corresponds to a microlens one by one to form phase focus information corresponding to the microlens.

[0141] As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, as shown in Figure 24 As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, as shown in Figure 26 As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, as shown in

[0142] As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, as shown in Figure 27 As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, as shown in ​ As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, as shown in

[0143] The output transistor is located at the center of the central opening region;

[0144] The floating diffusion region includes a first floating diffusion node and a second floating diffusion node located on both sides of the output transistor and connected to the corresponding transfer control gate; and

[0145] The device gate is connected to at least one floating diffusion node; wherein:

[0146] The second trench is arranged in the first trench at the periphery of the pixel unit.

[0147] Embodiment three:

[0148] The utility model further provides a kind of electronic equipment, including the image sensor as any one of above-mentioned scheme. Electronic equipment can be security monitoring, vehicle-mounted electronic, mobile phone camera, machine vision etc. equipment, based on the image sensor of the utility model can obtain high-quality image information, can be used for infrared utilization equipment.

[0149] As described above, the image sensor and electronic equipment of the present application first form the first trench and the first filling layer during preparation, prepare the second trench in the first filling layer, form the second filling layer with the first structure layer and the second structure layer based on the second trench, can form signal matching modulation structure and crosstalk improvement structure based on the second filling layer, can improve the matching difference between different pixels in pixel array while improving crosstalk based on the design of second filling layer, improve imaging quality. Therefore, the utility model effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0150] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. All equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. An image sensor, characterized in that, The image sensor includes: A semiconductor substrate having opposing first and second surfaces; A first trench extends from a second surface of the semiconductor substrate into the semiconductor substrate; The first filling layer fills at least the first trench; The second trench is located in the first filling layer, and the second trench extends from the second surface of the semiconductor substrate to the corresponding first trench; A second filling layer, located at least within the second trench, wherein: The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench and covers the surface of the first filling layer exposed by the second trench to form a signal matching modulation structure. The second structural layer is located on the second surface of the semiconductor substrate to form a crosstalk improvement structure.

2. The image sensor as described in claim 1, characterized in that, The image sensor also includes a surface cover layer located on the inner wall of the first trench and the surrounding surface of the semiconductor substrate.

3. The image sensor as described in claim 2, characterized in that, The number of surface coating layers is at least one; and / or, the thickness of a single surface coating layer is between 1 and 200 nm; and / or, the surface coating layer includes an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, or a tantalum oxide layer.

4. The image sensor as described in claim 1, characterized in that, The second filling layer includes a first structure and a second structure in contact, the first structure being located in the second trench and forming a first modified structure group based on the first and second structures; or, the second filling layer further includes a third structure located on a second surface of the semiconductor substrate, and forming a second modified structure group different from the first modified structure group based on the third structure; or, The image sensor includes an intermediate spacer layer located between the first structural layer and the second structural layer. The second filling layer includes corresponding first and second structures. The first structure is located in a second trench and forms a third modified structure group based on the first and second structures. Alternatively, the second filling layer also includes a third structure located on the intermediate spacer layer, and forms a fourth modified structure group different from the third modified structure group based on the third structure.

5. The image sensor as described in claim 4, characterized in that, When the second filling layer comprises the first and second structures in contact with each other, wherein: In the first modified structure group, the width of the second structure is greater than the width of the first structure; and / or, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench; and / or, at least the second structure has an extension extending toward the center of the pixel array, and the width of the extension at different positions from the center of the pixel array may be the same or different; or... When the second filling layer includes the corresponding first and second structures, wherein: In the third modified structure group, the width of the second structure is greater than the width of the first structure; and / or, the combination of the third modified structure group and the fourth modified structure group corresponds one-to-one with the first trench; and / or, at least the second structure has an offset distance relative to the corresponding first trench, and the offset distance is the same or different at different positions from the center of the pixel array.

6. The image sensor as claimed in claim 1, characterized in that, The depth of the first trench is greater than 0.5 μm and less than or equal to the thickness of the semiconductor substrate; and / or, the thickness of the semiconductor substrate is between 1 μm and 15 μm; and / or, the depth of the second trench is greater than 0.1 μm and less than the depth of the first trench; and / or, the number of the second trenches is less than the number of the first trenches; and / or, the first filling layer includes a light-transmitting material layer and has a different refractive index from the surrounding semiconductor substrate, and the second filling layer includes a light-absorbing material layer.

7. The image sensor as described in any one of claims 1-6, characterized in that, The semiconductor substrate includes a plurality of pixel blocks arranged in an array, each pixel block being arranged in a Bayer array, each pixel block corresponding to the same color filter and having at least a first sub-pixel and a second sub-pixel with different environments.

8. The image sensor as claimed in claim 7, characterized in that, The pixel block includes multiple pixel units to obtain different phase focusing information based on at least each pixel unit, wherein each pixel unit corresponds one-to-one with a microlens to form the phase focusing information corresponding to the microlens.

9. The image sensor as claimed in claim 8, characterized in that, Each pixel block includes four pixel units, each pixel unit includes four sub-pixels, and each sub-pixel includes a photoelectric conversion doped region and a transmission control gate corresponding to the photoelectric conversion doped region. The transmission control gates are arranged facing each other to form a central opening region. The pixel unit further includes: The output transistor is located at the center of the central opening region; The floating diffusion region includes a first floating diffusion node and a second floating diffusion node located on both sides of the output transistor and connected to the corresponding transmission control gate; and, The device gate is connected to at least one floating diffusion node; The second groove is disposed in the first groove surrounding the pixel unit.

10. The image sensor as described in claim 7, characterized in that, The first trench is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, wherein the second trench is formed between adjacent pixel blocks, or the second trench is also formed between adjacent pixel units to correspond to the light-gathering center of the pixel unit.

11. An electronic device, characterized in that, The electronic device includes an image sensor as described in any one of claims 1-10.

Images