Pixel and display device including same

Abstract

The utility model relates to a pixel and a display device including the same. The pixel includes: a light emitting element; a first transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the anode electrode of the light emitting element; a second transistor connected between the data line and the first node, the second transistor including a gate electrode connected to the first scan line; and a third transistor connected between the first power line and the second node, the third transistor including a gate electrode connected to the second node.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2024-0023555, filed on February 19, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to pixels and display devices including pixels, as well as electronic devices. Background Technology

[0004] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Therefore, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0005] Recently, head-mounted display devices (“HMDs”) have been developed. An HMD is a display device worn by a user in the form of glasses or a helmet to achieve virtual reality (“VR”) or augmented reality (“AR”), where the focus is formed at a distance close to the eyes. High-resolution panels are used in HMDs, and therefore, the number of pixels suitable for high-resolution panels is desired. Utility Model Content

[0006] The implementation provides pixels that can be applied to a high-resolution panel and a display device that includes the pixels.

[0007] According to an aspect of this disclosure, a pixel is provided, comprising: a light-emitting element; a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to an anode electrode of the light-emitting element; a second transistor connected between a data line and the first node, the second transistor including a gate electrode connected to a first scan line; and a third transistor connected between a first power line and a second node, the third transistor including a gate electrode connected to the second node.

[0008] The pixel may also include a storage capacitor connected between the first power line and the first node.

[0009] Storage capacitors can be metal oxide metal (“MOM”) capacitors, metal insulator metal (“MIM”) capacitors, or metal oxide semiconductor (“MOS”) capacitors.

[0010] The cathode electrode of the light-emitting element can be connected to a second power line, and a second power supply with a voltage lower than that of the first power supply is provided to the second power line.

[0011] The pixel may further include: a fourth transistor connected between the first power line and the third transistor, the fourth transistor including a gate electrode connected to the emission control line; and a fifth transistor connected between the anode electrode of the light-emitting element and the third power line, wherein initialization power is provided to the third power line, the fifth transistor including a gate electrode connected to the second scan line.

[0012] Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor can be a P-type transistor.

[0013] The high voltage supplied to the transmit control line may be different from the high voltage supplied to either the first scan line or the second scan line.

[0014] The high voltage supplied to the transmit control line can be set to a lower voltage than the high voltage supplied to either the first scan line or the second scan line.

[0015] Each of the first, second, and fifth transistors may be a high-voltage MOSFET, and each of the third and fourth transistors may be a medium-voltage MOSFET.

[0016] According to another aspect of this disclosure, a display device is provided, comprising: a pixel connected to a scan line and a data line; a scan driver configured to drive the scan line; and a data driver configured to drive the data line, wherein at least one pixel comprises: a light-emitting element; a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to an anode electrode of the light-emitting element; a second transistor connected between the first node and a corresponding data line of the data line, the second transistor including a gate electrode connected to the first scan line of the scan line; and a third transistor connected between the first power line and the second node, the third transistor including a gate electrode connected to the second node.

[0017] At least one pixel may also include a storage capacitor connected between the first power line and the first node.

[0018] Storage capacitors can be metal oxide metal (MOM) capacitors, metal insulator metal (MIM) capacitors, or metal oxide semiconductor (MOS) capacitors.

[0019] The cathode electrode of the light-emitting element can be connected to a second power line, and a second power supply with a voltage lower than that of the first power supply is provided to the second power line.

[0020] The display device may further include: an emission control line connected to a pixel; and an emission driver configured to drive the emission control line. At least one pixel may further include: a fourth transistor connected between a first power line and a third transistor, the fourth transistor including a gate electrode connected to a corresponding emission control line; and a fifth transistor connected between an anode electrode of a light-emitting element and the third power line, an initialization power supply being provided to the third power line, the fifth transistor including a gate electrode connected to a second scan line in the scan lines.

[0021] Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor can be a P-type transistor.

[0022] The high voltage supplied to the corresponding transmit control line may be different from the high voltage supplied to either the first scan line or the second scan line.

[0023] The high voltage supplied to the transmit control line can be set to a lower voltage than the high voltage supplied to either the first scan line or the second scan line.

[0024] Each of the first, second, and fifth transistors may be a high-voltage MOSFET, and each of the third and fourth transistors may be a medium-voltage MOSFET.

[0025] At least one pixel can be driven sequentially during an initialization cycle, a write cycle, a settling cycle, and an emit cycle. The emit driver can provide an emit disable control signal to the corresponding emit control line, causing the fourth transistor to turn off during a portion of the settling cycle and during the write cycle. The scan driver can provide an enable first scan signal to the first scan line, causing the second transistor to turn on during the initialization cycle and the write cycle. The scan driver can provide an enable second scan signal to the second scan line, causing the fifth transistor to turn on during the initialization cycle, the write cycle, and the settling cycle. The data driver can provide a data signal to the corresponding data line during the write cycle and provide a reference power supply voltage during other cycles.

[0026] At least one pixel can be driven sequentially during the initialization period, write period, stabilization period, and emit period. The emit driver can provide an emit disable control signal to the corresponding emit control line, causing the fourth transistor to turn off during a portion of the stabilization period and the write period. The scan driver can provide an enable first scan signal to the first scan line, causing the second transistor to turn on during the initialization period and the write period. The scan driver can provide an enable second scan signal to the second scan line, causing the fifth transistor to turn on during the initialization period, the write period, and the stabilization period. The data driver can provide data signals to the corresponding data lines during the initialization period and the write period.

[0027] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device includes: pixels connected to scan lines and data lines; a scan driver configured to drive the scan lines; and a data driver configured to drive the data lines, wherein at least one pixel includes: a light-emitting element; a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to an anode electrode of the light-emitting element; a second transistor connected between the first node and a corresponding data line of the data lines, the second transistor including a gate electrode connected to the first scan line of the scan lines; and a third transistor connected between the first power line and the second node, the third transistor including a gate electrode connected to the second node. Attached Figure Description

[0028] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings. However, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always denote the same elements.

[0030] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0032] Figure 3 It shows the driver Figure 2 The waveform diagram of the pixel method shown.

[0033] Figures 4A to 4C This is a diagram illustrating the principle of compensating for the threshold voltage of the first transistor.

[0034] Figure 5 It shows the basis Figure 2 The graph shows the voltage range of the data signal for the pixels shown.

[0035] Figure 6 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0036] Figure 7This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0037] Figure 8 It shows the driver Figure 7 The waveform diagram of the pixel method shown.

[0038] Figure 9 This illustrates a driver according to another embodiment. Figure 7 The waveform diagram of the pixel method shown.

[0039] Figure 10 This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0040] Figures 11 to 14 This is an example diagram illustrating an electronic device according to various embodiments of the present disclosure.

[0041] Figure 15 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment. Detailed Implementation

[0042] Exemplary embodiments are described in detail below with reference to the accompanying drawings, enabling those skilled in the art to readily practice this disclosure. This disclosure may be implemented in various different forms and is not limited to the exemplary embodiments described herein.

[0043] Parts irrelevant to the description will be omitted to clearly describe this disclosure, and identical or similar components will be designated with the same reference numerals throughout the specification. Therefore, the same reference numerals may be used to identify identical or similar elements in different drawings.

[0044] In the description, the expression "equal" can mean "substantially equal." That is, it can mean equal to the extent that a person skilled in the art would understand it as equal. Other expressions may omit "substantially."

[0045] The accompanying drawings depict several implementations of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented using logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connectors, and other electrical circuits. This can be achieved using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software to perform the various functions discussed in this disclosure, and can be selectively driven by firmware and / or software. Furthermore, each block, each unit, and / or each module can be implemented using dedicated hardware, or a combination of dedicated hardware for performing some functions of the block, unit, and / or module with a processor (e.g., one or more programmable microprocessors and associated circuitry) for performing other functions of the block, unit, and / or module. In some implementations, without departing from the scope of this disclosure, blocks, units, and / or modules can be physically separated into two or more separate blocks, two or more separate units, and / or two or more separate modules. Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules may be physically combined into more complex blocks, more complex units and / or more complex modules.

[0046] The term "connection" between two components can include both electrical and physical connections, but this disclosure is not necessarily limited to this. For example, the term "connection" used in a circuit diagram may mean an electrical connection, and the term "connection" used in sectional and plan views may mean a physical connection.

[0047] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed below may also be referred to as the “second” element.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “comprises” and / or “includes” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, this disclosure is not limited to the embodiments disclosed below and can be implemented in various forms. Each embodiment disclosed below may be implemented independently or may be combined with at least one other embodiment prior to implementation.

[0049] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0050] refer to Figure 1 The display device according to the embodiments of the present disclosure may include a display driver 210 and a display unit 110.

[0051] Display driver 210 can control display unit 110. For this purpose, display driver 210 may include timing controller 11 and data driver 12. Display unit 110 can display a predetermined image. For this purpose, display unit 110 may include scan driver 13 and pixel unit 14. Display driver 210 may be configured with one IC or multiple ICs.

[0052] The timing controller 11 can receive data corresponding to each frame and control signal from the processor 9. The processor 9 may correspond to a graphics processing unit (“GPU”), a central processing unit (“CPU”), an application processor (“AP”), etc. The control signals may include vertical synchronization signals, horizontal synchronization signals, data enable signals, etc.

[0053] Each period of the vertical synchronization signal can correspond to each frame period. Each period of the horizontal synchronization signal can correspond to each horizontal period. Data is provided in units of horizontal lines in each horizontal period, corresponding to pulses of the enable level of the data enable signal. Horizontal lines can refer to pixels connected to the same scan line (e.g., pixel rows).

[0054] The timing controller 11 can render data to correspond to the specifications of the display device. The timing controller 11 can correct the data, thereby displaying an image with uniform brightness on the pixel units 14. The data rendered or corrected by the timing controller 11 can be provided to the data driver 12. Furthermore, the timing controller 11 can provide data control signals to the data driver 12. Additionally, the timing controller 11 can provide scan control signals to the scan driver 13.

[0055] The data driver 12 can use the data and data control signals received from the timing controller 11 to generate data signals (or data voltages) to be provided to the data lines DL1, DL2, DL3, DL4... and DLm. Here, m can be a positive integer greater than 4.

[0056] The scan driver 13 can use scan control signals (e.g., clock signals, scan start signals, etc.) received from the timing controller 11 to generate enable scan signals to be provided to scan lines SL1, SL2, ..., SLn. Here, n can be a positive integer greater than 2. The enable scan signal can be set to a gate on-state voltage. In the example, when the scan signal is provided to a P-type transistor, the enable scan signal can be set to a low voltage. In the example, when the scan signal is provided to an N-type transistor, the enable scan signal can be set to a high voltage.

[0057] Scan driver 13 can sequentially provide enable scan signals to scan lines SL1 through SLn. Scan driver 13 can include scan stages configured as shift registers. Scan driver 13 can generate enable scan signals under the control of a clock signal by sequentially transmitting a scan start signal in the form of a pulse of conduction level to the next scan stage.

[0058] Pixel unit 14 may include pixels. Each pixel may be connected to a corresponding data line and a corresponding scan line. For example, pixel PXij may be connected to the i-th scan line and the j-th data line. Pixels may include pixels that emit light of a first color, pixels that emit light of a second color, and pixels that emit light of a third color. The first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue; the second color may be one of red, green, and blue other than the first color; and the third color may be one of red, green, and blue other than the first and second colors. Furthermore, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors.

[0059] Pixel unit 14 can be connected to a first power line PL1 and a second power line PL2. The first power line PL1 can provide a first drive power supply VDD from a power supply (not shown), and the second power line PL2 can provide a second drive power supply VSS from a power supply (not shown).

[0060] The first driving power supply VDD can be a power supply that provides driving current to the pixel. The second driving power supply VSS can be a power supply that provides driving current from the pixel. During the period when the pixel is set to the emission state, the first driving power supply VDD can be set to a voltage higher than that of the second driving power supply VSS.

[0061] The first power line PL1 and the second power line PL2 can be commonly connected to a pixel, but the embodiments of this disclosure are not limited thereto. In another embodiment, the first power line PL1 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels. In another embodiment, the second power line PL2 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels. That is, in the embodiments of this disclosure, each pixel can be connected to any one of the multiple power lines of the first power line PL1 and any one of the multiple power lines of the second power line PL2.

[0062] Figure 2 This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0063] refer to Figure 2 According to embodiments of this disclosure, pixel PXij can be connected to corresponding signal lines SLi and DLj. For example, pixel PXij can be connected to the i-th scan line SLi and the j-th data line DLj. In embodiments, pixel PXij can also be connected to a first power line PL1 and a second power line PL2.

[0064] According to embodiments of the present disclosure, a pixel PXij may include a light-emitting element LD and a pixel circuit for controlling the amount of current supplied to the light-emitting element LD.

[0065] The light-emitting element (LD) can be connected between a first electric power line PL1 and a second electric power line PL2. In the example, the first electrode (or anode electrode) of the LD can be electrically connected to the first electric power line PL1 via a first transistor M1 and a third transistor M3, and the second electrode (or cathode electrode) of the LD can be electrically connected to the second electric power line PL2. The LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the first electric power line PL1 to the second electric power line PL2 via the pixel circuit.

[0066] The light-emitting element (LD) can be selected as an organic light-emitting diode (OLED). Alternatively, the LD can be selected as an inorganic light-emitting diode such as a micro LED (light-emitting diode) or a quantum dot light-emitting diode. Furthermore, the LD can be a device configured with a combination of organic and inorganic materials. Figure 2 The image shows a pixel PXij comprising a single light-emitting element LD. However, in another embodiment, the pixel PXij may comprise multiple light-emitting elements LD, and the multiple light-emitting elements LD may be connected in series, in parallel, or in a series / parallel connection.

[0067] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst. In an embodiment, the first transistor M1 to the third transistor M3 may be formed using P-type transistors.

[0068] The first electrode of the first transistor M1 (or driving transistor) can be electrically connected to the second node N2, and the second electrode of the first transistor M1 can be connected to the first electrode (i.e., the anode electrode) of the light-emitting element LD. Furthermore, the gate electrode of the first transistor M1 can be connected to the first node N1. The term "connection" includes the meaning of "electrical connection." The first transistor M1 can control the amount of current flowing from the first driving power supply VDD through the light-emitting element LD to the second driving power supply VSS, corresponding to the voltage at the first node N1.

[0069] The second transistor M2 can be connected between the data line DLj and the first node N1. Furthermore, the gate electrode of the second transistor M2 can be connected to the scan line SLi (or the first scan line). The second transistor M2 can be turned on when an enable scan signal is provided to the scan line SLi to electrically connect the data line DLj and the first node N1 to each other.

[0070] The third transistor M3 can be connected between the first power line PL1 and the second node N2. Furthermore, the gate electrode of the third transistor M3 can be connected to the second node N2. The third transistor M3 can be connected in diode form (or diode connection) so that current can be supplied from the first power line PL1 to the second node N2. In this example, the third transistor M3 can supply a predetermined current from the first drive power supply VDD to the second node N2 while remaining in the ON state.

[0071] A storage capacitor Cst can be connected between the first power line PL1 and the first node N1. The storage capacitor Cst can store the voltage of the first node N1.

[0072] According to embodiments of this disclosure, pixel PXij can use source degradation to compensate for the threshold voltage of the first transistor M1. Source degradation can mean that a resistor or diode is connected to the source electrode of the transistor and the effect of intrinsic transconductance gm on equivalent transconductance GM is minimized through negative feedback.

[0073] When the light-emitting element LD is a miniature LED, pixel PXij can achieve white brightness at a current level of a few nA. When the diode-connected third transistor M3 is connected to the first electrode (i.e., the source electrode) of the first transistor M1 (or when a third transistor M3 with high resistance is connected), the current variation caused by the threshold voltage deviation of the first transistor M1 can be minimized by source degradation.

[0074] The equivalent transconductance GM of pixel PXij can be expressed as shown in Equation 1.

[0075] Equation 1

[0076]

[0077] In Equation 1, Rd can represent the resistance component of the third transistor M3. When Rd has a higher value than gm, GM ≒ 1 / Rd. Additionally, gm of the first transistor M1 can be expressed as shown in Equation 2.

[0078] Equation 2

[0079]

[0080] In Equation 2, μ can represent electron mobility, Cox can represent oxide capacitance, W can represent channel width, L can represent channel length, Vgs can represent the voltage difference between the gate and source electrodes of the first transistor M1, and Vth can represent the threshold voltage of the first transistor M1. Referring to Equations 1 and 2, when the resistive component Rd of the third transistor M3 is high, the current change caused by the threshold voltage difference of the first transistor M1 becomes insensitive.

[0081] In other words, in pixel PXij according to an embodiment of the present disclosure, a diode-connected third transistor M3 is connected to the first electrode of a first transistor M1, thereby minimizing the current variation caused by the threshold voltage difference of the first transistor M1.

[0082] Furthermore, the pixel PXij according to embodiments of the present disclosure includes three transistors M1, M2, and M3 and a capacitor Cst. Additionally, the pixel PXij according to embodiments of the present disclosure is connected to two power lines PL1 and PL2. Each of the pixels known in the art for compensating the threshold voltage of the first transistor M1 can be connected to four or more power lines and six or more transistors. That is, in the pixel PXij according to embodiments of the present disclosure, the area occupied by the power lines and the area occupied by the transistors can be minimized. Therefore, the pixel PXij can be applied to high-resolution panels.

[0083] Meanwhile, it can be predicted that the first transistor M1 will be formed using an N-type transistor. When the first transistor M1 is formed using an N-type transistor, the source electrode voltage of the first transistor M1 may be altered by the degradation of the light-emitting element LD connected to the source electrode of the first transistor M1, and therefore, it will be difficult to display an image with the desired brightness.

[0084] Figure 3 It shows the driver Figure 2 The waveform diagram of the pixel method shown. Figures 4A to 4C This is a diagram illustrating the principle of compensating for the threshold voltage of the first transistor. Figures 4A to 4C In the diagram, Ids2, indicated on the Y-axis, represents the current of the third transistor M3, and Vg2, indicated on the X-axis, represents the gate electrode voltage of the third transistor M3.

[0085] refer to Figure 3 An enable (or low-voltage) scan signal GW can be provided to the scan line SL1, causing the second transistor M2 to turn on. When the second transistor M2 is on, the data signal from the data line DLj can be provided to the first node N1. The storage capacitor Cst can store the voltage Vdata of the data signal provided to the first node N1.

[0086] Subsequently, a disable (or high-voltage) scan signal GW can be provided to scan line SL1, causing the second transistor M2 to turn off. Furthermore, the first transistor M1 can control the amount of current supplied from the first power line PL1 to the second power line PL2 via the light-emitting element LD, corresponding to the voltage of the first node N1 (i.e., the voltage Vdata of the data signal). The light-emitting element LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the first transistor M1.

[0087] When the threshold voltage of the first transistor M1 is relatively high, the first transistor M1 can provide a relatively low current to the light-emitting element LD. For example... Figure 4A As shown, the operating point of the third transistor M3 can be changed from the first point OP1 to the second point OP2.

[0088] As the voltage at the second node N2 increases, the voltage difference between the second node N2 and the first node N1 can increase (i.e., the voltage difference between the source and gate electrodes of the first transistor M1 can increase). When the voltage difference between the second node N2 and the first node N1 increases, the operating point of the third transistor M3 can change from the second point OP2 to the third point OP3, as shown below. Figure 4B As shown in the diagram. Then, the current to the third transistor M3 can be increased. However, the increased current can be set to be lower than that obtained through... Figure 4A The amount of current reduced due to the change in the operating point (from OP1 to OP2) is shown.

[0089] When the operating point of the third transistor M3 changes to point OP3, the voltage difference between the second node N2 and the first node N1 decreases as the voltage of the second node N2 decreases. When the voltage difference between the second node N2 and the first node N1 decreases, the operating point of the third transistor M3 can change from point OP3 to point OP4, as follows. Figure 4C As shown in the diagram. Then, the current to the third transistor M3 can be reduced. However, the reduced current can be set to be lower than that obtained through... Figure 4B The increase in current is shown by the change in the operating point (from OP2 to OP3).

[0090] When this process is repeated, the voltage of the second node N2 can be set to a predetermined voltage through negative feedback. The voltage of the second node N2 can be determined by reflecting the threshold voltage of the first transistor M1, and therefore, the threshold voltage of the first transistor M1 can be compensated.

[0091] Figure 5 It shows the basis Figure 2 The graph shows the voltage range of the pixel data signal. Figure 5 In the diagram, Ids1, indicated on the Y-axis, represents the current of the first transistor M1, and Vdata, indicated on the X-axis, represents the voltage of the data signal. Furthermore, Figure 5 The Iwhite value shown represents the current value used to display white, and Imax represents the maximum current that can flow through the first transistor M1. Additionally, Figure 5 The comparative example shown indicates that from Figure 2 The pixel PXij shown is the pixel of the third transistor M3 removed, and this disclosure indicates that... Figure 2 The pixel PXij shown.

[0092] refer to Figure 5In the comparative example, the voltage range (data swing range) of the data signal can be set to a first voltage range VR1. In contrast, the voltage range of the data signal in the pixel PXij of this disclosure can be set to a second voltage range VR2 that is wider than the first voltage range VR1 (or has a voltage range wider than the first voltage range VR1).

[0093] In the case of pixel PXij of this disclosure, the second voltage range VR2 can be further widened by source degradation to emit the same brightness as the comparative example. When the voltage range of the data signal is widened, the desired brightness can be stably achieved.

[0094] Figure 6 This is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 6 In the middle, omission and Figure 1 A detailed description of the overlapping components shown.

[0095] refer to Figure 6 The display device according to embodiments of the present disclosure may further include a transmission driver 15. The transmission driver 15 may be included in the display unit 110. In the example, the scan driver 13 and the transmission driver 15 may be formed together with the pixels in the pixel unit 14. Alternatively, the transmission driver 15 may not be included in the display unit 110.

[0096] The emitter driver 15 can receive emit drive signals (e.g., clock signals, emit start signals, etc.) from the timing controller 11. The emitter driver 15 can generate emit disable control signals to be provided to the emit control lines EL1, EL2, ..., ELn in response to the emit drive signals. The emit disable control signals can be set to a gate cutoff voltage. In the example, when the emit control signal is provided to a P-type transistor, the emit disable control signal can be set to a high voltage. In the example, when the emit control signal is provided to an N-type transistor, the emit disable control signal can be set to a low voltage.

[0097] Transmit driver 15 can sequentially provide transmit disable control signals to transmit control lines EL1 through ELn. Transmit driver 15 may include a transmit stage configured as a shift register. Transmit driver 15 can generate transmit disable control signals by sequentially transmitting transmit start signals in the form of cutoff level pulses to the next scan stage under the control of a clock signal.

[0098] Pixel unit 14 can also be connected to a third power line PL3. The third power line PL3 can provide an initialization power supply Vint. The voltage of the initialization power supply Vint can be set such that the light-emitting element LD is turned off when the voltage of the initialization power supply Vint is supplied to the first electrode (i.e., the anode electrode) of the light-emitting element LD. The third power line PL3 can be commonly connected to the pixel, but embodiments of this disclosure are not limited thereto. In another embodiment, the third power line PL3 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels.

[0099] Figure 7 This is a diagram illustrating pixels according to an embodiment of the present disclosure. Figure 7 In, with Figure 2 Components that are the same or similar to those shown are indicated by the same reference numerals.

[0100] refer to Figure 7 According to embodiments of this disclosure, pixel PXija can be connected to corresponding signal lines SLi and DLj. For example, pixel PXija can be connected to the i-th scan line SLi and the j-th data line DLj. The i-th scan line SLi may include the i-th first scan line SL1i and the i-th second scan line SL2i. In embodiments, pixel PXija can also be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0101] The pixel PXija according to embodiments of the present disclosure may include a light-emitting element LD and a pixel circuit for controlling the amount of current supplied to the light-emitting element LD.

[0102] The light-emitting element (LD) can be connected between a first electric field line PL1 and a second electric field line PL2. In the example, the first electrode (or anode electrode) of the LD can be electrically connected to the first electric field line PL1 via a first transistor M1, a third transistor M3, and a fourth transistor M4, and the second electrode (or cathode electrode) of the LD can be electrically connected to the second electric field line PL2. The LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the first electric field line PL1 to the second electric field line PL2 via the pixel circuit.

[0103] The light-emitting element (LD) can be selected as an organic light-emitting diode (OLED). Alternatively, the LD can be selected as an inorganic light-emitting diode such as a micro LED (light-emitting diode) or a quantum dot light-emitting diode. Furthermore, the LD can be a device configured with a combination of organic and inorganic materials. Figure 7The image shows a pixel PXija comprising a single light-emitting element (LD). However, in another embodiment, the pixel PXija may comprise multiple light-emitting elements (LDs), and the multiple light-emitting elements (LDs) may be connected in series, in parallel, or in a series / parallel connection.

[0104] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a storage capacitor Cst. In an embodiment, the first transistor M1 to the fifth transistor M5 may be formed using P-type transistors.

[0105] The first electrode of the first transistor M1 (or driving transistor) can be electrically connected to the second node N2, and the second electrode of the first transistor M1 can be connected to the first electrode (i.e., the anode electrode) of the light-emitting element LD. Furthermore, the gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current flowing from the first driving power supply VDD through the light-emitting element LD to the second driving power supply VSS, corresponding to the voltage at the first node N1.

[0106] The second transistor M2 can be connected between the data line DLj and the first node N1. Furthermore, the gate electrode of the second transistor M2 can be connected to the first scan line SL1i. The second transistor M2 can be turned on when the first scan signal GW is provided to the first scan line SL1i, thereby electrically connecting the data line DLj and the first node N1 to each other.

[0107] The third transistor M3 can be connected between the second electrode of the fourth transistor M4 and the second node N2. Furthermore, the gate electrode of the third transistor M3 can be connected to the second node N2. The third transistor M3 can be connected in diode form (or diode connection) so that current can be supplied from the first power line PL1 to the second node N2. In this example, the third transistor M3 can supply a predetermined current from the first drive power supply VDD to the second node N2 while remaining in the ON state.

[0108] The first electrode of the fourth transistor M4 can be connected to the first power line PL1, and the second electrode of the fourth transistor M4 can be connected to the first electrode of the third transistor M3. Furthermore, the gate electrode of the fourth transistor M4 can be connected to the transmit control line ELi. The fourth transistor M4 can be turned off when the transmit control signal EM is disabled and provided to the transmit control line ELi, and turned on when the transmit control signal EM is enabled and provided to the transmit control line ELi.

[0109] The fifth transistor M5 can be connected between the first electrode (i.e., the anode electrode) of the light-emitting element LD and the third power line PL3. Furthermore, the gate electrode of the fifth transistor M5 can be connected to the second scan line SL2i. The fifth transistor M5 can be turned on when the second scan signal GB is provided to the second scan line SL2i, so as to provide the voltage of the initialization power supply Vint from the third power line PL3 to the first electrode (i.e., the anode electrode) of the light-emitting element LD.

[0110] A storage capacitor Cst can be connected between the first power line PL1 and the first node N1. The storage capacitor Cst can store the voltage of the first node N1.

[0111] According to embodiments of the present disclosure, pixel PXija can use source degradation to compensate for the threshold voltage of the first transistor M1. That is, according to embodiments of the present disclosure, pixel PXija can use a diode-connected third transistor M3 to compensate for the threshold voltage of the first transistor M1.

[0112] The pixel PXija according to an embodiment of the present disclosure includes five transistors M1, M2, M3, M4, and M5 and a capacitor Cst. Furthermore, the pixel PXija according to an embodiment of the present disclosure is connected to three power lines PL1, PL2, and PL3. In the pixel PXija according to an embodiment of the present disclosure, the area occupied by the power lines and the area occupied by the transistors can be minimized. Therefore, the pixel PXija can be applied to high-resolution panels.

[0113] Figure 8 It shows the driver Figure 7 The waveform diagram of the pixel method shown.

[0114] refer to Figure 8 The pixel PXija according to the embodiments of this disclosure can be driven sequentially in the initialization period P_I, the write period P_W, the stabilization period P_S, and the emission period P_E.

[0115] During the initialization period P_I, an enable signal GW can be provided to the first scan line SL1i, and an enable signal GB can be provided to the second scan line SL2i. Additionally, during the initialization period P_I, a reference power supply Vref can be provided to the data line DLj.

[0116] When the first scan signal GW is enabled and provided to the first scan line SL1i, the second transistor M2 can be turned on. When the second transistor M2 is turned on, the voltage of the reference power supply Vref from the data line DLj can be provided to the first node N1. The reference power supply Vref can be set to a constant voltage. When the voltage of the reference power supply Vref is provided to the first node N1, the storage capacitor Cst can be initialized to the voltage of the reference power supply Vref.

[0117] When the second scan signal GB is enabled and supplied to the second scan line SL2i, the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the voltage of the initialization power supply Vint can be supplied to the first electrode (i.e., the anode electrode) of the light-emitting element LD. The parasitic capacitor (not shown) included in the light-emitting element LD discharges, thereby improving the black level performance.

[0118] During the write cycle P_W, an enable first scan signal GW can be provided to the first scan line SL1i, and an enable second scan signal GB can be provided to the second scan line SL2i. Furthermore, during the write cycle P_W, a data signal can be provided to the data line DLj, and a disable transmit control signal EM can be provided to the transmit control line ELi.

[0119] When the disable emission control signal EM is provided to the emission control line ELi, the fourth transistor M4 can be turned off. When the fourth transistor M4 is turned off, the electrical connection between the first power line PL1 and the first transistor M1 can be blocked, and therefore, the pixel PXija can be set to a non-emission state.

[0120] When the first scan signal GW is enabled and provided to the first scan line SL1i, the second transistor M2 can be turned on. When the second transistor M2 is turned on, the voltage Vdata of the data signal from the data line DLj can be provided to the first node N1. The voltage Vdata of the data signal can be stored in the storage capacitor Cst.

[0121] When the second scan signal GB is provided to the second scan line SL2i, the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the voltage of the initialization power supply Vint can be provided to the first electrode (i.e., the anode electrode) of the light-emitting element LD.

[0122] During the stable period P_S, a first scan disable signal GW can be provided to the first scan line SL1i. When the first scan disable signal GW is provided to the first scan line SL1i, the second transistor M2 can be turned off.

[0123] Furthermore, during the stabilization period P_S, an enable signal GB for the second scan line SL2i can be provided, and thus, the fifth transistor M5 can remain on. Additionally, during the stabilization period P_S, an enable transmit control signal EM (or a low-voltage transmit control signal EM) can be provided to the transmit control line ELi. When the enable transmit control signal EM is provided to the transmit control line ELi, the fourth transistor M4 can be turned on. When the fourth transistor M4 is on, the first power line PL1 and the first transistor M1 can be electrically connected to each other.

[0124] The first transistor M1 can supply a current corresponding to the voltage of the first node N1 to the first electrode (i.e., the anode electrode) of the light-emitting element LD. The current supplied from the first transistor M1 can be supplied to the third electric field line PL3 via the fifth transistor M5. That is, during the stabilization period P_S, the current from the first transistor M1 does not pass through the light-emitting element LD, but can be supplied to the third electric field line PL3. According to the stabilization period P_S, the black performance can be improved, and the light-emitting element LD can be prevented from emitting light with undesirable brightness in the initial emission.

[0125] During the emission period P_E, a second scan disable signal GB can be provided to the second scan line SL2i, causing the fifth transistor M5 to turn off. When the fifth transistor M5 is off, the current supplied from the first transistor M1 can be provided to the light-emitting element LD, and therefore, the light-emitting element LD can generate light with a predetermined brightness.

[0126] Furthermore, during the emission period P_E, the current flowing through the first transistor M1 can be expressed as shown in Equation 3.

[0127] Equation 3

[0128]

[0129] In Equation 3, Id can represent the current flowing through the first transistor M1, Vdsat3 can represent the saturation voltage, Vth3 can represent the threshold voltage of the third transistor M3, gm1 can represent the gm of the first transistor M1, Rd can represent the resistance component of the third transistor M3, and Vth1 can represent the threshold voltage of the first transistor M1.

[0130] Referring to Equation 3, it can be seen that when the resistance component Rd of the third transistor M3 increases, the coefficient of Vdata decreases, and therefore the voltage range of the data signal increases.

[0131] Figure 9 This illustrates a driver according to another embodiment. Figure 7 The waveform diagram of the pixel method shown. Figure 9 In the middle, omission and Figure 8 The description of the partially overlapping parts described in the text.

[0132] refer to Figure 9 The pixel PXija according to the embodiments of this disclosure can be driven sequentially in the initialization period P_Ia, the write period P_W, the stabilization period P_S, and the emission period P_E.

[0133] During the initialization period P_Ia, an enable signal GW can be provided to the first scan line SL1i, and an enable signal GB can be provided to the second scan line SL2i. Furthermore, during the initialization period P_Ia, a data signal voltage Vdata can be provided to the data line DLj.

[0134] When the first scan signal GW is enabled and provided to the first scan line SL1i, the second transistor M2 can be turned on. When the second transistor M2 is turned on, the voltage Vdata of the data signal from the data line DLj can be provided to the first node N1. When the voltage Vdata of the data signal is provided to the first node N1, the voltage Vdata of the data signal can be stored in the storage capacitor Cst.

[0135] When the second scan signal GB is enabled and supplied to the second scan line SL2i, the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the voltage of the initialization power supply Vint can be supplied to the first electrode (i.e., the anode electrode) of the light-emitting element LD. The parasitic capacitor (not shown) included in the light-emitting element LD discharges, thereby improving the black level performance.

[0136] Already referenced Figure 8 The write cycle P_W, the stabilization cycle P_S, and the emit cycle P_E are described, and therefore, overlapping descriptions will be omitted.

[0137] Figure 10 This is a diagram illustrating pixels according to an embodiment of the present disclosure. Figure 10 In, with Figure 7 Components that are identical or similar to those shown are indicated by the same reference numerals, and overlapping descriptions will be omitted.

[0138] refer to Figure 2 and Figure 7 Storage capacitors Cst can be formed as metal oxide metal (MOM) capacitors or metal insulator metal (MIM) capacitors.

[0139] refer to Figure 10 Storage capacitors Csta can be formed as metal-oxide-semiconductor (MOS) capacitors.

[0140] In other words, in the embodiments of this disclosure, the storage capacitor Cst or Csta can be formed as any one of a MOM capacitor, a MIM capacitor, and a MOS capacitor.

[0141] In addition, Figure 7 and Figure 10 In the pixel PXija shown, the size of the first transistor M1 can be increased to improve short-range uniformity (“SRU”). For this purpose, the first transistor M1, the second transistor M2, and the fifth transistor M5 can be formed using high-voltage MOSFETs (e.g., 6V, 8V, or 10V), and the third transistor M3 and the fourth transistor M4 can be formed using medium-voltage MOSFETs (e.g., 3.3V or 5V).

[0142] When the third transistor M3 and the fourth transistor M4 are formed using a medium-voltage MOSFET, the mounting side of the third transistor M3 and the fourth transistor M4 can be reduced, and therefore, the pixel PXija can be applied to a high-resolution panel.

[0143] In an implementation, when the fourth transistor M4 is set as a medium-voltage MOSFET, the high voltage of the transmit control signal EM (e.g., the voltage that disables the transmit control signal) can be set to a different high voltage than either the scan signals GW and GB (e.g., the voltage that disables the scan signal). In an example, the high voltage of the transmit control signal EM can be set to a voltage lower than the high voltage of either the scan signals GW and GB.

[0144] In one implementation, when the third transistor M3 is formed as a medium-voltage MOSFET, its threshold voltage can be set lower compared to when it is formed as a high-voltage MOSFET. This ensures an additional drive voltage margin. However, the embodiments of this disclosure are not limited thereto. In another example, the first transistors M1 through M5 can be formed using high-voltage MOSFETs.

[0145] Figures 11 to 14 This is an example diagram illustrating an electronic device according to various embodiments of the present disclosure.

[0146] refer to Figure 11 A display device employing pixels according to the above embodiments can be applied to smart glasses. Smart glasses include a frame 111 and a lens portion 112. Smart glasses are wearable electronic devices that can be worn on a user's face and may have a structure in which a portion of the frame 111 is folded or unfolded. For example, smart glasses may be a wearable device for augmented reality (AR).

[0147] The frame 111 may include a housing 111b that supports the lens portion 112 and a leg portion 111a that allows the user to wear smart glasses. The leg portion 111a may be hinged to the housing 111b for folding or unfolding.

[0148] The battery, touchpad, microphone, and / or camera can be built into the frame 111. Additionally, a projector for outputting light and / or a processor for controlling the light signal can be built into the frame 111.

[0149] The lens portion 112 may be an optical component that allows light to pass through or to be reflected. The lens portion 112 may include glass and / or transparent synthetic resin.

[0150] A display device employing pixels according to the above embodiment can be applied to the lens portion 112. In this example, a user can recognize an image displayed by a light signal transmitted from a projector in the frame 111 through the lens portion 112. For example, a user can recognize information displayed on the lens portion 112, including time, data, etc.

[0151] refer to Figure 12 The display device employing the pixels according to the above embodiments can be applied to a head-mounted display (HMD). An HMD may include a headband 121 and a display housing 122. For example, an HMD is a wearable electronic device that can be worn on a user's head.

[0152] The headband 121 can be connected to the display housing 122 to secure the display housing 122. The headband 121 may include a horizontal strap and a vertical strap to secure the HMD to the user's head. The horizontal strap may be positioned around the side of the user's head, and the vertical strap may be positioned around the top of the user's head. However, this disclosure is not necessarily limited thereto, and the headband 121 may be implemented in the shape of an eyeglass frame or a helmet.

[0153] The display housing 122 houses the display device and may include at least one lens. The at least one lens can provide an image to the user. For example, a display device employing pixels according to the above embodiment can be used to implement left-eye and right-eye lenses within the display housing 122.

[0154] refer to Figure 13 The display device employing the pixels according to the above embodiment can be applied to a smartwatch. A smartwatch may include a display portion 131 and a strap portion 133. A smartwatch is a wearable electronic device that can be worn on a user's wrist. The display device employing the pixels according to the above embodiment can be applied to the display portion 131. For example, the display portion 131 can provide image data including information such as time and data.

[0155] refer to Figure 14 The display device employing the pixels according to the above embodiments can be applied to automotive displays. In the example, an automotive display can refer to an electronic device installed inside / outside a vehicle to provide image data.

[0156] For example, a display device using pixels according to the above embodiments can be applied to at least one of an infotainment panel 141, an instrument panel 142, a passenger display 143, a head-up display 144, a side mirror display 145, and a rear seat display 146 installed in a vehicle.

[0157] Figure 15 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0158] refer to Figure 15 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices or other systems.

[0159] For example, electronic device 1000 may be a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, head-mounted display device, etc.

[0160] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, etc. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0161] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory of the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0162] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0163] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, and mouse, as well as output devices such as speakers and printers. In some embodiments, display device 1060 may be integrated with I / O device 1040.

[0164] The power supply 1050 can provide the power required to operate the electronic device 1000. For example, the power supply 1050 may include a power management integrated circuit (PMIC). In one embodiment, the power supply 1050 may provide power to the display device 1060.

[0165] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0166] In the pixels and display devices including the pixels according to this disclosure, a transistor with a diode connected to the source electrode of the driving transistor can be used to compensate for the threshold voltage. Therefore, the circuit structure of the pixel can be simplified, and thus, the pixel can be applied to a high-resolution panel.

[0167] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A pixel, characterized in that, include: Light-emitting elements; The first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to the anode electrode of the light-emitting element; A second transistor is connected between the data line and the first node, and the second transistor includes a gate electrode connected to the first scan line; as well as A third transistor is connected between the first power line and the second node, the third transistor including a gate electrode connected to the second node.

2. The pixel according to claim 1, characterized in that, It also includes a storage capacitor connected between the first power line and the first node.

3. The pixel according to claim 2, characterized in that, The storage capacitor is a metal oxide capacitor, a metal insulator capacitor, or a metal oxide semiconductor capacitor.

4. The pixel according to claim 1, characterized in that, The cathode electrode of the light-emitting element is connected to a second power line, and a second power supply with a voltage lower than that of the first power supply is provided to the second power line.

5. The pixel according to claim 1, characterized in that, Also includes: A fourth transistor is connected between the first power line and the third transistor, the fourth transistor including a gate electrode connected to the emitter control line; as well as A fifth transistor is connected between the anode electrode of the light-emitting element and the third power line, and initialization power is provided to the third power line. The fifth transistor includes a gate electrode connected to the second scan line.

6. The pixel according to claim 5, characterized in that, Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor is a P-type transistor.

7. The pixel according to claim 5, characterized in that, The high voltage supplied to the transmit control line is different from the high voltage supplied to either the first scan line or the second scan line.

8. The pixel according to claim 7, characterized in that, The high voltage supplied to the transmit control line is set to a lower voltage than the high voltage supplied to either the first scan line or the second scan line.

9. The pixel according to claim 5, characterized in that, Each of the first transistor, the second transistor, and the fifth transistor is a high-voltage MOSFET, and each of the third transistor and the fourth transistor is a medium-voltage MOSFET.

10. A display device, characterized in that, include: Pixels are connected to scan lines and data lines; A scan driver configured to drive the scan lines; as well as The data driver is configured to drive the data line. Wherein, at least one pixel in the pixels includes: Light-emitting elements; The first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to the anode electrode of the light-emitting element; A second transistor is connected between the first node and a corresponding data line of the data line, the second transistor including a gate electrode connected to a first scan line in the scan line; and A third transistor is connected between the first power line and the second node, the third transistor including a gate electrode connected to the second node.

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