Electronic package and substrate structure thereof
By designing conductive blind vias in the substrate structure that do not overlap with the opening edge of the insulating protective layer, the problem of solder resist layer cracking caused by stress concentration in the prior art is solved, thereby improving the reliability of the package and reducing production costs.
Patent Information
- Application Number
- CN202520174484.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2025-01-16
- Filing Date
- 2025-01-26
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-01-26
AI Technical Summary
During probe testing of existing semiconductor packages, stress concentration occurs because the conductive blind vias in the substrate structure overlap with the opening edge of the solder resist layer, which can easily cause the solder resist layer to crack and affect the reliability of the package.
Design a substrate structure in which the position of the conductive blind via does not overlap with the opening edge of the insulating protective layer. By combining the insulating layer, wiring layer and conductive blind via, stress concentration is avoided. The multi-layer insulating layer and conductive blind via design are used to improve reliability.
It effectively avoids the breakage of the insulating protective layer during probe testing, improves the reliability of electronic packages, and does not require changes to existing packaging processes or the purchase of special equipment, thus reducing production costs.
Smart Images
Figure CN223912868U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor packaging technology, in particular to an electronic package and a substrate structure thereof capable of improving reliability. BACKGROUND
[0002] Currently, the electrical test equipment used in the packaging and testing stage of the packaging and testing factory adopts a standardized detection machine to detect semiconductor packages and their terminal products.
[0003] As shown in Figure 1A , in the existing detection operation, a semiconductor package 1 of a ball grid array (BGA) specification is arranged on a probe card 9 to contact the solder balls 19 on the lower side of the semiconductor package 1 by the probes 90 of the probe card, and the probe card 9 transmits test signals to a test machine (not shown) through external circuits, so that when testing, the upper side of the semiconductor package 1 needs to be pressed down so that each probe 90 can correspondingly contact the solder ball 19.
[0004] However, in the existing semiconductor package 1, if the conductive blind hole 102 of the substrate structure 10 and the solder resist layer 17 overlap each other with the edge of the opening 170 of the exposed electrical contact pad 103, as shown in Figure 1B , when the semiconductor package 1 is subjected to probe testing (probe ball insertion), the solder resist layer 17 is prone to stress concentration, thereby causing the solder resist layer 17 to crack, especially when the conductive blind hole 102 of the substrate structure 10 is designed as a staggered hole, the stress concentration is more likely to occur.
[0005] Therefore, how to overcome the shortcomings of the prior art has become an urgent problem to be solved at present. INVENTION CONTENTS
[0006] In view of the various shortcomings of the prior art, the present application provides a substrate structure, comprising: an insulating layer; a wiring layer formed on the insulating layer and having an electrical contact pad; a conductive blind hole formed in the insulating layer; and an insulating protective layer formed on the insulating layer and having an opening, so that the electrical contact pad is exposed to the opening, wherein the position of the conductive blind hole does not overlap the edge of the opening.
[0007] In the foregoing substrate structure, the conductive blind hole is completely located within the edge of the opening.
[0008] In the foregoing substrate structure, the conductive blind hole is completely located outside the edge of the opening. For example, the conductive blind hole corresponds to the edge of the electrical contact pad, the conductive blind hole is completely located outside the edge of the electrical contact pad, or the conductive blind hole corresponds to the edge of the opening.
[0009] In the aforementioned substrate structure, the insulating layer is multi-layered, and the plurality of conductive blind vias are formed in the insulating layer by using a via-in-via design.
[0010] The present application also provides an electronic package, comprising: a substrate structure as aforementioned; and an electronic component disposed on the substrate structure to electrically connect the wiring layer.
[0011] The aforementioned electronic package further comprises a conductive element coupled to the electrical contact pad.
[0012] The aforementioned electronic package further comprises a covering layer coupled to the substrate structure to cover the electronic component. For example, a conductive pillar is formed on the substrate structure to electrically connect the wiring layer, so that the covering layer covers the conductive pillar. Further, a circuit structure is formed on the covering layer to electrically connect the conductive pillar.
[0013] As can be seen from the above, the electronic package and the substrate structure thereof of the present application mainly avoid the stress concentration of the insulating protective layer during the probe test by the position of the conductive blind via not overlapping the edge of the opening of the insulating protective layer. Therefore, compared with the prior art, the insulating protective layer of the present application will not be broken during the test, thereby effectively improving the reliability of the electronic package. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1A is a sectional view of a conventional semiconductor package during testing.
[0015] Figure 1B is a partial top view of Figure 1A .
[0016] Figure 2A is a sectional view of the electronic package and the substrate structure thereof of the present application during testing.
[0017] Figure 2B is a partial top view of Figure 2A .
[0018] Figure 3 is a partial sectional view of another embodiment of the electronic package and the substrate structure thereof of the present application.
[0019] Figure 4A , Figure 4B and Figure 4C are partial top views of other embodiments of the electronic package and the substrate structure thereof of the present application.
[0020] REFERENCE SIGNS
[0021] 1 semiconductor package
[0022] 10, 20, 30 substrate structure
[0023] 102, 202, 302, 402 conductive blind via
[0024] 103, 203 electrical contact pad
[0025] 17 solder resist
[0026] 170, 270 opening
[0027] 19 solder ball
[0028] 2 electronic package
[0029] 20a first side
[0030] 20b second side
[0031] 200 insulating layer
[0032] 201 wiring layer
[0033] 204 contact
[0034] 21 electronic element
[0035] 210 conductive bump
[0036] 23 conductive pillar
[0037] 24 line structure
[0038] 240 dielectric layer
[0039] 241 line layer
[0040] 25 covering layer
[0041] 27 insulating protective layer
[0042] 29 conductive element
[0043] 9 probe card
[0044] 90 probe DETAILED DESCRIPTION
[0045] The present application is herein described, by way of example only, with the
[0046] It is to be understood that the structures, proportions, sizes, etc. shown in the drawings accompanying the present specification are to be taken as illustrative only and are not to be construed as limiting the scope of the present application, and that any structural, proportional or size modifications, changes or adjustments, which do not affect the effects and purposes that the present application can produce, shall still fall within the scope of the technical content disclosed by the present application. Meanwhile, the terms such as "upper", "first", "second", and "one" etc. cited in the present specification are only for the convenience of clear description, and are not intended to limit the scope of the present application, and any changes in relative relationship or adjustment without substantial changes in technical content shall also be considered as the scope of the present application.
[0047] Figure 2A A cross-sectional view of an electronic package 2 of the present application is shown. As shown in Figure 2A , the electronic package 2 includes a substrate structure 20, at least one electronic component 21, a plurality of conductive pillars 23, a covering layer 25, a circuit structure 24, and a plurality of conductive elements 29.
[0048] The substrate structure 20 is, for example, a package substrate with a core layer or a coreless package substrate, which adopts a redistribution layer (RDL) specification, and the substrate structure 20 includes an insulating layer 200, a wiring layer 201 disposed on the insulating layer 200, and a plurality of conductive blind vias 202 disposed in the insulating layer 200 and electrically connected to the wiring layer 201.
[0049] In the present embodiment, the substrate structure 20 is defined with a first side 20a and a second side 20b opposite to each other, and the wiring layer 201 of the first side 20a and the second side 20b has a plurality of contacts 204 and a plurality of electrical contact pads 203.
[0050] Further, an insulating protective layer 27 is formed on the insulating layer 200 of the second side 20b, so that the insulating protective layer 27 has a plurality of openings 270, and each of the plurality of electrical contact pads 203 is exposed to each of the plurality of openings 270. It should be understood that the outermost insulating layer 200 of the first side 20a can serve as a solder mask to expose the plurality of contacts 204.
[0051] Please refer to Figure 2B , in an embodiment, the conductive blind via 202 is completely located within the edge of the opening 270 without overlapping on the edge of the opening 270.
[0052] In addition, the material of the wiring layer 201 is copper, the material of the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), Prepreg (PP), and the material of the insulating protective layer 27 is a solder mask material such as green paint and ink.
[0053] The electronic element 21 is an active element, a passive element, or a combination thereof, disposed on the first side 20a of the substrate structure 20. The active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor.
[0054] In this embodiment, the electronic element 21 is disposed on the contact 204 in a flip-chip manner through a plurality of conductive bumps 210 such as solder material and is electrically connected to the wiring layer 201. Alternatively, the electronic element 21 can be electrically connected to the contact 204 in a wire-bonding manner through a plurality of wire bonds (not shown). Alternatively, the electronic element 21 can directly contact the contact 204. However, the manner in which the electronic element 21 is electrically connected to the substrate structure 20 is not limited to the above.
[0055] The conductive pillar 23 is disposed on the contact 204 of the first side 20a of the substrate structure 20 to electrically connect the wiring layer 201.
[0056] In this embodiment, the conductive pillar 23 is a metal pillar such as a copper pillar. It should be understood that a solder ball can also be used as the conductive pillar 23, but is not limited to the above.
[0057] The covering layer 25 is an insulating material formed on the first side 20a of the substrate structure 20 to cover the electronic element 21 and the plurality of conductive pillars 23.
[0058] In this embodiment, the covering layer 25 is an insulating material such as polyimide (PI), a dry film, an encapsulation adhesive such as epoxy, or a molding compound. For example, the process of forming the covering layer 25 can be selected from a liquid compound, injection, lamination, or compression molding.
[0059] The line structure 24 is disposed on the covering layer 25 and is electrically connected to the plurality of conductive pillars 23.
[0060] In the embodiment, the circuit structure 24 includes a plurality of dielectric layers 240 and a plurality of circuit layers 241, such as a redistribution layer (RDL) specification, disposed on the plurality of dielectric layers 240. The outermost dielectric layer 240 can serve as a solder mask layer, and the outermost circuit layer 241 is exposed to the solder mask layer for bonding to an electronic device (not shown). Alternatively, the circuit structure 24 can include only a single dielectric layer 240 and a single circuit layer 241.
[0061] Further, the circuit layer 241 is formed of copper, and the dielectric layer 240 is formed of a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or a solder mask material such as green paint or ink.
[0062] The conductive element 29 is a solder ball or a metal bump such as a copper bump disposed on the electrical contact pad 203 of the substrate structure 20 and electrically connected to the wiring layer 201.
[0063] During testing, the electronic package 2 is disposed on a probe card 9 with the conductive elements 29 so that the probes 90 of the probe card 9 contact the conductive elements 29, and the probe card 9 transmits test signals to a testing machine (not shown) through external circuits.
[0064] Therefore, the electronic package 2 of the present application is mainly disposed within the edge of the opening 270 without overlapping the edge of the opening 270 by the conductive blind via 202 of the substrate structure 20, so that each probe 90 can contact the conductive element 29 when the electronic package 2 is pressed during the probe testing (probe ball insertion) operation, and the stress concentration of the insulating protective layer 27 can be avoided. Thus, compared with the prior art, the insulating protective layer 27 will not crack during the testing operation, thereby effectively improving the reliability of the electronic package 2.
[0065] Referring to Figure 3 , in another embodiment, when the substrate structure 30 adopts a via design to form the conductive blind via 202, 302 of each layer, the stress concentration of the insulating protective layer 27 can also be effectively avoided.
[0066] Further, the electronic package 2 of the present application not only improves the reliability of the electronic package 2, but also does not need to change the appearance of the substrate structure, and can be manufactured by the existing semiconductor packaging process without the need to develop a special process or purchase special equipment, thereby reducing the production cost of the product.
[0067] In other embodiments, the conductive blind via 402 can also be located completely outside the edge of the opening 270 without overlapping on the edge of the opening 270, such as shown in FIG. 2B, which corresponds to cutting the edge of the electric contact pad 203, or such as shown in FIG. 2C, which is completely located outside the edge of the electric contact pad 203, or such as shown in FIG. 2D, which corresponds to cutting the edge of the opening 270. Figure 4A Figure 4B Figure 4C
[0068] Therefore, the position of the conductive blind via can be set according to requirements, as long as it does not overlap on the edge of the opening of the insulating protective layer 27, and is not limited to the above.
[0069] In summary, the electronic package and the substrate structure thereof of the present application avoid the stress concentration of the insulating protective layer during the probe test by locating the conductive blind via completely outside the edge of the opening of the insulating protective layer, so that the insulating protective layer of the present application does not break during the test, thereby effectively improving the reliability of the electronic package.
[0070] The above embodiments are used to illustrate the principles and effects of the present application, and are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the claims.
Claims
1. A substrate structure, characterized by, The substrate structure comprises: an insulating layer; a wiring layer disposed on the insulating layer and having an electrical contact pad; a conductive blind via disposed in the insulating layer; and an insulating protective layer disposed on the insulating layer and having an opening to expose the electrical contact pad at the opening, wherein the conductive blind via is not aligned with an edge of the opening. The conductive blind via is entirely within the edge of the opening.
2. The substrate structure of claim 1, wherein, The conductive blind via is entirely outside the edge of the opening.
3. The substrate structure of claim 1, wherein, The conductive blind via corresponds to the edge of the electrical contact pad.
4. The substrate structure of claim 3, wherein, The conductive blind via is entirely outside the edge of the electrical contact pad.
5. The substrate structure of claim 3, wherein, The conductive blind via corresponds to the edge of the opening.
6. The substrate structure of claim 3, wherein, The insulating layer is multi-layered to form a plurality of the conductive blind vias in the insulating layer by using a via-in-via design.
7. The substrate structure of claim 1, wherein, The substrate structure comprises:
8. An electronic package, characterized by any one of claims 1 to 7; and an electronic component disposed on the substrate structure to electrically connect the wiring layer. The electronic package further comprises a conductive element bonded to the electrical contact pad. The electronic package further comprises a covering layer formed on the substrate structure to cover the electronic component.
9. The electronic package of claim 8, wherein, The electronic package further comprises a conductive pillar formed on the substrate structure to electrically connect the wiring layer, and the covering layer covers the conductive pillar.
10. The electronic package of claim 8, wherein, The electronic package further comprises a circuit structure formed on the covering layer and electrically connected to the conductive pillar.
11. The electronic package of claim 10, wherein, 12. The electronic package of claim 11, wherein,