Low-noise amplification chip, low-noise amplifier and radio frequency front-end module

Abstract

The utility model provides a low-noise amplification chip, which comprises a chip, a first power supply port arranged on the chip, a control module, a low-noise amplification module and a first voltage stabilization unit, and is characterized in that the control module comprises an interface unit and a decoding unit; the first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive clock signals and data signals, and the signal output end of the interface unit is connected with the signal input end of the decoding unit. The decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to the plurality of control ends in the low-noise amplification module, and the first voltage stabilizing unit is connected to a connection path between the first power supply port and the power supply end of the decoding unit; therefore, jittering of the control signal finally output to the low-noise amplification module by the decoding unit is avoided, and the noise performance of the low-noise amplification chip is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to radio frequency technical field, concretely relates to a kind of low noise amplifier chip, low noise amplifier and radio frequency front-end module. BACKGROUND

[0002] With the rapid development of modern wireless communication technology, the performance requirements of radio frequency front-end circuit are also higher and higher. As a key component of the radio frequency receiver front-end, the performance of low noise amplifier directly affects the sensitivity and communication quality of the whole receiving system. However, there are some problems to be solved in the design and application of low noise amplifier. SUMMARY

[0003] The utility model aims at providing a kind of low noise amplifier chip, low noise amplifier and radio frequency front-end module, to improve the problem of poor noise performance of low noise amplifier chip.

[0004] A kind of low noise amplifier chip, including chip, first power supply port, control module, low noise amplifier module and first voltage stabilizing unit being arranged on the chip, the control module includes interface unit and decoding unit;The first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit respectively, the signal input end of the interface unit is configured to receive clock signal and data signal, the signal output end of the interface unit is connected with the signal input end of the decoding unit, the decoding unit includes multiple signal output ends, multiple signal output ends of the decoding unit are connected to multiple control ends in the low noise amplifier module, the first voltage stabilizing unit is connected on the connecting path between the first power supply port and the power supply end of the decoding unit.

[0005] A kind of low noise amplifier chip, including chip, first power supply port, control module, low noise amplifier module and second voltage stabilizing unit being arranged on the chip, the control module includes interface unit and decoding unit;The first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit respectively, the signal input end of the interface unit is configured to receive clock signal and data signal, the signal output end of the interface unit is connected with the signal input end of the decoding unit, the decoding unit includes multiple signal output ends, multiple signal output ends of the decoding unit are connected to multiple control ends in the low noise amplifier module, the second voltage stabilizing unit is connected on the connecting path between the first power supply port and the power supply end of the interface unit.

[0006] A low-noise amplifier includes a first power supply port, a control module, a low-noise amplification circuit, and a first voltage regulator unit. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals, and the signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to multiple switching units in the low-noise amplification circuit to control the switching units to be turned on or off. The first voltage regulator unit is connected in the connection path between the first power supply port and the power supply terminal of the decoding unit.

[0007] A radio frequency front-end module includes a first power supply port, a control module, a switching module, and a first voltage regulator unit. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals. The signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to control terminals corresponding to multiple different switching units in the switching module. The first voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the decoding unit.

[0008] In this embodiment, a low-noise amplifier chip includes a chip, a first power supply port, a control module, a low-noise amplifier module, and a first voltage regulator unit disposed on the chip. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals, and the signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to multiple control terminals in the low-noise amplifier module. The first voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the decoding unit. In this embodiment, by connecting the first voltage regulator unit on the connection path between the first power supply port and the power supply terminal of the decoding unit, the first voltage regulator unit can block voltage fluctuations output from the first power supply port and filter out voltage fluctuations output from the first power supply port to ground, preventing voltage fluctuations output from the first power supply port from being transmitted to the power supply terminal of the decoding unit. This avoids jitter in the control signal ultimately output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0010] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a low-noise amplifier chip according to the present invention;

[0012] Figure 2 This is another structural schematic diagram of a low-noise amplifier chip according to the present invention;

[0013] Figure 3 This is another structural schematic diagram of a low-noise amplifier chip according to the present invention;

[0014] Figure 4 This is another structural schematic diagram of a low-noise amplifier chip according to the present invention;

[0015] Figure 5 This is another structural schematic diagram of a low-noise amplifier chip according to the present invention;

[0016] Figure 6 This is a schematic diagram of a low-noise amplifier according to the present invention;

[0017] Figure 7 This is a structural schematic diagram of the radio frequency front-end module of this utility model. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0019] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0020] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0022] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0023] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0024] The low-noise amplifier chip provided in this application embodiment can be applied to terminal devices such as mobile phones, tablets, wearable devices, vehicle devices, and laptops. Specifically, it can also be applied to the radio frequency front-end module of these terminal devices. This embodiment does not impose any restrictions on the specific type of terminal device.

[0025] This embodiment provides a low-noise amplifier chip, as follows: Figure 1As shown, the device includes a chip, a first power supply port, a control module, a low-noise amplification module, and a first voltage regulator unit disposed on the chip. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The first power supply port is configured to be connected to a first power supply. The signal input terminal of the interface unit is configured to receive clock signals and data signals. The signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to multiple control terminals in the low-noise amplification module. The first voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the decoding unit.

[0026] In at least one embodiment, the low-noise amplifier chip can be manufactured using any process technology, such as SiGe HBT, GaAs pHEMT, or CMOS. The low-noise amplifier chip includes a chip 100, a first power supply port VIO, a control module 10, a low-noise amplifier module 20, and a voltage regulator unit disposed on the chip. The control module 10 can be used to control the operating state of the low-noise amplifier module to ensure its normal operation. For example, the control module 10 can control the on / off state of the switches in the low-noise amplifier module 20 to selectively activate amplification branches or bypass branches in specific frequency bands; it can also control the state of the bias circuit in the low-noise amplifier module 20 to dynamically adjust the gain of the low-noise amplifier module 20 to adapt to input signals of different intensities. This embodiment improves circuit integration by integrating the control module 10 and the low-noise amplifier module 20 onto a single chip.

[0027] In at least one embodiment, the control module includes an interface unit and a decoding unit. The interface unit is also referred to as a MIPI (Mobile Industry Processor Interface) unit. The interface unit transmits clock and data signals using two signal lines (SCLK and SDATA). To ensure the interface unit can properly drive the clock and data signals, and for the decoding unit to function correctly, both the interface unit and the decoding unit require power from a power supply (VIO). In this embodiment, the interface unit and the decoding unit share a first power supply. The power supply terminals of both the interface unit and the decoding unit are connected to a first power supply port on the chip. This first power supply port is configured to connect to the first power supply (VIO). The first power supply transmits a power supply voltage to the power supply terminals of the interface unit and the decoding unit through the first power supply port, providing power to both units and ensuring their normal operation. In this embodiment, the voltage transmitted from the first power supply (VIO) to the power supply terminals of the interface unit and the decoding unit can be 1.8V.

[0028] In at least one embodiment, the low-noise amplifier chip is an insulated silicon chip.

[0029] In at least one embodiment, the decoding unit includes multiple signal output terminals, which are connected to multiple control terminals in the low-noise amplification module. It should be noted that in this embodiment, the number of signal output terminals of the decoding unit and the number of control terminals in the low-noise amplification module may be the same or different. Each signal output terminal of the decoding unit can be connected to a corresponding control terminal in the low-noise amplification module in a one-to-one correspondence, i.e., many-to-many; each signal output terminal of the decoding unit can also be connected to multiple control terminals in the low-noise amplification module in a one-to-many correspondence; or the multiple signal output terminals of the decoding unit can be connected to a single control terminal in the low-noise amplification module in a many-to-one correspondence. The relationship between the multiple signal output terminals of the decoding unit and the multiple control terminals in the low-noise amplification module can be one-to-one, many-to-one, or one-to-many.

[0030] In at least one embodiment, the decoding unit is a common digital logic circuit whose function is to convert the input encoded signal into a corresponding output signal and transmit it to the low-noise amplifier module. The decoding unit works by mapping the input signal at the signal input terminal to a specific output signal using combinational logic circuits. Its core components include AND gates, OR gates, and inverters. The decoding unit includes multiple signal output terminals, each outputting a corresponding control signal. These multiple output terminals can output multiple control signals, which are independent of each other. These different control signals are used to control multiple different control terminals in the low-noise amplifier module. For example, the decoding unit includes four signal output terminals, each outputting four control signals: 00, 10, 11, and 01. These four control signals (00, 10, 11, and 01) are used to control the control terminals of four different switches in the low-noise amplifier module, thereby controlling the operating state of the four switches.

[0031] In at least one embodiment, the low-noise amplifier chip further includes a first connection trace and a second connection trace. The first connection trace is configured to connect the first power supply port and the power supply terminal of the decoding unit, and the second connection trace is configured to connect the first power supply port and the power supply terminal of the interface unit. The first connection trace can be equivalent to a first trace resistance, and the second connection trace can be equivalent to a second trace resistance. The first trace resistance and the second trace resistance can also reduce the voltage fluctuation transmitted from the first power supply port to the power supply terminal of the decoding unit to a certain extent.

[0032] In one specific embodiment, since the two signal lines (SCLK and SDATA) used to transmit clock and data signals at the input of the interface unit are typically driven by open drain, these two signal lines (SCLK and SDATA) are pulled high by pull-up resistors. When the master or slave device actively pulls these two signal lines (SCLK and SDATA) low, a dynamic current is generated. The magnitude of this dynamic current is directly related to the frequency of the clock signal. The higher the frequency of the clock signal, the faster the signal switching rate, the higher the charging and discharging frequency, and the greater the dynamic current. Furthermore, during the data transmission of clock and data signals, the constant switching of logic levels (high / low) between the clock and data signals causes the parasitic capacitance to charge and discharge with each level switch, resulting in transient current consumption. The higher the density of data signal transmission (i.e., the more logic flips on the signal line), the greater the dynamic current consumption. When transmitting a large number of commands and data, even more current is consumed. This causes the interface unit to draw current from the first power supply port, resulting in voltage fluctuations in the power supply voltage output from the first power supply port. This, in turn, affects the normal operation of the decoding unit, causing jitter in the control signal ultimately output by the decoding unit to the low-noise amplifier module. This deteriorates the noise performance of the low-noise amplifier, for example, causing noise spikes to appear at certain specific frequencies.

[0033] To address this, this application connects a first voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the decoding unit. The first voltage regulator unit can block voltage fluctuations output from the first power supply port and also filter out voltage fluctuations output from the first power supply port to ground, preventing voltage fluctuations output from the first power supply port from being transmitted to the power supply terminal of the decoding unit. This avoids jitter in the control signal ultimately output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0034] Furthermore, by connecting the first voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the decoding unit, this embodiment addresses the issue of noise performance degradation in the low-noise amplifier by using fewer voltage regulator units compared to related technologies that connect the voltage regulator unit to the path between the output terminal of the control module and the control terminal in the low-noise amplifier module. This avoids the need to connect a voltage regulator unit to every connection path between each output terminal of the control module and the corresponding control terminal in the low-noise amplifier module, thus significantly reducing the number of components and lowering costs.

[0035] In at least one embodiment, the first voltage regulator unit may include at least one or a combination of a capacitor unit, a resistor unit, and an inductor unit. For example, the first voltage regulator unit includes a resistor unit connected in series in the connection path between the first power supply port and the power supply terminal of the decoding unit. Alternatively, the first voltage regulator unit includes a capacitor unit, with a first terminal connected to the power supply terminal of the decoding unit and a second terminal grounded. Alternatively, the first voltage regulator unit may include a capacitor unit and a resistor unit, with the resistor unit connected in series in the connection path between the first power supply port and the power supply terminal of the decoding unit, a first terminal connected to the power supply terminal of the decoding unit, and a second terminal grounded.

[0036] In this embodiment, a low-noise amplifier chip includes a chip, a first power supply port, a control module, a low-noise amplifier module, and a first voltage regulator unit disposed on the chip. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals, and the signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to multiple control terminals in the low-noise amplifier module. The first voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the decoding unit. In this embodiment, by connecting the first voltage regulator unit on the connection path between the first power supply port and the power supply terminal of the decoding unit, the first voltage regulator unit can block voltage fluctuations output from the first power supply port and filter out voltage fluctuations output from the first power supply port to ground, preventing voltage fluctuations output from the first power supply port from being transmitted to the power supply terminal of the decoding unit. This avoids jitter in the control signal ultimately output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0037] In one specific embodiment, the first voltage regulator unit is configured to reduce voltage fluctuations transmitted to the power supply terminal of the decoding unit.

[0038] In at least one embodiment, because the interface unit draws current from the first power supply port during operation, the power supply voltage VIO experiences dynamic current consumption. This causes voltage fluctuations in the power supply voltage transmitted from the first power supply voltage VIO to the decoding unit via the first power supply port, affecting the control signal output from the decoding unit to the low-noise amplifier module and degrading the noise performance of the low-noise amplifier module. To address this, this embodiment connects a first voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the decoding unit. The first voltage regulator unit is configured to reduce voltage fluctuations transmitted to the power supply terminal of the decoding unit, thereby reducing jitter in the control signal output from the decoding unit to the low-noise amplifier module and improving the noise performance of the low-noise amplifier chip.

[0039] In one specific embodiment, the first voltage regulator unit includes a first capacitor C1, the first end of the first capacitor C1 is connected to the power supply terminal of the decoding unit, and the second end of the first capacitor C1 is grounded.

[0040] In at least one embodiment, the first capacitor C1 can be any type of capacitor unit such as a MOSFET capacitor, a MOS capacitor, or an SMD capacitor. The first end of the first capacitor C1 is connected to the power supply terminal of the decoding unit, and the second end of the first capacitor is grounded. The first capacitor is configured to filter out voltage fluctuations caused by the interface unit to ground, thereby ensuring that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port is free from voltage fluctuations. This avoids jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0041] In one specific embodiment, the first voltage regulator unit includes a first resistor R1, the first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply terminal of the decoding unit.

[0042] In at least one embodiment, the first resistor R1 can be any type of resistor unit such as a polysilicon resistor or a metal resistor. The first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply terminal of the decoding unit. The first resistor is configured to block voltage fluctuations caused by the interface unit from being transmitted to the decoding unit, thereby ensuring that the power supply voltage VIO output by the first power supply voltage is free from voltage fluctuations transmitted to the decoding unit through the first power supply port. This prevents jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0043] In one specific embodiment, the first voltage regulator unit includes a first capacitor C1 and a first resistor R1. A first terminal of the first capacitor is connected to the power supply terminal of the decoding unit, and a second terminal of the first capacitor is grounded. A first terminal of the first resistor R1 is connected to the first power supply port, and a second terminal of the first resistor is connected to the power supply terminal of the decoding unit. The first capacitor is configured to filter out voltage fluctuations in the first power supply caused by the interface unit and ground them. The first resistor is configured to block voltage fluctuations in the first power supply caused by the interface unit from being transmitted to the decoding unit. With the combined action of the first resistor and the first capacitor, voltage fluctuations transmitted to the decoding unit can be filtered out more effectively, thereby preventing jitter in the control signal ultimately output by the decoding unit to the low-noise amplifier module, and thus improving the noise performance of the low-noise amplifier chip.

[0044] In one specific embodiment, the resistance value of the first resistor is in the range of [5 ohms, 500 ohms].

[0045] In at least one embodiment, the resistance value of the first resistor is in any at least one range of [5 ohms, 50 ohms], (50 ohms, 100 ohms], (100 ohms, 200 ohms], (200 ohms, 300 ohms], (300 ohms, 400 ohms], (400 ohms, 500 ohms], etc.

[0046] Preferably, the first resistor is a polysilicon resistor, thereby improving circuit stability and enabling high-precision resistance value adjustment.

[0047] In one specific embodiment, the first capacitor is an interpolated capacitor (MOM capacitor), and the capacitance value of the first capacitor is in the range of [1pF, 10pF].

[0048] In at least one embodiment, the capacitance value of the first capacitor is in any at least one range such as [1pF, 3pF], (3pF, 5pF], (5pF, 8pF], (8pF, 10pF].

[0049] Preferably, the first capacitor is a MOM capacitor. Since the first voltage regulator unit in this embodiment is integrated into the chip, the first capacitor is a MOM capacitor, which can reduce the occupied area while ensuring performance.

[0050] In this embodiment, the first capacitor is a MOM capacitor. Compared to related technologies that connect a grounded capacitor to the path between the output of the control module and the control terminal in the low-noise amplifier module, this application uses a MOM capacitor instead of a MIM capacitor, and the capacitance value of the first capacitor is in the range of [1pF, 10pF]. It should be noted that in related technologies, the capacitance value of the grounded capacitor connected to the path between the output of the control module and the control terminal in the low-noise amplifier module needs to be less than 1pF; therefore, a MIM capacitor is typically used. If the capacitance value of the grounded capacitor connected to the path between the output of the control module and the control terminal in the low-noise amplifier module is greater than or equal to 1pF, the output switching of the decoding unit will be slower, thus slowing down the gear switching time of the low-noise amplifier module and affecting its normal operation. This application connects a grounded first capacitor to the connection path between the first power supply port and the power supply terminal of the decoding unit. The first capacitor is an interdigitated capacitor (MOM capacitor), and the capacitance value of the first capacitor can be set in the range of [1pF, 10pF]. This not only improves the noise performance of the low-noise amplifier chip, but also saves the number of components and reduces costs, and does not affect the range switching time of the low-noise amplifier module.

[0051] In one specific embodiment, the low-noise amplifier chip further includes a second voltage regulator unit, which is connected on the connection path between the first power supply port and the power supply terminal of the interface unit.

[0052] In at least one embodiment, since the signal input terminal of the interface unit receives a data signal (DATA) and a clock signal (CLK), and the clock signal and data signal continuously switch logic levels (high / low), the interface unit generates noise signals (e.g., repetitive pull-up current). These noise signals leak from the power supply terminal of the interface unit or flow back to the first power supply port, causing voltage fluctuations in the first power supply connected to the first power supply port, thus affecting the normal operation of the decoding unit. To address this, this application connects a second voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the interface unit. The second voltage regulator unit is configured to block the noise signals leaked from the interface unit to the first power supply port; thereby preventing voltage fluctuations in the first power supply from affecting the normal operation of the decoding unit; and thus improving the noise performance of the low-noise amplifier chip.

[0053] In at least one embodiment, the second voltage regulator unit may adopt a circuit structure similar to that of the first voltage regulator unit. For example, the second voltage regulator unit may include at least one or a combination of capacitor unit, resistor unit and inductor unit.

[0054] In one embodiment, the second voltage regulator unit includes a second capacitor, a first terminal of which is connected to the power supply terminal of the interface unit, and a second terminal of which is grounded. The second capacitor is configured to filter out noise signals generated by the interface unit and send them to ground.

[0055] In one embodiment, the second voltage regulator unit includes a second resistor, a first end of which is connected to the first power supply port, and a second end of which is connected to the power supply terminal of the interface unit. The second resistor is configured to block noise signals generated by the interface unit, preventing noise signals generated by the interface unit from flowing back or leaking to the first power supply port.

[0056] In one specific embodiment, the second voltage regulator unit includes a second capacitor and a second resistor. The first terminal of the second capacitor is connected to the power supply terminal of the interface unit, and the second terminal of the second capacitor is grounded. The first terminal of the second resistor is connected to the first power supply port, and the second terminal of the second resistor is connected to the power supply terminal of the interface unit. The second capacitor is configured to filter out noise signals generated by the interface unit to ground, and the second resistor is configured to block noise signals generated by the interface unit. With the combined action of the second capacitor and the second resistor, the backflow or leakage of noise signals generated by the interface unit to the first power supply port can be better prevented, thus avoiding noise signals generated by the interface unit from affecting the normal power supply of the first power supply to the decoding unit and the interface unit.

[0057] It should be noted that the implementation of the second capacitor in this embodiment is similar to that of the first capacitor described above, and the implementation of the second resistor is similar to that of the first resistor described above, so there will be no redundant description here.

[0058] In one specific embodiment, the low-noise amplification module includes multiple switching units, and multiple signal output terminals of the decoding unit are connected to multiple control terminals corresponding to the multiple switching units to control the multiple switching units to be turned on or off respectively.

[0059] In at least one embodiment, the low-noise amplifier module includes multiple switching units. For example, the switching unit can be a switching unit in a bypass branch, a switching unit in an amplification branch, or a switching unit in a gain adjustment circuit, or any other switching unit in the low-noise amplifier module. Since the switching units at different connection positions in the low-noise amplifier module operate in different states, multiple independent control signals are needed to control the state of the corresponding switching units in the low-noise amplifier module. That is, the multiple signal output terminals of the decoding unit are connected to the control terminals of the corresponding switching units in the low-noise amplifier module through multiple connection paths to meet the normal operation requirements of the noise amplifier module. This embodiment, by connecting the first voltage regulator unit on the connection path between the first power supply port and the power supply terminal of the decoding unit, instead of connecting multiple first voltage regulator units on the connection path between the multiple signal output terminals of the decoding unit and the control terminals of the corresponding switching units in the low-noise amplifier module, can significantly save chip space and reduce costs while improving the noise performance of the low-noise amplifier.

[0060] In one specific embodiment, as follows: Figure 4 As shown, the decoding unit has multiple signal output terminals, including a first signal output terminal and a second signal output terminal. The low-noise amplification module includes an amplification unit 301 and a bypass unit. The amplification unit 301 is connected between the RF input terminal and the RF output terminal and is used to amplify the first RF signal input at the RF input terminal. The bypass unit is connected between the RF input terminal and the RF output terminal. The bypass unit includes a bypass switch S301 and a pull-down switch S302. The bypass switch S301 is connected in series between the RF input terminal and the RF output terminal. The first terminal of the pull-down switch S302 is connected to the bypass switch, and the second terminal of the pull-down switch S302 is grounded. The first signal output terminal of the decoding unit is connected to the control terminal of the bypass switch, and the second signal output terminal of the decoding unit is connected to the control terminal of the pull-down switch.

[0061] In at least one embodiment, the states of the bypass switch S301 and the pull-down switch S302 are each controlled by two independent control signals. The state of the bypass switch S301 is controlled by a first control signal output from the first signal output terminal of the decoding unit, and the state of the pull-down switch S302 is controlled by a second control signal output from the second signal output terminal of the decoding unit.

[0062] In at least one embodiment, the amplification unit includes a first amplifying transistor and a second amplifying transistor. The base (gate) of the first amplifying transistor is connected to a signal input terminal, and the collector (source) of the first amplifying transistor is connected to the emitter (drain) of the second amplifying transistor. The emitter (drain) of the first amplifying transistor is grounded. The base (gate) of the second amplifying transistor is connected to a bias control terminal, the collector (source) is connected to a signal output terminal, and it is connected to a power supply port VDD via a load inductor. In at least one embodiment, the power supply voltage received by the power supply port VDD can be 1.2V.

[0063] When the amplification unit 301 is configured to be in the working state, the first control signal (00) output by the first signal output terminal of the decoding unit controls the bypass switch S301 to open, and the second control signal output by the second signal output terminal of the decoding unit controls the pull-down switch S302 to close (11); when the amplification unit 301 is configured to be in the non-working state, the first control signal (11) output by the first signal output terminal of the decoding unit controls the bypass switch S301 to close, and the second control signal (00) output by the second signal output terminal of the decoding unit controls the pull-down switch S302 to open; in this embodiment, by connecting the first voltage regulator unit on the connection path between the first power supply port and the power supply terminal of the decoding unit, the jitter of the first control signal output by the first signal output terminal of the decoding unit and the second control signal output by the second signal output terminal of the decoding unit can be effectively avoided, thereby improving the noise performance of the low-noise amplifier chip.

[0064] In one specific embodiment, as follows: Figure 5As shown, the decoding unit has multiple signal output terminals including a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal. The low-noise amplification module includes a first signal amplification unit and a second signal amplification unit. The first output node of the first signal amplification unit and the second output node of the second signal amplification unit are connected. The first signal amplification unit includes a first amplification transistor 201, a first switching switch S201, and a first isolation switch S203. The second signal amplification unit includes a second amplification transistor 202, a second switching switch S202, and a second isolation switch S204. The first terminal of the first amplifying transistor is connected to the first terminal of the first switching switch and the first terminal of the first isolating switch; the second terminal of the first amplifying transistor is connected to the ground terminal, and the third terminal of the first amplifying transistor is connected to the first input node of the first signal amplification unit; the second terminal of the first isolating switch is connected to the ground terminal, and the second terminal of the first switching switch is connected to the first output node of the first signal amplification unit; the first terminal of the second amplifying transistor is connected to the first terminal of the second switching switch and the first terminal of the second isolating switch, the second terminal of the second amplifying transistor is connected to the ground terminal, the third terminal of the second amplifying transistor is connected to the second input node of the second signal amplification unit, the second terminal of the second isolating switch is grounded, and the second terminal of the second switching switch is connected to the first output node of the first signal amplification unit. The first signal output terminal of the decoding unit is connected to the control terminal of the first switching switch, the second signal output terminal of the decoding unit is connected to the control terminal of the first isolating switch, the third signal output terminal of the decoding unit is connected to the control terminal of the second switching switch, and the fourth signal output terminal of the decoding unit is connected to the control terminal of the second isolating switch.

[0065] In at least one embodiment, when the first signal amplification unit is in a signal amplification state and the second signal amplification unit is in a de-energized state, the first control signal output from the first signal output terminal of the decoding unit controls the first switching switch to turn on, the first control signal output from the second signal output terminal of the decoding unit controls the first isolation switch to turn off, the third control signal output from the third signal output terminal of the decoding unit controls the second switching switch to turn off, and the fourth control signal output from the fourth signal output terminal of the decoding unit controls the second isolation switch to turn on. Since the second switching switch is off, ideally, no signal passes through the second signal amplification unit. However, since the switch is effectively equivalent to a capacitor in the off state, in practical applications, the radio frequency signal in the first signal amplification unit will still leak to the second amplifying transistor through the second switching switch in the off state, causing the second amplifying transistor to be in a slightly on state. Therefore, by connecting a second isolating switch to ground at the first terminal of the second amplifying transistor, and turning on the second isolating switch when the second switching switch is off, the second isolating switch in the conducting state can pull the voltage at the first terminal of the second amplifying transistor to the ground potential terminal, so as to release the radio frequency signal leaked from the first signal amplifying unit to ground, prevent the signal in the first signal amplifying unit from leaking to the second amplifying transistor, thereby avoiding the phenomenon of micro-conduction in the second amplifying transistor, improving the isolation between the first signal amplifying unit and the second signal amplifying unit, and thus ensuring the stability of the operation of the first signal amplifying unit.

[0066] In at least one embodiment, when the second signal amplification unit is in a signal amplification state and the first signal amplification unit is in a turn-off state, the first control signal output from the first signal output terminal of the decoding unit controls the first switching switch to turn off, the second control signal output from the second signal output terminal of the decoding unit controls the first isolation switch to turn on, and the third control signal output from the third signal output terminal of the decoding unit controls the second switching switch to turn on. The fourth control signal output from the fourth signal output terminal of the decoding unit controls the second isolation switch to turn off. Ideally, no signal passes through the first signal amplification unit. However, since the switch is actually equivalent to a capacitor in the turn-off state, in actual applications, the radio frequency signal in the second signal amplification unit will still leak to the first amplifying transistor through the first switching switch in the turn-off state, causing the first amplifying transistor to be in a slightly conducting state. By connecting a first isolating switch to ground at the first terminal of the first amplifying transistor, and turning on the first isolating switch when the first switching switch is off, the first isolating switch in the on state can pull the voltage at the first terminal of the first amplifying transistor to the ground potential terminal, so as to release the radio frequency signal leaked from the second signal amplifying unit to ground, prevent the signal in the second signal amplifying unit from leaking to the first amplifying transistor, thereby avoiding the phenomenon of micro-conduction in the first amplifying transistor, improving the isolation between the first signal amplifying unit and the second signal amplifying unit, and thus ensuring the stability of the operation of the second signal amplifying unit.

[0067] This embodiment connects the first voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the decoding unit, thereby effectively preventing jitter in the first control signal output from the first signal output terminal of the decoding unit, the second control signal output from the second signal output terminal of the decoding unit, the third control signal output from the third signal output terminal of the decoding unit, and the fourth control signal output from the fourth signal output terminal of the decoding unit, thereby improving the noise performance of the low-noise amplifier chip.

[0068] This application also provides a low-noise amplifier chip, such as Figure 2 As shown, the device includes a chip 100, a first power supply port, a control module 10, a low-noise amplifier module 20, and a second voltage regulator unit disposed on the chip. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals. The signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to multiple control terminals in the low-noise amplifier module. The second voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the interface unit.

[0069] In at least one embodiment, since the signal input terminal of the interface unit receives a data signal (DATA) and a clock signal (CLK), and the clock signal and data signal continuously switch logic levels (high / low), the interface unit generates noise signals (e.g., repetitive pull-up current). These noise signals leak from the power supply terminal of the interface unit or flow back to the first power supply port, causing voltage fluctuations in the first power supply connected to the first power supply port, thus affecting the normal operation of the decoding unit. To address this, this application connects a second voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the interface unit. The second voltage regulator unit is configured to block the noise signals leaked from the interface unit to the first power supply port; thereby preventing voltage fluctuations in the first power supply from affecting the normal operation of the decoding unit; and thus improving the noise performance of the low-noise amplifier chip.

[0070] In one embodiment, the second voltage regulator unit includes a second capacitor, a first terminal of which is connected to the power supply terminal of the interface unit, and a second terminal of which is grounded. The second capacitor is configured to filter out noise signals generated by the interface unit and send them to ground.

[0071] In one embodiment, the second voltage regulator unit includes a second resistor, a first end of which is connected to the first power supply port, and a second end of which is connected to the power supply terminal of the interface unit. The second resistor is configured to block noise signals generated by the interface unit, preventing noise signals generated by the interface unit from flowing back or leaking to the first power supply port.

[0072] In one specific embodiment, the second voltage regulator unit includes a second capacitor and a second resistor. The first terminal of the second capacitor is connected to the power supply terminal of the interface unit, and the second terminal of the second capacitor is grounded. The first terminal of the second resistor is connected to the first power supply port, and the second terminal of the second resistor is connected to the power supply terminal of the interface unit. The second capacitor is configured to filter out noise signals generated by the interface unit to ground, and the second resistor is configured to block noise signals generated by the interface unit. With the combined action of the second capacitor and the second resistor, the backflow or leakage of noise signals generated by the interface unit to the first power supply port can be better prevented, thus avoiding noise signals generated by the interface unit from affecting the normal power supply of the first power supply to the decoding unit and the interface unit.

[0073] It should be noted that the implementation of the second capacitor in this embodiment is similar to that of the first capacitor described above, and the implementation of the second resistor is similar to that of the first resistor described above, so there will be no redundant description here.

[0074] This application also provides a low-noise amplifier, such as Figure 7 As shown, the system includes a first power supply port, a control module, a low-noise amplifier circuit, and a first voltage regulator unit. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals. The signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to multiple switching units in the low-noise amplifier circuit to control the switching units to be turned on or off. The first voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the decoding unit.

[0075] In at least one embodiment, the control module and the low-noise amplifier circuit can be integrated on a single chip or on separate chips. For example, both the control module and the low-noise amplifier circuit can be integrated on a GaAs chip, or the control module can be integrated on a CMOS chip and the low-noise amplifier circuit on a GaAs chip.

[0076] In at least one embodiment, the first voltage regulator unit may be disposed on a substrate or integrated with the control module on a single chip.

[0077] In one specific embodiment, the system further includes a substrate, and a metal oxide semiconductor chip (CMOS chip), a silicon insulator chip (SOI chip), and a first voltage regulator unit disposed on the substrate; the control module is integrated on the metal oxide semiconductor chip (CMOS chip), and the low-noise amplifier circuit is integrated on the silicon insulator chip (SOI chip).

[0078] In at least one embodiment, the low-noise amplifier circuit typically includes multiple switching units, such as: bypass switches and pull-down switches in the bypass branch; isolation switches and switching switches in the amplification branch; and adjustment switches in the gain adjustment circuit. The switching units at different connection positions in the low-noise amplifier module operate in different states. Therefore, multiple independent control signals are needed to control the state of the corresponding switching units in the low-noise amplifier module. That is, the multiple signal output terminals of the decoding unit are connected to the control terminals of the corresponding switching units in the low-noise amplifier module through multiple connection paths to meet the normal operation requirements of the noise amplifier module. This embodiment, by connecting the first voltage regulator unit on the connection path between the first power supply port and the power supply terminal of the decoding unit, instead of connecting multiple first voltage regulator units on the connection path between the multiple signal output terminals of the decoding unit and the control terminals of the corresponding switching units in the low-noise amplifier module, can significantly save chip space and reduce costs while improving the noise performance of the low-noise amplifier.

[0079] In one specific embodiment, the first voltage regulator unit includes a first capacitor C1, the first end of the first capacitor C1 is connected to the power supply terminal of the decoding unit, and the second end of the first capacitor C1 is grounded.

[0080] In at least one embodiment, the first capacitor C1 can be any type of capacitor unit such as a MOM capacitor, MOS capacitor, or SMD capacitor. The first end of the first capacitor C1 is connected to the power supply terminal of the decoding unit, and the second end of the first capacitor is grounded. The first capacitor is configured to filter out voltage fluctuations caused by the interface unit to ground, thereby ensuring that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port is free from voltage fluctuations. This avoids jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0081] In one specific embodiment, the first voltage regulator unit includes a first resistor R1, the first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply terminal of the decoding unit.

[0082] In at least one embodiment, the first resistor R1 can be any type of resistor unit such as a polysilicon resistor or a metal resistor. The first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply terminal of the decoding unit. The first resistor is configured to block voltage fluctuations caused by the interface unit from being transmitted to the decoding unit, thereby ensuring that the power supply voltage VIO output by the first power supply voltage is free from voltage fluctuations transmitted to the decoding unit through the first power supply port. This prevents jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0083] In at least one embodiment, the first voltage regulator unit includes a first capacitor C1 and a first resistor R1. A first terminal of the first capacitor is connected to the power supply terminal of the decoding unit, and a second terminal of the first capacitor is grounded. A first terminal of the first resistor R1 is connected to the first power supply port, and a second terminal of the first resistor is connected to the power supply terminal of the decoding unit. The first capacitor is configured to filter out voltage fluctuations in the first power supply caused by the interface unit and ground, and the first resistor is configured to block voltage fluctuations in the first power supply caused by the interface unit from being transmitted to the decoding unit. Under the combined action of the first resistor and the first capacitor, voltage fluctuations transmitted to the decoding unit can be filtered out more effectively, thereby avoiding jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, and thus improving the noise performance of the low-noise amplifier chip.

[0084] This application also provides an RF front-end module, such as Figure 7 As shown, the system includes a first power supply port, a control module 10, a switching module 30, and a first voltage regulator unit. The control module includes an interface unit and a decoding unit. The first power supply port is connected to the power supply terminals of the interface unit and the decoding unit, respectively. The signal input terminal of the interface unit is configured to receive clock signals and data signals. The signal output terminal of the interface unit is connected to the signal input terminal of the decoding unit. The decoding unit includes multiple signal output terminals, which are connected to the control terminals corresponding to multiple different switching units in the switching module. The first voltage regulator unit is connected on the connection path between the first power supply port and the power supply terminal of the decoding unit.

[0085] In at least one embodiment, the control module and the switch module can be integrated on a single chip or on separate chips. For example, both the control module and the switch module can be integrated on a silicon-on-insulator (SOI) chip, or the control module can be integrated on a metal-oxide-semiconductor (CMOS) chip, and the switch module can be integrated on a silicon-on-insulator (SOI) chip.

[0086] In at least one embodiment, the RF front-end module typically includes multiple different switching units. For example, a band selection switching unit, an ASM switching unit, or a tuning switching unit. The switching units at different connection locations in the RF front-end module operate in different states, therefore multiple independent control signals are needed to control the state of the corresponding switching units. That is, the multiple signal outputs of the decoding unit are connected to the control terminals of the corresponding switching units through multiple connection paths to meet the normal operation requirements of the RF front-end module. This embodiment, by connecting the first voltage regulator unit on the connection path between the first power supply port and the power supply terminal of the decoding unit, instead of connecting multiple first voltage regulator units on the connection path between the multiple signal outputs of the decoding unit and the control terminals of the corresponding switching units, can significantly save chip space and reduce costs while improving the noise performance of the RF front-end module.

[0087] In one specific embodiment, the first voltage regulator unit includes a first capacitor C1, the first end of the first capacitor C1 is connected to the power supply terminal of the decoding unit, and the second end of the first capacitor C1 is grounded.

[0088] In at least one embodiment, the first capacitor C1 can be any type of capacitor unit such as a MOM capacitor, MOS capacitor, or SMD capacitor. The first end of the first capacitor C1 is connected to the power supply terminal of the decoding unit, and the second end of the first capacitor is grounded. The first capacitor is configured to filter out voltage fluctuations caused by the interface unit to ground, so that the power supply voltage VIO output by the first power supply voltage and transmitted to the decoding unit through the first power supply port is free from voltage fluctuations, thereby avoiding jitter in the control signal finally output by the decoding unit to the switching module and improving the noise performance of the switching module.

[0089] In one specific embodiment, the first voltage regulator unit includes a first resistor R1, the first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply terminal of the decoding unit.

[0090] In at least one embodiment, the first resistor R1 can be any type of resistor unit such as a polysilicon resistor or a metal resistor. The first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply terminal of the decoding unit. The first resistor is configured to block voltage fluctuations caused by the interface unit from being transmitted to the decoding unit, thereby ensuring that the power supply voltage VIO output by the first power supply voltage is free from voltage fluctuations transmitted to the decoding unit through the first power supply port. This prevents jitter in the control signal finally output by the decoding unit to the switching module, thereby improving the noise performance of the switching module.

[0091] In at least one embodiment, the first voltage regulator unit includes a first capacitor C1 and a first resistor R1. A first terminal of the first capacitor is connected to the power supply terminal of the decoding unit, and a second terminal of the first capacitor is grounded. A first terminal of the first resistor R1 is connected to the first power supply port, and a second terminal of the first resistor is connected to the power supply terminal of the decoding unit. The first capacitor is configured to filter out voltage fluctuations in the first power supply caused by the interface unit and ground, and the first resistor is configured to block voltage fluctuations in the first power supply caused by the interface unit from being transmitted to the decoding unit. Under the combined action of the first resistor and the first capacitor, voltage fluctuations transmitted to the decoding unit can be filtered out more effectively, thereby avoiding jitter in the control signal finally output by the decoding unit to the switching module, and thus improving the noise performance of the switching module.

[0092] In one specific embodiment, the radio frequency front-end module further includes a second voltage regulator unit, which is connected to the connection path between the first power supply port and the power supply terminal of the interface unit.

[0093] In at least one embodiment, since the signal input terminal of the interface unit receives a data signal (DATA) and a clock signal (CLK), and the clock signal and data signal continuously switch logic levels (high / low), the interface unit generates noise signals (e.g., repetitive pull-up current). These noise signals leak from the power supply terminal of the interface unit or flow back to the first power supply port, causing voltage fluctuations in the first power supply connected to the first power supply port, thus affecting the normal operation of the decoding unit. To address this, this application connects a second voltage regulator unit to the connection path between the first power supply port and the power supply terminal of the interface unit. The second voltage regulator unit is configured to block the noise signals leaked from the interface unit to the first power supply port; thereby preventing voltage fluctuations in the first power supply from affecting the normal operation of the decoding unit; and thus improving the noise performance of the RF front-end module.

[0094] In at least one embodiment, the second voltage regulator unit may adopt a circuit structure similar to that of the first voltage regulator unit. For example, the second voltage regulator unit may include at least one or a combination of capacitor unit, resistor unit and inductor unit.

[0095] In one specific embodiment, the second voltage regulator unit includes a second resistor, which is connected in series on the connection path between the first power supply port and the power supply terminal of the interface unit.

[0096] And / or, the voltage regulator unit includes a second capacitor, the first end of which is connected to the connection path between the first power supply port and the power supply terminal of the interface unit, and the second end of which is grounded.

[0097] In one embodiment, the second voltage regulator unit includes a second capacitor, a first terminal of which is connected to the power supply terminal of the interface unit, and a second terminal of which is grounded. The second capacitor is configured to filter out noise signals generated by the interface unit and send them to ground.

[0098] In one embodiment, the second voltage regulator unit includes a second resistor, a first end of which is connected to the first power supply port, and a second end of which is connected to the power supply terminal of the interface unit. The second resistor is configured to block noise signals generated by the interface unit, preventing noise signals generated by the interface unit from flowing back or leaking to the first power supply port.

[0099] In one specific embodiment, the second voltage regulator unit includes a second capacitor and a second resistor. The first terminal of the second capacitor is connected to the power supply terminal of the interface unit, and the second terminal of the second capacitor is grounded. The first terminal of the second resistor is connected to the first power supply port, and the second terminal of the second resistor is connected to the power supply terminal of the interface unit. The second capacitor is configured to filter out noise signals generated by the interface unit to ground, and the second resistor is configured to block noise signals generated by the interface unit. With the combined action of the second capacitor and the second resistor, the backflow or leakage of noise signals generated by the interface unit to the first power supply port can be better prevented, thus avoiding noise signals generated by the interface unit from affecting the normal power supply of the first power supply to the decoding unit and the interface unit.

[0100] It should be noted that the implementation of the second capacitor in this embodiment is similar to that of the first capacitor described above, and the implementation of the second resistor is similar to that of the first resistor described above, so there will be no redundant description here.

[0101] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A low noise amplifier chip, characterized by, The chip comprises a first power supply port, a control module, a low-noise amplification module and a first voltage stabilizing unit arranged on the chip, the control module comprises an interface unit and a decoding unit; the first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit respectively, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the first voltage stabilizing unit is connected to a connection path between the first power supply port and the power supply end of the decoding unit.

2. The low noise amplifier chip of claim 1, wherein, The first voltage stabilizing unit is configured to reduce voltage fluctuation transmitted to the power supply end of the decoding unit.

3. The low noise amplifier chip of claim 1, wherein, The first voltage stabilizing unit comprises a first capacitor, a first end of the first capacitor is connected to the power supply end of the decoding unit, and a second end of the first capacitor is grounded.

4. The low-noise amplification chip of claim 1 or 3, wherein The first voltage stabilizing unit comprises a first resistor, a first end of the first resistor is connected to the first power supply port, and a second end of the first resistor is connected to the power supply end of the decoding unit.

5. The low noise amplifier chip of claim 4, wherein, The resistance value of the first resistor is in the range of [5 ohms, 500 ohms].

6. The low noise amplifier chip of claim 3, wherein, The first capacitor is an interdigital capacitor, and the capacitance value of the first capacitor is in the range of [1 pF, 10 pF].

7. The low noise amplifier chip of claim 1, wherein, The low-noise amplification chip further comprises a second voltage stabilizing unit, and the second voltage stabilizing unit is connected to a connection path between the first power supply port and the power supply end of the interface unit.

8. The low noise amplifier chip of claim 7, wherein, The second voltage stabilizing unit is configured to reduce the spurious signal leaked by the interface unit to the first power supply port.

9. The low noise amplifier chip of claim 7, wherein, The second voltage stabilizing unit comprises a second capacitor, a first end of the second capacitor is connected to the power supply end of the interface unit, and a second end of the second capacitor is grounded.

10. The low noise amplifier chip of claim 8 or 9, wherein, The second voltage stabilizing unit comprises a second resistor, a first end of the second resistor is connected to the first power supply port, and a second end of the second resistor is connected to the power supply end of the interface unit.

11. The low noise amplifier chip of claim 1, wherein, The low-noise amplification module comprises a plurality of switch units, and the plurality of signal output ends of the decoding unit are connected to a plurality of control ends corresponding to the plurality of switch units to control the conduction or turn-off of the plurality of switch units, respectively.

12. The low noise amplifier chip of claim 1, wherein, The multiple signal output ends of the decoding unit include a first signal output end and a second signal output end, the low-noise amplification module includes an amplification unit and a bypass unit, the amplification unit is connected between the radio frequency input end and the radio frequency output end, and is used for amplifying the first radio frequency signal input by the radio frequency input end, the bypass unit is connected between the radio frequency input end and the radio frequency output end, the bypass unit includes a bypass switch and a pull-down switch, the bypass switch is connected in series between the radio frequency input end and the radio frequency output end, a first end of the pull-down switch is connected with the bypass switch, and a second end of the pull-down switch is grounded, the first signal output end of the decoding unit is connected to a control end of the bypass switch, and the second signal output end of the decoding unit is connected to a control end of the pull-down switch.

13. The low noise amplifier chip of claim 1, wherein, The multiple signal output ends of the decoding unit include a first signal output end, a second signal output end, a third signal output end and a fourth signal output end, the low-noise amplification module includes a first signal amplification unit and a second signal amplification unit, a first output node of the first signal amplification unit and a second output node of the second signal amplification unit are connected, the first signal amplification unit includes a first amplification transistor, a first switching switch and a first isolation switch, the second signal amplification unit includes a second amplification transistor, a second switching switch and a second isolation switch; a first end of the first amplification transistor is connected with a first end of the first switching switch and a first end of the first isolation switch; a second end of the first amplification transistor is connected with a ground end, and a third end of the first amplification transistor is connected with a first input node of the first signal amplification unit; a second end of the first isolation switch is connected with the ground end, and a second end of the first switching switch is connected with a first output node of the first signal amplification unit; a first end of the second amplification transistor is connected with a first end of the second switching switch and a first end of the second isolation switch, a second end of the second amplification transistor is connected with the ground end, a third end of the second amplification transistor is connected with a second input node of the second signal amplification unit, a second end of the second isolation switch is grounded, a second end of the second switching switch is connected with the first output node of the first signal amplification unit, the first signal output end of the decoding unit is connected to a control end of the first switching switch, the second signal output end of the decoding unit is connected to a control end of the first isolation switch, the third signal output end of the decoding unit is connected to a control end of the second switching switch, and the fourth signal output end of the decoding unit is connected to a control end of the second isolation switch.

14. The low noise amplifier chip of claim 1, wherein, The low-noise amplification chip is an insulating silicon chip.

15. A low noise amplifier chip, characterized by The chip, a first power supply port, a control module, a low-noise amplification module and a second voltage stabilizing unit are arranged on the chip, the control module comprises an interface unit and a decoding unit; the first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit respectively, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the second voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the interface unit.

16. A low noise amplifier, characterized by The chip, a first power supply port, a control module, a low-noise amplification module and a second voltage stabilizing unit are arranged on the chip, the control module comprises an interface unit and a decoding unit; the first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit respectively, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the second voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the interface unit. The first voltage stabilizing unit comprises a first capacitor, a first end of the first capacitor is connected to the power supply end of the decoding unit, and a second end of the first capacitor is grounded. And / or, the first voltage stabilizing unit comprises a first resistor, a first end of the first resistor is connected to the first power supply port, and a second end of the first resistor is connected to the power supply end of the decoding unit.

17. The low noise amplifier of claim 16, wherein, Further comprising a substrate, a metal oxide semiconductor chip, an insulating silicon chip and a first voltage stabilizing unit arranged on the substrate; the control module is integrated on the metal oxide semiconductor chip, and the low-noise amplification circuit is integrated on the insulating silicon chip. The chip, a first power supply port, a control module, a low-noise amplification module and a second voltage stabilizing unit are arranged on the chip, the control module comprises an interface unit and a decoding unit; the first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit respectively, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the second voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the interface unit.

18. The low noise amplifier of claim 16, wherein, 20. The radio frequency front end module of claim 19, wherein 19. A radio frequency front end module, comprising: the first voltage stabilizing unit comprises a first resistor, and the first resistor is connected in series to the connection path between the first power supply port and the power supply end of the decoding unit. ​ ​ ​ And / or, the voltage stabilizing unit comprises a first capacitor, a first end of the first capacitor is connected on a connection path between the first power supply port and a power supply end of the decoding unit, and a second end of the first capacitor is grounded.

21. The radio frequency front end module of claim 19, wherein the first and second switches are configured to be controlled by a single control signal. The radio frequency front end module further comprises a second voltage stabilizing unit, which is connected on a connection path between the first power supply port and a power supply end of the interface unit.

22. The radio frequency front end module of claim 21, wherein the first and second switches are configured to be controlled by a single control signal. The second voltage stabilizing unit comprises a second resistor, which is connected in series on the connection path between the first power supply port and the power supply end of the interface unit. And / or, the voltage stabilizing unit comprises a second capacitor, a first end of the second capacitor is connected on the connection path between the first power supply port and the power supply end of the interface unit, and a second end of the second capacitor is grounded.

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