Circuit board and storage module product
By adjusting the width of the fan-out trace to match the width of the pad and setting a hollow area in the inner layer, the problem of discontinuous impedance of the fan-out signal was solved, and high-quality signal transmission was achieved.
Patent Information
- Application Number
- CN202423321223.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2034-12-31
AI Technical Summary
When traditional memory products fan out signals, the impedance of the traces in the fan-out section is discontinuous, causing the signal to reflect between the via and the pad, which affects the normal operation of the DRAM load.
By adjusting the width of the fan-out trace to match the width of the pad, and setting a cutout area in the inner layer below the connection trace, the reference height is adjusted to match the impedance, reducing impedance discontinuities.
It effectively reduces signal reflection, improves signal quality and stability, and ensures smooth signal transmission between pads and vias.
Smart Images
Figure CN223928510U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chips, in particular to a circuit board and a storage module product. BACKGROUND
[0002] In a conventional memory product, the trace impedance of the fan-out part is consistent with the impedance of the overall signal network channel during fan-out. However, due to the inconsistent spacing between layers, the trace width of the fan-out part is inconsistent with the pad and via width, which causes discontinuity of impedance. During signal transmission, the signal is reflected back and forth between the via and the pad, so that the DRAM (Dynamic Random Access Memory) load cannot correctly receive the signal and cannot work normally.
[0003] Therefore, how to reduce signal reflection and improve signal quality has become a problem to be solved in the field. CONTENT OF THE UTILITY MODEL
[0004] The purpose of the present application is to provide a circuit board and a storage module product to reduce signal reflection and improve signal quality.
[0005] The circuit board disclosed by the embodiments of the present application comprises a bottom layer, a top layer and an inner layer, the inner layer is located between the top layer and the bottom layer, the top layer is provided with a pad, a via is provided through the top layer, the bottom layer and the inner layer, the circuit board further comprises a plurality of fan-out traces, each of the fan-out traces comprises a connection trace, the connection trace is located between the opening of the via close to the pad and the pad; one end of the connection trace is connected with the pad, and the other end extends to the via; the width of the connection trace is the same as the width of the pad; the inner layer is a multi-layer laminated structure, at least one of the inner layers is provided with a hollow area at a position corresponding to the connection trace, and the hollow area is used to expose a reference layer below a position corresponding to the connection trace.
[0006] Optionally, the connection trace comprises a first end and a second end, the first end is connected with the pad, the second end extends towards the via, the first end covers the pad, and the second end covers the opening of the via.
[0007] Optionally, the area of the first end is equal to the area of the pad, and the shape of the first end is the same as the shape of the pad.
[0008] Optionally, the area of the projection of the hollow area on the bottom layer is greater than or equal to the area of the projection of the connection trace on the bottom layer.
[0009] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively.
[0010] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively.
[0011] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively.
[0012] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively.
[0013] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively.
[0014] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively.
[0015] Optionally, the hollowed-out region has an area of a normal projection on the bottom layer that is greater than or equal to a total area of a normal projection of the connection trace, the pad, and the via on the bottom layer, and shapes of two ends of the hollowed-out region are matched with shapes of the pad and an opening of the via, respectively. BRIEF DESCRIPTION OF DRAWINGS
[0016] The accompanying drawings, which are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:
[0017] Figure 1 is a schematic diagram of a first embodiment of a circuit board of the present application;
[0018] Figure 2 is a partial top view of a top layer in the first embodiment of the circuit board of the present application,
[0019] Figure 3 is a partial top view of a top layer in a second embodiment of the circuit board of the present application,
[0020] Figure 4 is a partial top view of a top layer in a third embodiment of the circuit board of the present application,
[0021] Figure 5 is a partial top view of a top layer in a fourth embodiment of the circuit board of the present application,
[0022] Figure 6 is a schematic diagram of an embodiment of a memory module product of the present application.
[0023] wherein 10, memory module product; 100, circuit board; 200, chip; 110, bottom layer; 120, top layer; 121, pad; 130, inner layer; 131, reference layer; 132, hollowed-out area; 133, first hole end; 134, second hole end; 140, via hole; 150, fan-out trace; 151, connection trace; 152, first end; 153, second end. DETAILED DESCRIPTION
[0024] The application will be described in detail below with reference to the drawings and optional embodiments. It should be noted that the following described embodiments or technical features can be combined in any manner to form new embodiments without conflict.
[0025] Figure 1 is a schematic diagram of a first embodiment of a circuit board of the present application, Figure 2 is a partial top view of a top layer in the first embodiment of the circuit board of the present application, Figure 1 and Figure 2As shown, the embodiment of the present application discloses a circuit board 100, comprising a bottom layer 110, a top layer 120 and an inner layer 130, the inner layer 130 is located between the top layer 120 and the bottom layer 110, the top layer 120 is provided with a pad 121, a via hole 140 is provided through the top layer 120, the bottom layer 110 and the inner layer 130, the circuit board 100 further comprises a plurality of fan-out wires 150, each of the fan-out wires 150 comprises a connection wire 151, the connection wire 151 is located between the opening of the via hole 140 close to the pad 121 and the pad 121; one end of the connection wire 151 is connected with the pad 121, and the other end extends to the via hole 140; the width of the connection wire 151 is the same as the width of the pad 121; the inner layer 130 is a multi-layer laminated structure, at least one inner layer 130 corresponding to the position of the connection wire 151 is provided with a hollow area 132, and the hollow area 132 is used for exposing the reference layer 131 below the position corresponding to the connection wire 151.
[0026] The present application improves the connection wire 151 between the pad 121 and the via hole 140 in the fan-out wire 150 of the circuit board 100 and the inner layer 130 below the connection wire 151, so that the width of the connection wire 151 is equal to the width of the pad 121, and at least one inner layer 130 below the connection wire 151 is provided with a hollow area 132 at the same time. Since the line impedance is determined by the width of the wire and the height of the reference plane, the width of the connection wire 151 is set to be the same as the width of the pad 121, so that the impedance of the connection wire 151 and the impedance of the pad 121 are consistent as much as possible. At least one inner layer 130 below the connection wire 151 is hollow processed, so that at least one hollow area 132 exposes the reference layer 131 below according to the actual height adjustment, thereby increasing the height of the connection wire 151 to the actual reference layer 131. That is, by synchronously adjusting the width and the reference height of the connection wire 151, on the one hand, the impedance of the connection wire 151 matches the impedance of the pad 121, and on the other hand, the height difference between the distance of the connection wire 151 to the reference layer 131 and other parts to the reference layer 131 is minimized, thereby ensuring the impedance continuity of the entire fan-out wire 150, reducing the impedance discontinuity and inconsistency, which can effectively reduce signal reflection and improve signal quality.
[0027] It should be noted that in the entire wire path, if the impedance difference of different parts is large, it will cause signal reflection and distortion. In the present application, the fan-out wire 150 has multiple wires, and the wire between the pad 121 and the opening of the via hole 140 is the connection wire 151.
[0028] Specifically, the impedance calculation formula is as follows:
[0029]
[0030] wherein, (epsilon): dielectric constant of the substrate material; h: height of the signal from the reference layer 131; w: line width; t: thickness of the trace.
[0031] From the above impedance calculation formula, since the fan-out portion of the trace needs to be consistent with the impedance of the overall network, the impedance is fixed, and since the spacing between layers is inconsistent, h will change, and t will be inconsistent, that is, the width of the fan-out trace ≠ the width of the pad ≠ the width of the via. The inconsistency of these widths will cause discontinuity of impedance, which will cause signal reflection during signal transmission.
[0032] According to the signal impedance calculation formula, the line impedance on the same circuit board 100 is determined by the trace width and the height of the reference plane, that is, under the same reference plane, the wider the trace, the smaller the impedance.
[0033] The application adjusts the width of the connection trace 151 between the pad 121 and the opening of the via 140 to be the width of the pad 121, and hollows out at least one layer of the inner layer 130 below the connection trace 151. This changes the reference plane of the connection trace 151, so that it no longer refers to the immediately adjacent reference layer 131, but refers to the next lower reference layer 131, or the reference layer 131 below. In this way, the distance from the connection trace 151 to the reference layer 131 can be made as close as possible to the distance from the other parts of the trace to the reference layer 131, thereby reducing the impedance difference. This helps to maintain the impedance continuity of the entire trace, thereby reducing signal reflection and improving signal quality.
[0034] That is, by setting the number of hollowed-out areas 132, the height of the connection trace 151 to the actual reference layer 131 can be controlled by different numbers of hollowed-out areas 132, so that the spacing between the connection trace 151 and the actual reference layer 131 is close to the spacing between the other parts of the fan-out trace 150 and the reference layer 131. This helps to maintain the impedance continuity of the entire trace, thereby reducing signal reflection and improving signal quality.
[0035] Further, the connection trace 151 includes a first end 152 and a second end 153, the first end 152 is connected to the pad 121, and the second end 153 extends towards the via 140, the first end 152 covers the pad 121, and the second end 153 covers the opening of the via 140.
[0036] The first end 152 of the connection trace 151 covering the pad 121 is conducive to impedance matching between the connection trace 151 and the pad 121, and increases the contact area of the connection trace 151 and the pad 121, thereby enhancing the stability of the connection between the connection trace 151 and the pad 121, so that the connection trace 151 is not easily detached from the pad 121.
[0037] The second end 153 of the connection trace 151 covering the opening of the via 140 is conducive to impedance matching between the connection trace 151 and the via 140, which can reduce the impedance change when transitioning from the trace to the via 140, thereby reducing signal reflection. By covering the first end 152 and the second end 153 of the connection trace 151 with the pad 121 and the opening of the via 140 respectively, the signal transmission between the pad 121, the trace and the via 140 is smoother, thereby improving the stability of signal transmission.
[0038] Further, the area of the first end 152 is equal to the area of the pad 121, and the shape of the first end 152 is the same as the shape of the pad 121.
[0039] When the area of the first end 152 of the connection trace 151 is equal to the area of the pad 121 and the shape is the same, impedance matching between the connection trace 151 and the pad 121 can be ensured, which can reduce the impedance change when transitioning from the pad 121 to the trace, thereby reducing signal reflection and distortion. In addition, the first end 152 of the connection trace 151 serves as the connection end with the pad 121, and under the same area and shape, the mechanical strength of the connection point is higher, and the connection failure caused by stress is reduced.
[0040] Further, the area of the first end 152 is equal to the area of the pad 121, and the shape of the first end 152 is the same as the shape of the pad 121.
[0041] In the embodiment, the area of the hollow region 132 is greater than or equal to the area of the connection trace 151, so that the connection trace 151 is exposed to the reference layer 131 of the next layer by the hollow region 132, and the connection trace 151 directly corresponds to the reference layer 131 of the next layer. This can make the reference plane of the connection trace 151 in this area more consistent, thereby reducing the discontinuity of impedance caused by the change of the reference plane. It is conducive to reducing signal reflection caused by the change of the reference plane, and improving the quality and stability of the signal.
[0042] Figure 3 The second embodiment of the circuit board is a partial top view of the top layer of the circuit board, as shown in Figure 3As shown, the orthographic projection area of the cutout area 132 on the bottom layer 110 is greater than or equal to the total orthographic projection area of the connecting trace 151, pad 121 and via 140 on the bottom layer 110, and the shapes of the two ends of the cutout area 132 are respectively matched with the opening shapes of the pad 121 and via 140.
[0043] The difference between this embodiment and the previous embodiment is that the area of the cutout region 132 is further enlarged, making the area of the cutout region 132 larger than the total area of the connection trace 151, the pad 121 and the via 140. Moreover, the shape of the cutout region 132 can match the overall shape of the opening of the connection trace 151, the pad 121 and the via 140. By utilizing the cutout region 132 on the reference layer 131 adjacent to the connection trace 151, the connection trace 151, the pad 121 and the via 140 are completely exposed to the reference layer 131 of the next layer below the corresponding position.
[0044] In the circuit board 100, a region 132 is cut out at the location of the connection trace 151 on the reference layer 131, and the orthographic projection area of the cut-out region 132 on the bottom layer 110 is greater than or equal to the total orthographic projection area of the connection trace 151, the pad 121, and the via 140 on the bottom layer 110. By cutting out the region 132 on the reference layer 131, the reference plane of the connection trace 151, the pad 121, and the via 140 can be changed. If the orthographic projection area of the cut-out region 132 is greater than or equal to the total orthographic projection area of the via 140, the connection trace 151, and the pad 121 on the bottom layer 110, the reference plane of the via 140, the connection trace 151, and the pad 121 in this region can be more consistent, thereby reducing impedance discontinuities caused by changes in the reference plane. This can significantly reduce signal reflections caused by changes in the reference plane, which helps to improve signal quality and stability.
[0045] Furthermore, the extension direction of the cutout area 132 is the same as the extension direction of the connecting trace 151, and the length of the cutout area 132 is greater than or equal to the length of the connecting trace 151. When the length of the cutout area 132 matches the length of the connecting trace 151, the consistency of the signal path can be better maintained. This design can effectively reduce impedance discontinuities caused by path changes, thereby reducing signal reflection.
[0046] Figure 4 This is a partial top view of the top layer in the third embodiment of the circuit board of this application. Figure 4 The illustrated embodiment is based on Figure 3 Improvements, such as Figure 4 As shown, the length of the cutout area 132 is greater than or equal to the total length of the pad 121, the connecting trace 151, and the via 140 in the horizontal direction.
[0047] The difference between this embodiment and the previous embodiment is that the length of the hollowed-out area 132 is improved. When the length of the hollowed-out area 132 matches the total length of the pad 121, the connection trace 151 and the via 140 in the horizontal direction, and the extension direction of the hollowed-out area 132 is consistent with the connection direction of the pad 121, the connection trace 151 and the via 140, the hollowed-out area 132 makes the pad 121, the connection trace 151 and the via 140 as a whole face the reference layer 131 of the next layer. In this way, the consistency of the signal path can be better maintained, which helps to reduce the impedance discontinuity caused by the change of the path, thereby reducing signal reflection. By further increasing the length of the hollowed-out area 132, the crosstalk between different signals can also be reduced, thereby improving the performance of the overall circuit.
[0048] Figure 5 Figure 6 is a schematic view of a fourth embodiment of a circuit board of the present application, showing a partial top view of the top layer of the circuit board. Figure 5 As shown in Figure 6, the hollowed-out area 132 includes a first hole end 133 and a second hole end 134. The first hole end 133 is arranged at the position corresponding to the pad 121, and the second hole end 134 is arranged at the position corresponding to the opening of the via 140. The shape of the first hole end 133 is the same as that of the pad 121, and the area of the first hole end 133 is greater than or equal to that of the pad 121. The shape of the second hole end 134 is the same as that of the opening of the via 140, and the area of the second hole end 134 is greater than the opening area of the via 140.
[0049] The shape of the hollowed-out area 132 is improved in this embodiment. The shapes of the first hole end 133 corresponding to the position of the pad 121 and the second hole end 134 corresponding to the opening position of the via 140 are matched with the shapes of the pad 121 and the opening of the via 140 respectively. The area of the first hole end 133 is greater than or equal to that of the pad 121, and the area of the second hole end 134 is greater than or equal to the opening area of the via 140.
[0050] In this way, the end of the connection trace 151 connected to the pad 121 and the pad 121, and the end of the connection trace 151 extending to the via 140 and the via 140 are completely exposed to the reference layer 131 of the next layer through the hollowed-out area 132. The connection trace 151 is completely matched to the reference layer 131 of the next layer, so that the distance from the connection trace 151 to the reference layer 131 is as close as possible to the distance from other parts of the trace to the reference layer 131, thereby reducing the difference in impedance. This helps to maintain the impedance continuity of the entire trace, thereby reducing signal reflection and improving signal quality.
[0051] Figure 6 Figure 7 is a schematic view of an embodiment of a storage module product of the present application, showing a partial top view of the top layer of the circuit board. Figure 6As shown, the embodiment of the present application also discloses a storage module product 10, comprising a chip 200, the storage module product 10 further comprises the circuit board 100 described above, and the chip 200 is arranged on the circuit board 100. The circuit board 100 and the chip 200 can be connected through the bonding pad 121, a lead or a flip-chip 200 (Flip-Chip) and the like, and the circuit board 100 can ensure that the signals between the chip 200 and the external circuit can be transmitted efficiently and reliably; and the circuit board 100 not only provides physical support for the chip 200, so that the chip 200 can work stably under various environmental conditions and reduce damage caused by external factors such as vibration and impact; but also can protect the chip 200 from the influence of external environmental water vapor and dust to a certain extent, and prolong the service life of the chip 200.
[0052] However, the circuit board 100 of the storage module product 10 is inconsistent in the spacing between layers, and the width of the fan-out trace is inconsistent with the width of the bonding pad 121 and the via 140, which will cause discontinuity of impedance, and in the process of signal transmission, the signal will be reflected back and forth between the via 140 and the bonding pad 121, affecting the normal work of the storage module product 10.
[0053] Based on the above problems, the circuit board 100 of the storage module product 10 is improved in the present application, and a section of the connection trace 151 between the bonding pad 121 and the via 140 in the fan-out trace 150 of the circuit board 100 and the inner layer 130 below the connection trace 151 are improved, so that the width of the connection trace 151 is equal to the width of the bonding pad 121, and at least one layer of the inner layer 130 below the connection trace 151 is provided with a hollow area 132, so that the connection trace 151 corresponds to a reference layer 131 of a lower layer. Since the line impedance is determined by the width of the trace and the height of the reference plane, the width of the connection trace 151 is set to be the same as the width of the bonding pad 121, so that the impedance of the connection trace 151 and the impedance of the bonding pad 121 can be as consistent as possible. At least one layer of the inner layer 130 below the connection trace 151 is hollowed out, so that at least one hollow area 132 exposes the reference layer 131 below according to the actual height adjustment, thereby increasing the height of the connection trace 151 to the actual reference layer 131. That is, the width and reference height of the connection trace 151 are adjusted synchronously in the present application, on the one hand, the impedance of the connection trace 151 matches the impedance of the bonding pad 121, and on the other hand, the distance between the connection trace 151 and the reference layer 131 is minimized, and the height difference between other parts and the reference layer 131 is minimized, so as to ensure the impedance continuity of the entire fan-out trace 150, reduce the problem of impedance discontinuity and impedance inconsistency, thereby effectively reducing signal reflection, improving signal quality, and further improving the quality of the storage module product 10.
[0054] It should be noted that the inventive concept of the present application can form very many embodiments, but the length of the application file is limited and cannot list them one by one, so the above described embodiments or technical features can be combined to form new embodiments without conflict, and the combination of each embodiment or technical feature will enhance the original technical effect.
[0055] The above is a further detailed description of the present application in combination with specific optional embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For ordinary skilled persons in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as belonging to the protection scope of the present application.
Claims
1. A circuit board comprising a bottom layer, a top layer, and an inner layer, the inner layer being located between the top layer and the bottom layer, the top layer being provided with a land, a via being provided through the top layer, the bottom layer, and the inner layer, characterized in that, The circuit board further comprises a plurality of fan-out wires, each of the fan-out wires comprising a connecting wire, the connecting wire being located between the opening of the via close to the pad and the pad, and one end of the connecting wire being connected to the pad and the other end of the connecting wire extending to the via; the width of the connecting wire is the same as the width of the pad. The inner layer is a multi-layer laminated structure, and at least one of the inner layers is provided with a hollow region corresponding to the position of the connecting wire, and the hollow region is used to expose the reference layer below the position corresponding to the connecting wire.
2. The circuit board of claim 1, wherein, The connecting wire comprises a first end and a second end, the first end is connected to the pad, and the second end extends towards the via, the first end covers the pad, and the second end covers the opening of the via.
3. The circuit board of claim 2, wherein, The area of the first end is equal to the area of the pad, and the shape of the first end is the same as the shape of the pad.
4. The circuit board of claim 3, wherein, The area of the first end is equal to the area of the pad, and the shape of the first end is the same as the shape of the pad.
5. The circuit board of claim 3, wherein, The area of the first end is equal to the area of the pad, and the shape of the first end is the same as the shape of the pad.
6. The circuit board of claim 3, wherein, The area of the first end is equal to the area of the pad, and the shape of the first end is the same as the shape of the pad.
7. The circuit board of claim 6, wherein, The extension direction of the hollow region is the same as the extension track of the connecting wire, and the length of the hollow region is equal to the length of the connecting wire.
8. The circuit board of claim 7, wherein, The length of the hollow region is greater than or equal to the total length of the pad, the connecting wire and the via in the horizontal direction.
9. The circuit board of claim 8, wherein, The hollow region comprises a first hole end and a second hole end, the first hole end is arranged corresponding to the position of the pad, and the second hole end is arranged corresponding to the position of the via, the shape of the first hole end is the same as the shape of the pad, and the shape of the second hole end is the same as the shape of the opening of the via.
10. A memory module product comprising a chip, characterized by The area of the first hole end is greater than or equal to the area of the pad; and the area of the second hole end is greater than the opening area of the via. The storage module product further comprises the circuit board according to any one of claims 1 to 9, and the chip is arranged on the circuit board.