Storage and control blade based on FT2000+ / 64

Abstract

The utility model discloses a storage control blade based on FT2000 + / 64, which comprises a processor unit, and the processor unit is electrically connected with a bridge piece unit, a BMC health management unit, a 10-gigabit network card unit, a gigabit network card unit, a CPLD unit, an IPMB interface unit, a clock unit, a hot plug unit and a power rail. The BMC health management unit is electrically connected with the IPMB interface unit; the clock unit and the hot plug unit are electrically connected with the power rail. A domestic Feiteng FT2000 + / 64 core processor is used as a core, front-end data comprehensive processing is completed, and operation resource support is provided for achieving functions of task management, system management, data fusion, comprehensive detection, comprehensive identification and the like. In addition, a Feiteng X100 bridge chip is adopted, and the system has the advantages of being high in universality, flexible in expansion, low in power consumption and the like. The application requirements of various markets can be met, the method can be widely applied to the market fields of desktops / portable terminals, servers, embedded type and the like, and the product competitiveness is effectively improved.

Description

Technical Field

[0001] This utility model belongs to the field of computer technology, specifically relating to a storage control blade based on FT2000+ / 64. Background Technology

[0002] With the continuous improvement of modern technology, wireless communication technology has penetrated into all walks of life, bringing significant technological innovation and improvement. Storage and control blades can provide eight 10 Gigabit Ethernet (SFP+) interfaces and Gigabit Ethernet (1000Base-T) interfaces to carry service data, as well as Gigabit Ethernet interfaces to carry management data. In recent years, the country has advocated for independent and controllable national defense, prioritizing the use of domestically produced computers in defense, industry, and other fields. Therefore, how to achieve independent controllability of storage and control blades has become a crucial issue that urgently needs to be addressed. Utility Model Content

[0003] To overcome the above-mentioned shortcomings, this utility model provides a storage control blade based on FT2000+ / 64 to solve the above problems.

[0004] To achieve the above objectives, this utility model provides the following technical solution:

[0005] A storage control blade based on FT2000+ / 64 includes a processor unit, which is electrically connected to a bridge chip unit, a BMC health management unit, a 10 Gigabit network card unit, a gigabit network card unit, a CPLD unit, an IPMB interface unit, a clock unit, a hot-swappable unit, and a power rail.

[0006] The BMC health management unit is electrically connected to the IPMB interface unit;

[0007] The clock unit and the hot-swappable unit are electrically connected to the power rail.

[0008] Preferably, the processor unit includes a Phytium FT2000+ / 64-core processor, which integrates eight DDR4 memory controllers on its own chip. The eight DDR4 memory controllers are fixed on the front and back of the core processor by means of board-mount memory chips, and the DDR4 memory chip CXDQ3BFAM-IJ-A is used as the DDR4 memory chip of the board.

[0009] Preferably, the bridge chip unit includes a Phytium X100 bridge chip, which integrates a low-power GPU and three DisplayPort 1.4 display interfaces.

[0010] Preferably, the BMC health management unit uses the AST2500 chip as the main control chip. The AST2500 chip integrates a display function and is electrically connected to a display unit, which is an LCD screen. The I2C interface and RGMII interface of the AST2500 chip are electrically connected to the processor unit.

[0011] Preferably, the 10 Gigabit network card unit uses the N10G-X8I chip, and the gigabit network card unit uses the WX1860AL4 chip.

[0012] Preferably, the CPLD unit uses the EF2L45BG256B chip.

[0013] Preferably, the IPMB interface unit includes an I2C isolation chip, the model of which is AT9511ADP.

[0014] Preferably, the clock unit includes a clock chip based on the AT8339 clock, and the hot-swappable unit includes a hot-swappable circuit based on the BT9352.

[0015] The technical effects and advantages of this utility model are as follows: It uses the domestically produced Phytium FT2000+ / 64-core processor as its core to complete front-end data processing and provide computing resources for tasks, system management, data fusion, comprehensive detection, and comprehensive identification. Furthermore, it employs the Phytium X100 bridge chip, interconnecting with the CPU via a PCIe bridge chip and PCIE switch, offering strong versatility, flexible expansion, and low power consumption. It can meet the application needs of various markets and is widely used in desktop / portable terminals, servers, embedded systems, and other market sectors, effectively improving product competitiveness. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the blade principle of this utility model;

[0017] Figure 2 This is a schematic diagram of the BMC unit of this utility model;

[0018] Figure 3 This is a functional schematic diagram of the YT8521S chip of this utility model;

[0019] Figure 4 This is a schematic diagram of the 10 Gigabit Ethernet card unit of this utility model;

[0020] Figure 5 This is a schematic diagram of the gigabit network unit of this utility model;

[0021] Figure 6 This is a schematic diagram of the clock unit of this utility model;

[0022] Figure 7This is a schematic diagram of the hot-swappable unit of this utility model;

[0023] Figure 8 This is a schematic diagram of the power rail of this utility model. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0025] Definitions of abbreviations and key terms:

[0026] BMC: Baseboard Management Controller

[0027] CPLD: Complex Programmable Logic Device

[0028] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.

[0029] IPMB: Intelligent Platform Management Bus

[0030] Referring to Figure 1, a storage control blade based on FT2000+ / 64 includes a processor unit, a bridge unit, a BMC health management unit, a 10 Gigabit network card unit, a Gigabit network card unit, a CPLD unit, an IPMB interface unit, a clock unit, a hot-swappable unit, and a power rail.

[0031] Based on the Phytium FT2000+ / 64-core processor, it completes the front-end data processing and provides computing resources to support the implementation of functions such as task management, system management, data fusion, comprehensive detection, and comprehensive identification. In addition, it can provide external interfaces such as PCIE, DDR4, and debug serial port.

[0032] The Phytium FT2000+ / 64-core processor can provide two PCIe x16 slots and one PCIe x1 slot. Each PCIe x16 slot can be split into two PCIe x8 slots, supporting rotation.

[0033] The first PCIe x8 port is used to connect to a 10GbE network controller chip, which is used to expand to 8 10G SFI interfaces;

[0034] The second PCIe x8 interface is used to connect to the IO expansion chip, which is used to expand interfaces such as USB, SATA, PCIe, and Gigabit Ethernet. The PCIe interface pulled out by the IO expansion chip is used to connect to the Gigabit Ethernet controller WX1860AL4, expanding two 1000Base-T ports, which are connected to the VPX connector.

[0035] Two PCIe x8 interfaces are connected to the VPX connector, and the interfaces can be expanded via the rear panel.

[0036] One PCIe x1 signal is used to connect to the BMC chip AST2500, and the VGA is used to connect to the front panel.

[0037] The module uses the AST2500 as the management controller (BMC), which outputs a VGA signal and connects to the front panel and VPX connector via a VGA switching chip. It monitors and collects board-level temperature, voltage, and current signals through sensors, analyzes position identification encoding information, and is responsible for monitoring system power-on and reset. It also works with the CPLD chip EF2L45BG256B to complete the overall board power timing management.

[0038] The slot number signal on the blade is uniformly pulled up. Valid slot number information needs to be pulled down via the baseboard. The BMC obtains the slot number information through GPIO. The chassis number and rack number are sent to the Phytium 2000+ via serial port through the BMC chip.

[0039] The board has reserved LED indicators and test points for various power levels or chips. For CPLD or FPGA chips, a JTAG programming interface is provided for easy debugging and maintenance later.

[0040] Furthermore, the FT2000+ / 64 processor integrates eight DDR4 memory controllers: MC0, MC1, MC2, MC3, MC4, MC5, MC6, and MC7. These eight DDR4 memory controllers are mounted on both sides of the processor core using a board-mount memory chip configuration. This achieves the required 32GB memory capacity through eight channels, each with 4GB of memory mounted on both sides. The DDR4 memory chip, CXDQ3BFAM-IJ-A, is an 8Gbit memory chip from Changxin. Since each channel requires 4GB of capacity, five memory chips (including one ECC chip) are needed per channel. During DDR4 memory routing, the 64-bit data lines are divided into eight groups, using a point-to-point topology with symmetrical placement on both sides. The 64-bit data lines are routed to equal length in each group, while the address and control lines use a fly-by topology.

[0041] Specifically, the bridge chip unit mainly uses the Phytium X100 bridge chip, which integrates a low-power GPU. Graphics display can be achieved through external LPDDR4. The Phytium X100 bridge chip has one DP channel, one of which is led out to VGA through the DP to VGA chip CS5233AN and extended to the front panel and VPX connector through a switching chip. The other DP channel is connected to the VPX connector. These two signals are reserved only. The system does not support the simultaneous use of two display chips. The Phytium X100 bridge chip integrates three DisplayPort 1.4 display interfaces, with two supporting a maximum resolution of 3840x2160@60Hz and one supporting a maximum resolution of 1920x1080@60Hz. The upstream of the Phytium X100 bridge chip supports 16 lanes of PCIe 3.0 for CPU interconnection, and the downstream supports up to 8 lanes of PCIe 3.0 transmission. Simultaneously, the Phytium X100 bridge chip has built-in SATA and USB controllers, supporting up to eight USB 3.1 Gen1 expansion interfaces and four SATA 3.0 interfaces, providing excellent I / O expansion capabilities. The blade's interface units (VGA, USB, GbE, SATA, etc.) can all be implemented through the PCIe bridge device, achieving communication with the CPU through the PCIe bridge chip and PCIe switch interconnection. It features strong versatility, flexible expansion, and low power consumption. It can meet the application needs of various markets and is widely used in desktop / portable terminals, servers, embedded systems, and other market fields.

[0042] Specifically, the BMC health management unit uses the AST2500 chip as the main control chip. The AST2500 chip integrates display functionality and is electrically connected to a display unit (LCD). The I2C and RGMII interfaces of the AST2500 chip are electrically connected to the processor unit. It can monitor the main module's voltage and temperature, perform remote power-off and restart operations, and its message protocol conforms to the IPMI standard. It provides two I2C interfaces, used as IPMB-A and IPMB-B buses respectively. Combined with onboard sensors, it can detect the main module's voltage, temperature, and other health status. It supports module self-testing and fault diagnosis functions, provides status and fault alarm indications, and supports unit log management, KVM over IP, time synchronization, and user management functions; it also supports iKVM functionality.

[0043] The AST2500, as the core control chip of the BMC health management unit, adopts the ARM9 architecture, 400MHz core frequency, 16-bit DDR4 memory controller, and has multiple gigabit Ethernet, I2C, SPI, VGA and other interfaces. The rich interface types can facilitate communication with various functional units of the system and are compatible with various sensors.

[0044] To facilitate remote management and monitoring of the compute blades without requiring users to operate them in front of the machine, the AST2500's web server management interface supports KVM over IP functionality.

[0045] The blade display function is integrated into the AST2500 chip of the BMC health management unit. The built-in integrated display function can be achieved through the BMC. (See attached document for details.) Figure 2 As shown.

[0046] The BMC unit has two RGMII interfaces. One of these RGMII interfaces is converted to 1000Base-T via a YT8521S converter and connected to the VPX connector. Remote customers can monitor the hardware status information and power on / off operations of the local module, and it supports KVM over IP. Simultaneously, the BMC unit can also communicate with the CPU via UART to obtain the CPU's clock speed, model, number of cores, and other operating status information, and supports IPMI custom command queries.

[0047] The main technical specifications of YT8521S are as follows:

[0048] Supports 802.3, 802.3u, and 802.3ab protocols;

[0049] Supports RGMII / SGMII MAC interfaces;

[0050] Supports SGMII / 1000BASE-X interface;

[0051] Supports RGMII to SGMII and Fiber to UTP conversion modes;

[0052] Supports automatic UTP / Fiber detection;

[0053] Supports 18KB jumbo frames (100M / 1000M) and 10KB jumbo frames (10M);

[0054] Supports Wake-on-LAN (WoL);

[0055] Typical power consumption: 0.75W;

[0056] The functional block diagram of the YT8521S chip can be found in the attached diagram. Figure 3 As shown.

[0057] To monitor system temperature, a digital temperature sensor was incorporated, capable of monitoring a temperature range of -55 to +125°C with an accuracy of ±2°C. The CPU temperature was acquired and transmitted to the BMC unit via I2C.

[0058] To monitor the system's operating status, its built-in ADC channel is used to monitor the voltage and current status at various levels, including 5V, 3.3V, 2.5V, 1.2V, 1.1V, 1.0V, and 12V. The system can read its output data via the I2C interface. If an abnormality occurs, an alarm and a reset interrupt signal are generated.

[0059] For details, please refer to the appendix. Figure 4 As shown, the 10 Gigabit Ethernet unit uses the N10G-X8I chip, independently designed by Wuxi Muchuang. It can provide eight 10GbE SFP+ interfaces. The N10G-X8I effectively balances the network load on the CPU core, improving data throughput and CPU utilization, exhibiting excellent performance in multi-CPU processor systems. This chip supports 2, 4, and 8-port 10G and 8-port 1G network applications. It is primarily used in servers, network security equipment, embedded systems, and other network application areas.

[0060] Please refer to the attached document. Figure 5As shown, the gigabit network interface card (NIC) unit uses the Netcom WX1860AL4 chip solution. The WX1860AL4 chip has two 1000Base-T ports connected to the VPX connector via a network transformer. It features four fully integrated gigabit Ethernet media access control (MAC) and physical layer (PHY) modules, and four RGMII interfaces that can be connected to external PHYs. This solution also features low power consumption and easy software adaptation. Since the technical protocol requires two 1000Base-T ports to be output later, and the WX1860 can output four MDI interfaces, two 1000Base-T ports are directly output and connected to the VPX connector via a network transformer. The front port is reserved.

[0061] Specifically, the CPLD unit uses the EF2L45BG256B chip. The CPLD unit is designed based on the EF2L45BG256B from Shanghai Anlu Information Technology Co., Ltd. The EF2L45BG256B is a SALELF 2 series FPGA product from Shanghai Anlu Information Technology, and is the second-generation product of the "Little Elf" series launched by Shanghai Anlu Information Technology. It has abundant logic resources, supports multiple I / O level standards, and embeds block static random access memory, digital signal processing modules, and phase-locked loop resources. In addition, it has embedded Flash resources, making it a non-volatile FPGA product with low power consumption, instant startup, low cost, high security, small product size, and convenient and flexible use. The EF2L45BG256B has 6 banks, a maximum of 207 I / Os, and integrates 4Mb of Flash, with 4480 LUTs and 4480 DFFs.

[0062] The EF2L45BG256B can be used for power-on timing control of various power supplies for the blade processor, and is responsible for monitoring system power-on and reset. It is also responsible for level conversion of CPU processor GPIO signals, UART signals, and LPC signals.

[0063] Specifically, this module provides at least 4 USB ports: 2 USB 3.0 ports on the front panel, 4 USB 2.0 ports and 2 USB 3.0 ports from the VPX. The USB ports are brought out from the X100 I / O expansion chip. In the actual design, 6 USB ports are provided: 2 USB 3.0 ports on the front panel, 4 USB 2.0 ports and 2 USB 3.0 ports from the VPX. It also provides at least 3 SATA ports: 1 SATA port from the mSATA connector and 2 SATA ports from the VPX. This blade uses the X100 controller to expand the SATA ports, providing 3 SATA ports.

[0064] This module provides two PCI-E 3.0x8 expansion buses, with the processor's PCIe bus being used for direct output.

[0065] It also features an IPMB interface unit, where sensors on the module monitor in real time information such as temperature, voltage, fan operating status, and power supply of each core component. The BMC chip acquires the data from the sensors, encapsulates it using the standard IPMI protocol, and sends it to the intelligent platform management bus via the physical layer's I2C protocol. The I2C isolation chip is implemented using the domestically produced AT9511ADP from Wuhan Xinjing.

[0066] For specific details, please refer to the attached WX1860 time synchronization design block diagram. Figure 5 As shown, the clock unit includes a clock chip based on the AT8339 clock and the IEEE 1588V2 protocol. The clock chip has two implementation methods: time greater than a second is implemented using the AT8339 from Wuhan Xinjing Technology, and time less than a second is obtained through the IEEE 1588V2 protocol. It is connected to the CPU via the I2C bus and can continuously send clock and calendar information to the CPU.

[0067] IEEE 1588 is a Precision Time Protocol (PTP) used to synchronize clocks in computer networks. In local area networks (LANs), it can control clock accuracy within the sub-microsecond range, making it suitable for measurement and control systems. Its basic working principle involves master and slave nodes sending synchronization data frames, recording the transmission and reception times of the data frames, and adding this time information to the data frames. Slave nodes obtain this time information, calculate the time deviation between their local clock and the master clock, and the transmission delay between network nodes, correcting their local clocks to synchronize with the master clock. A PTP network can only have one master clock. The PTP protocol mainly consists of two parts to implement clock synchronization:

[0068] 1. Establishing a synchronization system: The protocol uses the Best Master Clock Algorithm (BMCA) to select a master clock, establish a master-slave topology, and thus establish a synchronization system throughout the entire PTP network.

[0069] 2. Synchronize local clock: The protocol uses the Local Clock Synchronization Algorithm (LCS), which calculates the time deviation between the local clock of each slave node and the master clock through the exchange of PTP data packets between the master and slave nodes in the network, and adjusts the local clock to synchronize with the master clock.

[0070] The IEEE 1588 V2 protocol requires hardware support. The WX1860 network card chip supports the 1588 protocol and can achieve more accurate network time synchronization on this basis.

[0071] The hot-swap unit comprises a hot-swap circuit based on the BT9352. The hot-swap unit utilizes the domestically produced BT9352, with a soft-start time of approximately 2ms to suppress inrush current during blade power-up. The BT9352 employs an external N-channel MOSFET to generate a near-ideal diode. This replaces a high-power Schottky diode and associated heatsink, saving power and board space. The ideal diode function enables low-loss power holding applications. Fast turn-on reduces load voltage drop during power switching. A fast turn-off function minimizes reverse current in case of input power failure or short circuit. The controller can be powered from 2.9V to 18V. An external power supply is required at low voltages. The power path is disabled under under- or over-voltage conditions. This controller also features an open-circuit MOSFET detection circuit that issues an indication signal if the voltage drop across the MOSFET is excessive during the on-state. See Appendix [link to Appendix]. Figure 7 As shown.

[0072] The power rails, based on the VPX general architecture and the motherboard's own power requirements, convert the single-board 12V power bus into the voltage required by each chip through multiple POLs (Points of Load). The +3.3V_AUX power supply is used to power the blade BMC, CPLD, and some monitoring circuits, and must be powered on before all other voltages. The power architecture can be found in the attached diagram. Figure 8 As shown.

[0073] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A storage and control blade based on FT2000+ / 64, characterized in that: include: The processor unit is electrically connected to a bridge chip unit, a BMC health management unit, a 10 Gigabit network card unit, a gigabit network card unit, a CPLD unit, an IPMB interface unit, a clock unit, a hot-swappable unit, and a power rail. The BMC health management unit is electrically connected to the IPMB interface unit; The clock unit and the hot-swappable unit are electrically connected to the power rail.

2. The storage and control blade based on FT2000+ / 64 according to claim 1, characterized in that: The processor unit includes a Phytium FT2000+ / 64-core processor, which integrates eight DDR4 memory controllers. The eight DDR4 memory controllers are fixed on the front and back of the core processor by means of board-mount memory chips. The DDR4 memory chip CXDQ3BFAM-IJ-A is used as the DDR4 memory chip of the board.

3. The storage and control blade based on FT2000+ / 64 according to claim 1, characterized in that: The bridge chip unit includes the Phytium X100 bridge chip, which integrates a low-power GPU and three DisplayPort 1.4 display interfaces.

4. The storage and control blade based on FT2000+ / 64 according to claim 1, characterized in that: The BMC health management unit uses the AST2500 chip as the main control chip. The AST2500 chip integrates display functions and is electrically connected to the display unit, which is an LCD screen. The I2C interface and RGMII interface of the AST2500 chip are electrically connected to the processor unit.

5. A storage control blade based on FT2000+ / 64 according to claim 1, characterized in that: The 10 Gigabit network card unit uses the N10G-X8I chip, and the gigabit network card unit uses the WX1860AL4 chip.

6. The storage and control blade based on FT2000+ / 64 according to claim 1, characterized in that: The CPLD unit uses the EF2L45BG256B chip.

7. The storage and control blade based on FT2000+ / 64 according to claim 1, characterized in that: The IPMB interface unit includes an I2C isolation chip, model AT9511ADP.

8. A storage control blade based on FT2000+ / 64 according to claim 1, characterized in that: The clock unit includes a clock chip based on the AT8339 clock, and the hot-swappable unit includes a hot-swappable circuit based on the BT9352.

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