Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate layer, a signal line, a first insulating layer, a patch cord, a second insulating layer, a trepanning structure, a bridging layer and a GOA circuit. The signal line extends along a first direction, the patch cord extends along a second direction, the trepanning structure comprises an outer hole, a first sub-hole and a second sub-hole, the outer hole extends from the top of the second insulating layer to the substrate layer, the first sub-hole and the second sub-hole are arranged at an interval and are communicated with the bottom of the outer hole, and the bottom of the first sub-hole is exposed out of part of the surface of the signal line; the bottom of the second sub-hole exposes part of the surface of the patch cord. In the second direction, the distance between at least one of the edge of the outer hole, the edge of the first sub-hole and the edge of the second sub-hole and the starting end of the patch cord is larger than or equal to 2 micrometers, and the starting end is the end, away from the display area, of the patch cord. The patch cord is electrically connected with the signal line through the bridging layer. The GOA circuit is electrically connected with the patch cord.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] A pressure cooker test (PCT) evaluates the sealing performance of a display panel by a high-temperature, high-pressure and high-humidity environment, so as to prevent the problem of water vapor intrusion into the box of the display panel in an extremely harsh environment.

[0003] GOA is the abbreviation of Gate Driven on Array, which is a technology of integrating gate driving on an array substrate, and is used for realizing the function of row-by-row scanning driving of a display panel. The GOA circuit is arranged in a non-display area of the display panel and is electrically connected with a signal line through a transition line. In the related art, during the PCT test, water vapor may intrude into the box along the transition line, thereby causing the PCT performance of the display panel to be substandard.

[0004] It should be noted that the information of the background art part of the above-mentioned utility model is only used to strengthen the understanding of the background of the present application, and therefore can include information which does not constitute the prior art known to those of ordinary skill in the art. CONTENT OF THE UTILITY MODEL

[0005] The embodiments of the present application provide an array substrate, a display panel and a display device, which can at least delay the time of water vapor intrusion into the box and improve the PCT performance of the display panel.

[0006] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0007] The first aspect of the embodiments of the present application provides an array substrate, comprising: a display area and a non-display area arranged on at least one side of the display area, and the array substrate comprises:

[0008] a substrate layer;

[0009] a signal line arranged on one side of the substrate layer and located in the non-display area and extending along a first direction;

[0010] a first insulating layer covering the signal line;

[0011] a transition line arranged on a side of the first insulating layer away from the substrate layer and located in the non-display area and extending along a second direction, and the second direction intersects the first direction;

[0012] a second insulating layer covering the transition line;

[0013] The sleeve hole structure comprises an outer hole, a first sub-hole and a second sub-hole, the outer hole extends from the top of the second insulating layer to the substrate layer, the first sub-hole and the second sub-hole are arranged in a spaced manner and communicate with the bottom of the outer hole, the bottom of the first sub-hole exposes part of the surface of the signal line, and the bottom of the second sub-hole exposes part of the surface of the transfer line;

[0014] At least one of the edges of the outer hole, the edges of the first sub-hole and the edges of the second sub-hole and the starting end of the transfer line in the second direction are spaced apart by greater than or equal to 2 μm, and the starting end is the end of the transfer line away from the display area;

[0015] The jumper layer covers the outer hole, the first sub-hole and the second sub-hole, and the transfer line is electrically connected to the signal line through the jumper layer;

[0016] The GOA circuit is arranged on one side of the substrate layer between the signal line and the display area and is electrically connected to the transfer line.

[0017] Optionally, the second insulating layer comprises a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer arranged in sequence, the first sub-insulating layer comprises a first blocking portion, the second sub-insulating layer comprises a second blocking portion, and the third sub-insulating layer comprises a third blocking portion, the first blocking portion, the second blocking portion and the third blocking portion are arranged in sequence, and the third blocking portion covers the side surface of the first blocking portion;

[0018] The outer hole is a plurality of outer holes, and the plurality of outer holes comprise:

[0019] The first outer hole extends from the top of the third sub-insulating layer to the substrate layer, and the first sub-hole communicates with the bottom of the first outer hole;

[0020] The second outer hole extends from the top of the third sub-insulating layer to the substrate layer, and the second sub-hole communicates with the bottom of the second outer hole;

[0021] In the second direction, the starting end of the transfer line and the first sub-hole are provided with the first blocking portion and the third blocking portion covering the side surface of the first blocking portion.

[0022] Optionally, the second insulating layer comprises a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer arranged in sequence, and the third sub-insulating layer comprises a fourth blocking portion;

[0023] The outer hole is one, and the first sub-hole and the second sub-hole communicate with the bottom of the outer hole;

[0024] In the second direction, the fourth blocking portion is arranged between the starting end of the transfer line and the first sub-hole.

[0025] Optionally, the first sub-insulating layer and the third sub-insulating layer are inorganic insulating layers, and the second sub-insulating layer is an organic insulating layer.

[0026] Optionally, in the second direction, the starting end is located between the first sub-hole and the second sub-hole, a first spacing is provided between an edge of the first sub-hole close to the display area and the starting end, a second spacing is provided between an edge of the second sub-hole away from the display area and the starting end, a third spacing is provided between an edge of the outer hole away from the display area and an edge of the first sub-hole away from the display area, and a fourth spacing is provided between an edge of the outer hole close to the display area and an edge of the second sub-hole close to the display area.

[0027] At least one of the first spacing, the second spacing, the third spacing, and the fourth spacing is greater than or equal to 2 μm.

[0028] Optionally, at least one of the first spacing, the second spacing, the third spacing, and the fourth spacing is greater than or equal to 2.5 μm.

[0029] Optionally, at least one of the following conditions is met:

[0030] The ratio between the third spacing and the first spacing ranges from 0.6 to 0.9.

[0031] The ratio between the fourth spacing and the second spacing ranges from 0.6 to 0.9.

[0032] The ratio between the sum of the first spacing and the third spacing and the sum of the second spacing and the fourth spacing ranges from 0.6 to 0.9.

[0033] Optionally, the ratio between the fourth spacing and the second spacing ranges from 0.5 to 1.0.

[0034] Optionally, at least one of the following conditions is met:

[0035] In the second direction, the width of the first sub-hole ranges from 3 μm to 6 μm.

[0036] In the second direction, the width of the second sub-hole ranges from 3 μm to 6 μm.

[0037] In the second direction, the width of the outer hole ranges from 5 μm to 20 μm.

[0038] Optionally, a side wall of the outer hole has a smaller inclination angle than a side wall of the first sub-hole, and / or a side wall of the outer hole has a smaller inclination angle than a side wall of the second sub-hole.

[0039] Optionally, the display panel further comprises:

[0040] a first metal layer disposed between the substrate layer and the first insulating layer, the signal line being located in the first metal layer;

[0041] a second metal layer disposed between the first insulating layer and the second insulating layer, the transfer line being located in the second metal layer;

[0042] In a direction perpendicular to the substrate layer, a depth of the first sub-hole is greater than a depth of the second sub-hole.

[0043] Optionally, the signal line comprises a clock signal line.

[0044] Optionally, the display panel further comprises:

[0045] a transfer hole extending from a top of the second insulating layer to the substrate layer and exposing a part of a surface of the transfer line, the transfer line being electrically connected to the GOA circuit through the transfer hole.

[0046] A second aspect of the embodiments of the present application provides a display panel, comprising: the array substrate according to any one of the first aspect, a color film substrate disposed in a lute manner with the array substrate, and a liquid crystal layer located between the array substrate and the color film substrate.

[0047] A third aspect of the embodiments of the present application provides a display device, comprising: the array substrate according to any one of the first aspect, or the display panel according to the second aspect.

[0048] The array substrate of the embodiment of the present application comprises a display area and a non-display area arranged at least one side of the display area. The array substrate comprises a substrate layer, a signal line, a first insulating layer, a second insulating layer, a sleeve hole structure, a bridging layer and a GOA circuit. The signal line is arranged at one side of the substrate layer, located in the non-display area and extends along a first direction. The first insulating layer covers the signal line. The jumper line is arranged at a side of the first insulating layer away from the substrate layer, located in the non-display area and extends along a second direction intersecting the first direction. The second insulating layer covers the jumper line. The sleeve hole structure comprises an outer hole, a first sub-hole and a second sub-hole, the outer hole extends from the top of the second insulating layer to the substrate layer, the first sub-hole and the second sub-hole are arranged at intervals and communicate with the bottom of the outer hole, the bottom of the first sub-hole exposes part of the surface of the signal line, and the bottom of the second sub-hole exposes part of the surface of the jumper line. In the second direction, the spacing between at least one of the edge of the outer hole, the edge of the first sub-hole and the edge of the second sub-hole and the starting end of the jumper line is greater than or equal to 2 μm, and the starting end is the end of the jumper line away from the display area. The bridging layer covers the outer hole, the first sub-hole and the second sub-hole, and the jumper line is electrically connected to the signal line through the bridging layer. The GOA circuit is arranged at one side of the substrate layer, located between the signal line and the display area and electrically connected to the jumper line.

[0049] Therefore, the present application finds that the starting end of the jumper line is the weak point of water vapor invasion, and the spacing between at least one of the edge of the outer hole, the edge of the first sub-hole and the edge of the second sub-hole and the starting end of the jumper line is greater than or equal to 2 μm, which can delay the time of water vapor invading the box along the extension direction of the jumper line to a certain extent, and subsequently help to improve the PCT performance of the display panel.

[0050] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0051] The drawings incorporated into the specification and forming part of the specification, show embodiments consistent with the present application, and together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0052] Figure 1 The connection relationship between the clock signal line and the GOA circuit is shown in the schematic diagram;

[0053] Figure 2 The planar layout schematic diagram of the array substrate of the embodiment of the present application is shown;

[0054] Figure 3A first partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0055] Figure 4 A top view of the through-hole structure in Figure 3

[0056] Figure 5 A second partial cross-sectional diagram of an array substrate of an embodiment of the present application is shown.

[0057] Figure 6 A third partial cross-sectional diagram of an array substrate of an embodiment of the present application is shown.

[0058] Figure 7 A top view of the through-hole structure in Figure 6

[0059] Figure 8 An enlarged view of the dashed box in Figure 3

[0060] Figure 9 A fourth partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0061] Figure 10 A fifth partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0062] Figure 11 A sixth partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0063] Figure 12 A seventh partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0064] Figure 13 An eighth partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0065] Figure 14 A ninth partial cross-sectional structure diagram of an array substrate of an embodiment of the present application is shown.

[0066] Figure 15 A structure diagram of a display panel of an embodiment of the present application is shown.

[0067] Figure 16 A structure block diagram of a display device of an embodiment of the present application is shown.

[0068] ​​​100 - array substrate; 101 - display area; 102 - non-display area; 1 - substrate layer; 2 - signal line; 21 - clock signal line; 3 - first insulating layer; 4 - transfer line; 41 - starting end; 5 - second insulating layer; 51 - first sub-insulating layer; 52 - second sub-insulating layer; 53 - third sub-insulating layer; 51A - first blocking part; 52A - second blocking part; 53A - third blocking part; 53B - fourth blocking part; 6 - sleeve hole structure; 61 - outer hole; 61A - first outer hole; 61B - second outer hole; 62 - first sub-hole; 63 - second sub-hole; 7 - bridging layer; 8 - GOA circuit; 9 - gate line; X - first direction; Y - second direction; Z - direction perpendicular to the substrate layer; H1 - depth of the first sub-hole; H2 - depth of the second sub-hole; D1 - first pitch; D2 - second pitch; D3 - third pitch; D4 - fourth pitch; a - side wall corner of the outer hole; b2 - side wall inclination angle of the first sub-hole; b2 - side wall inclination angle of the second sub-hole; 10 - transfer hole; 200 - display panel; 21 - color film substrate; 22 - liquid crystal layer; 23 - frame sealant; 201 - first alignment film; 202 - second alignment film; 203 - cover layer; 204 - light shielding layer; 205 - color film layer; 300 - display device. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0070] The block diagram shown in the drawings is only a functional entity, which does not necessarily correspond to a physically independent entity. That is, the functional entity can be realized in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0071] The flowchart shown in the drawings is only an exemplary description, which does not necessarily include all the contents and operations / steps, and does not necessarily be executed in the described order. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so that the actual execution order may be changed according to the actual situation.

[0072] It should also be noted that the terms "first", "second", and the like, in the description and in the claims of the present application, as well as in the above Figure description, are used for distinguishing between similar objects and are not necessarily used to describe a specific sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of orderly execution or performance with variations of ordering of the steps or operational orders in the description or claims, outside of those specifically described.

[0073] As used herein, "about", "substantially", "approximately", or "near" include the value being discussed and the average range of acceptable deviation from the value being discussed, as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0074] As used herein, "parallel", "perpendicular", "equal" include the value being discussed and the approximate value that is near the value being discussed, within an acceptable range of deviation, as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation of, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation of, for example, within 5°. "Equal" includes absolute equality and near equality, where near equality can have an acceptable range of deviation of, for example, less than or equal to 5% of either of the two values being compared.

[0075] The scale of the drawings in the present application can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present application are only schematic diagrams, and one embodiment of the present application is not limited to the shapes or values shown in the drawings.

[0076] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integrally connected; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate parts, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0077] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0078] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0079] In this specification, "electrically connected" includes the case where components are connected through an element having some function. There is no particular limitation on the element having some function as long as electric signals can be transmitted and received between components connected. Examples of the element having some function include an electrode and a wiring as well as a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0080] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0081] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0082] A pressure cooker test (PCT) is a test for evaluating the sealing property of a display panel by a high-temperature, high-pressure, and high-humidity environment, so that the display panel is prevented from being damaged by moisture intrusion into a case in an extremely severe environment.

[0083] In the development process of display panels, compared with the improvement of product display performance, the research and improvement of PCT performance of display panels in the industry are relatively lagging behind, mainly due to the limitation of the complex film layer structure of display panels and the lack of a method for characterizing the water vapor invasion interface and traces. The early PCT test requires the display panel to meet the 24-hour test standard (i.e. in a high temperature, high pressure and high humidity environment, water vapor cannot invade the inside of the display panel within 24 hours), in recent years, due to the difficulty of some display panels to meet the standard, the test standard is gradually reduced, and even some display panels do not meet the 12-hour test standard.

[0084] Taking LCD (Liquid Crystal Display) as an example, at present, it is generally believed that the PCT performance of LCD display panel is mainly related to the material of sealant, alignment film and PVX (passivation layer) film layer. However, in the case that the process of each of the above film layers is gradually stable and common, the body of the above film layers is basically solidified, and there is almost no difference in the above film layers or materials used by different LCD display panels. Therefore, if some LCD display panels still cannot meet the PCT test standard, it may not be caused by the above film layers or materials.

[0085] The utility model person further researches and finds that according to Fick's law of diffusion theory, when mass transfer phenomenon does not rely on macroscopic mixing effect, the law describing the relationship between mass transfer flux and concentration gradient in the molecular diffusion process. The law points out that the diffusion material flow (diffusion flux, indicated by J) per unit time through the unit section area perpendicular to the diffusion direction is proportional to the concentration gradient at the section, and the mathematical expression is simplified as follows: J = akx -1 Wherein, a indicates material diffusion coefficient, k indicates proportional constant, and x indicates water vapor diffusion distance. It can be known from the above mathematical expression that with the increase of water vapor diffusion distance, the diffusion speed and concentration quality will decrease in inverse exponential form. It can be inferred that if there is a difference between the PCT performance of the existing display panel, it is proved that the water vapor does not invade from the body of the sealant, the alignment film and the PVX film layer as generally believed, and the physical gap between the film layers may cause the water vapor diffusion to intensify, thereby causing the PCT performance of the display panel to fail to meet the test standard.

[0086] At present, the PCT performance of the display panel using oxide can basically meet the 24-hour test standard, and the PCT limit test of some oxide display panels can even reach 36 hours or 48 hours. However, for the display panel using a-Si (amorphous silicon), the PCT performance of some a-Si display panels is still poor, which can only meet the 12-hour standard at most.

[0087] In view of the performance difference of different display panels in PCT test, the inventor analyzes the reasons as follows: firstly, the PCT performance difference of oxide display panel and a-Si display panel is mainly caused by the structure difference of PVX1 (first passivation layer) film layer of the two, wherein the PVX1 film layer of a-Si display panel is thinner (PVX1 covers the adapter line, and when PVX1 is thinner, physical gap is prone to be generated between the adapter line). Secondly, the PCT performance difference of display panels with or without GIMask (gate insulating layer mask) is mainly caused by the structure difference of the sleeve hole structure (for adapter signal line and adapter line) between the signal line and the adapter line, wherein the sleeve hole structure of the display panel without GIMask needs to be prepared separately. Thirdly, the PCT performance difference is also likely to occur between display panels with a-Si and without GI Mask, which is mainly caused by the structure difference or performance difference of the adapter line in each display panel (for example: structure difference of the adapter line itself or coverage difference of PVX1 to the adapter line).

[0088] It can be known from the above reason analysis that the sleeve hole structure of the signal line and the adapter line, the coverage of the PVX1 film layer to the adapter line (adapter line appearance, PVX1 material or thickness) and other factors will affect the PCT performance of the display panel. At present, it is found through research that the PCT performance of the display panel with a-Si and without GIMask is overall poor. Therefore, the PCT performance of the display panel of the above type can be improved by the embodiments of the application.

[0089] It can be known from the above introduction that the parts related to the PCT performance of the display panel that cannot meet the test standard include the signal line, the adapter line and the GOA circuit. The related principles of the GOA circuit are introduced as follows.

[0090] In a traditional active matrix display, the row scanning signal is realized by an external integrated circuit (G-COF). The GOA circuit driving is to realize the row scanning driving function by using the same process as the thin film transistor (TFT) to manufacture a row scanning driving circuit on the basis of providing several control signals by the external circuit. Therefore, the GOA driving saves the scanning driving related integrated circuit, reduces the manufacturing cost of the display panel, and is conducive to the narrow frame design.

[0091] From the driving principle of the display panel, it can be seen that the row scanning driving circuit actually corresponds to the function of a shift register. Under the action of control signals of external circuits, a shift pulse signal is generated, which not only drives the pixels of the current row to make the TFT (thin film transistor) open, but also serves as the starting signal (the first row is triggered by the frame starting signal STV) and the ending signal of the previous row. The control signals of the external circuits mainly include the frame starting signal (STV), the clock signal pair CLK and CLKB with opposite phases, the direct current voltage signal VSS (generally -8V) for driving the thin film transistor to close, and possibly the direct current voltage signal VDD.

[0092] The GOA circuit can include multiple GOA circuits, which are cascaded with each other and controlled by the voltage phase-dependent clock signal pair CLK and CLKB, the input signal (Input), the gate closing signal (VSS), the reset signal (Reset), and the output signal (Output) of the current row. Among them, the output signal of the current row (such as Output N) not only drives the pixels of the current row, but also serves as the reset signal of the previous row and the input signal of the next row. In the entire GOA driving circuit, the input signal of the first row GOA circuit is the frame starting signal STV, and the first row does not output the reset signal. The last row GOA circuit is connected with a row of redundant GOA circuits to realize the reset of the current row. In this way, under the action of external control signals, the GOA units between rows also affect each other, generate shift pulse signals, and sequentially perform row-by-row scanning.

[0093] Figure 1 The connection relationship between the clock signal line and the GOA circuit is shown in the schematic diagram.

[0094] As Figure 1As shown, taking the clock signal line 21 as an example, the GOA circuit 8 can scan the gate lines 9 in the product row by row through the alternative switching of the multi-phase clock signals (for example, clock signal pairs CLK and CLKB) which need to be transmitted to different GOA circuits 8 in a specific order. Among them, the clock signal line 21 and the GOA circuit 8 are arranged in the non-display area 102 of the display panel. Considering factors such as layout space, preparation process of the clock signal line 21 and the GOA circuit 8, the clock signal line 21 may not be directly connected with the GOA circuit 8. On this basis, in order to realize the electrical connection between the clock signal line 21 and the GOA circuit 8, the adapter line 4 can be arranged to connect the clock signal line 21 and the GOA circuit 8 respectively. In some cases, the adapter line 4 and the clock signal line 21 are arranged in different layers. In order to realize the electrical connection between the adapter line 4 and the clock signal line 21, the sleeve hole structure 6 can be arranged to connect the clock signal line 21 and the adapter line 4. In addition, the GOA circuit 8 is connected with the gate lines 9 arranged in the display area 101, and the gate driving signal is output by the GOA circuit 8 to scan each pixel unit in the pixel array of the display area 101 row by row.

[0095] On the basis of analyzing the reasons for causing the PCT performance of the display panel to fail to meet the test standard and introducing the related principles of the GOA circuit 8, the related structure and principles of the array substrate 100 contained in the display panel of the embodiment of the present application will be introduced in combination with specific drawings.

[0096] The array substrate 100 proposed in the embodiment of the present application can at least delay the time of water vapor invading the box, which is helpful to improve the PCT performance of the display panel.

[0097] Figure 2 The planar layout schematic diagram of the array substrate of the embodiment of the present application is shown; Figure 3 The first partial cross-sectional structure schematic diagram of the array substrate of the embodiment of the present application is shown; Figure 4 The top view of the sleeve hole structure in Figure 3

[0098] ​In some embodiments, the array substrate 100 comprises a display area 101 (AA area) and a non-display area 102 arranged on at least one side of the display area 101, the non-display area 102 is located in a frame area and can be divided into an upper frame, a lower frame, a left frame and a right frame, wherein the lower frame is provided with a DP (Date Pad, data trace side) and comprises a glass electrode side for binding external electronic devices (such as a driving IC and a flexible circuit board); the upper frame is provided with a DPO (Date Pad Opposite, data trace opposite side) and comprises a Gate (gate metal trace area); the left frame and / or the right frame is provided with a GOA (Gate on Array, gate driving integrated area) and the area is provided with a Gate (gate metal layer), an SD (source-drain metal layer), an Active (active layer) and a passivation layer.

[0099] In some embodiments, the array substrate 100 comprises a substrate layer 1, a signal line 2, a first insulating layer 3, a transition line 4, a second insulating layer 5, a sleeve hole structure 6, a bridging layer 7 and a GOA circuit 8. The signal line 2 is arranged on one side of the substrate layer 1 and located in the non-display area 102, extending along a first direction X. The first insulating layer 3 covers the signal line 2. The transition line 4 is arranged on a side of the first insulating layer 3 away from the substrate layer 1 and located in the non-display area 102, extending along a second direction Y intersecting the first direction X. The second insulating layer 5 covers the transition line 4. The sleeve hole structure 6 comprises an outer hole 61, a first sub-hole 62 and a second sub-hole 63, the outer hole 61 extends from the top of the second insulating layer 5 to the substrate layer 1, the first sub-hole 62 and the second sub-hole 63 are arranged at intervals and communicate with the bottom of the outer hole 61, the bottom of the first sub-hole 62 exposes part of the surface of the signal line 2, and the bottom of the second sub-hole 63 exposes part of the surface of the transition line 4. In the second direction Y, the distance between at least one of the edge of the outer hole 61, the edge of the first sub-hole 62 and the edge of the second sub-hole 63 and the starting end 41 of the transition line 4 is greater than or equal to 2 μm, and the starting end 41 is an end of the transition line 4 away from the display area 101. The bridging layer 7 covers the outer hole 61, the first sub-hole 62 and the second sub-hole 63, and the transition line 4 is electrically connected to the signal line 2 through the bridging layer 7. The GOA circuit 8 is arranged on one side of the substrate layer 1 and located between the signal line 2 and the display area 101, and is electrically connected to the transition line 4.

[0100] Next, taking the array substrate 100 of an LCD display panel as an example, the mechanism of water vapor entering the cell of the display panel is described:

[0101] In the PCT test process, water vapor first diffuses along the physical gap between the interfaces in the second insulating layer 5 (which can include multiple organic insulating layers and / or inorganic insulating layers) to the sleeve hole structure 6, accumulates in the outer hole 61, the first sub-hole 62, and the second sub-hole 63, and invades the starting end 41 of the transition line 4 through the first sub-hole 62 and / or the second sub-hole 63. Due to the etching damage of the buffer (a buffer layer located on the side of the transition line 4 close to the substrate layer 1, not shown), the side of the transition line 4 close to the substrate layer 1 is exposed, forming a water vapor invasion end, or due to the Tip (a sharp edge formed by uneven etching of the transition line 4), Undercut (the upper layer is suspended due to excessive etching of the lower layer of the transition line 4), and other defects of the multi-layer structure of the transition line 4, which are prone to occur at the starting end 41 of the transition line 4, that is, the starting end 41 is the weak point of water vapor invasion. In addition, there is a physical gap between the transition line 4 and the second insulating layer 5. Water vapor invades the starting end 41 of the transition line 4 along the physical gap between the transition line 4 and the second insulating layer 5, and invades the box along the physical gap between the transition line 4 and the second insulating layer 5. That is, the invasion path of water vapor after reaching the starting end 41 of the transition line 4 is basically consistent with the extension direction of the transition line 4. When extending to the display area 101 along the physical gap between the transition line 4 and the second insulating layer 5, it can continue to invade through the transition hole 10 (for electrically connecting the transition line 4 and the GOA circuit 8) close to the display area 101. Taking an LCD display panel as an example, water vapor can also invade the liquid crystal layer of the LCD through the transition hole 10, thereby causing the PCT performance of the display panel to fail to meet the test standard.

[0102] Through analysis of the mechanism of water vapor invading the box, the starting end 41 of the transition line 4 is an important weak point in the process of water vapor invading the box, that is, the position is prone to water vapor invasion. Combined with the path of water vapor invasion, water vapor mainly invades the starting end 41 of the transition line 4 from the first sub-hole 62 and / or the second sub-hole 63 of the sleeve hole. On this basis, the present application embodiment is to make the distance between at least one of the edge of the outer hole 61 of the sleeve hole structure 6, the edge of the first sub-hole 62, and the edge of the second sub-hole 63 and the starting end 41 of the transition line 4 greater than or equal to 2 μm, so that under this distance, the distance of water vapor from the sleeve hole structure 6 to the starting end 41 of the transition line 4 can be increased to a certain extent, thereby delaying the time of water vapor invading the starting end 41 of the transition line 4 to a certain extent, and further making the PCT performance of the display panel meet the test standard.

[0103] In some embodiments, the signal lines 2 can be multiple, for example, 4, 6, 8, etc., and the multiple signal lines are arranged at intervals and extend along the first direction X. Among them, the signal lines 2 and the adapter lines 4 can be in a one-to-one relationship, a one-to-many relationship, or a many-to-one relationship, for example, one signal line 2 is electrically connected with one adapter line 4.

[0104] For example, the signal lines 2 include a clock signal line 21, which is electrically connected with the adapter lines 4 through the via structure 6 and the jumper layer 7, and further electrically connected with the GOA circuit 8. The clock signal line 21 is used to provide a timing control signal for the GOA circuit 8, and through periodic high-low level switching, the internal transistor of the GOA circuit 8 is gradually turned on or off, thereby generating a scanning signal to activate the pixel units in the display panel row by row.

[0105] Of course, it can be understood that the signal lines 2 in the embodiments of the present application can also be a frame start signal line 2STV, a power signal line 2, and a reset signal line 2Reset, etc., which are not limited here.

[0106] In some embodiments, the adapter lines 4 can be multiple, for example, 4, 6, 8, etc., and the multiple adapter lines 4 are arranged at intervals and extend along the second direction Y. For example, one adapter line 4 is connected with one signal line 2.

[0107] Figure 5 A second partial cross-sectional schematic view of the array substrate in the embodiments of the present application is shown.

[0108] In some embodiments, further comprising:

[0109] The adapter hole 10 extends from the top of the second insulating layer 5 to the substrate layer 1 and exposes part of the surface of the adapter line 4, and the adapter line 4 is electrically connected with the GOA circuit 8 through the adapter hole 10.

[0110] Among them, the GOA circuit 8 is provided with a clock signal input end, and the adapter line 4 can be electrically connected with the clock signal input end of the GOA circuit 8 through the adapter hole 10. It can be understood that the adapter hole 10 should be filled with a conductive jumper layer 7.

[0111] In some embodiments, the array substrate 100 further comprises a first metal layer and a second metal layer (not shown). The first metal layer is arranged between the substrate layer 1 and the first insulating layer 3, and the signal lines 2 are located in the first metal layer; the second metal layer is arranged between the first insulating layer 3 and the second insulating layer 5, and the adapter lines 4 are located in the second metal layer; in the direction perpendicular to the substrate layer 1, the depth H1 of the first sub-hole is greater than the depth H2 of the second sub-hole.

[0112] That is, the embodiment of the present application can be prepared in the first metal layer, in the non-display area 102 with the signal line 2, the same reason, can be prepared in the second metal layer, in the non-display area 102 with the adapter line 4, thereby improving the process efficiency. Wherein, the first metal layer can be a gate metal layer, the second metal layer can be a source-drain metal layer; or, the first metal layer can be a source-drain metal layer, the second metal layer can be a gate metal layer, not limited here. For example, the first metal layer is a gate metal layer, and the second metal layer is a source-drain metal layer. When the gate metal layer is prepared in the display area 101, the signal line 2 can be prepared in the non-display area 102. When the source-drain metal layer is prepared in the display area 101, the adapter line 4 can be prepared in the non-display area 102.

[0113] It can be understood that, since the signal line 2 is located in the first metal layer, the adapter line 4 is located in the second metal layer, and the first metal layer is closer to the substrate layer 1 than the second metal layer, in order to expose the surface of the signal line 2, the depth H1 of the first sub-hole is etched to be greater than the depth H2 of the second sub-hole in the direction Z perpendicular to the substrate layer. The first sub-hole 62 extends from the bottom of the outer hole 61 to the surface of the signal line 2, and the second sub-hole 63 extends from the bottom of the outer hole 61 to the surface of the adapter line 4.

[0114] In some embodiments, when the first metal layer is a gate metal layer, the first insulating layer 3 can be a gate insulating layer, which covers the signal line 2 in the non-display area 102 and provides protection for the signal line 2.

[0115] In some embodiments, the second insulating layer 5 includes a first sub-insulating layer 51, a second sub-insulating layer 52, and a third sub-insulating layer 53 arranged in sequence.

[0116] It can be understood that the first sub-insulating layer 51 and the third sub-insulating layer 53 can be organic insulating layers, and the second sub-insulating layer 52 can be an inorganic insulating layer, for example: the first sub-insulating layer 51 can be PVX1 (first passivation layer), the third sub-insulating layer 53 can be PVX2 (second passivation layer), and the second sub-insulating layer 52 can be ORG (Organic Gate Insulator, organic gate insulating layer). Wherein, the first passivation layer and the second passivation layer are used to protect the internal circuit from the environment (such as moisture, ion contamination, mechanical damage), while providing electrical insulation and surface flattening, which can be prepared by using silicon nitride, silicon oxide and other materials; wherein, the organic gate insulating layer is an organic dielectric layer for transistors (such as OTFT, organic thin film transistor) or special device structure, which is used as an insulating medium between the gate and the channel, which can be prepared by using polymethyl methacrylate, polystyrene, polyvinyl phenol, polyvinylidene fluoride (PVDF) and its copolymer and other materials.

[0117] For a-Si display panel, the thickness of PVX1 is usually thin in the direction Z perpendicular to the substrate layer, so that when PVX1 covers the jumper 4, a physical gap is easily formed between the interface of PVX1 and the jumper 4, thereby providing a physical channel for water vapor intrusion.

[0118] Figure 6 A third partial cross-sectional schematic view of the array substrate of the embodiment of the present application is shown. Figure 7 A top view of the sleeve hole structure in Figure 6 A top view of the sleeve hole structure in

[0119] In some embodiments, the first sub-insulating layer 51 includes a first blocking portion 51A, the second sub-insulating layer 52 includes a second blocking portion 52A, and the third sub-insulating layer 53 includes a third blocking portion 53A, the first blocking portion 51A, the second blocking portion 52A, and the third blocking portion 53A are sequentially stacked, and the third blocking portion 53A covers the side surface of the first blocking portion 51A; the outer hole 61 is a plurality of outer holes, and the plurality of outer holes 61 include a first outer hole 61A and a second outer hole 61B. The first outer hole 61A extends from the top of the third sub-insulating layer 53 to the substrate layer 1, and the first sub-hole 62 communicates with the bottom of the first outer hole 61A; the second outer hole 61B extends from the top of the third sub-insulating layer 53 to the substrate layer 1, and the second sub-hole 63 communicates with the bottom of the second outer hole 61B; in the second direction Y, the first blocking portion 51A and the third blocking portion 53A covering the side surface of the first blocking portion 51A are provided between the starting end 41 of the jumper 4 and the first sub-hole 62.

[0120] It can be understood that by providing a plurality of outer holes 61, i.e., one outer hole 61 communicates with one sub-hole, the plurality of sub-insulating layers can be used to block between the first outer hole 61A and the second outer hole 61B, and between the first sub-hole 62 and the second sub-hole 63, i.e., by using the first blocking portion 51A, the second blocking portion 52A, and the third blocking portion 53A for blocking, thereby increasing the coverage of the second insulating layer 5 to the starting end 41 of the jumper 4, eliminating the erosion of the etching of the first sub-hole 62 to the coverage of the second insulating layer 5 in the lateral direction (the second direction Y) of the second sub-hole 63, thereby eliminating the possibility of water vapor intrusion from the first sub-hole 62 to the starting end 41 of the jumper 4 by using the blocking of the first blocking portion 51A to the third blocking portion 53A, increasing the lateral (second direction Y) coverage protection of the second insulating layer 5 to the starting end 41 (weak point) of the jumper 4, delaying the time of water vapor intrusion to the starting end 41 of the jumper 4, and subsequently helping to improve the PCT performance of the display panel.

[0121] In some embodiments, the second insulating layer 5 comprises a first sub-insulating layer 51, a second sub-insulating layer 52 and a third sub-insulating layer 53 which are sequentially stacked, and the third sub-insulating layer 53 comprises a fourth blocking part 53B. There is one outer hole 61, and the first sub-hole 62 and the second sub-hole 63 communicate with the bottom of the outer hole 61; in the second direction Y, the fourth blocking part 53B is arranged between the starting end 41 of the adapter wire 4 and the first sub-hole 62.

[0122] It can be understood that when one outer hole 61 respectively communicates with the first sub-hole 62 and the second sub-hole 63, due to etching, part of the area at the top of the adapter wire 4 only covers the third sub-insulating layer 53, and the other part of the area sequentially covers the first sub-insulating layer 51, the second sub-insulating layer 52 and the third sub-insulating layer 53. On this basis, the third sub-insulating layer 53 has poor lateral coverage of the starting end 41 of the adapter wire 4, so that water vapor may enter the starting end 41 of the adapter wire 4 from the first sub-hole 62, causing poor PCT performance of the display panel. On this basis, the present application is to make the distance between at least one of the edge of the outer hole 61 of the sleeve hole structure 6, the edge of the first sub-hole 62 and the edge of the second sub-hole 63 and the starting end 41 of the adapter wire 4 greater than or equal to 2 μm, so that under this distance, the distance of water vapor from the sleeve hole structure 6 to the starting end 41 of the adapter wire 4 can be increased to a certain extent, thereby delaying the time of water vapor entering the starting end 41 of the adapter wire 4 to a certain extent, and further making the PCT performance of the display panel meet the test standard.

[0123] Figure 8 A partial enlarged view in the dashed box in FIG. 1 is shown. Figure 3

[0124] In some embodiments, in the second direction Y, the starting end 41 is located between the first sub-hole 62 and the second sub-hole 63, the edge of the first sub-hole 62 close to the display area 101 has a first distance D1 with the starting end 41, the edge of the second sub-hole 63 away from the display area 101 has a second distance D2 with the starting end 41, the edge of the outer hole 61 away from the display area 101 has a third distance D3 with the edge of the first sub-hole 62 away from the display area 101, and the edge of the outer hole 61 close to the display area 101 has a fourth distance D4 with the edge of the second sub-hole 63 close to the display area 101; wherein at least one of the first distance D1, the second distance D2, the third distance D3 and the fourth distance D4 is greater than or equal to 2 μm (microns), for example, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc.

[0125] ​It can be understood that, within the range allowed by the wiring space of the non-display area 102 of the array substrate 100, one or more of the first spacing D1, the second spacing D2, the third spacing D3, and the fourth spacing D4 can be set as large as possible, so that at least one of the edge of the outer hole 61, the edge of the first sub-hole 62, and the edge of the second sub-hole 63 maintains a larger spacing from the starting end 41 of the adapter line 4, thereby increasing the path of moisture intrusion to some extent, delaying the time of moisture intrusion to the starting end 41 of the adapter line 4, and further delaying the time of moisture intrusion into the box, which helps to improve the PCT performance of the display panel.

[0126] It should be noted that if one outer hole 61 is in communication with the first sub-hole 62 and the second sub-hole 63, the outer hole 61 has two edges in the second direction Y, i.e., the edge of the outer hole 61 away from the display area 101 (referred to as the first edge) and the edge of the outer hole 61 close to the display area 101 (referred to as the second edge). Among them, the first edge refers to the edge of the projection of the outer hole 61 on the substrate layer 1 farthest from the display area 101, and the second edge refers to the edge of the projection of the outer hole 61 on the substrate layer 1 closest to the display area 101. If the first outer hole 61A is in communication with the first sub-hole 62 and the second outer hole 61B is in communication with the second sub-hole 63, in the second direction Y, the first edge can refer to the edge of the projection of the first outer hole 61A on the substrate layer 1 farthest from the display area 101, and the second edge can refer to the edge of the projection of the second outer hole on the substrate layer 1 closest to the display area 101.

[0127] It should be noted that the edge of the first sub-hole 62 close to the display area 101 (referred to as the third edge) can refer to the edge of the projection of the first sub-hole 62 on the substrate layer 1 closest to the display area 101, and the edge of the second sub-hole 63 close to the display area 101 (referred to as the fourth edge) can refer to the edge of the projection of the second sub-hole 63 on the substrate layer 1 closest to the display area 101.

[0128] Figure 9 A fourth partial cross-sectional structure schematic diagram of the array substrate of the embodiment of the present application is shown. By comparison Figure 9 and Figure 3 It can be seen that Figure 9 the first spacing D1 is increased.

[0129] It can be understood that if the first spacing D1 is increased as much as possible, the transmission path of the moisture in the first sub-hole 62 to the starting end 41 of the adapter line 4 can be increased, the time of moisture intrusion into the starting end 41 of the adapter line 4 is delayed, and the time of moisture intrusion into the box is further delayed, thereby improving the PCT performance of the display panel.

[0130] Figure 10A fifth partial cross-sectional structure diagram of the array substrate of the embodiment of the present application is shown. By comparison Figure 10 and Figure 3 it can be seen that Figure 10 the second distance D2 in the second sub-hole 63 is increased.

[0131] Figure 11 A sixth partial cross-sectional structure diagram of the array substrate of the embodiment of the present application is shown. By comparison Figure 11 and Figure 5 it can be seen that Figure 11 the second distance D2 in the second sub-hole 63 is increased.

[0132] If the second distance D2 is increased as much as possible, the transmission path of the water vapor in the second sub-hole 63 to the starting end 41 of the transfer line 4 can be increased, the time for the water vapor to invade the starting end 41 of the transfer line 4 is delayed, and the time for the water vapor to invade the box is further delayed, thereby improving the PCT performance of the display panel.

[0133] Figure 12 A seventh partial cross-sectional structure diagram of the array substrate of the embodiment of the present application is shown. By comparison Figure 12 and Figure 3 it can be seen that Figure 12 the third distance D3 in the second sub-hole 63 is increased.

[0134] If the third distance D3 is increased as much as possible, that is, the width of the outer hole 61 in the second direction Y is increased, the time for the water vapor entering the outer hole 61 to accumulate to the first sub-hole 62 and / or the second sub-hole 63 can be delayed, the time for the water vapor to invade the starting end 41 of the transfer line 4 is further delayed, and the time for the water vapor to invade the box is further delayed, thereby improving the PCT performance of the display panel PCT.

[0135] Figure 13 An eighth partial cross-sectional structure diagram of the array substrate of the embodiment of the present application is shown. By comparison Figure 13 and Figure 3 it can be seen that Figure 13 the fourth distance D4 in the second sub-hole 63 is increased.

[0136] Figure 14 A ninth partial cross-sectional structure diagram of the array substrate of the embodiment of the present application is shown. By comparison Figure 14 and Figure 5 it can be seen that Figure 14 the fourth distance D4 in the second sub-hole 63 is increased.

[0137] If the fourth distance D4 is increased as much as possible, that is, the width of the outer hole 61 in the second direction Y is increased, the time for the water vapor entering the outer hole 61 to accumulate to the first sub-hole 62 and / or the second sub-hole 63 can be delayed, the time for the water vapor to invade the starting end 41 of the transfer line 4 is further delayed, and the time for the water vapor to invade the box is further delayed, thereby improving the PCT performance of the display panel PCT.

[0138] It can be understood that, since the second sub-hole 63 is located on the surface of the adapter line 4, the water vapor in the second sub-hole 63 is more likely to enter the starting end 41 of the adapter line 4, and therefore, under the condition that the total width of the first distance D1 and the second distance D2 is constant, the second distance D2 can be ensured to be greater than or equal to 2 μm first.

[0139] It should be noted that the third distance D3 refers to the distance between the edge of the outer hole 61 away from the display area 101 and the edge of the first sub-hole 62 away from the display area 101, that is, the distance between the edge of the outer hole 61 away from the display area 101 and the starting end 41 of the adapter line 4 is actually equal to the sum of the third distance D3, the width of the first sub-hole 62 and the first distance D1, and therefore, under the condition that the third distance D3 is greater than or equal to 2 μm, the distance between the edge of the outer hole 61 away from the display area 101 and the starting end 41 of the adapter line 4 is also greater than or equal to 2 μm; in addition, the fourth distance D4 refers to the distance between the edge of the outer hole 61 close to the display area 101 and the edge of the second sub-hole 63 close to the display area 101, that is, the distance between the edge of the outer hole 61 close to the display area 101 and the starting end 41 of the adapter line 4 is actually equal to the sum of the fourth distance D4, the width of the second sub-hole 63 and the second distance D2, and therefore, under the condition that the fourth distance D4 is greater than or equal to 2 μm, the distance between the edge of the outer hole 61 close to the display area 101 and the starting end 41 of the adapter line 4 is also greater than or equal to 2 μm.

[0140] It can be understood that, in the manufacturing process, when the sleeve hole structure 6 is formed based on the photoetching process, at least one of the first distance D1 to the fourth distance D4 can be greater than or equal to 2 μm by precisely controlling the mask design. For example, the first distance D1 can be set to 3 μm to ensure that the starting end 41 of the adapter line 4 has sufficient water vapor delay distance from the first sub-hole 62; the second distance D2 can be set to 2.5 μm to ensure that the starting end 41 of the adapter line 4 has sufficient water vapor delay distance from the second sub-hole 63; the third distance D3 and the fourth distance D4 are set to 3 μm to ensure that the edge of the outer hole 61 has sufficient water vapor delay distance from the starting end 41 of the adapter line 4.

[0141] In some embodiments, at least one of the first distance D1, the second distance D2, the third distance D3 and the fourth distance D4 is greater than or equal to 2.5 μm, for example, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, etc.

[0142] It can be understood that the increase of the first distance D1 to the fourth distance D4 can be realized by increasing the width of the outer hole 61 in the second direction Y, or by reducing the width of the first sub-hole 62 or the width of the second sub-hole 63, or by adjusting the etching position of the first sub-hole 62 and the second sub-hole 63. Limited by the wiring space, the width of the outer hole 61 has certain limitations; limited by the exposure process limit, the reduction of the width of the first sub-hole 62 and the second sub-hole 63 also has certain limitations; limited by the position relationship of the outer hole 61 and the first sub-hole 62 and the second sub-hole 63, the etching position of the first sub-hole 62 and the second sub-hole 63 also has certain limitations. It can be understood that on the basis of the above limitations, at least one of the first distance D1 to the fourth distance D4 is increased as much as possible, so that the water vapor intrusion can be delayed to a certain extent.

[0143] In some embodiments, at least one of the following is satisfied: the ratio between the third distance D3 and the first distance D1 ranges from 0.6 to 0.9, for example, is 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.; the ratio between the fourth distance D4 and the second distance D2 ranges from 0.6 to 0.9, for example, is 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.; the ratio between the sum of the first distance D1 and the third distance D3 and the sum of the second distance D2 and the fourth distance D4 ranges from 0.6 to 0.9, for example, is 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.

[0144] It can be understood that in the embodiments of the present application, the restrictions of various distances and the restrictions of various ratio ranges are asynchronized as much as possible, and the restrictions of the ratio ranges can be ensured preferentially when the distances cannot be ensured simultaneously.

[0145] In some embodiments, the ratio between the fourth distance D4 and the second distance D2 ranges from 0.5 to 1.0, for example, is 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0.

[0146] It can be understood that, when the first outer hole 61 A is communicated with the first sub-hole 62, and the second outer hole 61B is communicated with the second sub-hole 63, the coverage of the second insulating layer 5 to the starting end 41 of the adapter wire 4 is increased due to the blocking by the first blocking part 51A, the second blocking part 52A and the third blocking part 53A, the erosion of the etching of the first sub-hole 62 to the coverage of the second insulating layer 5 in the lateral direction (the second direction Y) of the second sub-hole 63 is eliminated, the possibility of the water vapor invading the starting end 41 of the adapter wire 4 from the first sub-hole 62 is eliminated, and the lateral (second direction Y) coverage protection of the second insulating layer 5 to the starting end 41 (weak point) of the adapter wire 4 is increased. In this case, the first spacing D1 and the third spacing D3 are substantially increased, and in this case, the second spacing D2 and / or the fourth spacing D4 can be considered to be greater than or equal to 2 μm, or greater than or equal to 2.5 μm. In addition, considering that the mutual independence of the first sub-hole 62 and the second sub-hole 63 can delay the invasion of water vapor to a certain extent, the requirement of the ratio range of the fourth spacing D4 and the second spacing D2 can be relaxed, that is, set to 0.5-1.0.

[0147] In some embodiments, at least one of the following is satisfied: in the second direction Y, the width of the first sub-hole 62 ranges from 3 μm to 6 μm, for example, 3 μm, 4 μm, 5 μm or 6 μm; in the second direction Y, the width of the second sub-hole 63 ranges from 3 μm to 6 μm, for example, 3 μm, 4 μm, 5 μm or 6 μm; in the second direction Y, the width of the outer hole 61 ranges from 5 μm to 20 μm, for example, 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, 15 μm, 16 μm, 18 μm, 20 μm.

[0148] It can be understood that when the outer hole 61 is one, the width of one outer hole 61 can be set to be larger, for example, set to 15 μm-20 μm; when the outer hole 61 is multiple, the width of each outer hole 61 can be set to be smaller, for example, 5 μm-10 μm.

[0149] Continuing to refer to Figure 3 In some embodiments, the side wall inclination angle of the outer hole 61 is smaller than the side wall inclination angle of the first sub-hole 62, and / or the side wall inclination angle of the outer hole 61 is smaller than the side wall inclination angle β2 of the second sub-hole.

[0150] It should be noted that the side wall inclination angle of the outer hole 61 refers to the included angle between the outer hole 61 and the plane where the substrate layer 1 is located, the side wall inclination angle β2 of the first sub-hole refers to the included angle between the side wall of the first sub-hole 62 and the plane where the substrate layer 1 is located, and the side wall inclination angle β2 of the second sub-hole refers to the included angle between the side wall of the second sub-hole 63 and the plane where the substrate layer 1 is located.

[0151] It can be understood that when the side wall angle of the outer hole 61 is smaller than the side wall angle of the first sub-hole 62, and / or the side wall angle of the outer hole 61 is smaller than the side wall angle β2 of the second sub-hole, for example, the side wall angle of the outer hole 61 is smaller than 90 degrees, and the side wall angles of the first sub-hole 62 and the second sub-hole β2 are substantially equal to 90 degrees. Thus, it is more difficult for water vapor to accumulate from the outer hole 61 to the first sub-hole 62 and / or the second sub-hole 63, so that water vapor intrusion can be delayed to a certain extent.

[0152] In some embodiments, the array substrate 100 further comprises:

[0153] A pixel electrode layer (not shown) is disposed on the side of the second insulating layer 5 away from the substrate, in the display area 101.

[0154] A common electrode layer (not shown) is disposed on the side of the second insulating layer 5 away from the substrate, in the display area 101.

[0155] The jumper layer 7 is located in the pixel electrode layer or the common electrode layer.

[0156] It can be understood that the pixel electrode layer and the common electrode layer can be made of ITO (Indium Tin Oxide), one of the pixel electrode layer and the common electrode layer is referred to as 1ITO, and the other is referred to as 2ITO.

[0157] Taking an LCD display panel as an example, 1ITO and 2ITO respectively refer to different layers or functions of ITO (Indium Tin Oxide) conductive layers, 1ITO can refer to the first layer of ITO conductive layer close to the glass substrate in the LCD panel, located on one side of the liquid crystal layer, used as an electrode layer to form an electric field to drive the liquid crystal molecules to deflect. 2ITO refers to the ITO conductive layer on the other side of the LCD panel, opposite to 1ITO, with liquid crystal material in between, used as a common electrode to form an electric field with 1ITO to drive the liquid crystal.

[0158] The jumper layer 7 located in the pixel electrode layer or the common electrode layer can be: the jumper layer 7 is prepared in the same layer as the pixel electrode layer or the common electrode layer, for example, in the same layer as 2ITO. That is, when 2ITO is prepared in the display area 101, the jumper layer 7 can be prepared in the non-display area 102 using the same material, and the jumper layer 7 is used to realize the electrical connection between the signal line 2 and the jumper line 4, and / or realize the jumper line.

[0159] Figure 15 A structural schematic diagram of a display panel of an embodiment of the present application is shown.

[0160] The second aspect of the embodiment of the present application provides a display panel 200, comprising: the array substrate according to any one of the first aspect, a color film substrate 21 arranged in a cell with the array substrate, and a liquid crystal layer 22 between the array substrate and the color film substrate 21.

[0161] The display area of the display panel 200 is provided with a pixel circuit for controlling the display of the pixel unit, the pixel circuit comprises a plurality of gate lines and a plurality of data lines arranged in a cross manner, and further comprises a thin film transistor connected between the gate line and the data line, the thin film transistor is arranged corresponding to the pixel unit, the thin film transistors in the same row of pixel units are connected to the same gate line, and the thin film transistors in the same column of pixel units are connected to the same data line.

[0162] The non-display area of the display panel 200 is provided with a gate drive circuit and a data drive circuit, the gate drive circuit is connected with the gate line of the display area, and the data drive circuit is connected with the data line of the display area. In use, each pixel unit in the pixel array is scanned row by row by outputting a gate drive signal by the gate drive circuit; the data drive circuit can convert the display data to be displayed into a data voltage signal, and at the same time of scanning each row of gate lines, the data drive circuit writes the data voltage signal corresponding to the row of pixels into the pixel circuit of the row of pixels through each data line, so as to light up the row of pixel units, thereby realizing the picture display of the entire display area.

[0163] In some embodiments, the display panel 200 further comprises:

[0164] A first alignment film 201 is arranged on the side of the second insulating layer away from the substrate.

[0165] A sealant 23 is arranged between the first alignment film 201 and the color film substrate 21 and located in the non-display area.

[0166] The color film substrate 21 further comprises: a color film layer 205, a light shielding layer 204 (for example, a black matrix), a cover layer 203 and a second alignment film 202 which are sequentially stacked, and the sealant 23 is arranged between the first alignment film 201 and the second alignment film 202.

[0167] Figure 16 A structural block diagram of the display device of the embodiment of the present application is shown.

[0168] The third aspect of the embodiment of the present application provides a display device 300, comprising the array substrate 100 according to any one of the first aspect or the display panel 200 according to the second aspect.

[0169] For example, the display device 300 can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any product or component with a display function.

[0170] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that one skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps not listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices, apparatuses or means can be listed, which can be implemented by one and the same item of hardware or software. The use of the terms first, second and third, etc. does not imply any ordering, but rather are used for naming purposes only. Features, steps or elements of the application can be per-formed by means of hardware, software, and any combination thereof. One or more of the disclosed embodiments can be implemented as a computer program product, i.e., a computer program tangibly embodied in a machine-readable storage medium for execution by, or to control the operation of, a data processing apparatus, and / or a computer program product. The program can be implemented in a high-level procedural or object-oriented programming and / or scripting language, or multiple languages. The program can be implemented according to the process flow of the disclosed embodiments, or other process flow. The program can be implemented in a software package, a suite of routines comprising a software development kit, or an object-oriented development system, for use with, for example, an operating system or a standalone machine. The program can be written in any form of programming language, including compiled or interpreted languages, and / or computer scripts. The program can be deployed in any form, including as a stand-alone program, a subroutine, a software module, or as an applet within a larger program or in a distribution of such a program. Any input, output, or inputs and outputs can be in an electronic, optical, magnetic, electromagnetic, infrared, or optical form, and can be compiled, interpreted, or otherwise processed.

[0171] The above description is merely illustrative of the application, and is not intended to limit the scope of the application. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the application shall fall within the scope of the application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a display area and a non-display area arranged on at least one side of the display area, and the array substrate comprises: a substrate layer; a signal line arranged on one side of the substrate layer and located in the non-display area and extending in a first direction; a first insulating layer covering the signal line; a transition line arranged on a side of the first insulating layer away from the substrate layer, located in the non-display area, and extending in a second direction intersecting the first direction; a second insulating layer covering the transition line; a sleeve hole structure comprising an outer hole, a first sub-hole and a second sub-hole, the outer hole extending from the top of the second insulating layer to the substrate layer, the first sub-hole and the second sub-hole being arranged at intervals and communicating with the bottom of the outer hole, the bottom of the first sub-hole exposing part of the surface of the signal line, and the bottom of the second sub-hole exposing part of the surface of the transition line; wherein, in the second direction, the distance between at least one of the edge of the outer hole, the edge of the first sub-hole and the edge of the second sub-hole and the starting end of the transition line is greater than or equal to 2 microns, the starting end being the end of the transition line away from the display area; a bridging layer covering the outer hole, the first sub-hole and the second sub-hole, the transition line being electrically connected to the signal line through the bridging layer; a GOA circuit arranged on one side of the substrate layer, located between the signal line and the display area, and electrically connected to the transition line.

2. The array substrate of claim 1, wherein, The second insulating layer comprises a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer arranged in sequence, the first sub-insulating layer comprises a first blocking portion, the second sub-insulating layer comprises a second blocking portion, and the third sub-insulating layer comprises a third blocking portion, the first blocking portion, the second blocking portion and the third blocking portion being arranged in sequence, and the third blocking portion covering the side surface of the first blocking portion; The outer hole is a plurality of outer holes comprising: a first outer hole extending from the top of the third sub-insulating layer to the substrate layer, the first sub-hole communicating with the bottom of the first outer hole; a second outer hole extending from the top of the third sub-insulating layer to the substrate layer, the second sub-hole communicating with the bottom of the second outer hole; In the second direction, the starting end of the transition line and the first sub-hole are provided with the first blocking portion and the third blocking portion covering the side surface of the first blocking portion.

3. The array substrate of claim 1, wherein, The second insulating layer comprises a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer arranged in sequence, and the third sub-insulating layer comprises a fourth blocking portion; The outer hole is one, and the first sub-hole and the second sub-hole communicate with the bottom of the one outer hole; In the second direction, the starting end of the transition line and the first sub-hole are provided with the fourth blocking portion.

4. The array substrate according to claim 2 or 3, characterized by, The first sub-insulating layer and the third sub-insulating layer are inorganic insulating layers, and the second sub-insulating layer is an organic insulating layer.

5. The array substrate according to any one of claims 1 to 3, wherein, In the second direction, the starting end is located between the first sub-hole and the second sub-hole, a side edge of the first sub-hole close to the display area has a first distance from the starting end, a side edge of the second sub-hole away from the display area has a second distance from the starting end, a side edge of the outer hole away from the display area has a third distance from the side edge of the first sub-hole away from the display area, and a side edge of the outer hole close to the display area has a fourth distance from the side edge of the second sub-hole close to the display area. At least one of the first distance, the second distance, the third distance, and the fourth distance is greater than or equal to 2 μm.

6. The array substrate of claim 5, wherein, At least one of the first distance, the second distance, the third distance, and the fourth distance is greater than or equal to 2.5 μm.

7. The array substrate of claim 5, wherein, At least one of the following is satisfied: The ratio between the third distance and the first distance ranges from 0.6 to 0.

9. The ratio between the fourth distance and the second distance ranges from 0.6 to 0.

9. The ratio between the sum of the first distance and the third distance and the sum of the second distance and the fourth distance ranges from 0.6 to 0.

9.

8. The array substrate of claim 5, wherein, The ratio between the fourth distance and the second distance ranges from 0.5 to 1.

0.

9. The array substrate according to any one of claims 1-3, 6-8, wherein, At least one of the following is satisfied: In the second direction, the width of the first sub-hole ranges from 3 μm to 6 μm. In the second direction, the width of the second sub-hole ranges from 3 μm to 6 μm. In the second direction, the width of the outer hole ranges from 5 μm to 20 μm.

10. The array substrate of claim 1, wherein, The side wall angle of the outer hole is smaller than the side wall angle of the first sub-hole, and / or the side wall angle of the outer hole is smaller than the side wall angle of the second sub-hole.

11. The array substrate of claim 1, wherein, Further comprising: a first metal layer disposed between the substrate layer and the first insulating layer, the signal line being located in the first metal layer; a second metal layer disposed between the first insulating layer and the second insulating layer, the transfer line being located in the second metal layer; In a direction perpendicular to the substrate layer, the depth of the first sub-hole is greater than the depth of the second sub-hole.

12. The array substrate of claim 1, wherein, The signal line includes a clock signal line.

13. The array substrate of claim 1, wherein, Further comprising: a transfer hole extending from the top of the second insulating layer to the substrate layer and exposing part of the surface of the transfer line, the transfer line being electrically connected to the GOA circuit through the transfer hole.

14. A display panel, characterized by, Comprising: The array substrate as claimed in any one of claims 1-13, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer between the array substrate and the color film substrate.

15. A display device comprising: The display panel as claimed in claim 14, or the array substrate as claimed in any one of claims 1-13.

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