Display panel and display device

Abstract

The display panel and the display device disclosed by the utility model comprise an array substrate and an opposite substrate which are oppositely arranged, the pixel electrode is positioned on one side of the substrate; a first electrode of the transistor is electrically connected with the pixel electrode; the grid line is electrically connected with the grid electrode of the transistor, the grid line comprises a notch structure for accommodating the connection position of the pixel electrode and the first electrode of the transistor, and the side, close to the pixel electrode, of the notch structure is arranged in a closed mode; the opposite substrate comprises a first common electrode close to one side of the array substrate, and the first common electrode and the pixel electrode are at least partially overlapped in the direction perpendicular to the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Utility Model Content

[0003] The display panel and display device provided in this disclosure are specifically designed as follows:

[0004] On one hand, embodiments of this disclosure provide a display panel, including:

[0005] An array substrate and a counter substrate are disposed opposite to each other, wherein the array substrate includes:

[0006] Substrate;

[0007] The pixel electrode is located on one side of the substrate.

[0008] A transistor, wherein the first electrode of the transistor is electrically connected to the pixel electrode;

[0009] The gate line is electrically connected to the gate of the transistor. The gate line includes a notch structure that accommodates the first electrode connection position of the pixel electrode and the transistor. The notch structure is closed on the side near the pixel electrode. The opposing substrate includes a first common electrode on the side near the array substrate. In a direction perpendicular to the substrate, the first common electrode and the pixel electrode at least partially overlap.

[0010] In some embodiments, the notch structure in the display panel provided in the present disclosure is a closed structure.

[0011] In some embodiments, in the display panel provided in the present disclosure, the notch structure is a groove structure with an opening on the side away from the pixel electrode.

[0012] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a data line, a second common electrode, and a first common electrode line that is on the same layer as and adjacent to the gate line. The second common electrode is electrically connected to the first common electrode line. The connection position of the second common electrode and the first common electrode line is located within the notch structure. The connection positions of the second common electrode and the first common electrode line and the connection positions of the pixel electrode and the first electrode of the transistor overlap with each other in the data line extension direction.

[0013] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a data line and a second common electrode, wherein the orthographic projection of the second common electrode on the substrate does not overlap with the orthographic projection of the data line on the substrate in the region between two adjacent pixel electrodes along the extension direction of the gate line.

[0014] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a transparent trace that is on the same layer as the second common electrode and is in direct contact with the data line. The orthographic projection of the transparent trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate in the region between two adjacent pixel electrodes along the extension direction of the gate line.

[0015] In some embodiments, in the display panel provided in the present disclosure, in a cross-sectional direction perpendicular to the substrate, the transparent trace covers a first side, a second side, and a third side of the data line. The first side extends in the same direction as the substrate, the second side and the third side are opposite to each other, and the two ends of the first side are connected.

[0016] In some embodiments, in the display panel provided in the present disclosure, the transparent trace layer is located between the data line layer and the substrate, and the orthographic projection of the data line on the substrate is located within the orthographic projection of the transparent trace on the substrate.

[0017] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a data line and a second common electrode, wherein the orthographic projection of the second common electrode on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0018] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a first insulating layer located on the side of the data line layer away from the substrate, and the second common electrode layer is located on the side of the first insulating layer away from the substrate.

[0019] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a color resist layer on the side of the layer where the second common electrode is located away from the substrate and in direct contact with the second common electrode.

[0020] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a color resist layer between the layer containing the second common electrode and the first insulating layer, and in direct contact with the second common electrode.

[0021] In some embodiments, in the display panel provided in the present disclosure, the color resist layer includes a plurality of color resists, the edges of adjacent color resists overlap each other, and the orthogonal projection of the overlapping color resist edges on the substrate covers the orthogonal projection of the data line on the substrate.

[0022] In some embodiments, in the display panel provided in the present disclosure, the second common electrode and the pixel electrode overlap to form a storage capacitor.

[0023] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a data line, a second common electrode, a second common electrode line, and a shielding electrode, wherein the second common electrode line is on the same layer as the data line, the shielding electrode is on the same layer as the pixel electrode, and the second common electrode line is electrically connected to the second common electrode through the shielding electrode.

[0024] In some embodiments, in the display panel provided in the present disclosure, the shielding electrode includes a first shielding electrode and a second shielding electrode. In a direction perpendicular to the substrate, the first shielding electrode overlaps with the data line, and the second shielding electrode is disposed in the region between two adjacent rows of pixel electrodes. The second shielding electrode is electrically connected to the second common electrode line and the second common electrode.

[0025] In some embodiments, in the display panel provided in the present disclosure, two gate lines are disposed between adjacent pixel electrode rows, the second common electrode line is disposed between two adjacent data lines, the second shielding electrode overlaps with at least one of the two gate lines, and the second shielding electrode includes a widened portion, which overlaps with the second common electrode line and achieves electrical connection.

[0026] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes data lines and light-shielding electrodes on the same layer as the data lines, the area where the pixel electrodes are located includes multiple domain regions, and the light-shielding electrodes are disposed in the gaps between the domain regions.

[0027] In some embodiments, in the display panel provided in the present disclosure, the plurality of domain regions include a first domain region, a second domain region, a third domain region, and a fourth domain region, wherein the first domain region is close to the data line and the transistor, the second domain region is located on the side of the first domain region away from the data line, the third domain region is located on the side of the first domain region away from the gate line, and the fourth domain region is located on the side of the second domain region away from the gate line.

[0028] The light-shielding electrode is also disposed at at least one of the following: the edge of the first domain region away from the third domain region; the edge of the second domain region away from the first domain region; the edge of the third domain region away from the fourth domain region; and the edge of the fourth domain region away from the second domain region.

[0029] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a second common electrode line on the same layer as the data line, and the light-shielding electrode is integrally disposed with the second common electrode line.

[0030] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0031] Figure 1 A schematic diagram of a structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure;

[0032] Figure 2 For along Figure 1 Schematic diagram of the cross-sectional structure of line I-I' in the middle;

[0033] Figure 3 for Figure 1 A magnified structural diagram of the Z1 region;

[0034] Figure 4 This is a schematic diagram of a gate wire structure provided in an embodiment of the present disclosure;

[0035] Figure 5 This is a schematic diagram of another gate wire structure provided in an embodiment of the present disclosure;

[0036] Figure 6 for Figure 1 Schematic diagram of the structure of the layer containing the middle grid lines;

[0037] Figure 7 for Figure 1 A schematic diagram of the active layer structure;

[0038] Figure 8 for Figure 1 A schematic diagram of the structure of the layer where the data cable is located;

[0039] Figure 9 for Figure 1 Schematic diagram of the structure of the intermediate color resist layer;

[0040] Figure 10 for Figure 1 Schematic diagram of the structure of the layer where the second common electrode is located;

[0041] Figure 11 for Figure 1 Schematic diagram of the structure of the layer containing the via;

[0042] Figure 12 for Figure 1 Schematic diagram of the structure of the layer where the middle pixel electrode is located;

[0043] Figure 13 for Figure 2 A parallel technical solution;

[0044] Figure 14 This is a schematic diagram of another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure;

[0045] Figure 15 For along Figure 14 Schematic diagram of the cross-sectional structure of line II-II';

[0046] Figure 16 for Figure 14 Schematic diagram of the structure of the layer containing the middle grid lines;

[0047] Figure 17 for Figure 14 Schematic diagram of the structure of the layer where the second common electrode is located;

[0048] Figure 18 This is a schematic diagram of another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure;

[0049] Figure 19 For along Figure 18 Schematic diagram of the cross-sectional structure of line III-III';

[0050] Figure 20 for Figure 18 Schematic diagram of the structure of the layer where the second common electrode is located;

[0051] Figure 21 for Figure 18Schematic diagram of the structure of the layer where the middle pixel electrode is located;

[0052] Figure 22 for Figure 19 A parallel scheme;

[0053] Figure 23 for Figure 19 Another parallel scheme;

[0054] Figure 24 for Figure 19 Another parallel scheme;

[0055] Figure 25 For along Figure 18 Schematic diagram of the cross-sectional structure of line IV-IV';

[0056] Figure 26 For along Figure 18 Schematic diagram of the cross-sectional structure of the V-V' line;

[0057] Figure 27 for Figure 2 Another parallel technical solution;

[0058] Figure 28 for Figure 13 A parallel technical solution;

[0059] Figure 29 A schematic diagram of the structure of the storage capacitor provided in the embodiments of this disclosure;

[0060] Figure 30 This is a schematic diagram of another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure;

[0061] Figure 31 This is a schematic diagram of another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure;

[0062] Figure 32 This is a schematic diagram of another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure;

[0063] Figure 33 for Figure 32 A schematic diagram of sub-pixel overlay dark patterns;

[0064] Figure 34 for Figure 13 Another parallel technical solution;

[0065] Figure 35 for Figure 15 A parallel technical solution;

[0066] Figure 36 for Figure 19 A parallel technical solution;

[0067] Figure 37 for Figure 19 Another parallel technical solution;

[0068] Figure 38 for Figure 1 Another parallel technical solution;

[0069] Figure 39 for Figure 13 Another parallel technical solution;

[0070] Figure 40 For along Figure 39 Schematic diagram of the cross-sectional structure of line VII-VII' in the middle;

[0071] Figure 41 For along Figure 38 and Figure 39 Schematic diagram of the cross-sectional structure of VIII-VIII'. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the following description will be made in conjunction with the accompanying drawings of the embodiments of this disclosure. For clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shapes in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shapes of the regions or reflect true proportions, but are only intended to illustrate the content of this disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0073] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0074] In the following description, when an element or layer is referred to as "on" another element or layer or "connected" to another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" another element or layer" or "directly connected" to another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items. The various embodiments of this disclosure may be combined and integrated with each other without conflict.

[0075] Figure 1 This is a schematic diagram of the structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure. Figure 2 For along Figure 1 Schematic diagram of the cross-sectional structure of line I-I' in the middle. Figure 3 for Figure 1 A magnified structural diagram of the Z1 region. (See diagram below.) Figures 1 to 3As shown, the display panel provided in this embodiment includes an array substrate 001 and a opposing substrate 002 placed opposite each other. The array substrate 001 includes a substrate 101, a pixel electrode 102, a transistor 103, and a gate line 104 located on one side of the substrate 101. The first electrode d of the transistor 103 is electrically connected to the pixel electrode 102 through a first via V1 penetrating the insulating layer between them (optionally, the first electrode d of the transistor 103 and the pixel electrode 102 can also be directly contacted and electrically connected without the first via V1). The gate line 104 includes a accommodating element for the pixel electrode 102. The notch structure GS of the first electrode d connection position (e.g., the first via V1) of the transistor 102 and the first electrode d of the transistor 103 is open on the side near the pixel electrode 102; the opposing substrate 002 includes a substrate 201 and a first common electrode 202 on the side of the substrate 201 near the array substrate 001. In the direction Z perpendicular to the substrate 101, the first common electrode 202 and the pixel electrode 102 at least partially overlap. Optionally, the first common electrode 202 is designed in a block shape in the display area AA, which can be a whole surface design or multiple block structures connected together, etc.

[0076] Depend on Figure 3 As can be seen, the notch structure GS is designed to be right-angled, but due to exposure diffraction and other reasons, it is usually made at an angle in practice. Metal corners (especially 45° or close to 45° angles) are prone to scattering, refraction, and polarization, leading to light leakage in dark states. Therefore, it is essential to avoid the presence of metal corners in the pixel aperture area. Based on this, this disclosure provides... Figure 4 and Figure 5 Two new schemes, combining Figure 1 , Figure 4 and Figure 5 As can be seen, this disclosure allows for a closed configuration of the notch structure GS on the side closest to the pixel electrode 102, wherein... Figure 4 The notch structure GS is a closed structure. Figure 5 The notch structure GS is designed as a groove structure with an opening on the side away from the pixel electrode 102, thereby avoiding the presence of metal corners in the pixel opening area and effectively solving the problem of dark-state light leakage caused by metal corners. Furthermore... Figure 4 The notch structure of GS adopts a closed design, which has better resistance to process fluctuations (when the process fluctuates, the fluctuations of different display panels and different positions of the display panel are small - no matter how the two metal layers are offset, their overall load is small), and has better stability for related image quality. Figure 5 The design of opening on the side away from pixel electrode 102, as shown, makes the notch structure GS farther away from the pixel opening area, with a larger light-shielding margin and a larger shift margin between the anti-array substrate and the opposing substrate.

[0077] In some embodiments, Figures 6 to 12It shows Figure 1 Schematic diagrams of the structures of different membrane layers, such as Figure 1 , Figure 2 , Figures 6 to 12 As shown, the array substrate 001 of this disclosure may further include a data line 105 and a second common electrode 106. The orthographic projection of the second common electrode 106 on the substrate 101 overlaps with the orthographic projection of the data line 105 on the substrate 101. For example, the second common electrode 106 completely covers the data line 105 between two adjacent pixel electrodes 102 in the extension direction X of the gate line 104 to avoid dark light leakage and ensure a large aperture ratio.

[0078] See also Figure 2 As can be seen, the layer containing the second common electrode 106 of this disclosure is in direct contact with the color resist layer CF on the side of the color resist layer CF away from the substrate 101. Compared with the design scheme in which an organic layer is provided between the layer containing the second common electrode 106 and the color resist layer CF, and a first via V1 connecting the first electrode of the pixel electrode 102 and the transistor 103 is formed on the organic layer using a mask process, this disclosure directly fabricates the second common electrode 106 on the color resist layer CF, eliminating the organic layer between the layer containing the second common electrode 106 and the color resist layer CF, thereby saving the mask process of the organic layer, reducing process costs, and improving process yield. Specifically, Figure 2 The masking process of the illustrated embodiment can be sequentially as follows: ① Masking process of the layer containing the gate line 104 → ② Masking process of the active layer (which may be amorphous silicon, low-temperature polysilicon, oxide such as IGZO, etc.) → ③ Masking process of the layer containing the data line 105 → Masking process of the color resist layer CF (which may include three masks: red color resist R, green color resist G, and blue color resist B) → ④ Masking process of the layer containing the second common electrode 106 → ⑤ Masking process of the second insulating layer 112 → ⑥ Masking process of the layer containing the pixel electrode 102. The masking process of the color resist layer CF (which may include three masks: red color resist R, green color resist G, and blue color resist B) is generally attributed to the opposing substrate 002. Therefore, the array substrate 001 of this disclosure has a total of 6 masking processes.

[0079] Figure 13 for Figure 2 A parallel technical solution, by Figure 13 As can be seen, this disclosure also allows the second common electrode 106 to be directly fabricated between the first insulating layer 109 and the color resist layer CF, with the second common electrode 106 in direct contact with the color resist layer CF, and the number of mask processes being the same. Figure 2 The illustrated embodiment differs in that the masking process for the second common electrode 106 is adjusted to precede the masking process for the color resist layer CF. Specifically, Figure 13The masking process of the embodiment shown can be as follows: ① masking process of the layer where the gate line 104 is located → ② masking process of the active layer → ③ masking process of the layer where the data line 105 is located → masking process of the layer where the second common electrode 106 is located → ④ masking process of the color resist layer CF (which may include three masks: red color resist R, green color resist G, and blue color resist B) → ⑤ masking process of the second insulating layer 112 → ⑥ masking process of the layer where the pixel electrode 102 is located.

[0080] Figure 14 This is a schematic diagram illustrating yet another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure. Figure 15 For along Figure 14 Schematic diagram of the cross-sectional structure of line II-II'. Figure 16 for Figure 14 A schematic diagram of the structure of the layer where the gate line 104 is located (the storage capacitor Cst in related technologies includes a MIM capacitor composed of the first electrode of transistor 101 and the common electrode line of the layer where the gate line 104 is located, which has a low aperture ratio. The storage capacitor Cst of this disclosure is composed of a second common electrode 106 and a pixel electrode 102, which can omit the common electrode line of the layer where the gate line 104 is located used to form the MIM capacitor, thereby maximizing the aperture ratio and improving the transmittance.) Figure 17 for Figure 14 A schematic diagram of the structure of the layer where the second common electrode 106 is located. Figure 14 Other membrane structures can be referenced. Figure 1 The relevant film layers in the illustrated embodiment. For example... Figures 14 to 17 As shown, the second common electrode 106 can also overlap with the edge portion of the data line 105 between two adjacent pixel electrodes 102 in the X-direction of the gate line 104, thereby improving dark-state light leakage while reducing the load on the data line 105. Optionally, at the overlap position of the data line 105 and the second common electrode 106, the second common electrode 106 is designed with a notch, as shown in the reference. Figure 17 A trench can be a single trench or multiple trenches in the vertical direction; this is not a limitation. Figures 14 to 17 The number and sequence of mask processing steps in the illustrated embodiment are the same as those in the previous embodiment. Figure 13 The embodiments shown are the same and will not be described again here.

[0081] Figure 18 This is a schematic diagram illustrating yet another structure of 1*2 sub-pixels in a display panel provided in an embodiment of this disclosure. Figure 19 For along Figure 18 Schematic diagram of the cross-sectional structure of line III-III'. Figure 20 for Figure 18 A schematic diagram of the structure of the layer where the second common electrode 106 is located. Figure 21 for Figure 18 A schematic diagram of the structure of the layer where the middle pixel electrode is located. Figure 18 The pattern of the layer containing grid line 104 can be seen in [reference]. Figure 16 The pattern of the active layer IGZO can be found in [reference needed]. Figure 7 The pattern of the layer containing data cable 105 can be found in [reference]. Figure 8 The pattern of the color resist layer CF can be seen in [reference]. Figure 9 The structure of the layer containing the via can be found in [reference]. Figure 11 .like Figures 18 to 21 As shown, the orthographic projection of the second common electrode 106 on the substrate 101 can be made to not overlap with the orthographic projection of the data line 105 in the region between two adjacent pixel electrodes 102 along the extension direction X of the gate line 104 on the substrate 101. Furthermore, a first shielding electrode 1111 of the same layer and material as the pixel electrode 102 can be provided, and the orthographic projection of the first shielding electrode 1111 on the substrate 101 can overlap with the orthographic projection of the data line 103 on the substrate 101. This not only helps to reduce the loading of the data line 105, making it suitable for high-resolution, high-refresh-rate products, but also allows the first shielding electrode 1111 to block dark-state light leakage. Figure 18 The number and sequence of mask processing steps in the illustrated embodiment are the same as those in the previous embodiment. Figure 13 The embodiments shown are the same and will not be described again here.

[0082] Figures 22 to 24 They are respectively Figure 19 A parallel scheme. With Figure 19 The difference is: Figure 19 A first insulating layer 109 is provided between the layer where the second common electrode 106 is located and the layer where the data line 105 is located. Figures 22 to 24 The layer containing the second common electrode 106 is adjacent to the layer containing the data line 105, and Figure 22 and Figure 23 The array substrate 001 also has a transparent trace 107 that is on the same layer and made of the same material as the second common electrode 106 and is in direct contact with the data line 105. The orthographic projection of the transparent trace 107 on the substrate 101 can at least partially overlap with the orthographic projection of the data line 105 in the region between two adjacent pixel electrodes 102 along the X-direction of the gate line 104, which helps to reduce the impedance of the data line 105. Optionally, as Figure 22 As shown, the layer containing the transparent trace 107 is located between the layer containing the data line 105 and the substrate 101, and the orthogonal projection of the data line 105 on the substrate 101 lies within the orthogonal projection of the transparent trace 107 on the substrate 104. This also prevents metal ions (e.g., Cu ions) from the data line 105 from diffusing to the underlying third insulating layer 108. Alternatively, as... Figure 23As shown, the transparent trace 107 is located on the side of the data line 105 away from the substrate 101. In the direction Z perpendicular to the substrate 101, the transparent trace 107 can cover the first side, the second side, and the third side of the data line 105. The first side is in the same direction as the extension of the substrate 11, and the second and third sides are opposite to each other and connect the two ends of the first side. That is, the first side is the side of the data line 105 away from the upper surface of the substrate 101, and the second and third sides are the left and right sides of the data line 105. This can also prevent the data line 105 from being corroded.

[0083] Figure 22 The masking process of the embodiment shown can be as follows: ① masking process of the layer where the gate line 104 is located → ② masking process of the active layer → ③ masking process of the layer where the second common electrode 106 is located → ④ masking process of the layer where the data line 105 is located → masking process of the color resist layer CF (which may include three masks: red color resist R, green color resist G, and blue color resist B) → ⑤ masking process of the second insulating layer 112 → ⑥ masking process of the layer where the pixel electrode 102 is located. Figure 23 The masking process of the embodiment shown can be as follows: ① Masking process of the layer where the gate line 104 is located → ② Masking process of the active layer → ③ Masking process of the layer where the data line 105 is located → ④ Masking process of the layer where the second common electrode 106 is located → Masking process of the color resist layer CF (which may include three masks: red color resist R, green color resist G, and blue color resist B) → ⑤ Masking process of the second insulating layer 112 → ⑥ Masking process of the layer where the pixel electrode 102 is located. Figure 24 The number and sequence of mask processing steps in the illustrated embodiment can be compared with... Figure 22 or Figure 23 The embodiments shown are the same and will not be described again here.

[0084] Figure 25 For along Figure 18 Schematic diagram of the cross-sectional structure of line IV-IV'. Figure 26 For along Figure 18 A schematic diagram of the cross-sectional structure of the V-V' line, combined with... Figures 18 to 21 , Figure 25 and Figure 26As can be seen, this disclosure may also include a second common electrode line 110 of the same layer and material as the data line 105, and a shielding electrode 111 of the same layer and material as the pixel electrode 102. The second common electrode line 110 is electrically connected to the second common electrode 106 through the shielding electrode 111. Optionally, the shielding electrode 111 includes a first shielding electrode 1111 and a second shielding electrode 1112. In the direction Z perpendicular to the substrate 101, the first shielding electrode 1111 overlaps with the data line 105 to block dark-state light leakage. The second shielding electrode 1112 is disposed in the area between two adjacent rows of pixel electrodes 102. The second shielding electrode 1112 is electrically connected to the second common electrode line 110 and the second common electrode 106 to improve the uniformity of the common voltage signal, greatly optimize the recovery capability of the second common electrode, and improve image quality issues such as crosstalk. In some embodiments, two gate lines 104 are disposed between two adjacent rows of pixel electrodes 102, a second common electrode line 110 is disposed between two adjacent data lines 105, a second shielding electrode 1112 overlaps with at least one of the two gate lines 104, the second shielding electrode 1112 includes a widened portion WP, the widened portion WP overlaps with the second common electrode line 110 and is electrically connected through a second via V2, optionally, the second via V2 and the two gate lines 104 do not overlap.

[0085] Figure 27 for Figure 2 A parallel technical solution, Figure 27 and Figure 2 The difference lies in that the overlapping area of ​​adjacent color resists (e.g., red color resist R and green color resist G) is increased. The orthographic projection of the overlapping portion of adjacent color resists (e.g., red color resist R and green color resist G) on the substrate 101 covers the orthographic projection of the data line 105 on the substrate 101. In this way, the edge overlap of adjacent color resists can be used to block edge light leakage of the data line 105, thereby improving contrast. This disclosure can also appropriately reduce the linewidth of the data line 105, thereby reducing the parasitic capacitance of the data line 105 to the pixel electrode 102, improving image quality and pixel aperture ratio. Figure 27 The number and sequence of mask processing steps in the illustrated embodiment can be compared with... Figure 1 The embodiments shown are the same and will not be described again here.

[0086] It should be noted that, without conflict, the feature of increasing overlap area between adjacent color resists can be arbitrarily combined with the other aforementioned schemes, for example... Figure 28 To replace adjacent color resists with those having a larger overlapping area Figure 13 The solution obtained by color resist in the embodiment shown. Figure 28 The number and sequence of mask processing steps in the illustrated embodiment can be compared with... Figure 13 The embodiments shown are the same and will not be described again here.

[0087] Figure 29 A schematic diagram of the structure of the storage capacitor provided in the embodiments of this disclosure is shown below. Figure 29 As shown, the storage capacitor Cst of this disclosure can be formed by overlapping the second common electrode 106 and the pixel electrode 102. The storage capacitor Cst of related technologies includes a MIM capacitor composed of the first electrode of the transistor 101 and the common electrode line of the layer containing the gate line 104, which has a low aperture ratio. The storage capacitor Cst of this disclosure is composed of the second common electrode 106 and the pixel electrode 102, which can omit the common electrode line of the layer containing the gate line 104 used to form the MIM capacitor, thereby maximizing the aperture ratio and improving transmittance. In some embodiments, such as in a UV2A panel design where the pixel electrode 102 is a block electrode and is aligned to ultraviolet light, the size of the storage capacitor Cst of this disclosure can be adjusted according to the charging requirements by changing the area of ​​the second common electrode 106. In an SUVA panel design where the pixel electrode 102 uses a slit electrode, the area of ​​the second common electrode 106, as well as the slit size and orientation of the pixel electrode 102, can be adjusted by comprehensively considering requirements such as charging, dark patterns, and color shift. In some embodiments, the actual area of ​​the second common electrode 106 can be adjusted by opening a central opening in the second common electrode 106 of a sub-pixel.

[0088] Figures 30 to 32 These are schematic diagrams illustrating another structural representation of 1*2 sub-pixels in a display panel provided in this embodiment of the present disclosure. Figure 33 for Figure 32 A schematic diagram of subpixel overlay dark patterns. (See diagram below.) Figures 30 to 33 As shown, this disclosure may also include a light-shielding electrode 113 of the same layer and material as the data line 105, which may be integrally formed with the second common electrode line 110. Optionally, the area where the pixel electrode 102 is located includes multiple domain regions (e.g., D1 to D4), which may be formed by ultraviolet light alignment and / or by slits with different orientations designed in the pixel electrode 102. The light-shielding electrode 113 may be disposed in the gap between the domain regions (e.g., D1 to D4) to block dark lines through metal, which can effectively improve the color shift caused by liquid crystal disorder in the dark line area leading to light leakage at a wide viewing angle. Figures 30 to 32 The number and sequence of mask processing steps in the illustrated embodiment can be compared with... Figure 1 , Figure 13 , Figure 22 , Figure 23 The embodiments shown are identical and will not be described in detail here.

[0089] See also Figures 31 to 33It is understood that the multiple domain regions disclosed herein may include a first domain region D1, a second domain region D2, a third domain region D3, and a fourth domain region D4. The first domain region D1 is close to the data line 105 and the transistor 103. The second domain region D2 is located on the side of the first domain region D1 away from the data line 105. The third domain region D3 is located on the side of the first domain region D1 away from the gate line 104. The fourth domain region D4 is located on the side of the second domain region D2 away from the gate line 104. The light-shielding electrode 113 may also be disposed at at least one of the edges of the first domain region D1 away from the third domain region D3, the second domain region D2 away from the first domain region D1, the third domain region D3 away from the fourth domain region D4, and the fourth domain region D4 away from the second domain region D2, so that the light-shielding electrode 113 can completely block the dark pattern as much as possible.

[0090] It should be noted that the color resist layer CF of this disclosure can be disposed not only in the array substrate 001 of the above embodiments, but also in the opposing substrate 002. In other words, the above-mentioned improvement scheme provided by the embodiments of this disclosure is not only applicable to COA panels with the color resist layer CF fabricated on the array substrate 001, but also applicable to non-COA panels with the color resist layer CF fabricated on the array substrate 001. For example Figure 34 To be Figure 13 The schematic diagram shows the structure of the color resist layer CF being moved from the array substrate 001 to the opposing substrate 002. Figure 35 To be Figure 15 The schematic diagram shows the structure of the color resist layer CF being moved from the array substrate 001 to the opposing substrate 002. Figure 36 To be Figure 19 The schematic diagram shows the structure of the color resist layer CF being moved from the array substrate 001 to the opposing substrate 002. Figure 37 To be Figure 19 The schematic diagram shows a structure where the color resist layer CF is moved from the array substrate 001 to the opposing substrate 002, and the first shielding electrode 1111 that overlaps with the data line 105 is not provided. It should be understood that the above... Figures 1 to 32 In the embodiment shown, the process after removing the color resist layer CF on the array substrate is the array substrate process for a non-COA panel.

[0091] Furthermore, the improvements provided in this disclosure are not only applicable to the dual-gate architecture, but also to the single-gate architecture. For example... Figure 38 for Figure 1 The illustrated embodiment is a structural diagram of a single-gate COA panel. Figure 38 A schematic diagram of the cross-sectional structure of line VI-VI' can be found here. Figure 2 ,For example Figure 39 for Figure 13 The illustrated embodiment is a structural diagram of a single-gate non-COA panel with the middle portion of the second common electrode 106 removed. Figure 40 For along Figure 39 Schematic diagram of the cross-sectional structure of line VII-VII' in the middle. Figure 41 For along Figure 38 and Figure 39 Schematic diagram of the cross-sectional structure of VIII-VIII'.

[0092] like Figure 38 , Figure 39 and Figure 41 As shown, in a single-gate architecture display panel, a first common electrode line 114, which is on the same layer, made of the same material, and adjacent to the gate line 104, can be provided. The second common electrode 106 and the first common electrode line 114 can be electrically connected through a third via V3. The connection position of the second common electrode 106 and the first common electrode line 114 (i.e., the third via V3) is also located within the notch structure GS of the gate line 104. Furthermore, the connection position of the second common electrode 106 and the first common electrode line 114 (i.e., the third via V3) and the connection position of the pixel electrode 102 and the first electrode d of the transistor 103 (i.e., the first via V1) overlap each other in the extension direction Y of the data line 105. This makes the wiring more compact and helps to improve the aperture ratio. Optionally, the second common electrode 106 and the first common electrode line 114 are electrically connected at the third via V3 through a transition electrode 115, which is on the same layer and made of the same material as the pixel electrode 102.

[0093] It is understood that the first common electrode line 114 of this disclosure is on the same layer as the gate line 104 and extends along the X direction of the gate line 104, and the second common electrode line 110 is on the same layer as the data line 105 and extends along the Y direction of the data line 105. Both are electrically connected to the second common electrode 106. In specific implementations, one or both can be set, and this disclosure does not make specific limitations.

[0094] In some embodiments, in the display panel provided in the present disclosure, such as Figures 1 to 12As shown, the gate g of transistor 103 can be integrally disposed with gate line 104, the second electrode s of transistor 103 can be integrally disposed with data line 15, and the second common electrode 106 can include a cutout structure OW that exposes transistor 103. The opposing substrate 002 may further include a black matrix 203. In the case where the data lines 105 between the second common electrode 106 and the adjacent pixel electrodes 102 arranged in the X direction along the gate line 104 overlap each other, and / or a first shielding electrode 1111 is provided that is in the same layer and material as the pixel electrode 102 and overlaps with the data lines 105 between the adjacent pixel electrodes 102 arranged in the X direction along the gate line 104, and / or the overlapping portion of the adjacent color resists (e.g., red color resist R and green color resist G) covers the data lines 105, at least one of the overlapping portion of the second common electrode 106, the first shielding electrode 1111, and the adjacent color resists (e.g., red color resist R and green color resist G) can play a light-shielding role. Therefore, the black matrix 203 may only be provided at the row gap of the pixel electrode 102, that is, the black matrix 203 is composed of a plurality of black matrix strips that extend in the X direction along the gate line 104 and are arranged in the Y direction along the data lines 105. Other conventional designs in the display panel are those that should be understood by a person skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0095] Based on the same inventive concept, this disclosure provides a display device, including the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).

[0096] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0097] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0098] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0099] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, comprising an array substrate and a counter substrate disposed opposite to each other, wherein, The array substrate includes: Substrate; The pixel electrode is located on one side of the substrate. A transistor, wherein the first electrode of the transistor is electrically connected to the pixel electrode; The gate line is electrically connected to the gate of the transistor. The gate line includes a notch structure that accommodates the first electrode connection position of the pixel electrode and the transistor. The notch structure is closed on the side near the pixel electrode. The opposing substrate includes a first common electrode on the side near the array substrate. In a direction perpendicular to the substrate, the first common electrode and the pixel electrode at least partially overlap.

2. The display panel as claimed in claim 1, wherein, The notch structure is a closed structure.

3. The display panel as claimed in claim 1, wherein, The notch structure is a groove structure with an opening on the side away from the pixel electrode.

4. The display panel as claimed in claim 3, wherein, The array substrate further includes a data line, a second common electrode, and a first common electrode line that is on the same layer as and adjacent to the gate line. The second common electrode is electrically connected to the first common electrode line. The connection position between the second common electrode and the first common electrode line is located within the notch structure. The connection positions between the second common electrode and the first common electrode line and the connection positions between the pixel electrode and the first electrode of the transistor overlap with each other in the data line extension direction.

5. The display panel as described in any one of claims 1 to 4, wherein, The array substrate further includes data lines and a second common electrode, wherein the orthographic projection of the second common electrode on the substrate does not overlap with the orthographic projection of the data line on the substrate in the region between two adjacent pixel electrodes along the extension direction of the gate line.

6. The display panel as claimed in claim 5, wherein, The array substrate further includes a transparent trace on the same layer as the second common electrode and in direct contact with the data line. The orthographic projection of the transparent trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate in the region between two adjacent pixel electrodes along the extension direction of the gate line.

7. The display panel as claimed in claim 6, wherein, In a cross-sectional direction perpendicular to the substrate, the transparent trace covers a first side, a second side, and a third side of the data line. The first side extends in the same direction as the substrate, the second side and the third side are opposite to each other, and the second side connects to the two ends of the first side.

8. The display panel as claimed in claim 7, wherein, The transparent trace is located between the data line layer and the substrate, and the orthographic projection of the data line on the substrate is within the orthographic projection of the transparent trace on the substrate.

9. The display panel according to any one of claims 1 to 4, wherein, The array substrate also includes a data line and a second common electrode, wherein the orthographic projection of the second common electrode on the substrate overlaps with the orthographic projection of the data line on the substrate.

10. The display panel as claimed in claim 5 or 9, wherein, The array substrate further includes a first insulating layer located on the side of the data line layer away from the substrate, and the second common electrode layer is located on the side of the first insulating layer away from the substrate.

11. The display panel as claimed in claim 10, wherein, The array substrate also includes a color resist layer on the side of the layer where the second common electrode is located away from the substrate and in direct contact with the second common electrode.

12. The display panel as claimed in claim 10, wherein, The array substrate further includes a color resist layer between the layer containing the second common electrode and the first insulating layer, and in direct contact with the second common electrode.

13. The display panel as claimed in claim 11 or 12, wherein, The color resist layer includes multiple color resists, the edges of adjacent color resists overlap each other, and the orthographic projection of the overlapping color resist edges on the substrate covers the orthographic projection of the data line on the substrate.

14. The display panel according to any one of claims 4 to 13, wherein, The second common electrode and the pixel electrode overlap to form a storage capacitor.

15. The display panel according to any one of claims 1 to 14, wherein, The array substrate further includes a data line, a second common electrode, a second common electrode line, and a shielding electrode, wherein the second common electrode line is on the same layer as the data line, the shielding electrode is on the same layer as the pixel electrode, and the second common electrode line is electrically connected to the second common electrode through the shielding electrode.

16. The display panel as claimed in claim 15, wherein, The shielding electrode includes a first shielding electrode and a second shielding electrode. In a direction perpendicular to the substrate, the first shielding electrode overlaps with the data line, and the second shielding electrode is disposed in the region between two adjacent rows of pixel electrodes. The second shielding electrode is electrically connected to the second common electrode line and the second common electrode.

17. The display panel as claimed in claim 16, wherein, Two gate lines are disposed between adjacent pixel electrode rows, and a second common electrode line is disposed between two adjacent data lines. The second shield electrode overlaps with at least one of the two gate lines. The second shield electrode includes a widened portion, which overlaps with the second common electrode line and achieves electrical connection.

18. The display panel according to any one of claims 1 to 17, wherein, The array substrate also includes data lines and light-shielding electrodes on the same layer as the data lines. The area where the pixel electrode is located includes multiple domain regions, and the light-shielding electrodes are disposed in the gaps between the domain regions.

19. The display panel as claimed in claim 18, wherein, The plurality of domain regions include a first domain region, a second domain region, a third domain region, and a fourth domain region, wherein the first domain region is close to the data line and the transistor, the second domain region is located on the side of the first domain region away from the data line, the third domain region is located on the side of the first domain region away from the gate line, and the fourth domain region is located on the side of the second domain region away from the gate line. The light-shielding electrode is also disposed at at least one of the following: the edge of the first domain region away from the third domain region; the edge of the second domain region away from the first domain region; the edge of the third domain region away from the fourth domain region; and the edge of the fourth domain region away from the second domain region.

20. The display panel as claimed in claim 18 or 19, wherein, The array substrate also includes a second common electrode line on the same layer as the data line, and the light-shielding electrode is integrally disposed with the second common electrode line.

21. A display device, wherein, It includes a display panel as described in any one of claims 1 to 20, and a backlight module located on the light-incident side of the display panel.

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