Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate; the plurality of grid lines and the plurality of data lines are arranged on the substrate in a different-layer crossing manner; the insulating layer is located on the substrate, and the insulating layer comprises a via hole; the spacer is located on the side, away from the substrate, of the insulating layer, and the orthographic projection of the spacer on the substrate and the orthographic projection of the via hole on the substrate are not overlapped; the via hole is at least partially filled with the insulating component, the surface of the side, away from the substrate, of the insulating component is located on the side, close to the substrate, of the surface of the side, away from the substrate, of the spacer, and the spacer and the insulating component are arranged to be overlapped with an area defined by one sub-pixel; and one sub-pixel correspondingly displays the same color and is driven by the same grid line and the same data line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Utility Model Content

[0003] The array substrate, display panel, and display device disclosed herein can improve the uniformity of the alignment layer while ensuring that there is no problem of poor support within the cell.

[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, embodiments of this disclosure provide an array substrate, including:

[0006] Substrate;

[0007] Multiple gate lines and multiple data lines are arranged in a cross-layer configuration on the substrate.

[0008] An insulating layer is located on the substrate, and the insulating layer includes vias;

[0009] A spacer is located on the side of the insulating layer away from the substrate, and the orthographic projection of the spacer on the substrate does not overlap with the orthographic projection of the via on the substrate.

[0010] An insulating member, at least partially filling the via, wherein the surface of the insulating member away from the substrate is located on the side of the spacer away from the substrate and close to the substrate, the spacer and the insulating member being disposed to overlap with an area defined by a sub-pixel, the sub-pixel corresponding to display the same color and being driven by the same gate line and the same data line.

[0011] In some embodiments, in the array substrate provided in the present disclosure, the spacer includes an auxiliary spacer, and in a direction perpendicular to the substrate, the distance between the surface of the auxiliary spacer away from the substrate and the surface of the insulating member away from the substrate is greater than or equal to a preset value.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the spacer includes a main spacer, and the surface of the main spacer away from the substrate is located on the side of the auxiliary spacer away from the substrate.

[0013] In some embodiments, in the array substrate provided in the present disclosure, the insulating member and the spacer are disposed in the same layer.

[0014] In some embodiments, the array substrate provided in this disclosure further includes pixel electrodes, transistors, and common electrode lines;

[0015] The sub-pixel includes every two adjacent pixel electrodes arranged along the data line direction, the two pixel electrodes being a first pixel electrode and a second pixel electrode, the via includes a first via and a second via, the gate line includes a first gate line and a second gate line, and the transistor includes a first transistor, a second transistor, and a third transistor;

[0016] The gate of the first transistor is electrically connected to the first gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first pixel electrode through the first via.

[0017] The gate of the second transistor is shared with the gate of the first transistor, the first electrode of the second transistor is shared with the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second pixel electrode through the second via.

[0018] The gate of the third transistor is electrically connected to the second gate line. The first electrode of the third transistor is shared with the second electrode of the first transistor. The second electrode of the third transistor overlaps with the common electrode line but does not overlap with the first pixel electrode.

[0019] In some embodiments, in the array substrate provided in the present disclosure, the insulating member includes a first insulating member and a second insulating member disposed at intervals, the first insulating member fills the first via, and the orthographic projection of the first insulating member on the substrate overlaps with the orthographic projection of the second gate line on the substrate, the second insulating member fills the second via, and the orthographic projection of the second insulating member on the substrate overlaps with the orthographic projection of the first gate line on the substrate.

[0020] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the first insulating member on the substrate overlaps with the orthographic projection of the common electrode line adjacent to the second gate line on the substrate, and the orthographic projection of the second insulating member on the substrate overlaps with the orthographic projection of the common electrode line adjacent to the first gate line on the substrate.

[0021] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the spacer on the substrate overlaps with the orthographic projections of the first gate line and the second gate line on the substrate.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the spacers include a main spacer and an auxiliary spacer. The orthographic projection of the main spacer on the substrate does not overlap with the orthographic projection of the second electrode of the third transistor on the substrate, while the orthographic projection of the auxiliary spacer on the substrate overlaps with the orthographic projection of the second electrode of the third transistor on the substrate.

[0023] In some embodiments, in the array substrate provided in the present disclosure, the sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels, and the spacers include main spacers and auxiliary spacers. The main spacers are disposed at the gap between the first pixel electrode and the second pixel electrode of the blue sub-pixel; the auxiliary spacers are disposed at the gap between the first pixel electrode and the second pixel electrode of the red sub-pixel, and / or, the auxiliary spacers are disposed at the gap between the first pixel electrode and the second pixel electrode of the green sub-pixel.

[0024] In some embodiments, the array substrate provided in this disclosure further includes a transition electrode, and the via further includes a third via. The transition electrode spans the first gate line and the second gate line and is electrically connected to the common electrode line through the third via.

[0025] On the other hand, this disclosure provides a display panel including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.

[0026] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate includes a red color resist, a green color resist, and a blue color resist. The thickness of the red color resist is approximately the same as the thickness of the green color resist, and the thickness of the red color resist is less than the thickness of the blue color resist.

[0027] The spacer includes a main spacer and an auxiliary spacer. The distance between the surface of the auxiliary spacer away from the substrate and the surface of the insulating member away from the substrate is greater than or equal to the thickness difference between the blue color resist and the red color resist. The main spacer is in contact with the blue color resist.

[0028] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel.

[0029] On the other hand, this disclosure provides a method for manufacturing the above-mentioned array substrate, including:

[0030] Provide a substrate;

[0031] An insulating layer including vias is formed on the substrate.

[0032] A spacer is formed that does not overlap with the via, and an insulating member is formed that at least partially fills the via, wherein the surface of the insulating member away from the substrate is located on the side of the surface of the spacer away from the substrate that is close to the substrate.

[0033] In some embodiments, the manufacturing method described above, which is provided in this disclosure, includes forming a spacer that does not overlap with the via and an insulating member that at least partially fills the via, specifically comprising:

[0034] A grayscale photomask is used to form a spacer that does not overlap with the via and an insulating member that at least partially fills the via. The grayscale photomask has a plurality of first light-transmitting areas for forming one insulating member, a grayscale photomask has a second light-transmitting area for forming one spacer, and the plurality of first light-transmitting areas corresponding to one insulating member are arranged side by side or interconnected to form a grid light-transmitting area.

[0035] In some embodiments, the above-described manufacturing method provided in this disclosure, while using a grayscale photomask to form a spacer that does not overlap with the via and an insulating member that at least partially fills the via, further includes: superimposing a semi-transparent photomask to form a spacer that does not overlap with the via and an insulating member that at least partially fills the via, wherein the semi-transparent photomask has a semi-transparent film in the first light-transmitting area and is hollowed out in the second light-transmitting area.

[0036] The beneficial effects of this utility model are as follows:

[0037] The array substrate, display panel, and display device provided in this disclosure include a substrate; multiple gate lines and multiple data lines, which are interleaved on the substrate; an insulating layer located on the substrate, the insulating layer including vias; spacers located on the side of the insulating layer away from the substrate, the orthographic projection of the spacers on the substrate not overlapping with the orthographic projection of the vias on the substrate; and an insulating member that at least partially fills the vias, the surface of the insulating member away from the substrate located on the side of the surface of the spacers away from the substrate closer to the substrate, the spacers and the insulating member overlapping an area defined by a sub-pixel, the sub-pixel displaying the same color and driven by the same gate line and the same data line. This disclosure can improve the uniformity of the alignment layer while ensuring no poor support within the cell. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of three sub-pixels in the array substrate;

[0039] Figure 2 For along Figure 1 A spliced ​​diagram of lines I-I' and II-II' in the middle;

[0040] Figure 3 for Figure 1 Schematic diagram of the structure of the layer containing the middle grid lines;

[0041] Figure 4 for Figure 1 A schematic diagram of the active layer structure;

[0042] Figure 5 for Figure 1 A schematic diagram of the structure of the layer where the data cable is located;

[0043] Figure 6 for Figure 1 Schematic diagram of the structure of the layer containing the via;

[0044] Figure 7 for Figure 1 A schematic diagram of the structure of the layer containing the middle pixel electrode;

[0045] Figure 8 for Figure 1 Schematic diagram of the structure of the layer containing the partition pad;

[0046] Figure 9 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of this disclosure;

[0047] Figure 10 A schematic diagram of a structure corresponding to an insulating component for a grayscale photomask provided in an embodiment of this disclosure;

[0048] Figure 11 This is another structural schematic diagram of a grayscale photomask corresponding to an insulating component provided in an embodiment of this disclosure;

[0049] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0050] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0052] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0053] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0054] In TFT-LCD display products, defects such as uneven alignment layer (PI) film thickness or non-adhesion of the alignment layer often exist at the vias of the insulating layer, leading to display anomalies such as bright spots, moiré patterns, and trace mura. In some embodiments, sub-spacers can be used to cover the vias, making the surface of the alignment layer to be formed planar. This prevents the alignment liquid from accumulating in the vias during the alignment layer fabrication process, resulting in a more uniform thickness of the final alignment layer, thereby effectively improving display anomalies such as bright spots, moiré patterns, and trace mura. However, the thickness of the red color resist can be equal to that of the green color resist but less than that of the blue color resist. As a result, the sub-spacers at the blue color resist location will contact the color filter substrate (also known as the opposing substrate) earlier than the sub-spacers at the red and green color resist locations, causing poor support within the cell.

[0055] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 This is a schematic diagram of the structure of three sub-pixels in the array substrate. Figure 2 For along Figure 1A spliced ​​diagram of lines I-I' and II-II'. Figures 3 to 8 for Figure 1 Schematic diagrams of the structures of different membrane layers. (e.g.) Figures 1 to 8 As shown, the array substrate of this disclosure may include:

[0056] The substrate 101 may optionally be a substrate that allows visible light to pass through, such as a material made of glass, quartz, or plastic.

[0057] Multiple gate lines 102 and multiple data lines 103 are arranged in a cross-layer configuration on the substrate 101. Optionally, the materials of the gate lines 102 and data lines 103 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate lines 102 and data lines 103 may be single-layer structures or multilayer structures. For example, the gate lines 102 may be a single-layer structure composed of a copper metal layer, and the data lines 103 may be a single-layer structure composed of an aluminum metal layer.

[0058] An insulating layer 104 is located on the substrate 101 and includes vias (e.g., a first via V1, a second via V2, and a third via V3). In some embodiments, the insulating layer 104 includes a first insulating layer 1041, a second insulating layer 1042, and a third insulating layer 1043. The first via V1 and the second via V2 can be shallow holes penetrating the first insulating layer 1041 and the second insulating layer 1042, and the third via V3 is a deep hole penetrating the first insulating layer 1041, the second insulating layer 1042, and the third insulating layer 1043. The material of the first insulating layer 1041 can be organic insulating materials such as polyacrylic acid resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin. The materials of the second insulating layer 1042 and the third insulating layer 1043 can be inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0059] Spacer 105 is located on the side of insulating layer 104 away from substrate 101. The orthographic projection of spacer 105 on substrate 101 does not overlap with the orthographic projection of vias (e.g., first via V1, second via V2, third via V3) on substrate 101. Spacer 105 of this disclosure may include main spacer 1051 and auxiliary spacer 1052. When not pressed, main spacer 1051 is in contact with the opposing substrate, and auxiliary spacer 1052 is at a certain distance from the opposing substrate; when pressed, main spacer 1051 is compressed, and auxiliary spacer 1052 comes into contact with the opposing substrate.

[0060] The insulating member 106 at least partially fills the vias (e.g., the first via V1, the second via V2, and the third via V3). Figure 2The illustration shows an example where the insulating member 106 completely fills the via. In some embodiments, the surface of the insulating member 106 away from the substrate 101 is located on the side of the spacer 105 away from the substrate 101, close to the substrate 101. The spacer 105 and the insulating member 106 overlap with the area defined by a sub-pixel (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B). The sub-pixel (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B) displays the same color and is driven by the same gate line 102 and the same data line 103. This disclosure uses an insulating member 106 lower than the spacer 105 to at least partially fill the via (e.g., the first via V1, the second via V2, and the third via V3). This improves the uniformity of the alignment layer and prevents the insulating member 106 from contacting the opposing substrate before the spacer 105. Furthermore, the insulating member 106 may not have a supporting function when it is lower, thereby ensuring that there is no problem of poor support within the cell.

[0061] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 As shown, in the direction Z perpendicular to the substrate 101, the distance between the surface of the auxiliary spacer 1052 away from the substrate 101 and the surface of the insulating member 106 away from the substrate 101 can be greater than or equal to a preset value. The surface of the main spacer 1051 away from the substrate 101 is located on the side of the auxiliary spacer 1052 away from the substrate 101, which corresponds to the heights of the insulating member 106, the auxiliary spacer 1052, and the main spacer 1051 increasing sequentially in this disclosure.

[0062] In some embodiments, the distance between the insulating member 106 filling the shallow holes (i.e., the first via V1 and the second via V2) and the auxiliary spacer 1052 in the Z direction is D1, and the distance between the insulating member 106 filling the deep holes (i.e., the third via V3) and the auxiliary spacer 1052 in the Z direction is D2. The thickness difference between the blue and red color resists is ΔD. Optionally, D1 is greater than or equal to ΔD and less than D2. This ensures that during the pressure process, the insulating member 106 filling both the shallow and deep holes contacts the opposing substrate later than the supporting auxiliary spacer 1052, thus not affecting the supporting force within the liquid crystal panel.

[0063] In some embodiments, in the array substrate provided in the present disclosure, the insulating member 106 can be disposed in the same layer and with the same material as the spacer 105, so that the same film-forming process can be used to form the film layer for making the insulating member 106 and the spacer 105, and then the insulating member 106 and the spacer 105 can be formed in one patterning process using the same mask. Therefore, the patterning process of the insulating member 106 is avoided separately, which helps to improve production efficiency.

[0064] In some embodiments, in the array substrate provided in the present disclosure, such as Figures 1 to 8 As shown, it may also include pixel electrodes 107, transistors 108, and common electrode lines 109. Optionally, the common electrode lines 109 and gate lines 102 are disposed on the same layer and made of the same material, and the edges of the common electrode lines 109 and pixel electrodes 107 overlap to form a storage capacitor. The common electrode lines 109 overlapping the pixel electrodes 107 in the same row can be integrally disposed, thereby reducing the overall resistance of the common electrode lines 109. The common electrode lines 109 may also overlap only with the edges of the data lines 103 between two adjacent pixel electrodes 107 in the same row, in order to reduce the load on the data lines 103. Sub-pixels (e.g., red sub-pixel R, green sub-pixel G, and blue sub-pixel B) may include every two adjacent pixel electrodes 107 arranged along the Y direction of the data lines 103. These two pixel electrodes 107 may be the first pixel electrode 1071 and the second pixel electrode 1072, respectively. The gate lines 102 may include the first gate line 1021 and the second gate line 1022. The transistors 108 include the first transistor T1, the second transistor T2, and the third transistor T3.

[0065] In this configuration, the gate g1 of the first transistor T1 is electrically connected to the first gate line 1021, the first electrode s1 of the first transistor T1 is electrically connected to the data line 103, and the second electrode d1 of the first transistor T1 is electrically connected to the first pixel electrode 1071 through a first via V1. Optionally, the second electrode d1 of the first transistor T1 includes a horizontal portion extending along the X direction of the gate line 102. This horizontal portion is provided with a first via V1 to achieve electrical connection with the first pixel electrode 1071, and this horizontal portion overlaps with the first pixel electrode 1071, the common electrode line 109, and the first insulating member 1061. The gate g2 of the second transistor T2 is shared with the gate g1 of the first transistor T1, the first electrode s2 of the second transistor T2 is shared with the first electrode s1 of the first transistor T1, and the second electrode d2 of the second transistor T2 is electrically connected to the second pixel electrode 1072 through a second via V2. The active layer a2 of transistor T2 is shared with the active layer a1 of the first transistor T1. Optionally, the second electrode d2 of the second transistor T2 includes a horizontal portion extending along the X direction of the gate line 102. The horizontal portion is provided with a second via V2 to achieve electrical connection with the second pixel electrode 1072. The horizontal portion overlaps with the second pixel electrode 1072, the common electrode line 109, and the second insulating member 1062. The gate g3 of the third transistor T3 is electrically connected to the second gate line 1022. The first electrode s3 of the third transistor T3 is shared with the second electrode d1 of the first transistor T1. The second electrode d3 of the third transistor T3 overlaps with the common electrode line 109 but does not overlap with the first pixel electrode 1071. The materials of the active layer a3 of the third transistor T3, the active layer a1 of the first transistor T1, and the active layer a2 of the second transistor T2 include, but are not limited to, amorphous silicon, polycrystalline silicon, indium gallium zinc oxide, etc.

[0066] In this disclosure, the first transistor T1 charges the first pixel electrode 1071, the second transistor T2 charges the second pixel electrode 1072, and the third transistor T3 releases part of the charge of the first pixel electrode 1071 into the capacitor formed by the overlap of the second electrode d3 of the third transistor T3 and the common electrode line 109. This results in the brightness of the first pixel electrode 1071 being lower than the brightness of the second pixel electrode 1072, enabling different brightness areas within the same sub-pixel (e.g., red sub-pixel R, green sub-pixel G, and blue sub-pixel B), thereby improving color shift and enhancing the display effect. Optionally, in this embodiment, the second electrode of the third transistor T3 can also be electrically connected to a discharge line, which can pass through the central region of the first pixel electrode. By setting the discharge line, the display brightness of the area corresponding to the first pixel electrode is lower than the brightness of the display area corresponding to the second pixel electrode, improving color shift and enhancing the display effect.

[0067] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 1 , Figure 3 and Figure 6 As shown, the insulating member 106 may include a first insulating member 1061 and a second insulating member 1062 spaced apart. The first insulating member 1061 fills the first via V1, and the orthographic projection of the first insulating member 1061 on the substrate 101 overlaps with the orthographic projection of the second gate line 1022 on the substrate 101. The orthographic projection of the first insulating member 1061 on the substrate 101 may also overlap with the orthographic projection of the common electrode line 109 adjacent to the second gate line 1022 on the substrate 101. The second insulating member 1062 fills the second via V2, and the orthographic projection of the second insulating member 1062 on the substrate 101 overlaps with the orthographic projection of the first gate line 1021 on the substrate 101. The orthographic projection of the second insulating member 1062 on the substrate 101 may also overlap with the orthographic projection of the common electrode line 109 adjacent to the first gate line 1021 on the substrate 101. This ensures that the first insulating member 1061 covers the first via V1 and the second insulating member 1062 covers the second via V2, thereby preventing the alignment layer from accumulating in the first via V1 and the second via V2 and effectively improving the uniformity of the alignment layer thickness.

[0068] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 1 , Figure 3 , Figure 5 and Figure 8 As shown, the orthographic projections of the main spacer 1051 and the auxiliary spacer 1052 on the substrate 101 overlap with the orthographic projections of the first gate line 1021 and the second gate line 1022 on the substrate 101. Figure 2 As can be seen, in this disclosure, the cross-sections of both the main spacer 1051 and the auxiliary spacer 1052 can be trapezoidal structures that are narrower at the top and wider at the bottom. Therefore, this disclosure... Figure 1 and Figure 8 The orthographic projection of the main spacer 1051 on the substrate 101 is equivalent to the orthographic projection of the bottom of the main spacer 1051 on the substrate 101, and the orthographic projection of the auxiliary spacer 1052 on the substrate 101 is equivalent to the orthographic projection of the bottom of the auxiliary spacer 1052 on the substrate 101. Based on this, by setting the orthographic projections of the main spacer 1051 and the auxiliary spacer 1052 on the substrate 101 to overlap with the orthographic projections of the first gate line 1021 and the second gate line 1022 on the substrate 101, this disclosure can ensure that the bottoms of the main spacer 1051 and the auxiliary spacer 1052 are both relatively large, which is beneficial for providing stable support.

[0069] See also Figure 1 , Figure 3 , Figure 5 and Figure 8As can be seen, the orthographic projection of the main spacer 1051 on the substrate 101 does not overlap with the orthographic projection of the second electrode d3 of the third transistor T3 on the substrate 101. However, the orthographic projection of the auxiliary spacer 1052 on the substrate 101 overlaps with the orthographic projection of the second electrode d3 of the third transistor T3 on the substrate 101, which means that the bottom of the auxiliary spacer 1052 is larger than the bottom of the main spacer 1051. In this disclosure, the main spacer 1051 abuts against the opposing substrate when not pressed, and it is not easy for it to slip during the pressing process. Furthermore, the main spacer 1051 is set to have a smaller bottom, which helps to avoid interference between the main spacer 1051 and the insulating member 106 filling the third via V3. The auxiliary spacer 1052 does not contact the opposing substrate when it is not pressed, but only when it is pressed. The bottom of the auxiliary spacer 1052 is relatively large, which can effectively prevent the auxiliary spacer 1052 from sliding during the pressing process, thereby ensuring that the auxiliary spacer 1052 can provide effective support.

[0070] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 1 , Figure 7 and Figure 8 As shown, the main spacer 1051 can be disposed at the gap between the first pixel electrode 1071 and the second pixel electrode 1072 of the blue sub-pixel B; the auxiliary spacer 1052 can be disposed at the gap between the first pixel electrode 1071 and the second pixel electrode 1072 of the red sub-pixel R, and / or, the auxiliary spacer 1052 can be disposed at the gap between the first pixel electrode 1071 and the second pixel electrode 1072 of the green sub-pixel G. Considering that the blue resist is thicker than the red and green resists, the main spacer 1051 is placed in the gap between the first pixel electrode 1071 and the second pixel electrode 1072 of the blue sub-pixel B. The auxiliary spacer 1052 can be placed in the gap between the first pixel electrode 1071 and the second pixel electrode 1072 of the red sub-pixel R and / or the green sub-pixel G. This ensures that when not pressed, the main spacer 1051 is in contact with the blue resist, while the auxiliary spacer 1052 is not in contact with the red or green resists. When pressed, the main spacer 1051 is compressed, and the auxiliary spacer 1052 is in contact with the red and green resists, thereby achieving a stable support effect inside the box.

[0071] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 1 , Figure 3 , Figure 6 and Figure 8As shown, it may also include a transition electrode 110 of the same layer and material as the pixel electrode 107. The transition electrode 110 crosses the first gate line 1021 and the second gate line 1022 and is electrically connected to the common electrode line 109 through the third via V3, thereby forming a mesh structure in the common electrode line 109 and improving the uniformity of the common voltage signal. Optionally, the third via V3 is located in the blue sub-pixel B. Since blue contributes the least to the overall brightness, even if the third via V3 is located in the blue sub-pixel B, sacrificing part of the aperture ratio of the blue sub-pixel B, it is not easy to cause optical problems and has little impact on the display effect.

[0072] In some embodiments, the array substrate provided in the present disclosure may further include a common electrode (com). Optionally, within a sub-pixel, one of the common electrode and the pixel electrode is a block electrode, and the other is a slit electrode. In some embodiments, the common electrode may also be disposed on an opposing substrate, and the common electrode may be a planar electrode within the display area. Other essential components of the array substrate are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0073] Based on the same inventive concept, this disclosure provides a method for manufacturing the above-mentioned array substrate. Since the principle of this manufacturing method in solving the problem is similar to that of the above-mentioned array substrate in solving the problem, the implementation of the manufacturing method provided in this disclosure can refer to the implementation of the above-mentioned array substrate provided in this disclosure, and repeated details will not be described again.

[0074] In some embodiments, the method for fabricating the array substrate provided in this disclosure is as follows: Figure 9 As shown, the following steps may be included:

[0075] S901, Provide a substrate;

[0076] S902. An insulating layer including vias is formed on a substrate.

[0077] S903, forming a spacer that does not overlap with the via, and an insulating member that at least partially fills the via, wherein the surface of the insulating member away from the substrate is located on the side of the surface of the spacer away from the substrate that is close to the substrate.

[0078] In some embodiments, in the manufacturing method provided in this disclosure, step S903 forms a spacer that does not overlap with the via and an insulating member that at least partially fills the via. Specifically, a grayscale mask (GTM) can be used to pattern the spacer that does not overlap with the via and the insulating member that at least partially fills the via. In this case, a plurality of first light-transmitting areas of the grayscale mask are used to form an insulating member, a second light-transmitting area of ​​the grayscale mask is used to form a spacer, and a plurality of first light-transmitting areas corresponding to an insulating member are arranged in parallel or interconnected to form a grid light-transmitting area.

[0079] Figure 10 The diagram shows multiple first light-transmitting zones A arranged side by side to form an insulating member. Figure 11 This diagram illustrates multiple first light-transmitting areas A interconnected to form a grid of light-transmitting areas for forming an insulating component. In some embodiments, the exposure energy for forming the insulating component area can be controlled by adjusting the width of the shading area B and the first light-transmitting area A on the grayscale mask. This allows for the fabrication of insulating components of different heights under the same mask and exposure conditions (HT%). Simultaneously, the performance of grayscale masks of different sizes (W&L) at different apertures can be tested to confirm the stability of the insulating component and its coverage effect on vias. Finally, a grayscale mask capable of fabricating insulating components that cover vias and exhibit good stability is selected for production. Additionally, [the diagram shows the use of...]. Figure 11 The grid-like light-transmitting area can reduce the exposure area.

[0080] In some embodiments, in the fabrication method provided in this disclosure, while using a grayscale photomask to pattern and form spacers that do not overlap with the vias, and insulating components that at least partially fill the vias, a half-tone mask (HTM) can also be superimposed to pattern and form spacers that do not overlap with the vias, and insulating components that at least partially fill the vias. The half-tone mask has a semi-transparent film in the first light-transmitting area and is hollowed out in the second light-transmitting area. After the grayscale photomask is superimposed with the half-tone mask, the first light-transmitting area changes from fully transparent to semi-transparent, and the photoresist pattern at the insulating component is easier to peel off.

[0081] It should be noted that in the fabrication method provided in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the actual pattern to be formed during the fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0082] Based on the same inventive concept, embodiments of this disclosure provide a display panel, such as... Figure 12 As shown, the display includes an array substrate 001 and a counter substrate 002 placed opposite each other. The array substrate 001 is the array substrate 001 provided in the embodiments of this disclosure. The counter substrate 002 may include a substrate 201, a black matrix 202, and a color resist 203. The color resist 203 may include a red color resist CF-R, a green color resist CF-G, and a blue color resist CF-B. The thickness of the red color resist CF-R is approximately the same as the thickness of the green color resist CF-G, and the thickness of the red color resist CF-R is less than the thickness of the blue color resist CF-B. The distance D1 & D2 between the surface of the auxiliary spacer 1052 away from the substrate 101 and the surface of the insulating member 106 away from the substrate 101 is greater than or equal to the thickness difference ΔD between the blue color resist CF-B and the red color resist CF-R. The main spacer 1051 is in contact with the blue color resist CF-B. Since the principle of this display panel in solving the problem is similar to that of the array substrate in solving the problem, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be repeated. In some embodiments, the black matrix 202, the red color resist CF-R, the green color resist CF-G, and the blue color resist CF-B may also be disposed on the array substrate 001, and this disclosure does not make specific limitations.

[0083] In some embodiments, such as Figure 12 As shown, the display panel provided in this embodiment may further include a liquid crystal layer 003 between the array substrate 001 and the opposing substrate 002, a first polarizer 004 on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 on the side of the opposing substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0084] Based on the same inventive concept, embodiments of this disclosure provide a display device, such as... Figure 13 As shown, the present disclosure includes the display panel PNL provided in the embodiments described above, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, an edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0085] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, greater resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0086] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0087] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0088] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a display panel, comprising: a substrate; a plurality of gate lines and a plurality of data lines arranged in layers and crossing each other on the substrate; an insulating layer on the substrate, the insulating layer comprising a via hole; a spacer on a side of the insulating layer away from the substrate, a projection of the spacer on the substrate not overlapping with a projection of the via hole on the substrate; an insulating member at least partially filling the via hole, a surface of the insulating member on a side away from the substrate being located on a side of a surface of the spacer on a side away from the substrate close to the substrate, the spacer and the insulating member being arranged to overlap with a region defined by one sub-pixel corresponding to displaying the same color and being driven by the same gate line and the same data line.

2. The array substrate of claim 1, wherein, The spacer comprises a secondary spacer, a distance between a surface of the secondary spacer on a side away from the substrate and a surface of the insulating member on a side away from the substrate being greater than or equal to a preset value in a direction perpendicular to the substrate.

3. The array substrate of claim 2, wherein, The spacer comprises a primary spacer, a surface of the primary spacer on a side away from the substrate being located on a side of a surface of the secondary spacer on a side away from the substrate away from the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein, The insulating member is arranged in the same layer as the spacer.

5. The array substrate according to any one of claims 1 to 3, wherein, The display panel further comprises a pixel electrode, a transistor and a common electrode line. Each two adjacent pixel electrodes arranged along the data line direction, the two pixel electrodes being a first pixel electrode and a second pixel electrode respectively, the via hole comprising a first via hole and a second via hole, the gate line comprising a first gate line and a second gate line, the transistor comprising a first transistor, a second transistor and a third transistor. A gate of the first transistor is electrically connected to the first gate line, a first pole of the first transistor is electrically connected to the data line, and a second pole of the first transistor is electrically connected to the first pixel electrode through the first via hole. A gate of the second transistor shares the gate of the first transistor, a first pole of the second transistor shares the first pole of the first transistor, and a second pole of the second transistor is electrically connected to the second pixel electrode through the second via hole. A gate of the third transistor is electrically connected to the second gate line, a first pole of the third transistor shares the second pole of the first transistor, and a second pole of the third transistor overlaps with the common electrode line but does not overlap with the first pixel electrode.

6. The array substrate of claim 5, wherein, The insulating member comprises a first insulating member and a second insulating member arranged at intervals, the first insulating member filling the first via hole, and a projection of the first insulating member on the substrate overlapping with a projection of the second gate line on the substrate, the second insulating member filling the second via hole, and a projection of the second insulating member on the substrate overlapping with a projection of the first gate line on the substrate.

7. The array substrate of claim 6, wherein, The first insulating member is adjacent to the common electrode line, and the second insulating member is adjacent to the first gate line.

8. The array substrate of claim 6 or 7, wherein, The spacer overlaps the first gate line and the second gate line.

9. The array substrate of claim 8, wherein, The spacer includes a main spacer and an auxiliary spacer, the main spacer does not overlap the second electrode of the third transistor, and the auxiliary spacer overlaps the second electrode of the third transistor.

10. The array substrate of any of claims 6, 7, 9, wherein, The sub-pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the spacer includes a main spacer and an auxiliary spacer, the main spacer is arranged at the gap between the first pixel electrode and the second pixel electrode of the blue sub-pixel, the auxiliary spacer is arranged at the gap between the first pixel electrode and the second pixel electrode of the red sub-pixel, and / or the auxiliary spacer is arranged at the gap between the first pixel electrode and the second pixel electrode of the green sub-pixel.

11. The array substrate of any of claims 6, 7, 9, wherein, The via further includes a third via, and the transfer electrode is electrically connected to the common electrode line through the third via.

12. A display panel, wherein, The display panel includes the array substrate and an opposite substrate opposite to the array substrate.

13. The display panel of claim 12, wherein, The opposite substrate includes a red color resist, a green color resist, and a blue color resist, the thickness of the red color resist is substantially the same as the thickness of the green color resist, and the thickness of the red color resist is less than the thickness of the blue color resist. The spacer includes a main spacer and an auxiliary spacer, the distance between the surface of the auxiliary spacer away from the substrate and the surface of the insulating member away from the substrate is greater than or equal to the thickness difference between the blue color resist and the red color resist, and the main spacer is in contact with the blue color resist.

14. A display device, wherein, The display panel includes the array substrate and an opposite substrate opposite to the array substrate. The display panel includes the array substrate and an opposite substrate opposite to the array substrate.

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