Chip packaging structure and magnetic-core-free Hall type current sensor
By employing substrate surface mounting technology and insulating layers, the problem of unstable relative positions between the coreless Hall chip and the output copper busbar was solved, improving detection accuracy and system stability, and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2026-03-06
AI Technical Summary
The relative position between the coreless Hall chip and the output copper busbar is easily shifted by external factors, resulting in low detection accuracy and an increased probability of system failure.
By employing surface mount technology, the distance between the Hall chip and the output copper busbar can be flexibly adjusted by changing the substrate thickness. Combined with surface mount pads, insulating layers, and resistive components, the relative position is ensured to be stable, avoiding the use of traditional connectors.
The detection accuracy of the coreless Hall chip in the vertical direction of the copper busbar has been improved, the influence of external factors on the detection accuracy has been reduced, the manufacturing process has been simplified, and the robustness of the system has been enhanced.
Smart Images
Figure CN223979022U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of Hall effect detection technology, and in particular to a chip packaging structure and a coreless Hall effect current sensor. Background Technology
[0002] Coreless Hall effect sensors are widely used in the automotive industry, such as in wheel speed detection, electronic compasses, position sensing, and speed sensing. Coreless Hall effect detection is a method that uses the Hall effect principle to detect magnetic fields. It does not rely on a traditional magnetic core to concentrate or guide the magnetic field. Because no magnetic core is needed, the size of the sensor assembly can be reduced, making it suitable for space-constrained applications. In this method, the Hall sensor directly detects the magnetic field generated by a target object or detects changes in the magnetic field caused by the target object.
[0003] Parallel detection of coreless Hall elements refers to placing the coreless Hall chip parallel to the magnetic field source being measured (such as a copper busbar). The coreless Hall chip directly detects the magnetic field perpendicular to its plane and the direction of the current, thereby indirectly measuring the current passing through it. A common parallel detection scheme structure involves a main board and an output copper busbar placed parallel and spaced apart (usually requiring a minimum gap). A substrate is added between the main board and the output copper busbar to allow the coreless Hall chip to be surface-mounted onto the substrate and positioned downwards close to the output copper busbar. The main board and the substrate are connected via connectors or wires.
[0004] Although the aforementioned coreless Hall parallel detection scheme aims to improve detection sensitivity and accuracy by increasing the substrate to bring the coreless Hall chip as close as possible to the copper busbar, thereby reducing the attenuation and interference that the magnetic field generated by the copper busbar may encounter during propagation, the use of connectors in practical applications creates a long dimensional chain. This makes it easier for the relative position between the coreless Hall chip and the copper busbar to shift under the influence of external factors such as vibration and temperature changes. In addition, connectors also increase the probability of system failures, such as terminal short circuits and the introduction of foreign objects. As a result, the coreless Hall parallel detection scheme cannot further improve the detection accuracy in the vertical direction of the copper busbar. Utility Model Content
[0005] The main purpose of this invention is to propose a chip packaging structure and a coreless Hall current sensor, which aims to solve the problem of the coreless Hall chip being too far away from the output copper busbar, while improving its detection accuracy in the vertical direction of the copper busbar.
[0006] To achieve the above objectives, this utility model proposes a chip packaging structure, comprising:
[0007] Motherboard;
[0008] An output copper busbar is positioned opposite to and spaced from the motherboard in a first direction.
[0009] A substrate, the substrate being surface-mounted on the side of the main board near the output copper busbar; and
[0010] A coreless Hall effect chip is surface-mounted on the side of the substrate near the output copper busbar and spaced apart from the output copper busbar in the first direction.
[0011] In one embodiment, the chip packaging structure includes a copper plating connection structure, and the substrate has surface mount pads on the side close to the motherboard, and the side of the surface mount pads facing away from the substrate is soldered to the motherboard.
[0012] In one embodiment, the chip package structure includes a plurality of surface mount pads, which are spaced apart along the edge of the substrate.
[0013] In one embodiment, the output copper busbar has a length direction and a width direction, and the output copper busbar includes a first vertical segment, a narrowing segment and a second vertical segment connected sequentially in the length direction. The width of the narrowing segment gradually decreases from both ends to the middle in the length direction. The narrowing segment is spaced apart from the chip body of the coreless Hall chip in the first direction. The first direction is perpendicular to both the length direction and the width direction.
[0014] The coreless Hall chip also includes two Hall elements, which are spaced apart on the chip body along the length or width direction. The two Hall elements are used to detect the magnetic field strength at two different positions within the magnetic field of the output copper busbar.
[0015] In one embodiment, the output copper busbar has a central axis extending along the length direction;
[0016] The projections of the two Hall elements onto the output copper busbar along the first direction are symmetrically arranged about the axis to detect the magnetic field strength at two symmetrical positions within the magnetic field of the output copper busbar.
[0017] In one embodiment, the chip package structure further includes a resistive capacitor, which is surface-mounted on the side of the substrate near the output copper busbar.
[0018] In one embodiment, the chip package structure further includes an insulating layer that covers the outside of the output copper busbar.
[0019] In one embodiment, the insulating layer is a plastic-coated component or an insulating film.
[0020] In one embodiment, the chip package structure further includes an insulating component, which is surface-mounted on the motherboard near the output copper busbar and covers the outside of the coreless Hall chip.
[0021] This invention also provides a coreless Hall effect current sensor, comprising the chip packaging structure described above.
[0022] The chip packaging structure provided by this utility model, by surface-mounting the substrate onto the motherboard and surface-mounting the coreless Hall chip onto the substrate, allows for flexible adjustment of the distance between the coreless Hall chip and the output copper busbar by modifying the substrate thickness. This ensures that the sensing distance between the coreless Hall chip and the output copper busbar remains within a suitable range under different environments or conditions, thus adapting to different application requirements. The use of surface-mount technology and substrate allows for overall tolerances superior to traditional connector solutions, resulting in high vertical detection accuracy and facilitating the structural design between the output copper busbar and the coreless Hall chip. This helps to further reduce system gap dimensions and improve detection accuracy. In addition, the use of surface-mount technology not only avoids traditional spot welding and pressing processes, simplifying the manufacturing process, but also eliminates the need for connectors, thereby reducing the impact of external factors (such as vibration, temperature changes, etc.) on detection accuracy and the probability of system failure. This ensures the stability of the relative position between the chip and the copper busbar, improving system robustness. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0024] Figure 1 A schematic diagram of an embodiment of the chip packaging structure provided by this utility model;
[0025] Figure 2 A schematic diagram of another embodiment of the chip packaging structure provided by this utility model.
[0026] Explanation of icon numbers:
[0027] 100. Chip packaging structure; 1. Motherboard; 2. Output copper busbar; 21. First vertical section; 22. Narrowing section; 23. Second vertical section; 3. Substrate; 4. Coreless Hall chip; 41. Hall element; 5. Surface mount pad; 6. Insulating layer; 61. Plastic coating.
[0028] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present utility model.
[0030] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0031] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0032] This utility model proposes a chip packaging structure 100.
[0033] Please see Figure 1 and Figure 2 In one embodiment of the present invention, the chip packaging structure 100 includes a motherboard 1, an output copper busbar 2, a substrate 3, and a coreless Hall chip 4. The output copper busbar 2 is opposite to and spaced apart from the motherboard 1 in a first direction. The substrate 3 is attached to the side of the motherboard 1 near the output copper busbar 2. The coreless Hall chip 4 is attached to the side of the substrate 3 near the output copper busbar 2 and is spaced apart from the output copper busbar 2 in the first direction.
[0034] The chip packaging structure 100 provided by this utility model, by surface-mounting the substrate 3 onto the motherboard 1 and surface-mounting the coreless Hall chip 4 onto the substrate 3, allows for flexible adjustment of the distance between the coreless Hall chip 4 and the output copper busbar 2 by modifying the thickness of the substrate 3 (manufacturers generally provide Hall circuit boards of different thicknesses). This ensures that the sensing distance between the coreless Hall chip 4 and the output copper busbar 2 remains within a suitable range under different environments or conditions, thus adapting to different application requirements. The use of surface-mount technology and substrate 3 allows for better overall tolerances than traditional connector solutions, resulting in high detection accuracy in the vertical direction and facilitating the structural design between the output copper busbar 2 and the coreless Hall chip 4. This helps to further reduce system gap dimensions and improve detection accuracy. In addition, the use of surface-mount technology (SMT) not only avoids traditional spot welding and crimping processes, simplifying the manufacturing process, but also eliminates the need for connectors, thereby reducing the impact of external factors (such as vibration, temperature changes, etc.) on detection accuracy and the probability of system failure. This ensures the stability of the relative position between the chip and the copper busbar, improving the robustness of the system.
[0035] It should be added that the coreless Hall chip 4 is a sensor based on the Hall effect. It can detect the strength and direction of a magnetic field. When current flows through the output copper busbar 2, a magnetic field is generated around the busbar. If the coreless Hall chip 4 is located near the output copper busbar 2, it will be affected by the magnetic field, thereby generating a Hall voltage. The magnitude of the Hall voltage is proportional to the strength of the magnetic field. Therefore, by measuring the Hall voltage, the current intensity in the output copper busbar 2 can be indirectly measured. In the above embodiment, the motherboard 1 includes a circuit board of any shape and size, as long as it is opposite to and spaced apart from the output copper busbar 2 in the first direction and can achieve electrical connection with the coreless Hall chip 4.
[0036] To further improve the stability of the chip packaging structure 100, in one embodiment, a surface mount pad 5 is provided on the side of the substrate 3 closest to the motherboard 1, and the side of the surface mount pad 5 facing away from the substrate 3 is soldered to the motherboard 1. In actual manufacturing, the size, shape, and position of the surface mount pad 5 on the substrate 3 need to be determined in advance, and an appropriate amount of solder paste is applied to the surface mount pad 5. The surface mount operation is performed through the soldering points reserved on the motherboard 1. The setting of the surface mount pad 5 provides a good electrical connection between the motherboard 1 and the substrate 3, reduces signal interference and resistance, and the solder joints after the surface mount process are firm, making the connection between the substrate 3 and the motherboard 1 more stable and suitable for vibration and shock environments.
[0037] Furthermore, in one embodiment, the chip package structure includes a plurality of surface mount pads 5, which are spaced apart along the edge of the substrate 3. The plurality of surface mount pads 5 facilitate connection with other electronic components or devices, ensuring a good electrical connection between the coreless Hall effect chip and the substrate 3, improving the flexibility and reliability of the connection, thereby enabling the chip to function normally. The specific number and layout of the surface mount pads 5 need to vary depending on the characteristics of the chip, packaging requirements, and application needs, but it is necessary to avoid poor soldering or component loss during reflow soldering.
[0038] In one embodiment, the output copper busbar 2 has a length direction and a width direction. The output copper busbar 2 includes a first vertical section 21, a narrowing section 22 and a second vertical section 23 connected sequentially in the length direction. The width of the narrowing section 22 gradually decreases from both ends to the middle in the length direction. The narrowing section 22 is spaced apart from the chip body of the coreless Hall chip 4 in a first direction. The first direction is perpendicular to both the length direction and the width direction. The coreless Hall chip 4 also includes two Hall elements 41. The two Hall elements 41 are spaced apart in the chip body along the length direction or the width direction. The two Hall elements 41 are used to detect the magnetic field strength at two different positions in the magnetic field of the output copper busbar 2. By setting a narrowing section 22 on the output copper busbar 2, the width of the copper busbar gradually decreases in the length direction, thereby increasing the current carrying area per unit length of the copper busbar and effectively improving the current density of the output copper busbar 2. When the current density increases, the current in the output copper busbar 2 also increases, which increases the electric field strength generated by the output copper busbar 2. Thus, when the two Hall elements 41 in the coreless Hall chip 4 detect the magnetic field on the output copper busbar 2, the detection sensitivity of the Hall elements 41 also increases due to the increase in electric field strength, thereby improving the detection accuracy.
[0039] To improve detection accuracy, in one embodiment, the projections of the two Hall elements 41 along the first direction onto the output copper busbar 2 are symmetrically arranged about the axis of symmetry of the mounting hole, so as to detect the magnetic field strength at two symmetrical positions within the magnetic field of the output copper busbar 2. This symmetrical arrangement helps to balance the signals detected by the two Hall elements 41, reducing errors caused by uneven copper busbar geometry or current distribution.
[0040] To further improve detection accuracy, in one embodiment, the output copper busbar 2 has a central axis extending along its length; the projections of two Hall elements 41 onto the output copper busbar 2 along a first direction are symmetrically arranged about the central axis to detect the magnetic field strength at two symmetrical positions within the magnetic field of the output copper busbar 2. Similarly, even without mounting holes, the two Hall elements 41 should be kept as symmetrically distributed as possible in the magnetic field. Symmetrical arrangement helps balance the signals detected by the two Hall elements 41, reducing errors caused by uneven copper busbar geometry or current distribution. For example, when the detection results are interfered with by external factors (such as temperature gradient, magnetic field gradient, etc.), the interference effects on the two elements are similar under a symmetrical structure. Therefore, interference can be eliminated through differential methods, thereby more accurately calculating and analyzing the magnetic field distribution, and thus improving the overall accuracy of magnetic field detection.
[0041] In one embodiment, the chip package structure 100 further includes a resistive capacitor component, which is surface-mounted on the side of the substrate 3 closest to the output copper busbar 2. The resistive capacitor component provides impedance and capacitance in the circuit, which helps to regulate the output signal of the coreless Hall chip 4, making it more stable and accurate. It can also effectively reduce noise and interference in the circuit, and improve signal quality and accuracy. Surface-mounting the resistive capacitor component on the substrate 3 allows for more efficient use of board space, enabling a more compact package design.
[0042] In one embodiment, the chip package structure 100 further includes an insulating component, which is surface-mounted on the side of the motherboard 1 near the output copper busbar 2 and covers the outer side of the coreless Hall chip 4. On one hand, the insulating component effectively isolates the electrical connection between the coreless Hall chip 4 and the output copper busbar 2, preventing short circuits and current leakage, and ensuring safe circuit operation. On the other hand, the insulating component also provides physical protection for the coreless Hall chip 4, reducing damage to the chip from external impacts or vibrations, improving the chip's durability and reliability, and helping to fix the position of the coreless Hall chip 4, preventing chip displacement due to vibration or other reasons. Simultaneously, the insulating component also provides a certain degree of thermal isolation, preventing the high temperature of the output copper busbar 2 from being directly transferred to the coreless Hall chip 4, helping to maintain the chip's operating temperature within its normal range. In practical use, the insulating component can be made of silicone or polyethylene material; alternatively, insulating materials with a certain electromagnetic shielding effect can be used to help reduce the impact of external electromagnetic interference on the coreless Hall chip 4.
[0043] In one embodiment, the chip package structure 100 further includes an insulating layer 6, which covers the outside of the output copper busbar 2. On one hand, the insulating layer 6 prevents short circuits between the output copper busbar 2 and other conductive components or signal lines on the circuit board, ensuring electrical safety. The insulating layer 6 also isolates the heat from the copper busbar, preventing direct heat transfer to other circuit components or the circuit board, thus helping to maintain the normal operating temperature of the circuit. On the other hand, the insulating layer 6 protects the output copper busbar 2 from environmental factors such as moisture, dust, and chemical corrosion, thereby extending the service life of the copper busbar and the entire package structure. The insulating layer 6 can be formed by a plastic-coated component 61 or by an adhesive insulating film. The plastic-coated insulating layer 6 forms a continuous protective layer around the copper busbar, providing comprehensive protection. It has high strength, heat resistance, and chemical resistance, making it suitable for copper busbars with complex shapes. Adhesive insulating films offer greater flexibility, are easier to operate, and are more cost-effective. They are suitable for copper busbars of different sizes and shapes, and different materials and thicknesses of insulating films can be selected according to requirements, making them suitable for small-batch production and scenarios requiring rapid replacement.
[0044] It should be added that, in the above embodiments, since the coreless Hall chip is susceptible to magnetic field interference, it is necessary to minimize the noise around the Hall, such as crosstalk or stray magnetic field effects caused by other metal devices. Crosstalk can be reduced by increasing the spacing of the output copper busbar 2. If the structural design cannot increase the spacing, crosstalk can be decoupled by software matrix. Alternatively, a shield can be added or the output copper busbar 2 can be designed as an S-bend to modify the direction of Hall detection and reduce crosstalk.
[0045] This utility model also provides a coreless Hall current sensor, including a chip package structure 100. The specific structure of the chip package structure 100 is as described in the above embodiments. Since the coreless Hall current sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.
[0046] The above description is merely an exemplary embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural transformations made based on the technical concept of the present utility model and the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.
Claims
1. A chip package structure, characterized by, The chip packaging structure comprises: a main board; an output copper strip opposite and spaced apart from the main board in a first direction; a substrate attached to a side of the main board close to the output copper strip; and a coreless Hall chip attached to a side of the substrate close to the output copper strip and spaced apart from the output copper strip in the first direction.
2. The chip package structure of claim 1, wherein, The substrate is a circuit board, and a surface-attached pad is arranged on a side of the circuit board close to the main board, and the surface-attached pad is welded to the main board from a side thereof away from the substrate.
3. The chip package structure of claim 2, wherein, The chip packaging structure comprises a plurality of surface-attached pads, and the plurality of surface-attached pads are spaced apart along an edge of the substrate.
4. The chip package structure of claim 1, wherein, The output copper strip has a length direction and a width direction, and comprises a first vertical segment, a narrowing segment and a second vertical segment connected in sequence in the length direction, wherein the width of the narrowing segment gradually decreases from both ends to the middle in the length direction, the narrowing segment is spaced apart from a chip body of the coreless Hall chip in the first direction, and the first direction is perpendicular to the length direction and the width direction. The coreless Hall chip further comprises two Hall elements, and the two Hall elements are arranged on the chip body in the length direction or the width direction, and the two Hall elements are used to detect the magnetic field strength at two different positions in the magnetic field of the output copper strip.
5. The chip package structure of claim 4, wherein, The output copper strip has a central axis extending in the length direction. The projections of the two Hall elements on the output copper strip in the first direction are symmetrically arranged about the axis to detect the magnetic field strength at two symmetric positions in the magnetic field of the output copper strip.
6. The chip package structure of any one of claims 1 to 5, wherein, The chip packaging structure further comprises a resistance-capacitance device attached to a side of the substrate close to the output copper strip.
7. The chip package structure of any one of claims 1 to 5, wherein, The chip packaging structure further comprises an insulating layer covering the outside of the output copper strip.
8. The chip package structure of claim 7, wherein, The insulating layer is a plastic-coated part or an insulating film.
9. The chip package structure of any one of claims 1 to 5, wherein, The chip packaging structure further comprises an insulating part attached to a side of the main board close to the output copper strip and covering the outside of the coreless Hall chip.
10. A coreless Hall effect current sensor, characterized by The chip packaging structure comprises any one of the chip packaging structures according to claims 1 to 9.