Array substrate and display device
By designing intersecting gate lines and data lines on the array substrate of the liquid crystal display panel and setting spaced common electrodes above the thin film transistors, the electric field shielding effect between adjacent pixel units is enhanced, solving the problems of color mixing and color gamut reduction caused by electric field crosstalk between adjacent pixels, and improving the display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-03-13
AI Technical Summary
In existing liquid crystal display panels, crosstalk between electric fields of adjacent pixels causes color mixing and a reduction in color gamut.
An array substrate is designed to define a pixel region by intersecting gate lines and data lines, and a common electrode is disposed above the thin-film transistors and data lines. The common electrode includes a plurality of first sub-electrodes arranged at intervals along a first direction. The spacing between adjacent pixel units and the size of the first sub-electrodes are increased to shield electric field crosstalk.
It effectively reduces electric field crosstalk between adjacent pixels, improves color mixing and color gamut reduction in the display panel, and enhances the display effect.
Smart Images
Figure CN223993035U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology
[0002] PCI (Plane-to-Line Inversion) is a liquid crystal driving technology mainly used in LCD (Liquid Crystal Display) panels such as IPS (In-Plane Switching) and ADS / FFS (Advanced Super Dimension Switch / Fringe Field Switching).
[0003] Currently, in PCI structure liquid crystal display panels, there are phenomena such as color mixing and color gamut reduction caused by crosstalk between adjacent pixel electric fields, which affect the display effect of the liquid crystal display panel. Utility Model Content
[0004] This application provides an array substrate and a display device, which aims to shield and shrink the electric field of adjacent pixels, reduce electric field crosstalk between adjacent pixels, and effectively improve defects such as color mixing and color gamut reduction in the display panel.
[0005] The first aspect of this application provides an array substrate, including:
[0006] Multiple gate lines and multiple data lines are intersected and define multiple pixel regions, each pixel region including a thin-film transistor;
[0007] The array substrate also includes a common electrode disposed above the thin-film transistor and the data line;
[0008] The common electrode includes a plurality of first sub-electrodes arranged at intervals along a first direction, wherein the orthographic projection of the first sub-electrodes on the array substrate at least partially overlaps with the orthographic projection of the data line on the array substrate.
[0009] In the first direction, the distance between the center points of two adjacent pixel units is the first distance, the distance between two adjacent first sub-electrodes is the second distance, and the value of the first distance is equal to the sum of the second distance and the size of one first sub-electrode.
[0010] Optionally, the common electrode further includes a plurality of second sub-electrodes, the second sub-electrodes extending along a second direction, the second sub-electrodes being disposed between two adjacent first sub-electrodes, and in the first direction, the distance between the second sub-electrodes and the adjacent first sub-electrodes is a third distance;
[0011] The value of the second spacing is equal to the sum of the dimensions of the two third spacings and the dimension of the second sub-electrode in the first direction;
[0012] The second direction is perpendicular to the first direction.
[0013] Optionally, the size of the third spacing is greater than or equal to 2.0 μm and less than or equal to 2.4 μm.
[0014] Optionally, the common electrode further includes a plurality of second sub-electrodes, which extend along a first direction and are disposed between two adjacent first sub-electrodes.
[0015] Optionally, the array substrate further includes a plurality of pixel electrodes disposed between the thin-film transistor and the common electrode;
[0016] In the orthographic projection of the substrate, the pixel electrode is located between two adjacent first sub-electrodes.
[0017] Optionally, in the first direction, the spacing between the pixel electrode and the adjacent first sub-electrode is a fourth spacing;
[0018] The size of the fourth spacing is greater than or equal to 0.3 μm.
[0019] Optionally, the size of the first spacing is less than 15 μm.
[0020] Optionally, the size of the second spacing is greater than or equal to 3.52 μm;
[0021] The array substrate further includes a plurality of pixel electrodes disposed between the substrate and the common electrode;
[0022] The spacing between two adjacent pixel electrodes in the first direction is greater than or equal to 5.4 μm.
[0023] Optionally, the common electrode further includes a plurality of second sub-electrodes, the second sub-electrodes extending along a second direction, the second sub-electrodes being disposed between two adjacent first sub-electrodes, and in the first direction, the distance between the second sub-electrodes and the adjacent first sub-electrodes is a third distance;
[0024] The array substrate further includes a plurality of pixel electrodes disposed between the thin-film transistor and the common electrode;
[0025] In the first direction, the spacing between the pixel electrode and the adjacent first sub-electrode is a fourth spacing;
[0026] The value of the third spacing is greater than the value of the fourth spacing.
[0027] This application implements a third aspect to provide a display device including a liquid crystal display panel, the liquid crystal display panel including the display panel provided in the first aspect of the embodiments of this application.
[0028] Beneficial effects:
[0029] This application provides an array substrate and a display device. The array substrate includes multiple intersecting gate lines and multiple data lines, which define multiple pixel regions. Each pixel region includes a thin-film transistor. The array substrate also includes a common electrode disposed above the thin-film transistor and the data lines. The common electrode includes multiple first sub-electrodes spaced apart along a first direction. The orthographic projection of the first sub-electrodes on the array substrate at least partially overlaps with the orthographic projection of the data lines on the array substrate. In the first direction, the distance between the center points of two adjacent pixel units is a first distance, and the distance between two adjacent first sub-electrodes is a second distance. The value of the first distance is equal to the sum of the second distance and the size of one first sub-electrode. This increases the size of the first sub-electrode itself in the first direction, thereby enhancing the electric field shielding effect between adjacent pixel units, reducing electric field crosstalk, and effectively improving defects such as color mixing and color gamut reduction in the display panel. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of a display panel for displaying the distribution of grid lines and data lines according to an embodiment of this application;
[0032] Figure 2 This is a schematic diagram of a planar structure of a display panel for displaying a common electrode and a pixel electrode, according to an embodiment of this application.
[0033] Figure 3 yes Figure 2 Schematic diagram of the structure of section a-a';
[0034] Figure 4 This is a schematic diagram of a display panel including a second sub-electrode extending along a first direction, according to an embodiment of this application.
[0035] Explanation of reference numerals in the attached figures: 11, gate line; 12, data line; 20, pixel area; 30, common electrode; 31, first sub-electrode; 32, second sub-electrode; 40, pixel electrode; L1, first pitch; L2, second pitch; L3, third pitch; L4, fourth pitch; X, first direction; Y, second direction. Detailed Implementation
[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0037] In related technologies, when the display panel is normally lit, the lit area can be roughly divided into adjacent sub-pixel area I, sub-pixel area II, and adjacent sub-pixel area III. Areas I, II, and III are independent sub-pixels, with corresponding color resists R, G, and B, respectively. They do not interfere with each other when lit, and each has its own independent voltage control unit.
[0038] In a typical solid-color display, when the liquid crystal in area II is driven by a voltage, sub-pixel area II is illuminated, while the adjacent sub-pixel areas I and III remain dark. However, with the increase in PPI (Pixel Per Inch) of existing products, the spacing between pixels has decreased, and the distance between pixel electrodes between adjacent pixels has also decreased. This leads to an increase in the electric field influence between adjacent pixels, causing color mixing or a reduction in color gamut in the display panel.
[0039] In view of this, embodiments of this application propose an array substrate and a display device, which aim to shield and shrink the electric field of adjacent pixels, reduce electric field crosstalk between adjacent pixels, and effectively improve defects such as color mixing and color gamut reduction in the display panel.
[0040] Reference Figure 1 As shown, an array substrate disclosed in an embodiment of this application is included. The array substrate includes a plurality of gate lines 11 and a plurality of data lines 12 arranged in a cross configuration. The gate lines 11 extend along a first direction X, and the data lines 12 extend along a second direction Y. The plurality of gate lines 11 and the plurality of data lines 12 arranged in a cross configuration define a plurality of pixel regions 20, and each pixel region 20 includes a thin-film transistor.
[0041] Specifically, this thin-film transistor can be used to control the transmission of light through pixel units. The thin-film transistor may include an active layer, a first gate insulating layer, a gate, a second gate insulating layer, an interlayer dielectric layer, a source, and a drain. Specifically, the active layer may be formed on a glass substrate, the first gate insulating layer covers the active layer, the gate is formed on the side of the first gate insulating layer opposite to the active layer, the second gate insulating layer covers the gate and the first gate insulating layer, the interlayer dielectric layer covers the second gate insulating layer, and the source and drain are formed on the side of the interlayer dielectric layer opposite to the glass substrate and located on opposite sides of the gate, respectively. The source and drain can contact the opposite sides of the active layer through vias (e.g., metal vias). Gate line 11 is disposed on the same layer as the gate, and data line 12 is disposed on the same layer as the source and drain.
[0042] Furthermore, referring to Figure 1 As shown, in the first direction X, the distance between the center points of two adjacent pixel units is the first distance L1.
[0043] The array substrate also includes a common electrode 30 disposed above the thin-film transistor and data line 12. It is understood that a corresponding insulating layer is disposed between the common electrode 30 and the thin-film transistor and data line 12, and the material of the insulating layer may include silicon nitride or silicon oxide, etc.
[0044] Reference Figure 2 and Figure 3 As shown, the common electrode 30 includes a plurality of first sub-electrodes 31, which are spaced apart along a first direction X and extend along a second direction Y. The orthographic projection of the first sub-electrodes 31 on the array substrate at least partially overlaps with the orthographic projection of the data line 12 on the array substrate; that is, the position of the first sub-electrodes 31 approximately corresponds to the data line 12. The first direction X is perpendicular to the second direction Y. The material of the common electrode 30 can be ITO (indium tin oxide).
[0045] Reference Figure 2 As shown, in the first direction X, the distance between two adjacent first sub-electrodes 31 is the second distance L2. In this embodiment, the value of the first distance L1 is equal to the sum of the second distance L2 and the size of one first sub-electrode 31. It can be understood that the value of the first distance L1 is a relatively fixed value, that is, in a specific type of array substrate, the first distance L1 between two adjacent pixel regions 20 is fixed. Therefore, in this embodiment, by reducing the value of the second distance L2, the size of the first sub-electrode 31 in the first direction X can be increased, thereby enhancing the electric field shielding between adjacent pixel units and reducing electric field crosstalk.
[0046] Reference Figure 2As shown, in one embodiment, the common electrode 30 further includes a plurality of second sub-electrodes 32 disposed between two adjacent first sub-electrodes 31. The second sub-electrodes 32 extend along a second direction Y and are used to form slits between two adjacent first sub-electrodes 31. The more slits there are, the higher the light efficiency of the liquid crystal. Furthermore, the dimension of the first sub-electrode 31 in the first direction X is larger than the dimension of the second sub-electrode 32 in the first direction X.
[0047] Reference Figure 2 As shown, in the first direction X, the distance between the second sub-electrode 32 and the adjacent first sub-electrode 31 is a third distance L3. In this embodiment, the value of the second distance L2 is equal to the sum of the dimensions of the two third distances L3 and the dimension of the second sub-electrode 32 in the first direction X. Specifically, in this embodiment, a second sub-electrode 32 is disposed between two adjacent first sub-electrodes 31. The second sub-electrode 32 extends along the second direction Y, that is, the second sub-electrode 32 is parallel to the first sub-electrode 31, and the distance between the second sub-electrode 32 and the first sub-electrodes 31 on both sides is the third distance L3.
[0048] In this embodiment, the dimension of the third spacing L3 is greater than or equal to 2.0 μm and less than or equal to 2.4 μm. It should be noted that the first sub-electrode 31 and the second sub-electrode 32 are formed in the same mask process. To further increase the dimension of the first sub-electrode 31 in the first direction X, the dimension of the third spacing L3 needs to be a limit value in the process. Therefore, the dimension of the third spacing L3 can be 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, etc. Meanwhile, under the limit value of this process, the dimension of the second sub-electrode 32 in the first direction X is 2.0 μm.
[0049] Reference Figure 2 As shown in the embodiment of this application, the array substrate further includes a plurality of pixel electrodes 40 disposed between the thin film transistor and the common electrode 30, and in the orthographic projection of the substrate, the pixel electrodes 40 are located between two adjacent first sub-electrodes 31.
[0050] Specifically, an insulating layer is also provided between the pixel electrode 40 and the common electrode 30. Each pixel region 20 has a corresponding pixel electrode 40, which is connected to the drain of the thin-film transistor so that the pixel electrode 40 can drive the corresponding pixel unit to transmit light. The material of the pixel electrode 40 can be ITO (indium tin oxide).
[0051] It is understandable that the pixel electrode 40 is actually a solid structure, but the pixel electrode 40 and the common electrode 30 are located in different film layers, and the common electrode 30 is located above the pixel electrode 40. Therefore, in Figure 2In the planar diagram, the pixel electrode 40 is represented by a dashed line.
[0052] It should be noted that by reducing the size of the pixel electrode 40 in the first direction X to increase the gap size between two adjacent pixel electrodes 40, the electric field between pixel units can be contracted, thereby reducing crosstalk between pixel units.
[0053] Therefore, referring to Figure 2 As shown in this embodiment, in the first direction X, the distance between the pixel electrode 40 and the adjacent first sub-electrode 31 is a fourth distance L4, and the size of the fourth distance L4 is greater than or equal to 0.3 μm. The fourth distance L4 between the pixel electrode 40 and the adjacent first sub-electrode 31 refers to the distance between the orthographic projection line of the edge of the pixel electrode 40 near the first sub-electrode 31 on the array substrate and the orthographic projection line of the edge of the first sub-electrode 31 near the pixel electrode 40 on the array substrate. By controlling the value of the fourth distance L4, the light-emitting effect of the pixel unit can be maintained without affecting the optimal electric field shielding effect.
[0054] In one embodiment, the size of the third spacing L1 is larger than the size of the fourth spacing L4, thereby ensuring optimal electric field shielding effect without affecting the light emission effect of the pixel unit.
[0055] In one embodiment, the size of the first spacing L1 is less than 15 μm. Exemplarily, the size of the first spacing L1 is 8 μm, 10 μm, 12 μm, 14 μm, etc.
[0056] In one embodiment, the size of the first spacing L1 is 10.32 μm. Furthermore, in this embodiment, the size of the second spacing L2 is greater than or equal to 3.52 μm, and the size of the gap between two adjacent pixel electrodes 40 in the first direction X is greater than or equal to 5.4 μm.
[0057] In one embodiment, reference is made to... Figure 4 As shown, the common electrode 30 includes a plurality of second sub-electrodes 32, which extend along the first direction X, and a plurality of second sub-electrodes 32 are disposed between two adjacent first sub-electrodes 31.
[0058] Specifically, in this embodiment, the dimensions of the second sub-electrode 32 in the second direction Y and the dimensions of two adjacent second sub-electrodes 32 in the second direction Y both satisfy the process limits. That is, the dimension limit of the second sub-electrode 32 in the second direction Y is 2.0 μm, and the dimension limit of two adjacent second sub-electrodes 32 in the second direction Y is greater than or equal to 2.0 μm and less than or equal to 2.4 μm. By changing the extension direction of the second sub-electrode 32, the spacing between two adjacent first sub-electrodes 31 can be made unrestricted, i.e., not limited by the process limits. At this time, the dimension of the first sub-electrode 31 in the first direction X can be enlarged, thereby achieving the effect of shielding adjacent electric fields.
[0059] In related technologies, the first sub-electrode 31 and the second sub-electrode 32 are manufactured using the same mask process. However, due to process limitations, the dimensions of the second sub-electrode 32 in the first direction X and the third distance L3 between the second sub-electrode 32 and the adjacent first sub-electrode 31 have limit values. Once the limit values are reached, the dimensions of the first sub-electrode 31 in the first direction X cannot be increased further.
[0060] Therefore, in one embodiment, to increase the size of the first sub-electrode 31 in the first direction X, the fabrication method of the common electrode 30 can also be changed. Specifically, the first sub-electrode 31 and the second sub-electrode 32 can be formed using two mask processes. That is, in the first mask process, multiple first sub-electrodes 31 are formed first; then in the second mask process, a second sub-electrode 32 is formed between two adjacent first sub-electrodes 31. In this way, the size of the second sub-electrode 32 and the third distance L3 between the second sub-electrode 32 and the first sub-electrode 31 are not limited by the equipment, that is, the size of the second sub-electrode 32 and the third distance L3 between the second sub-electrode 32 and the first sub-electrode 31 can be made smaller, thereby increasing the size of the first sub-electrode 31 in the first direction X, so as to shield the electric field between adjacent pixel units.
[0061] Based on the same inventive concept, embodiments of this application disclose a display panel, including any of the array substrates described above in the embodiments of this application.
[0062] Specifically, the display panel 10 in the embodiments of this application can also be a liquid crystal display panel. This application does not limit the type of display panel. It can be a vertical electric field type liquid crystal display panel, such as a twisted nematic (TN) type liquid crystal display panel or a multi-domain vertical alignment (MVA) type liquid crystal display panel. It can also be a horizontal electric field type liquid crystal display panel, such as a fringe field switching (FFS) type liquid crystal display panel or an in-plane switching (IPS) type liquid crystal display panel.
[0063] Based on the same inventive concept, embodiments of this application disclose a display device, including any of the display panels described above in the embodiments of this application.
[0064] Specifically, the display device may include computer monitors, televisions, billboards, laser printers with display functions, telephones, mobile phones, personal digital assistants (PDAs), laptops, digital cameras, portable camcorders, viewfinders, vehicles, large walls, theater screens, or stadium signs, etc.
[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0066] It should also be noted that, in this document, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations, nor should they be construed as indicating or implying relative importance. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. In the absence of further restrictions, an element defined by the phrase "includes a..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.
[0067] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand this application, and the content of this specification should not be construed as a limitation of this application. Furthermore, for those skilled in the art, there will be different forms of changes in the specific implementation methods and application scope based on this application. It is neither necessary nor possible to exhaustively list all implementation methods here, and obvious changes or modifications derived therefrom are still within the protection scope of this application.
Claims
1. An array substrate, characterized by, Comprising: a plurality of gate lines and a plurality of data lines cross arranged, the plurality of gate lines and the plurality of data lines defining a plurality of pixel regions, each of the pixel regions comprising a thin film transistor; the array substrate further comprising a common electrode disposed above the thin film transistor and the data line; the common electrode comprising a plurality of first sub-electrodes arranged in a first direction, a normal projection of the first sub-electrodes on the array substrate at least partially overlapping a normal projection of the data line on the array substrate; wherein, in the first direction, a spacing between center points of two adjacent pixel regions is a first spacing, a spacing between two adjacent first sub-electrodes is a second spacing, and a value of the first spacing is equal to a sum of the second spacing and a size of one first sub-electrode.
2. The array substrate of claim 1, wherein: the common electrode further comprises a plurality of second sub-electrodes, the second sub-electrodes extending in a second direction, the second sub-electrodes being disposed between two adjacent first sub-electrodes, and in the first direction, a spacing between the second sub-electrodes and the adjacent first sub-electrodes is a third spacing; a value of the second spacing is equal to a sum of sizes of two third spacings and a size of one second sub-electrode in the first direction; wherein the second direction is perpendicular to the first direction.
3. The array substrate of claim 2, wherein: a size of the third spacing is greater than or equal to 2.0 μm and less than or equal to 2.4 μm.
4. The array substrate of claim 1, wherein: the common electrode further comprises a plurality of second sub-electrodes, the second sub-electrodes extending in the first direction, and a plurality of second sub-electrodes being disposed between two adjacent first sub-electrodes.
5. The array substrate of claim 1, wherein: the array substrate further comprises a plurality of pixel electrodes disposed between the thin film transistor and the common electrode; in a normal projection of the array substrate, the pixel electrode is located between two adjacent first sub-electrodes.
6. The array substrate of claim 5, wherein: in the first direction, a spacing between the pixel electrode and the adjacent first sub-electrodes is a fourth spacing; a size of the fourth spacing is greater than or equal to 0.3 μm.
7. The array substrate of claim 1, wherein: a size of the first spacing is less than 15 μm.
8. The array substrate of claim 7, wherein: a size of the second spacing is greater than or equal to 3.52 μm; the array substrate further comprises a plurality of pixel electrodes disposed between the thin film transistor and the common electrode; a size of a spacing between two adjacent pixel electrodes in the first direction is greater than or equal to 5.4 μm.
9. The array substrate of claim 1, wherein: The common electrode further comprises a plurality of second sub-electrodes, the second sub-electrodes extend along a second direction, the second sub-electrodes are arranged between two adjacent first sub-electrodes, and in the first direction, a spacing between the second sub-electrodes and the adjacent first sub-electrodes is a third spacing; The array substrate further comprises a plurality of pixel electrodes arranged between the thin film transistors and the common electrode; In the first direction, a spacing between the pixel electrodes and the adjacent first sub-electrodes is a fourth spacing; A value of the third spacing is greater than a value of the fourth spacing.
10. A display device, characterized by comprising: A liquid crystal display panel comprising the array substrate according to any one of claims 1-9.