Multi-channel full-rate bit error rate testing equipment

Abstract

The utility model discloses multi-channel full-rate bit error rate test equipment, which comprises an MCU (Microprogrammed Control Unit) controller, a pseudo-random code pattern generator, a pseudo-random code pattern detector, a clock source circuit, a signal shaping circuit and a power supply circuit, the MCU controller, the clock source circuit and the signal shaping circuit are connected with the pseudo-random code pattern generator and the detector. And the MCU controller receives a user instruction to set test parameters, flexible adjustment can be performed according to different requirements, and the universality and applicability of the equipment are enhanced. The clock source circuit provides a time reference for signal processing, ensures accurate generation and synchronous detection of pseudo-random code patterns, and improves the statistical accuracy of bit error rates. The signal shaping circuit balances and filters input signals, compensates transmission distortion, improves signal quality, reduces misjudgment caused by distortion, and improves error rate calculation precision. The pseudo-random code pattern generator and the detector count the number of error codes and calculate the error rate, and provide key data for evaluating the transmission quality of a communication system.

Description

Technical Field

[0001] This utility model belongs to the field of communication testing technology, specifically a multi-channel full-rate bit error rate testing device. Background Technology

[0002] With the development of communication technology and the continuous improvement of data transmission rates, the emergence of high-speed communication standards such as 100G Ethernet necessitates instruments capable of accurately detecting and analyzing bit errors in 100G high-speed signals to ensure the reliability of communication systems. Traditional bit error rate testers are insufficient to meet the testing requirements of 100G high-speed signals. A 100G bit error rate tester, however, can adapt to the transmission rate of high-speed signals and provide high-precision bit error detection and analysis functions.

[0003] Many existing bit error rate testing devices on the market cannot meet the testing requirements of 100G high-speed signals, and it is also difficult to perform bit error detection on four channels simultaneously. This limits the relevant application directions, increases the cost of enterprise products, increases the development cycle, and reduces market competitiveness. Utility Model Content

[0004] The purpose of this invention is to provide a multi-channel, full-rate bit error rate testing device to solve the problem mentioned in the background art that the existing bit error rate testing devices cannot meet the testing requirements of 100G high-speed signals, thus increasing product development time and cost.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A multi-channel, full-rate bit error rate testing device includes an MCU controller, a pseudo-random code generator and detector, a clock source circuit, a signal shaping circuit, and a power supply circuit; wherein the MCU controller, clock source circuit, and signal shaping circuit are all connected to the pseudo-random code generator and detector, respectively.

[0007] The MCU controller is used to receive user input commands and set test parameters; the clock source circuit is used to provide a time reference for subsequent signal processing; the signal shaping circuit is used to equalize and filter the input signal to compensate for the distortion generated during signal transmission.

[0008] The pseudo-random code generator and detector are used to count the number of bit errors and calculate the bit error rate according to a preset time interval.

[0009] According to the above technical solution, the MCU controller includes controller A, controller B and controller C.

[0010] According to the above technical solution, controller A includes chip U1A, capacitor C749, resistor R748, resistor R750, resistor R859, transistor Q6, and diode D207.

[0011] Pin AA5 of chip U1A is connected to one end of capacitor C749 and resistor R750 respectively; the other end of resistor R750 is connected to the power supply, and the other end of capacitor C749 is grounded.

[0012] Pin Y4 of chip U1A is connected to one end of resistor R748. The other end of resistor R748 is connected to the base of transistor Q6. The emitter of transistor Q6 is grounded. The collector of transistor Q6 is connected to one end of diode D207. The other end of diode D207 is connected to one end of resistor R859. The other end of resistor R859 is connected to the power supply.

[0013] According to the above technical solution, the controller B includes chip U1B, connector J24, connector J25, connector J34, capacitor C750, capacitor C751, capacitor C810, capacitor C811, capacitor C812, capacitor C813, capacitor C814, capacitor C815, capacitor C816, capacitor C817, capacitor C818, capacitor C819, capacitor C841, capacitor C842, capacitor C843, capacitor C844, capacitor C845, capacitor C846, capacitor C847, capacitor C848, and connector Con9;

[0014] Pin A5 of chip U1B is connected to one end of capacitor C750, and the other end of capacitor C750 is connected to the clock source circuit; pin B4 of chip U1B is connected to one end of capacitor C751, and the other end of capacitor C751 is connected to the clock source circuit.

[0015] Pin B2 of chip U1B is connected to one end of capacitor C841, and the other end of capacitor C841 is connected to pin 1 of connector J34; pin D2 of chip U1B is connected to one end of capacitor C842, and the other end of capacitor C842 is connected to pin 2 of connector J34; pin G1 of chip U1B is connected to one end of capacitor C843, and the other end of capacitor C843 is connected to pin 3 of connector J34; pin J1 of chip U1B is connected to one end of capacitor C844, and the other end of capacitor C844 is connected to pin 4 of connector J34. Pin N1 of chip U1B is connected to one end of capacitor C845, and the other end of capacitor C845 is connected to pin 5 of connector J34; pin R1 of chip U1B is connected to one end of capacitor C846, and the other end of capacitor C846 is connected to pin 6 of connector J34; pin V2 of chip U1B is connected to one end of capacitor C847, and the other end of capacitor C847 is connected to pin 7 of connector J34; pin Y2 of chip U1B is connected to one end of capacitor C848, and the other end of capacitor C848 is connected to pin 8 of connector J34.

[0016] Pins 9 through 17 of connector J34 are all grounded;

[0017] Pin A7 of chip U1B is connected to one end of capacitor C810, and the other end of capacitor C810 is connected to one end of connector J24, with the other end of connector J24 grounded; pin B8 of chip U1B is connected to one end of capacitor C811, and the other end of capacitor C811 is connected to one end of connector J25, with the other end of connector J25 grounded; pin B10 of chip U1B is connected to one end of capacitor C812, and the other end of capacitor C812 is connected to pin 8 of connector Con9; pin D10 of chip U1B is connected to one end of capacitor C813, and the other end of capacitor C813 is connected to pin 7 of connector Con9; pin G11 of chip U1B is connected to one end of capacitor C814, and the other end of capacitor C814 is connected to pin 7 of connector Con9. Pin 6 is connected; pin J11 of chip U1B is connected to one end of capacitor C815, and the other end of capacitor C815 is connected to pin 5 of connector Con9; pin N11 of chip U1B is connected to one end of capacitor C816, and the other end of capacitor C816 is connected to pin 4 of connector Con9; pin R11 of chip U1B is connected to one end of capacitor C817, and the other end of capacitor C817 is connected to pin 3 of connector Con9; pin V10 of chip U1B is connected to one end of capacitor C818, and the other end of capacitor C818 is connected to pin 2 of connector Con9; pin Y10 of chip U1B is connected to one end of capacitor C819, and the other end of capacitor C819 is connected to pin 1 of connector Con9.

[0018] Pins 17 through 9 of connector Con9 are all grounded.

[0019] According to the above technical solution, the controller C includes chip U1C, inductor L16, inductor L17, inductor L18, inductor L19 and inductor L20;

[0020] Pins H4, K4, M4 and P4 of chip U1C are all connected to one end of inductor L16, and the other end of inductor L16 is connected to the power supply.

[0021] The H8, K8, M8 and P8 pins of chip U1C are all connected to one end of inductor L19, and the other end of inductor L19 is connected to the power supply.

[0022] Pins N5, N7, P6, R5, and R7 of chip U1C are all connected to one end of inductor L20, and the other end of inductor L20 is connected to the power supply.

[0023] Pin V8 of chip U1C is connected to one end of inductor L17, and the other end of inductor L17 is connected to one end of inductor L18 and the power supply.

[0024] Pins G5, G7, H6, J5, and J7 of chip U1C are all connected to the other end of inductor L18;

[0025] The remaining pins of chip U1C are all grounded.

[0026] According to the above technical solution, the clock source circuit includes chip U715, chip U716, crystal oscillator Y603, connector J7, capacitors C47, C48, C50, C51, C52, C53, C54, C55, C61, C62, C63, C64, C995, C996, C1005, C1006, C1007, resistors R15, R30, R31, R907, R908, R1125, R1128, diodes D5, D6, and D7.

[0027] Pins 21, 32, 39, and 40 of chip U715 are connected to one end of capacitors C48, C47, C996, and C995; the other end of capacitors C48, C47, C996, and C995 is grounded.

[0028] Pins 26, 8, and 9 of chip U715 are all connected to one end of capacitors C53, C54, and C55, while the other end of capacitors C53, C54, and C55 is grounded.

[0029] Pin 43 of chip U715 is connected to one end of capacitor C61, and the other end of capacitor C61 is connected to one end of connector J7.

[0030] Pin 44 of chip U715 is connected to one end of capacitor C62, and the other end of capacitor C62 is connected to the other end of connector J7.

[0031] Pin 1 of chip U715 is connected to one end of capacitor C63, and the other end of capacitor C63 is connected to pin 5 of chip U716; pin 2 of chip U715 is connected to one end of capacitor C64, and the other end of capacitor C64 is connected to pin 4 of chip U716; pin 1 of chip U716 is connected to one end of resistor R908 and one end of resistor R907; the other end of resistor R907 is connected to pin 3 of chip U716, and both resistor R907 and pin 3 of chip U716 are grounded; the other end of resistor R908 is connected to pin 6 of chip U716; both resistor R908 and pin 6 of chip U716 are connected to the power supply.

[0032] Pin 4 of chip U715 is connected to pins 2 and 4 of crystal oscillator Y603 and pin 7 of chip U715 respectively; pin 5 of chip U715 is connected to pin 3 of crystal oscillator Y603; pin 6 of chip U715 is connected to pin 1 of crystal oscillator Y603.

[0033] Pin 45 of chip U715 is grounded;

[0034] Pins 18, 23, 29, and 34 of chip U715 are connected to one end of capacitors C1007, C50, C51, C52, and resistor R15; the other ends of capacitors C1007, C50, C51, and C52 are grounded; and the other end of resistor R15 is connected to the power supply.

[0035] Pin 20 of chip U715 is connected to capacitor C750, and pin 19 of chip U715 is connected to capacitor C751.

[0036] Pin 31 of chip U715 is connected to one end of capacitor C1006, pin 30 of chip U715 is connected to one end of capacitor C1005, the other end of capacitor C1005 is connected to one end of resistor R1128, and the other end of resistor R1128 is grounded.

[0037] Pin 33 of chip U715 is connected to one end of resistor R1125, the other end of resistor R1125 is connected to one end of diode D7, and the other end of diode D7 is connected to the other ends of diodes D6 and D5 respectively.

[0038] Pin 27 of chip U715 is connected to one end of resistor R31, and the other end of resistor R31 is connected to the other end of diode D6. Pin 28 of chip U715 is connected to one end of resistor R30, and the other end of resistor R30 is connected to the other end of diode D5.

[0039] According to the above technical solution, pins 21, 32, 39, and 40 of chip U715, as well as capacitors C48, C47, C996, and C995, are all connected to the power supply.

[0040] According to the above technical solution, pins 26, 8, and 9 of chip U715, as well as capacitors C53, C54, and C55, are all connected to the power supply.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] In this invention, the MCU controller can receive user-input commands and set test parameters. This allows operators to flexibly adjust test conditions according to different test requirements, facilitating bit error rate testing for various types and rates of communication systems, thus enhancing the versatility and applicability of the equipment. The clock source circuit provides a time reference for subsequent signal processing, ensuring the accurate generation and synchronization of the pseudo-random code pattern and contributing to improved accuracy and reliability of bit error rate statistics. The signal shaping circuit performs equalization and filtering on the input signal, effectively compensating for signal distortion during transmission and improving signal quality. High-quality signals enable the pseudo-random code pattern generator and detector to more accurately identify signals, reducing misjudgments caused by signal distortion, thereby improving the accuracy of bit error rate calculation. Attached Figure Description

[0043] Figure 1 This is the circuit diagram of controller A of this utility model;

[0044] Figure 2 This is the circuit diagram of controller B of this utility model;

[0045] Figure 3 This is the circuit diagram of controller C of this utility model;

[0046] Figure 4 This is a circuit diagram of the clock source circuit of this utility model. Detailed Implementation

[0047] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0048] Example 1

[0049] A multi-channel full-rate bit error rate testing device, specifically relating to a multi-channel full-rate bit error rate testing circuit; including an MCU controller, a pseudo-random code generator and detector, a clock source circuit, a signal shaping circuit, and a power supply circuit; wherein, the MCU controller, clock source circuit, and signal shaping circuit are all connected to the pseudo-random code generator and detector, respectively;

[0050] The MCU controller is used to receive user input commands and set test parameters; the clock source circuit is used to provide a time reference for subsequent signal processing; the signal shaping circuit is used to equalize and filter the input signal to compensate for the distortion generated during signal transmission.

[0051] The pseudo-random code generator and detector are used to count the number of bit errors and calculate the bit error rate according to a preset time interval.

[0052] In this invention, the MCU controller can receive user-input commands and set test parameters. This allows operators to flexibly adjust test conditions according to different test requirements, facilitating bit error rate testing for various types and rates of communication systems, thus enhancing the versatility and applicability of the equipment. The clock source circuit provides a time reference for subsequent signal processing, ensuring the accurate generation and synchronization of the pseudo-random code pattern and contributing to improved accuracy and reliability of bit error rate statistics. The signal shaping circuit performs equalization and filtering on the input signal, effectively compensating for signal distortion during transmission and improving signal quality. High-quality signals enable the pseudo-random code pattern generator and detector to more accurately identify signals, reducing misjudgments caused by signal distortion, thereby improving the accuracy of bit error rate calculation.

[0053] Example 2

[0054] This embodiment is a further refinement of Embodiment 1.

[0055] like Figure 1 As shown, the MCU controller includes controller A, controller B and controller C.

[0056] Controller A includes chip U1A, capacitor C749, resistor R748, resistor R750, resistor R859, transistor Q6, and diode D207.

[0057] Pin AA5 of chip U1A is connected to one end of capacitor C749 and resistor R750 respectively; the other end of resistor R750 is connected to the power supply, and the other end of capacitor C749 is grounded.

[0058] Pin Y4 of chip U1A is connected to one end of resistor R748. The other end of resistor R748 is connected to the base of transistor Q6. The emitter of transistor Q6 is grounded. The collector of transistor Q6 is connected to one end of diode D207. The other end of diode D207 is connected to one end of resistor R859. The other end of resistor R859 is connected to the power supply.

[0059] like Figure 2 As shown, controller B includes chip U1B, connector J24, connector J25, connector J34, capacitors C750, C751, C810, C811, C812, C813, C814, C815, C816, C817, C818, C819, C841, C842, C843, C844, C845, C846, C847, C848, and connector Con9;

[0060] Pin A5 of chip U1B is connected to one end of capacitor C750, and the other end of capacitor C750 is connected to the clock source circuit; pin B4 of chip U1B is connected to one end of capacitor C751, and the other end of capacitor C751 is connected to the clock source circuit.

[0061] Pin B2 of chip U1B is connected to one end of capacitor C841, and the other end of capacitor C841 is connected to pin 1 of connector J34; pin D2 of chip U1B is connected to one end of capacitor C842, and the other end of capacitor C842 is connected to pin 2 of connector J34; pin G1 of chip U1B is connected to one end of capacitor C843, and the other end of capacitor C843 is connected to pin 3 of connector J34; pin J1 of chip U1B is connected to one end of capacitor C844, and the other end of capacitor C844 is connected to pin 4 of connector J34. Pin N1 of chip U1B is connected to one end of capacitor C845, and the other end of capacitor C845 is connected to pin 5 of connector J34; pin R1 of chip U1B is connected to one end of capacitor C846, and the other end of capacitor C846 is connected to pin 6 of connector J34; pin V2 of chip U1B is connected to one end of capacitor C847, and the other end of capacitor C847 is connected to pin 7 of connector J34; pin Y2 of chip U1B is connected to one end of capacitor C848, and the other end of capacitor C848 is connected to pin 8 of connector J34.

[0062] Pins 9 through 17 of connector J34 are all grounded;

[0063] Pin A7 of chip U1B is connected to one end of capacitor C810, and the other end of capacitor C810 is connected to one end of connector J24, with the other end of connector J24 grounded; pin B8 of chip U1B is connected to one end of capacitor C811, and the other end of capacitor C811 is connected to one end of connector J25, with the other end of connector J25 grounded; pin B10 of chip U1B is connected to one end of capacitor C812, and the other end of capacitor C812 is connected to pin 8 of connector Con9; pin D10 of chip U1B is connected to one end of capacitor C813, and the other end of capacitor C813 is connected to pin 7 of connector Con9; pin G11 of chip U1B is connected to one end of capacitor C814, and the other end of capacitor C814 is connected to pin 7 of connector Con9. Pin 6 is connected; pin J11 of chip U1B is connected to one end of capacitor C815, and the other end of capacitor C815 is connected to pin 5 of connector Con9; pin N11 of chip U1B is connected to one end of capacitor C816, and the other end of capacitor C816 is connected to pin 4 of connector Con9; pin R11 of chip U1B is connected to one end of capacitor C817, and the other end of capacitor C817 is connected to pin 3 of connector Con9; pin V10 of chip U1B is connected to one end of capacitor C818, and the other end of capacitor C818 is connected to pin 2 of connector Con9; pin Y10 of chip U1B is connected to one end of capacitor C819, and the other end of capacitor C819 is connected to pin 1 of connector Con9.

[0064] Pins 17 through 9 of connector Con9 are all grounded.

[0065] like Figure 3 As shown, controller C includes chip U1C, inductor L16, inductor L17, inductor L18, inductor L19 and inductor L20;

[0066] Pins H4, K4, M4 and P4 of chip U1C are all connected to one end of inductor L16, and the other end of inductor L16 is connected to the power supply.

[0067] The H8, K8, M8 and P8 pins of chip U1C are all connected to one end of inductor L19, and the other end of inductor L19 is connected to the power supply.

[0068] Pins N5, N7, P6, R5, and R7 of chip U1C are all connected to one end of inductor L20, and the other end of inductor L20 is connected to the power supply.

[0069] Pin V8 of chip U1C is connected to one end of inductor L17, and the other end of inductor L17 is connected to one end of inductor L18 and the power supply.

[0070] Pins G5, G7, H6, J5, and J7 of chip U1C are all connected to the other end of inductor L18;

[0071] The remaining pins of chip U1C are all grounded.

[0072] like Figure 4 As shown, the clock source circuit includes chip U715, chip U716, crystal oscillator Y603, connector J7, capacitors C47, C48, C50, C51, C52, C53, C54, C55, C61, C62, C63, C64, C995, C996, C1005, C1006, C1007, resistors R15, R30, R31, R907, R908, R1125, R1128, diodes D5, D6, and D7.

[0073] Pins 21, 32, 39, and 40 of chip U715 are connected to one end of capacitors C48, C47, C996, and C995; the other end of capacitors C48, C47, C996, and C995 is grounded.

[0074] Pins 26, 8, and 9 of chip U715 are all connected to one end of capacitors C53, C54, and C55, while the other end of capacitors C53, C54, and C55 is grounded.

[0075] Pin 43 of chip U715 is connected to one end of capacitor C61, and the other end of capacitor C61 is connected to one end of connector J7.

[0076] Pin 44 of chip U715 is connected to one end of capacitor C62, and the other end of capacitor C62 is connected to the other end of connector J7.

[0077] Pin 1 of chip U715 is connected to one end of capacitor C63, and the other end of capacitor C63 is connected to pin 5 of chip U716; pin 2 of chip U715 is connected to one end of capacitor C64, and the other end of capacitor C64 is connected to pin 4 of chip U716; pin 1 of chip U716 is connected to one end of resistor R908 and one end of resistor R907; the other end of resistor R907 is connected to pin 3 of chip U716, and both resistor R907 and pin 3 of chip U716 are grounded; the other end of resistor R908 is connected to pin 6 of chip U716; both resistor R908 and pin 6 of chip U716 are connected to the power supply.

[0078] Pin 4 of chip U715 is connected to pins 2 and 4 of crystal oscillator Y603 and pin 7 of chip U715 respectively; pin 5 of chip U715 is connected to pin 3 of crystal oscillator Y603; pin 6 of chip U715 is connected to pin 1 of crystal oscillator Y603.

[0079] Pin 45 of chip U715 is grounded;

[0080] Pins 18, 23, 29, and 34 of chip U715 are connected to one end of capacitors C1007, C50, C51, C52, and resistor R15; the other ends of capacitors C1007, C50, C51, and C52 are grounded; and the other end of resistor R15 is connected to the power supply.

[0081] Pin 20 of chip U715 is connected to capacitor C750, and pin 19 of chip U715 is connected to capacitor C751.

[0082] Pin 31 of chip U715 is connected to one end of capacitor C1006, pin 30 of chip U715 is connected to one end of capacitor C1005, the other end of capacitor C1005 is connected to one end of resistor R1128, and the other end of resistor R1128 is grounded.

[0083] Pin 33 of chip U715 is connected to one end of resistor R1125, the other end of resistor R1125 is connected to one end of diode D7, and the other end of diode D7 is connected to the other ends of diodes D6 and D5 respectively.

[0084] Pin 27 of chip U715 is connected to one end of resistor R31, and the other end of resistor R31 is connected to the other end of diode D6. Pin 28 of chip U715 is connected to one end of resistor R30, and the other end of resistor R30 is connected to the other end of diode D5.

[0085] Pins 21, 32, 39, and 40 of chip U715, as well as capacitors C48, C47, C996, and C995, are all connected to the power supply.

[0086] Pins 26, 8, and 9 of chip U715, as well as capacitors C53, C54, and C55, are all connected to the power supply.

[0087] Furthermore, all electronic components involved in this utility model are existing technologies. For example, chips U1A, U1B, and U1C all use IN012525-CQ type chips, and chip U715 uses SI5340 type chips.

[0088] The working principle of this invention is as follows: the user inputs instructions through the MCU controller, and controllers A, B, and C work together to receive and process these instructions, setting various parameters required for testing, such as the test code pattern, rate, and test time. Taking controller A as an example, chip U1A, through components such as capacitors, resistors, transistors, and diodes connected to its pins, realizes signal interaction and processing with other circuits, providing support for operations such as setting parameters.

[0089] The clock source circuit, consisting of chips U715 and U716 and crystal oscillator Y603, works together to generate a stable clock signal, providing a time reference for the signal processing of the entire bit error rate testing equipment and ensuring that all parts can operate synchronously and orderly. For example, multiple pins of chip U715 are connected to different capacitors, working with other components to generate, adjust, and transmit the clock signal. The capacitors serve to filter and stabilize the voltage, while crystal oscillator Y603 is the main source of the clock signal, providing a stable oscillation frequency.

[0090] The signal shaping circuit performs equalization and filtering on the input signal to compensate for distortions generated during transmission, ensuring the signal meets the requirements of subsequent processing and improving test accuracy. Under the control of the MCU controller, the pseudo-random code generator and detector generate specific pseudo-random codes according to set parameters and send them out. Simultaneously, the detector receives the transmitted signal, compares it with the original code, and counts the number of bit errors. Then, at preset time intervals, it calculates the bit error rate based on the counted number of bit errors and the total number of transmitted codes, and feeds the result back to the MCU controller for display or further processing.

[0091] Through the coordinated operation of its various components, this device can perform bit error rate testing on multi-channel full-rate signals, providing important technical support for signal quality testing in fields such as communication systems.

[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0093] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A multi-channel, full-rate bit error rate testing device, characterized in that: It includes an MCU controller, a pseudo-random code generator and detector, a clock source circuit, a signal shaping circuit, and a power supply circuit; wherein the MCU controller, clock source circuit, and signal shaping circuit are all connected to the pseudo-random code generator and detector, respectively. The MCU controller is used to receive user input commands and set test parameters; the clock source circuit is used to provide a time reference for subsequent signal processing; the signal shaping circuit is used to equalize and filter the input signal to compensate for the distortion generated during signal transmission. The pseudo-random code generator and detector are used to count the number of bit errors and calculate the bit error rate according to a preset time interval.

2. The multi-channel full-rate bit error rate testing device according to claim 1, characterized in that: The MCU controller includes controller A, controller B and controller C.

3. The multi-channel full-rate bit error rate testing device according to claim 2, characterized in that: Controller A includes chip U1A, capacitor C749, resistor R748, resistor R750, resistor R859, transistor Q6, and diode D207. Pin AA5 of chip U1A is connected to one end of capacitor C749 and resistor R750 respectively; the other end of resistor R750 is connected to the power supply, and the other end of capacitor C749 is grounded. Pin Y4 of chip U1A is connected to one end of resistor R748. The other end of resistor R748 is connected to the base of transistor Q6. The emitter of transistor Q6 is grounded. The collector of transistor Q6 is connected to one end of diode D207. The other end of diode D207 is connected to one end of resistor R859. The other end of resistor R859 is connected to the power supply.

4. The multi-channel full-rate bit error rate testing device according to claim 3, characterized in that: Controller B includes chip U1B, connectors J24, J25, J34, capacitors C750, C751, C810, C811, C812, C813, C814, C815, C816, C817, C818, C819, C841, C842, C843, C844, C845, C846, C847, C848, and connector Con9; Pin A5 of chip U1B is connected to one end of capacitor C750, and the other end of capacitor C750 is connected to the clock source circuit; pin B4 of chip U1B is connected to one end of capacitor C751, and the other end of capacitor C751 is connected to the clock source circuit. Pin B2 of chip U1B is connected to one end of capacitor C841, and the other end of capacitor C841 is connected to pin 1 of connector J34; pin D2 of chip U1B is connected to one end of capacitor C842, and the other end of capacitor C842 is connected to pin 2 of connector J34; pin G1 of chip U1B is connected to one end of capacitor C843, and the other end of capacitor C843 is connected to pin 3 of connector J34; pin J1 of chip U1B is connected to one end of capacitor C844, and the other end of capacitor C844 is connected to pin 4 of connector J34. Pin N1 of chip U1B is connected to one end of capacitor C845, and the other end of capacitor C845 is connected to pin 5 of connector J34; pin R1 of chip U1B is connected to one end of capacitor C846, and the other end of capacitor C846 is connected to pin 6 of connector J34; pin V2 of chip U1B is connected to one end of capacitor C847, and the other end of capacitor C847 is connected to pin 7 of connector J34; pin Y2 of chip U1B is connected to one end of capacitor C848, and the other end of capacitor C848 is connected to pin 8 of connector J34. Pins 9 through 17 of connector J34 are all grounded; Pin A7 of chip U1B is connected to one end of capacitor C810, and the other end of capacitor C810 is connected to one end of connector J24, with the other end of connector J24 grounded; pin B8 of chip U1B is connected to one end of capacitor C811, and the other end of capacitor C811 is connected to one end of connector J25, with the other end of connector J25 grounded; pin B10 of chip U1B is connected to one end of capacitor C812, and the other end of capacitor C812 is connected to pin 8 of connector Con9; pin D10 of chip U1B is connected to one end of capacitor C813, and the other end of capacitor C813 is connected to pin 7 of connector Con9; pin G11 of chip U1B is connected to one end of capacitor C814, and the other end of capacitor C814 is connected to pin 7 of connector Con9. Pin 6 is connected; pin J11 of chip U1B is connected to one end of capacitor C815, and the other end of capacitor C815 is connected to pin 5 of connector Con9; pin N11 of chip U1B is connected to one end of capacitor C816, and the other end of capacitor C816 is connected to pin 4 of connector Con9; pin R11 of chip U1B is connected to one end of capacitor C817, and the other end of capacitor C817 is connected to pin 3 of connector Con9; pin V10 of chip U1B is connected to one end of capacitor C818, and the other end of capacitor C818 is connected to pin 2 of connector Con9; pin Y10 of chip U1B is connected to one end of capacitor C819, and the other end of capacitor C819 is connected to pin 1 of connector Con9. Pins 17 through 9 of connector Con9 are all grounded.

5. The multi-channel full-rate bit error rate testing device according to claim 4, characterized in that: The controller C includes chip U1C, inductor L16, inductor L17, inductor L18, inductor L19 and inductor L20; Pins H4, K4, M4 and P4 of chip U1C are all connected to one end of inductor L16, and the other end of inductor L16 is connected to the power supply. The H8, K8, M8 and P8 pins of chip U1C are all connected to one end of inductor L19, and the other end of inductor L19 is connected to the power supply. Pins N5, N7, P6, R5, and R7 of chip U1C are all connected to one end of inductor L20, and the other end of inductor L20 is connected to the power supply. Pin V8 of chip U1C is connected to one end of inductor L17, and the other end of inductor L17 is connected to one end of inductor L18 and the power supply. Pins G5, G7, H6, J5, and J7 of chip U1C are all connected to the other end of inductor L18; The remaining pins of chip U1C are all grounded.

6. The multi-channel full-rate bit error rate testing device according to claim 5, characterized in that: The clock source circuit includes chip U715, chip U716, crystal oscillator Y603, connector J7, capacitors C47, C48, C50, C51, C52, C53, C54, C55, C61, C62, C63, C64, C995, C996, C1005, C1006, C1007, resistors R15, R30, R31, R907, R908, R1125, R1128, diodes D5, D6, and D7. Pins 21, 32, 39, and 40 of chip U715 are connected to one end of capacitors C48, C47, C996, and C995; the other end of capacitors C48, C47, C996, and C995 is grounded. Pins 26, 8, and 9 of chip U715 are all connected to one end of capacitors C53, C54, and C55, while the other end of capacitors C53, C54, and C55 is grounded. Pin 43 of chip U715 is connected to one end of capacitor C61, and the other end of capacitor C61 is connected to one end of connector J7. Pin 44 of chip U715 is connected to one end of capacitor C62, and the other end of capacitor C62 is connected to the other end of connector J7. Pin 1 of chip U715 is connected to one end of capacitor C63, and the other end of capacitor C63 is connected to pin 5 of chip U716; pin 2 of chip U715 is connected to one end of capacitor C64, and the other end of capacitor C64 is connected to pin 4 of chip U716; pin 1 of chip U716 is connected to one end of resistor R908 and one end of resistor R907; the other end of resistor R907 is connected to pin 3 of chip U716, and both resistor R907 and pin 3 of chip U716 are grounded; the other end of resistor R908 is connected to pin 6 of chip U716; both resistor R908 and pin 6 of chip U716 are connected to the power supply. Pin 4 of chip U715 is connected to pins 2 and 4 of crystal oscillator Y603 and pin 7 of chip U715 respectively; pin 5 of chip U715 is connected to pin 3 of crystal oscillator Y603; pin 6 of chip U715 is connected to pin 1 of crystal oscillator Y603. Pin 45 of chip U715 is grounded; Pins 18, 23, 29, and 34 of chip U715 are connected to one end of capacitors C1007, C50, C51, C52, and resistor R15; the other ends of capacitors C1007, C50, C51, and C52 are grounded; and the other end of resistor R15 is connected to the power supply. Pin 20 of chip U715 is connected to capacitor C750, and pin 19 of chip U715 is connected to capacitor C751. Pin 31 of chip U715 is connected to one end of capacitor C1006, pin 30 of chip U715 is connected to one end of capacitor C1005, the other end of capacitor C1005 is connected to one end of resistor R1128, and the other end of resistor R1128 is grounded. Pin 33 of chip U715 is connected to one end of resistor R1125, the other end of resistor R1125 is connected to one end of diode D7, and the other end of diode D7 is connected to the other ends of diodes D6 and D5 respectively. Pin 27 of chip U715 is connected to one end of resistor R31, and the other end of resistor R31 is connected to the other end of diode D6. Pin 28 of chip U715 is connected to one end of resistor R30, and the other end of resistor R30 is connected to the other end of diode D5.

7. The multi-channel full-rate bit error rate testing device according to claim 6, characterized in that: Pins 21, 32, 39, and 40 of chip U715, as well as capacitors C48, C47, C996, and C995, are all connected to the power supply.

8. The multi-channel full-rate bit error rate testing device according to claim 7, characterized in that: Pins 26, 8, and 9 of chip U715, as well as capacitors C53, C54, and C55, are all connected to the power supply.

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