Sub-pixel and display device

Abstract

The utility model relates to a sub-pixel and a display device. The sub-pixel includes: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between the data line and the third node and including a gate electrode connected to the first sub-gate line; a third transistor connected between the first node and a first power supply voltage node configured to supply the first power supply voltage, and including a gate electrode connected to an emission control line; and a light emitting element connected between the second node and a second power supply voltage node configured to supply a second power supply voltage lower than the first power supply voltage. The body electrode of the first transistor to the body electrode of the third transistor are biased with at least one voltage. The sub-pixel further includes a capacitor connected between the first node and the third node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0043179, filed on March 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments supported by this disclosure relate to electronic devices, and more specifically, to subpixels, display devices including subpixels, and display systems including display devices. Background Technology

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information is becoming increasingly prominent. In response, the use of display devices, such as liquid crystal displays and organic light-emitting diode displays, is increasing.

[0005] Recently, head-mounted display (HMD) devices have been developed. HMD devices are display devices worn by users in the form of glasses or helmets, enabling virtual reality (VR) or augmented reality (AR) with near-eye focus. High-resolution panels are used in HMD devices, and therefore, subpixels suitable for high-resolution panels may be required.

[0006] The above description is intended to aid in understanding the background technology used to develop the technical concept of this utility model. Therefore, it should not be construed as corresponding to prior art known to those skilled in the art to which this utility model pertains. Utility Model Content

[0007] Embodiments of this invention provide a display device including high-resolution subpixels.

[0008] Embodiments of this invention provide a display device including subpixels that can be manufactured at a reduced cost.

[0009] A sub-pixel included in a display device according to an embodiment supported by this disclosure may include: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line; a third transistor connected between the first node and a first power supply voltage node configured to supply a first power supply voltage, and the third transistor including a gate electrode connected to an emission control line; and a light-emitting element connected between the second node and a second power supply voltage node configured to supply a second power supply voltage lower than the first power supply voltage. The body electrodes of the first transistor to the third transistor are biased by at least one voltage. The sub-pixel also includes a capacitor connected between the first node and the third node, but no capacitor connected to the second node and the third node.

[0010] The first power supply voltage can be applied to the body electrode of the first transistor.

[0011] Subpixels may not include any capacitors other than capacitors.

[0012] The sub-pixel may further include: a fourth transistor connected between the second node and an initialization voltage node configured to supply an initialization voltage, and the fourth transistor includes a gate electrode connected to the second sub-gate line.

[0013] The first power supply voltage can be commonly applied to the body electrodes of the first transistor, the third transistor, and the fourth transistor.

[0014] Each of the first to fourth transistors can be a PMOS (P-channel metal-oxide-semiconductor) transistor.

[0015] The first to fourth transistors can be mounted on a silicon substrate.

[0016] The initial voltage can be equal to or lower than the second power supply voltage.

[0017] Another aspect of this invention relates to a display device. A display device according to embodiments supported by this disclosure may include: a plurality of sub-pixels connected to a plurality of gate lines and a plurality of emission control lines; and a gate driver configured to control the plurality of gate lines and the plurality of emission control lines. A sub-pixel may include: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line of the plurality of gate lines; a third transistor connected between the first node and a first power supply voltage node configured to supply a first power supply voltage, and the third transistor including a gate electrode connected to one of the plurality of emission control lines; and a light-emitting element connected between the second node and a second power supply voltage node configured to supply a second power supply voltage lower than the first power supply voltage. The body electrode of the first transistor to the body electrode of the third transistor is biased by at least one voltage. The sub-pixel also includes a capacitor connected between the first node and the third node, but no capacitor connected to the second node and the third node.

[0018] The first power supply voltage can be applied to the body electrode of the first transistor.

[0019] Subpixels may not include any capacitors other than capacitors.

[0020] The sub-pixel may further include: a fourth transistor connected between the second node and an initialization voltage node configured to supply an initialization voltage, and the fourth transistor includes a gate electrode connected to one of a plurality of gate lines, a second sub-gate line.

[0021] The first power supply voltage can be commonly applied to the body electrodes of the first transistor, the third transistor, and the fourth transistor.

[0022] The gate driver can be configured to: turn on a fourth transistor by supplying a second scan signal set to logic low to a second sub-gate line during a first, second, and third cycle provided sequentially; turn on a second transistor by supplying a first scan signal set to logic low to a first sub-gate line and turn off a third transistor by supplying an emit control signal set to logic high to one of a plurality of emit control lines during the second cycle; turn off a second transistor by setting a first scan signal to logic high during the third cycle; and turn off a fourth transistor by setting a second scan signal to logic high and turning on a third transistor by setting an emit control signal to logic low during the fourth cycle.

[0023] The display device may further include a data driver configured to control the data lines. The data driver may be configured to supply data signals to the data lines during the second cycle.

[0024] During the second cycle, the data signal on the data line can be reflected in the voltage of the third node through the second transistor. During the fourth cycle, based on the voltage of the third node, current can be supplied from the first power supply voltage node to the light-emitting element through the third transistor and the first transistor.

[0025] Another aspect of this invention relates to a display system. A display system according to embodiments supported by this disclosure may include: a processor; and at least one display device that displays an image through a plurality of sub-pixels based on image data from the processor. One of the plurality of sub-pixels includes: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line; a third transistor connected between the first node and a first power supply voltage node configured to supply a first power supply voltage, and the third transistor including a gate electrode connected to an emission control line; and a light-emitting element connected between the second node and a second power supply voltage node configured to supply a second power supply voltage lower than the first power supply voltage. The body electrodes of the first transistor to the body electrodes of the third transistor are biased by at least one voltage. One of the plurality of sub-pixels also includes a capacitor connected between the first node and the third node, but no capacitor connected to the second node and the third node. Attached Figure Description

[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to illustrate the principles of the present disclosure.

[0027] Figure 1 This is a block diagram of a display device according to an embodiment supported by the present disclosure.

[0028] Figure 2 It is shown Figure 1 A block diagram of an embodiment of a sub-pixel.

[0029] Figure 3 It is shown Figure 1 A block diagram of an embodiment of a display panel and a gate driver.

[0030] Figure 4 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0031] Figure 5 This indicates that it is provided during the display operation. Figure 4Timing diagram of an embodiment of the signal of a sub-pixel.

[0032] Figures 6 to 9 It is used to explain in Figure 5 A diagram of the subpixel operations in the first to fourth cycles.

[0033] Figure 10 It is shown Figure 1 A plan view of an embodiment of the display panel.

[0034] Figure 11 It is shown Figure 10 An exploded perspective view of a portion of the display panel.

[0035] Figure 12 This is a block diagram illustrating an embodiment of the display system.

[0036] Figure 13 It is shown Figure 12 A perspective view of an application example of the display system.

[0037] Figure 14 It is shown Figure 13 An image of a head-mounted display device worn by a user. Detailed Implementation

[0038] In the following description, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It should be noted that in the following description, only portions supporting the understanding of operation according to the present invention will be described, and descriptions of other portions will be omitted to avoid obscuring the essential points of the present invention. In some aspects, the present invention is not limited to the embodiments described herein and may be implemented in other forms. The embodiments described herein are provided only for sufficient detail to enable those skilled in the art to readily implement the technical concept of the present invention.

[0039] Throughout this specification, the phrase "connected" to another part includes not only cases where the two parts are "directly connected," but also cases where they are "indirectly connected" with the other part situated between them. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. Throughout this specification, unless otherwise stated, the phrase "comprising..." in a particular part means that the part may also include another component without excluding it. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). Here, "and / or" includes all combinations of one or more corresponding configurations.

[0040] Here, terms such as "first" and "second" as examples can be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Therefore, without departing from the scope disclosed herein, "first component" may refer to "second component" within that scope.

[0041] Spatial relative terms such as “below” and “above” can be used for descriptive purposes to describe the relationship between one element or feature and another element (or feature) or feature (or feature) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to include other orientations in use, in operation, and / or in manufacture. For example, when the device shown in the drawings is flipped upside down, the element depicted as positioned “below” other elements or features is positioned in an orientation “above” other elements or features. Thus, in embodiments, the term “below” can include both above and below orientations. In some aspects, the device may face other orientations (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relative terms used herein are interpreted accordingly.

[0042] As used herein, the term “substantially” means approximately or actually. The term “substantially equal” means approximately equal or actually equal. The term “substantially identical” means approximately identical or actually identical.

[0043] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate exemplary embodiments. Therefore, it will be anticipated that the shape may vary, for example, depending on tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, and should be interpreted as including changes in shape, for example, due to manufacturing processes. As described herein, the shapes shown in the drawings may not represent the actual shape of areas of the device, and this embodiment is not limited thereto.

[0044] Figure 1 This is a block diagram of a display device according to an embodiment supported by the present disclosure.

[0045] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0046] The display panel 110 may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn. m and n can each be a positive integer.

[0047] Each of the plurality of subpixels SP may include at least one light-emitting element configured to generate light. Therefore, each of the plurality of subpixels SP can generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more subpixels of the plurality of subpixels SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels can form a pixel PXL.

[0048] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output scan signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In some embodiments, gate control signal GCS may include a scan start signal indicating the start of each frame and a horizontal synchronization signal for outputting scan signals in timing synchronization with applied data signals, etc.

[0049] In some embodiments, first emission control lines EL1 to m-th emission control lines ELm connected to sub-pixels SP in the row direction may also be provided. In this case, gate driver 120 may include emission drivers configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission drivers may operate under the control of controller 150.

[0050] The gate driver 120 may be disposed on one side of the display panel 110. However, embodiments of the present invention are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separate drivers. These drivers may be disposed on one side of the display panel 110 and on another side of the display panel 110 opposite to said one side. Therefore, according to embodiments, the gate driver 120 may be disposed around the display panel 110 in various forms.

[0051] The data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. The data driver 130 can receive image data DATA and data control signals DCS from the controller 150. The data driver 130 can operate in response to the data control signals DCS. In some embodiments, the data control signals DCS may include source start pulse, source shift clock, and source output enable signal, etc.

[0052] The data driver 130 can use the voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. In the example where the scan signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed in the display panel 110.

[0053] In some embodiments, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0054] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device 100. For example, voltage generator 140 can be configured to generate multiple voltages by receiving an input voltage from outside display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0055] Voltage generator 140 can generate a first power supply voltage VDD and a second power supply voltage VSS, and provide the generated first power supply voltage VDD and second power supply voltage VSS to the sub-pixel SP. The first power supply voltage VDD can have a relatively high voltage level, and the second power supply voltage VSS can have a lower voltage level than the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS can be provided by a device external to the display device 100.

[0056] In some aspects, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to sub-pixel SP. In some embodiments, the initialization voltage can have the same voltage level as the second power supply voltage VSS. In other embodiments, the initialization voltage can have a voltage level between the first power supply voltage VDD and the second power supply voltage VSS. In still other embodiments, the initialization voltage can have a lower voltage level than the second power supply voltage VSS.

[0057] The controller 150 can control various operations of the display device 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0058] The controller 150 can convert input image data IMG to fit the display device 100 or display panel 110, generate image data DATA, and output the image data DATA to the data driver 130. In some embodiments, the controller 150 can output image data DATA by rearranging the input image data IMG to fit sub-pixels SP in rows.

[0059] Two or more components of the data driver 130, voltage generator 140, and controller 150 can be mounted in a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component separate from the driver integrated circuit (DIC).

[0060] Figure 2 It is shown Figure 1 A block diagram of an embodiment of a sub-pixel.

[0061] exist Figure 2 In Figure 1 Among the sub-pixels SP, the sub-pixel SPij arranged in the i-th row (i can be an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j can be an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0062] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0063] The light-emitting element (LD) can be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. In this case, the first power supply voltage node VDDN can be... Figure 1 The node to which the first power supply voltage VDD is applied, and the node to which the second power supply voltage VSSN is applied. Figure 1 The node to which the second power supply voltage VSS is applied.

[0064] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via the sub-pixel circuit SPC. The cathode electrode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0065] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi (also referred to as gate line GLi) among the first gate line GL1 to the m-th gate line GLm Figure 1 The first transmit control line EL1 to the m-th transmit control line ELm, the i-th transmit control line ELi (also known as the transmit control line ELi), and Figure 1 The j-th data line DLj (also referred to as data line DLj) is one of the first data lines DL1 to the nth data line DLn. The sub-pixel circuit SPC can be configured to control the light-emitting element LD based on the signals received through these signal lines.

[0066] The sub-pixel circuit SPC can operate in response to a scan signal received via the i-th gate line GLi. The i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to a scan signal received via the first sub-gate line SGL1 and the second sub-gate line SGL2.

[0067] The sub-pixel circuit SPC can operate in response to the transmission control signal received via the i-th transmission control line ELi.

[0068] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of a plurality of scan signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN according to the stored voltage, in response to an emission control signal received via the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0069] Figure 3 It is shown Figure 1 A block diagram of an embodiment of a display panel and a gate driver.

[0070] Reference Figure 3 The gate driver 120 may include a first gate driver 122, a second gate driver 124, and an emitter driver 126.

[0071] The first gate driver 122 can receive a first scan start signal FLM1. The first gate driver 122 can generate a first scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first gate driver 122 can sequentially supply the first scan signal to the first-first sub-gate line SGL11 to the m-th first sub-gate line SGL1m. Among the first-first sub-gate lines SGL11 to the m-th first sub-gate line SGL1m, the i-th first sub-gate line can be... Figure 2 The first sub-gate line SGL1 of the i-th gate line GLi.

[0072] The second gate driver 124 can receive the second scan start signal FLM2. The second gate driver 124 can generate the second scan signal while shifting the second scan start signal FLM2 in response to a clock signal. The second gate driver 124 can sequentially supply the second scan signal to the first-second sub-gate line SGL21 to the m-th-second sub-gate line SGL2m. Among the first-second sub-gate lines SGL21 to the m-th-second sub-gate line SGL2m, the i-th-second sub-gate line can be... Figure 2 The second sub-gate line SGL2 is the i-th sub-gate line GLi.

[0073] The first scan signal may have a gate on-state voltage, causing the transistor in the sub-pixel SP that receives the first scan signal to turn on. In other words, supplying the first scan signal to the sub-gate line means supplying the gate on-state voltage to the corresponding sub-gate line. Similarly, the second scan signal may have a gate on-state voltage, causing the transistor in the sub-pixel SP that receives the second scan signal to turn on. In other words, supplying the second scan signal to the sub-gate line means supplying the gate on-state voltage to the corresponding sub-gate line.

[0074] Transmit driver 126 can receive a transmit start signal EFLM. Transmit driver 126 can generate transmit control signals while shifting the transmit start signal EFLM in response to a clock signal. Transmit driver 126 can sequentially supply transmit control signals to transmit control lines EL1 to ELm. The transmit control signals can have a gate cutoff voltage, causing the transistors of the sub-pixel SP to turn off. In other words, supplying transmit control signals to transmit control lines can mean supplying a gate cutoff voltage to the corresponding transmit control line.

[0075] The first scan start signal FLM1, the second scan start signal FLM2, and the transmit start signal EFLM can be included in Figure 1 The gate control signal GCS may also include clock signals provided to the first gate driver 122, the second gate driver 124, and the transmit driver 126.

[0076] Each of the plurality of sub-pixels SP may include a P-type transistor. For example, each of the plurality of sub-pixels SP may include a P-channel metal-oxide-semiconductor (PMOS) transistor. In this case, the first scan signal and the second scan signal may have a logic-low gate on voltage and a logic-high gate off voltage, and the transmit control signal may have a logic-low gate on voltage and a logic-high gate off voltage.

[0077] Figure 4 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0078] Reference Figure 4 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0079] A light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be physically disposed between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​of the LD may be electrically connected to a first power supply voltage node VDDN via a second node N2, a first transistor M1, and a third transistor M3. The cathode electrode CE of the LD may be electrically connected to a second power supply voltage node VSSN. The LD can generate light with a predetermined brightness based on the amount of current supplied between the first power supply voltage node VDDN and the second power supply voltage node VSSN via the sub-pixel circuit SPC.

[0080] The light-emitting element (LD) may include an organic light-emitting diode (OLED). However, embodiments of the present invention are not limited thereto. For example, the light-emitting element (LD) may include an inorganic light-emitting diode, a micro light-emitting diode (LED), or a quantum dot light-emitting diode. For example, the light-emitting element (LD) may be a device comprising both organic and inorganic materials. Figure 4 In the diagram, subpixel SPij is shown as including one light-emitting element LD, but is not limited thereto. For example, subpixel SPij may include two or more light-emitting elements. In this case, the two or more light-emitting elements may be connected in series or in parallel.

[0081] The sub-pixel circuit SPC may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor CP.

[0082] The first transistor M1 to the fourth transistor M4 can be P-channel metal-oxide-semiconductor (PMOS) transistors.

[0083] The first transistor M1 can be connected between the first node N1 and the second node N2. The gate electrode of the first transistor M1 can be connected to the third node N3. The first transistor M1 can control the amount of current supplied from the first power supply voltage node VDDN to the light-emitting element LD and to the second power supply voltage node VSSN in response to the voltage of the third node N3.

[0084] The second transistor M2 can be connected between the data line DLj and the third node N3. The gate electrode of the second transistor M2 can be connected to the first sub-gate line SGL1 of the gate line GL1. When the first scan signal GW is supplied to the first sub-gate line SGL1 (when the first scan signal GW is at a logic low gate on-state voltage), the second transistor M2 can be turned on and electrically connected to the data line DLj and the third node N3. In this case, the data signal DS of the data line DLj can be transmitted to the third node N3 via the second transistor M2.

[0085] The third transistor M3 can be connected between the first power supply voltage node VDDN and the first node N1. The gate electrode of the third transistor M3 can be connected to the emit control line ELi. When the emit control signal EM is supplied to the emit control line ELi (when the emit control signal EM is at a logic high gate cutoff voltage), the third transistor M3 can be turned off.

[0086] A fourth transistor M4 can be connected between the second node N2 and the initialization voltage node VinTN. The gate electrode of the fourth transistor M4 can be connected to the second sub-gate line SGL2 of the gate line GLi. When the second scan signal EB is supplied to the second sub-gate line SGL2 (when the second scan signal EB is at a logic low gate on-state voltage), the fourth transistor M4 can be turned on, electrically connecting the second node N2 to the initialization voltage node VinTN. The initialization voltage node VinTN can have an initialization voltage. The initialization voltage can be determined by... Figure 1 A voltage generator 140 is provided. In an example where the fourth transistor M4 is turned on and an initialization voltage is supplied to the anode electrode AE ​​of the light-emitting element LD, the light-emitting element LD can be turned off. The anode electrode AE ​​of the light-emitting element LD can be initialized.

[0087] The first transistor M1 to the fourth transistor M4 can be implemented on a silicon substrate. The first transistor M1 to the fourth transistor M4 can be metal-oxide-semiconductor field-effect transistors (MOSFETs), each including body electrodes BE1 to BE4. (See display panel 110) Figure 3The substrate of the display panel 110 may include semiconductor materials such as silicon, germanium, and / or silicon-germanium, suitable for forming the first transistor M1 to the fourth transistor M4. For example, a well can be formed within the silicon substrate by an ion implantation process, and the source and drain regions of the well can serve as the semiconductor portions of each transistor. In some aspects, conductive patterns disposed on the substrate can serve as the gate electrode of each transistor. The body electrode of each transistor can be electrically connected to the corresponding well. The first transistor M1 to the fourth transistor M4 implemented on the silicon substrate can be mounted in a small area. Therefore, the sub-pixels SP of the display panel 110 (see...) Figure 1 It can have a relatively high resolution.

[0088] When the first transistor M1 to the fourth transistor M4 are implemented on a silicon substrate, biasing the body electrodes BE1 to BE4 of the first transistor M1 to the fourth transistor M4 can ensure operational reliability. In some embodiments, the body electrodes BE1 to BE4 of the first transistor M1 to the fourth transistor M4 can be biased with a first supply voltage VDD (see...). Figure 1 Bias. For example, the body electrodes BE1 to BE4 of the first transistor M1 to the fourth transistor M4 can be commonly connected to the first power supply voltage node VDDN. Therefore, the body electrodes BE1 to BE4 of the first transistor M1 to the fourth transistor M4 can be effectively biased.

[0089] A capacitor CP can be connected between the first node N1 and the third node N3. The capacitor CP can be driven as a coupling capacitor. For example, the capacitor CP can transmit a voltage change in the third node N3 to the first node N1, or vice versa. The capacitor CP can store the voltage of the third node N3, for example, the voltage of the data signal DS received via data line DLj and the second transistor M2.

[0090] As described herein, the first transistor M1 through the fourth transistor M4 can be mounted in a relatively small area. Therefore, the sub-pixel SP (see...) Figure 1 A single subpixel can have a relatively high resolution. In some other subpixels, the size of each subpixel may be relatively large when the number of capacitors included in each subpixel is relatively large. Therefore, the resolution of such other subpixels may be reduced.

[0091] According to embodiments supported by this disclosure, in a sub-pixel SPij comprising a first transistor M1 to a fourth transistor M4 respectively having body electrodes BE1 to BE4, the sub-pixel SPij may include a capacitor CP connected between a first node N1 and a third node N3, but not a capacitor between a second node N2 and a third node N3. The sub-pixel SPij may include a single capacitor CP connected between the first node N1 and the third node N3, without any other capacitors (e.g., the sub-pixel SPij may be implemented without any capacitors other than the capacitor CP). Therefore, the display panel 110 and / or display device 100 can be reduced in size (see...). Figure 1 The cost (or manufacturing cost) of subpixels. In some respects, subpixels (SPs) can be designed to have increased resolution.

[0092] In some embodiments, the capacitor CP may be implemented as a metal-oxide-metal (MOM) capacitor, but is not limited thereto.

[0093] Figure 5 This indicates that it is provided during the display operation. Figure 4 Timing diagram of an embodiment of the signal of a sub-pixel. Figures 6 to 9 It is used to explain in Figure 5 A diagram of the subpixel operations in the first to fourth cycles.

[0094] First, refer to Figure 4 and Figure 5 During the first cycle T1, the second scan signal EB can be enabled with a gate on voltage (in other words, the second scan signal EB can be at a logic low level). The first scan signal GW can be disabled with a gate off voltage (in other words, the first scan signal GW can be at a logic high level), and the transmit control signal EM can be enabled with a gate on voltage (in other words, the transmit control signal EM can be at a logic low level).

[0095] Figure 6 Show Figure 4 The timing diagram 600 and operation example 601 for the sub-pixel SPij are shown. (Refer to...) Figure 6 During the first cycle T1, the third transistor M3 can be turned on in response to the emit control signal EM. Therefore, the first power supply voltage VDD of the first power supply voltage node VDDN (see...) Figure 1The initial voltage of the initialization voltage node VINTN can be transmitted to the first node N1 via the third transistor M3 (see path a). The fourth transistor M4 can be turned on in response to the second scan signal EB. Therefore, the initial voltage of the initialization voltage node VINTN can be transmitted to the second node N2 via the fourth transistor M4 (see path b). Thus, each of the first node N1 and the anode electrode AE ​​of the light-emitting element LD can be initialized to a predetermined voltage. As described herein, the first power supply voltage VDD can be applied to the body electrodes BE1 to BE4 of the first transistor M1 to the fourth transistor M4. This first cycle T1 can be referred to as the initialization cycle.

[0096] Refer again Figure 4 and Figure 5 In the second cycle T2, the first scan signal GW can be enabled with a gate on voltage (in other words, the first scan signal GW can transition to a logic low level or be at a logic low level). The transmit control signal EM can transition to a gate off voltage (logic high level). In some embodiments, the transmit control signal EM can transition to a gate off voltage after a predetermined time from the point when the first scan signal GW transitions to a gate on voltage. The second scan signal EB can continuously maintain a gate on voltage.

[0097] In the second period T2, with the sub-pixel SP in the i-th row (see...) Figure 1 The corresponding data signal can be applied to Figure 1 The first data line DL1 to the nth data line DLn. Therefore, Figure 5 The i-th data signal DSi can be applied as the data signal DS to Figure 4 The data line DLj. In the following text, the i-th data signal DSi can also be referred to as the data signal DSi.

[0098] Figure 7 Show Figure 4 The timing diagram 700 and operation example 701 for the sub-pixel SPij are shown below. (Refer to...) Figure 7 In the second cycle T2, the second transistor M2 can be turned on in response to the first scan signal GW. Therefore, the data signal DSi can be supplied to the third node N3 (see path c). The third transistor M3 can be turned off in response to the transmit control signal EM. The second node N2 can be continuously connected to the initialization voltage node VINTN (see path b) via the turned-on fourth transistor M4.

[0099] The gate electrode of the first transistor M1 can be connected to the third node N3. The gate electrode of the first transistor M1 can have a voltage (Vdata) of the data signal DSi. The capacitor CP can store the voltage (Vdata) of the data signal DSi. This second cycle T2 can be referred to as the data write cycle.

[0100] The source electrode of the first transistor M1 can be connected to the first node N1. The voltage of the first node N1 can be obtained by subtracting the threshold voltage (Vth) of the first transistor M1 from the voltage of its gate electrode. In this case, the threshold voltage (Vth) of the first transistor M1 can be a threshold voltage that reflects the body effect associated with the first transistor M1. For example, the gate-source voltage (Vgs) of the first transistor M1 can be determined according to Equation 1 below.

[0101] [Formula 1]

[0102] Vgs = Vdata - (Vdata - Vth)

[0103] In Equation 1, Vdata can represent the voltage of the data signal DSi, Vth can represent the threshold voltage of the first transistor M1, and Vgs can represent the gate-source voltage of the first transistor M1. The gate voltage of the first transistor M1 can be the voltage (Vdata) of the data signal DSi. The source voltage of the first transistor M1 can be obtained by subtracting the threshold voltage (Vth) of the first transistor M1 from the voltage (Vdata) of the data signal DSi. According to Equation 1, the gate-source voltage (Vgs) of the first transistor M1 can be the threshold voltage (Vth) of the first transistor M1.

[0104] The threshold voltage (Vth) of the first transistor M1 can be a reflection of the first power supply voltage VDD applied to the body electrode BE1 of the first transistor M1 (see [reference]). Figure 1 The threshold voltage of the body effect. For example, the threshold voltage (Vth) of the first transistor M1 can be determined according to Equation 2 below.

[0105] [Equation 2]

[0106] Vth=Vth0+α×((Vdata-Vth)-VDD)

[0107] In Equation 2, Vth0 can represent the intrinsic threshold voltage of the first transistor M1, and α can be a coefficient associated with the bulk effect and can be a constant. The coefficient (α) can be determined by the capacitance of the oxide layer disposed between the gate electrode and the channel of the first transistor M1 and the doping concentration of the n-well of the first transistor M1, etc. VDD can represent the first power supply voltage.

[0108] As shown in Equation 2, the threshold voltage (Vth) of the first transistor M1 can be determined by the sum of the intrinsic threshold voltage (Vth0) of the first transistor M1 and the threshold voltage due to the body effect. Here, the intrinsic threshold voltage (Vth0) of the first transistor M1 can be determined by the configuration of the first transistor M1 according to the manufacturing process, such as the channel width of the first transistor M1. The threshold voltage due to the body effect can be determined by subtracting the voltage of the body electrode BE1 of the first transistor M1 from the voltage of the source electrode of the first transistor M1.

[0109] As described herein, the source voltage of the first transistor M1 can be obtained by subtracting the threshold voltage (Vth) of the first transistor M1 from the voltage (Vdata) of the data signal DSi. The voltage of the body electrode BE1 of the first transistor M1 can be the first power supply voltage VDD.

[0110] According to Equation 2, Vth can be expressed as Equation 3 below.

[0111] [Formula 3]

[0112]

[0113] Refer again Figure 4 and Figure 5 In the third cycle T3, the first scan signal GW can be deactivated with a gate cutoff voltage (in other words, the first scan signal GW can transition to a logic high level or remain at a logic high level). The second scan signal EB can continuously maintain a gate on voltage (logic low level), and the transmit control signal EM can continuously maintain a gate off voltage (logic high level).

[0114] The first period T1 to the third period T3 can be defined as the sub-pixel SP of a row (see...). Figure 1 The horizontal cycle HP.

[0115] Figure 8 Show Figure 4 The timing diagram 800 and operation example 801 for the sub-pixel SPij. (Refer to...) Figure 8 The second transistor M2 can be turned off according to the gate cutoff voltage (logic high level) of the first scan signal GW. Since the second scan signal EB maintains the gate on voltage, the fourth transistor M4 can remain in a continuously on state (i.e., continuously on). The second node N2 can remain electrically connected to the initialization voltage node VINTN (see path b). Therefore, in the third cycle T3, the second node N2 can be continuously biased with the initialization voltage.

[0116] Due to the operation in the second period T2, the voltage of the second node N2 may increase undesirably. Therefore, unnecessary or unwanted current may be supplied to the light-emitting element LD. For example, even when the sub-pixel SPij (see...) Figure 4 When driven at the lowest gray level, if the voltage of the second node N2 increases undesirably, the light-emitting element LD may temporarily emit light. According to one or more embodiments of this disclosure, biasing the second node N2 with an initialization voltage while turning off the second transistor M2 in the third cycle T3 can prevent the light-emitting element LD from undesirably emitting light. Therefore, the display device 100 (see [link to relevant documentation]) can be improved. Figure 1 The grayscale performance of ). This third cycle T3 can be called the brightness control cycle.

[0117] In other embodiments, the third period T3 may be omitted.

[0118] Refer again Figure 4 and Figure 5 In the fourth cycle T4, the second scan signal EB can be deactivated with a gate cutoff voltage (in other words, the second scan signal EB can transition to a logic high level or remain at a logic high level). The transmit control signal EM can transition to a gate on voltage.

[0119] Figure 9 Show Figure 4 The timing diagram 900 and operation example 901 for the sub-pixel SPij are shown. (Refer to...) Figure 9 The fourth transistor M4 can be turned off in response to the second scan signal EB. The third transistor M3 can be turned on in response to the emission control signal EM. Therefore, the first transistor M1 can control the amount of current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN in response to the voltage of the third node N3 (see path d). During the fourth cycle T4, the light-emitting element LD can generate light with a brightness corresponding to the amount of current flowing through the first transistor M1. This fourth cycle T4 can be referred to as the emission cycle.

[0120] In some embodiments, during the fourth period T4, the first node N1 may have a first supply voltage VDD (see...). Figure 1 The voltage level of the first transistor M1. In this case, the body electrode BE1 and the source electrode of the first transistor M1 can be at essentially the same voltage. Therefore, the body effect of the first transistor M1 can be eliminated. Due to the capacitance of the capacitor CP, the capacitor CP can store the gate-source voltage (Vgs') of the first transistor M1 as the difference between the voltages across the capacitor CP. For example, in the fourth cycle T4, the gate-source voltage (Vgs') of the first transistor M1 can be Vth in Equation 3. Equation 3 can be expressed as Equation 4 below.

[0121] [Formula 4]

[0122]

[0123] In Equation 4, Vgs' can represent the gate-source voltage of the first transistor M1 in the fourth cycle T4.

[0124] Based on the gate-source voltage (Vgs') of the first transistor M1, the first transistor M1 can determine or control the amount of current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN. Referring to Equation 4, the gate-source voltage (Vgs') of the first transistor M1 can be changed according to the voltage (Vdata) of the data signal DSi. For example, the gate-source voltage (Vgs') of the first transistor M1 can increase as the voltage (Vdata) of the data signal DSi increases. The gate-source voltage (Vgs') of the first transistor M1 can decrease as the voltage (Vdata) of the data signal DSi decreases. In this way, the light-emitting element LD can emit light such that the amount of emitted light changes according to the voltage (Vdata) of the data signal DSi.

[0125] Referring to Equation 4, the voltage (Vdata) of the data signal DSi can be determined according to... This is reflected in the gate-source voltage (Vgs') of the first transistor M1. Therefore, the change in the gate-source voltage (Vgs') of the first transistor M1 can be relatively small compared to the change in the voltage (Vdata) of the data signal DSi. Considering that the allowable range of the voltage applied to the electrodes of the first transistor M1 may be limited, the allowable swing width of the voltage (Vdata) of the data signal DSi can be increased as the coefficient (α) decreases. Therefore, according to Equation 4, the range of the voltage (Vdata) of the data signal DSi can be extended. Thus, for example, the voltage (Vdata) of the data signal DSi has improved reliability in representing each gray level.

[0126] The intrinsic threshold voltage (Vth0) of the first transistor M1 can be determined according to... The ratio is reflected in the gate-source voltage (Vgs') of the first transistor M1. The variation in the gate-source voltage (Vgs') of the first transistor M1 can be relatively small compared to the error (e.g., process error) of the intrinsic threshold voltage (Vth0) of the first transistor M1. Therefore, the light-emitting element LD can be driven with relatively high reliability based on the data signal DSi.

[0127] Due to errors during the manufacturing process, and stress caused by the drive, etc. Figure 1The first transistor of a sub-pixel SP can have different intrinsic threshold voltages. In other words, the intrinsic threshold voltages of the first transistor of a sub-pixel SP can have a specific distribution. For example, if the error in the intrinsic threshold voltage (Vth0) of the first transistor M1 of each sub-pixel increases, the distribution of the intrinsic threshold voltage can become wider. In this case, undesirable muras may appear in the image displayed by the sub-pixel SP. Figure 1 The controller 150 can employ at least one of various algorithms for compensating for blemishes in an image. The blemish compensation algorithm of the controller 150 can process the input image data IMG (see [link to relevant documentation]) using various methods. Figure 1 ) or image data DATA (see Figure 1 The processed data is then provided to data drive 130 (see [link]). Figure 1 The data driver 130 can drive the sub-pixel SP based on the processed data. Therefore, the sub-pixel SP can be driven with higher reliability based on the data signal.

[0128] Figure 10 It is shown Figure 1 A plan view of an embodiment of the display panel.

[0129] Reference Figure 10 Display panel DP ( Figure 1 One embodiment of the display panel 110 may include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0130] The display panel (DP) can include a substrate (SUB), subpixels (SP), and pads (PD).

[0131] When the display panel DP is used as a display screen for head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, or augmented reality (AR) devices, the display panel DP can be positioned very close to the user's eyes. In this case, it may be necessary to have relatively highly integrated sub-pixels SP. To increase the integration of the sub-pixels SP, the substrate SUB can be provided as a silicon substrate. The sub-pixels SP can be formed on the substrate SUB, which is a silicon substrate. Display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see...) Figure 1 This can be referred to as an organic light-emitting diode (OLEDoS) display device on silicon.

[0132] Subpixels SP can be disposed on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, embodiments of the present invention are not limited thereto. For example, subpixels SP can be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0133] Two or more sub-pixels SP can form a pixel PXL.

[0134] Components for controlling subpixels SP can be set on the base SUB in the non-display area NDA. For example, such as... Figure 1 The first gate line GL1 to the m-th gate line GLm, Figure 1 The first transmit control line EL1 to the m-th transmit control line ELm, and Figure 1 Taking the first data line DL1 to the nth data line DLn as an example, the wiring can be set in the non-display area NDA.

[0135] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 may be integrated into the non-display area NDA of the display panel DP. In some embodiments, Figure 1 The gate driver 120 can be mounted on the display panel DP and disposed in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP.

[0136] The pad PD can be positioned on the substrate SUB within the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wiring. For example, the pad PD can be connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0137] The pad PD can connect the display panel DP interface to the display device 100 (see...). Figure 1 Other components. In some embodiments, voltages and signals supporting the operation of components included in the display panel DP can be transmitted from the pads PD via... Figure 1 A driver integrated circuit (DIC) is provided. For example, first data lines DL1 to nth data lines DLn can be connected to the driver integrated circuit (DIC) via pad PD. For example, a first power supply voltage VDD can be received from the driver integrated circuit (DIC) via pad PD (see...). Figure 1 ) and the second power supply voltage VSS (see Figure 1In an example where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS (see...) Figure 1 It can be transferred from the driver integrated circuit DIC to the gate driver 120 via the pad PD.

[0138] In some embodiments, a conductive adhesive component, such as an anisotropic conductive film, can be used to electrically connect the circuit board to the pads (PD). In this case, the circuit board can be a flexible circuit board (FPCB) or a flexible film formed of a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board and electrically connected to the pads (PD).

[0139] In some embodiments, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, or ellipses.

[0140] In some embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially curved. In some embodiments, the display panel DP may be bent, folded, or rolled. In these cases, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0141] Figure 11 It is shown Figure 10 An exploded perspective view of a portion of the display panel. Figure 11 For clarity and conciseness, the display panel DP is schematically shown (see [link]). Figure 10 ) and Figure 10 The portion corresponding to two pixels PXL1 and PXL2 among the multiple pixels PXL. The other portions of the display panel DP corresponding to the remaining pixels PXL can be configured similarly.

[0142] Reference Figure 10 and Figure 11 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, embodiments of the present invention are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0143] exist Figure 11In the diagram, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are shown as having a rectangular shape and the same size when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2. However, embodiments of the present invention are not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be modified to have various shapes.

[0144] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), an outer coating layer (OC), and a cover window (CW).

[0145] In some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0146] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and a conductive pattern disposed between the insulating layer. The conductive pattern of the pixel circuit layer (PCL) can be used as at least some of circuit elements and wiring, etc. The conductive pattern may include copper, but embodiments of the present invention are not limited thereto.

[0147] The circuit elements may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see [link to circuit diagram]). Figure 2 Subpixel circuitry (SPC) may include... Figure 4The first transistor M1 to the fourth transistor M4 and the capacitor CP are included. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included within the substrate SUB, and the gate electrode may be included within the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. The body electrode of each transistor may be further provided on the bottom of the substrate SUB or in a region adjacent to the bottom of the substrate SUB. The capacitor CP may include electrodes spaced apart from each other. For example, the capacitor CP may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, the capacitor CP may include electrodes spaced apart from each other on a third direction DR3, with an insulating layer between the electrodes. If the sub-pixel circuit SPC does not include any capacitors other than the capacitor CP, the area occupied by the sub-pixel circuit SPC can be reduced, and the cost (or manufacturing cost) of the sub-pixel circuit SPC can be reduced.

[0148] The wiring of the pixel circuit layer (PCL) may include signal lines, such as gate lines, emit control lines, and data lines, connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The wiring may also include connections to... Figure 2 The wiring of the first power supply voltage node VDDN. In some aspects, the wiring may also include connections to... Figure 2 Wiring of the second power supply voltage node VSSN.

[0149] The light-emitting element layer (LDL) may include an anode electrode (AE), a pixel-defining layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0150] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material that can reflect light, but embodiments of this invention are not limited thereto.

[0151] A pixel-defining layer (PDL) may be disposed on an anode electrode (AE). The PDL may include an opening (OP) that exposes a portion of each of a plurality of anode electrodes (AE). The opening (OP) of the PDL can be understood as an emission region corresponding to each of a first sub-pixel (SP1), a second sub-pixel (SP2), and a third sub-pixel (SP3).

[0152] In some embodiments, the pixel-defining layer (PDL) may comprise an inorganic material. In this case, the pixel-defining layer (PDL) may comprise multiple stacked inorganic layers. For example, the pixel-defining layer (PDL) may comprise silicon oxide (SiO2). x ) and silicon nitride (SiN)x In other embodiments, the pixel defining layer (PDL) may include an organic material. However, the material of the pixel defining layer (PDL) is not limited thereto.

[0153] The light-emitting structure (EMS) can be disposed on each of a plurality of anode electrodes (AEs) exposed by the opening (OP) of the pixel-defining layer (PDL). The light-emitting structure (EMS) may include a light-emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes, etc.

[0154] In some embodiments, the light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL, but can be completely disposed on top of the pixel-defining layer PDL. In other words, the light-emitting structure EMS can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this case, at least some of the multiple layers of the light-emitting structure EMS can break or bend at the boundary between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, a trench can be formed in the pixel-defining layer PDL, and due to the trench, the light-emitting structure EMS can break or bend at the boundary between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, embodiments of the present invention are not limited thereto. For example, the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be separated from each other and spaced apart, and each of the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be disposed within the opening OP of the pixel-defining layer PDL.

[0155] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this way, the cathode electrode CE can be used as a common electrode for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0156] The cathode electrode CE can be a thin metal layer with a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE can be formed of a metallic material or a transparent conductive material to have a relatively thin thickness. In some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited to these.

[0157] Any one of the multiple anode electrodes AE, the portion of the light-emitting structure EMS overlapping with the anode electrode AE, and the portion of the cathode electrode CE overlapping with the anode electrode AE ​​can be understood as constituting a light-emitting element LD (see [link to LD]). Figure 2 In other words, each of the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include an anode electrode, a portion of the light-emitting structure EMS overlapping the anode electrode, and a portion of the cathode electrode CE overlapping the anode electrode. In each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE can be transferred to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined based on the configuration of the light-emitting layer.

[0158] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In some embodiments, the encapsulation layer TFE can include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layers can include silicon nitride, silicon oxide, or silicon oxynitride (SiO2). x N y For example, the organic layer may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic and inorganic layers of the encapsulation layer TFE are not limited to these.

[0159] To improve the encapsulation effect of the TFE encapsulation layer, the TFE encapsulation layer may also include aluminum oxide (AlO2). x A thin film, including aluminum oxide, can be positioned on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0160] Thin films including alumina can be formed using atomic layer deposition (ALD). However, embodiments of the present invention are not limited thereto. The encapsulation layer TFE may also comprise a thin film formed from at least one of a variety of materials suitable for improving encapsulation performance.

[0161] The optical functional layer (OFL) can be disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0162] A color filter layer (CFL) can be disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL can be configured to filter light emitted from the light-emitting structure (EMS) and selectively output light of a wavelength range or color corresponding to each sub-pixel. The CFL may include color filters (CF) corresponding to first sub-pixels SP1, SP2, and SP3. Each of the multiple color filters (CF) allows light within the wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the light-emitting structure (EMS) of each sub-pixel, at least some of the multiple color filters (CF) may be omitted.

[0163] A lens array LA can be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Each of the plurality of lenses LS can improve light output efficiency by outputting light emitted from the light-emitting structure EMS via a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the outer coating OC. In some embodiments, the lenses LS may include organic materials. In some embodiments, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not limited thereto.

[0164] An outer coating OC can be disposed on the lens array LA. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layer from foreign substances such as dust or moisture. For example, the outer coating OC can include at least one of inorganic and organic insulating layers. For example, the outer coating OC can include epoxy resin, but embodiments of the present invention are not limited thereto. The outer coating OC can have a lower refractive index than the lens array LA.

[0165] A cover window CW can be disposed on the outer coating OC. The cover window CW can be configured to protect the layer beneath it. The cover window CW can have a higher refractive index than the outer coating OC. The cover window CW can include glass, but embodiments of the present invention are not limited thereto. For example, the cover window CW can be encapsulation glass configured to protect components disposed beneath it. In other embodiments, the cover window CW may be omitted.

[0166] Figure 12 This is a block diagram illustrating an embodiment of the display system.

[0167] Reference Figure 12 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0168] The processor 1100 can perform various tasks and calculations. In some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, and a central processing unit (CPU), etc. The processor 1100 can be connected to and control other components of the display system 1000 via a bus system.

[0169] exist Figure 12 In the diagram, the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 is connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0170] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be used with a reference... Figure 1 The described display device 100 is similarly configured. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as follows: Figure 1 The input image data is IMG and the control signal is CTRL.

[0171] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be used with a reference... Figure 1 The described display device 100 is similarly configured. In this case, the second image data IMG2 and the second control signal CTRL2 can be provided as follows: Figure 1 The input image data is IMG and the control signal is CTRL.

[0172] As described in this article, Figure 1 The display device 100 has multiple sub-pixels SP (see Figure 1 Each of the following can include connections in Figure 4A single capacitor CP is used between the first node N1 and the third node N3, without any other capacitors (e.g., each of the multiple sub-pixels SP can be implemented without any other capacitors besides capacitor CP). Therefore, the display system 1000 can be designed to include sub-pixels SP with increased resolution. In some respects, this can reduce the cost (or manufacturing cost) of the display system 1000.

[0173] Display system 1000 may include computing systems that provide image display capabilities, such as portable computers, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). In some aspects, display system 1000 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0174] Figure 13 It is shown Figure 12 A perspective view of an application example of the display system.

[0175] Reference Figure 13 , Figure 12 The display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0176] The head-mounted display device 2000 may include a headband 2100 and a display device storage housing 2200. The headband 2100 may be connected to the display device storage housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, embodiments of the present invention are not limited thereto. For example, the headband 2100 may be implemented in the form of an eyeglass frame or a helmet, etc.

[0177] The display device storage casing 2200 can accommodate Figure 12 The first display device 1210 and the second display device 1220. The display device storage housing 2200 can also accommodate... Figure 12 The processor is 1100.

[0178] Figure 14 It is shown Figure 13 An image of a head-mounted display device worn by a user.

[0179] Reference Figure 14Within the head-mounted display device 2000, a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220 may be provided. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0180] Within the display device storage housing 2200, the right eye lens RLNS can be positioned between the first display panel DP1 and the user's right eye. Within the display device storage housing 2200, the left eye lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0181] The image output from the first display panel DP1 can be displayed to the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to guide it towards the user's right eye. The right eye lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0182] The image output from the second display panel DP2 can be displayed to the user's left eye via the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 to guide it towards the user's left eye. The left eye lens LLNS can perform optical functions to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0183] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. In this case, each display panel can output an image corresponding to a sub-region of the multi-channel lens, and the output image can pass through the corresponding sub-region and be displayed to the user.

[0184] The effects of the embodiments of this utility model are not limited to those described herein, and various other effects are included in this specification.

[0185] Although specific embodiments and applications have been described herein, other embodiments and variations can be derived from the above description. Therefore, the spirit of this invention is not limited to the exemplary embodiments, but extends to the scope of the claims set forth herein, various obvious modifications and equivalents.

Claims

1. A sub-pixel, included in a display device, characterized by, The sub-pixels include: A first transistor is connected between a first node and a second node and includes a gate electrode connected to a third node; The second transistor is connected between the data line and the third node and includes a gate electrode connected to the first sub-gate line; A third transistor is connected between the first node and a first power supply voltage node configured to supply a first power supply voltage, and the third transistor includes a gate electrode connected to an emitter control line; and A light-emitting element is connected between the second node and a second power supply voltage node configured to supply a second power supply voltage lower than the first power supply voltage. Wherein, the body electrode of the first transistor to the body electrode of the third transistor are biased by at least one voltage, and The sub-pixel also includes a capacitor connected between the first node and the third node, but not a capacitor connected between the second node and the third node.

2. The sub-pixel of claim 1, wherein, The first power supply voltage is applied to the body electrode of the first transistor.

3. The sub-pixel of claim 1, wherein, The sub-pixel does not include any capacitors other than the capacitor itself.

4. The sub-pixel of claim 1, wherein, The sub-pixel also includes: A fourth transistor is connected between the second node and an initialization voltage node configured to supply an initialization voltage, and the fourth transistor includes a gate electrode connected to the second sub-gate line.

5. The sub-pixel of claim 4, wherein, The first power supply voltage is commonly applied to the body electrode of the first transistor, the body electrode of the third transistor, and the body electrode of the fourth transistor.

6. The sub-pixel of claim 4, wherein, Each of the first to the fourth transistors is a P-channel metal-oxide-semiconductor transistor.

7. The sub-pixel of claim 4, wherein, The first to the fourth transistors are mounted on a silicon substrate.

8. A display device, characterized by comprising: The display device includes: Multiple sub-pixels, connected to multiple gate lines and multiple emission control lines; and A gate driver configured to control the plurality of gate lines and the plurality of emitter control lines. The sub-pixels among the plurality of sub-pixels include: A first transistor is connected between a first node and a second node and includes a gate electrode connected to a third node; The second transistor is connected between the data line and the third node and includes a gate electrode connected to a first sub-gate line of one of the plurality of gate lines; A third transistor is connected between the first node and a first power supply voltage node configured to supply a first power supply voltage, and the third transistor includes a gate electrode connected to one of the plurality of emitter control lines; and A light-emitting element is connected between the second node and a second power supply voltage node configured to supply a second power supply voltage lower than the first power supply voltage. Wherein, the body electrode of the first transistor to the body electrode of the third transistor are biased by at least one voltage, and The sub-pixel also includes a capacitor connected between the first node and the third node, but not a capacitor connected between the second node and the third node.

9. The display device according to claim 8, wherein The first power supply voltage is applied to the body electrode of the first transistor.

10. The display device according to claim 8, wherein The sub-pixel does not include any capacitors other than the capacitor itself.

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