Display device

Abstract

A display device includes: a first buffer layer disposed on a substrate; an etch stop layer disposed on the first buffer layer; a second buffer layer disposed on the etch stop layer, the second buffer layer including a first hole exposing at least a portion of an upper surface of the etch stop layer; an active layer disposed on the second buffer layer, the active layer including a conductive region and a second hole exposing the first hole; and an inorganic layer disposed on the active layer, the inorganic layer filling the first hole and the second hole.

Description

Technical Field

[0001] The embodiments relate to a display device. More specifically, the embodiments relate to a display device and a method of manufacturing the display device. Background Technology

[0002] A display device is a device that displays images to provide visual information to a user. With the development of information technology, the importance of display devices, which act as a connection medium between users and information, has increased. For example, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) is on the rise.

[0003] A display device may include a partially doped active layer and multiple layers disposed around the active layer. During the manufacture of the display device, a portion of the active layer may be etched. During the etching process, steps may form between the active layer and the layers surrounding it. If the steps are large, moisture may easily penetrate into the display device. Consequently, the reliability of the display device may be reduced. Summary of the Invention

[0004] The embodiment provides a display device with improved reliability.

[0005] According to an embodiment of the present disclosure, a display device includes: a first buffer layer disposed on a substrate; an etch stop layer disposed on the first buffer layer; a second buffer layer disposed on the etch stop layer, the second buffer layer including a first hole exposing at least a portion of the upper surface of the etch stop layer; an active layer disposed on the second buffer layer, the active layer including a conductive region and a second hole exposing the first hole; and an inorganic layer disposed on the active layer, the inorganic layer filling the first hole and the second hole.

[0006] In an embodiment, the etch stop layer may include a material different from that of the second buffer layer.

[0007] In embodiments, the etch stop layer may include a metal oxide, silicon (Si), or silicon nitride (SiN). x ) and silicon nitride oxide (SiN) x O y At least one compound in the group consisting of ).

[0008] In an embodiment, the second buffer layer may include silicon oxide (SiO2). x ).

[0009] In an embodiment, the display device may further include a third buffer layer disposed between the first buffer layer and the etch stop layer, and the etch stop layer may include a material different from that of the third buffer layer.

[0010] In an embodiment, the third buffer layer may include silicon oxide.

[0011] In an embodiment, the sum of the depths of the first hole and the second hole may be less than or equal to approximately 30 nm.

[0012] In this embodiment, the etch stop layer can directly contact the inorganic layer through the first and second holes.

[0013] In one embodiment, the inorganic layer may cover the ends of each of the active layer and the second buffer layer exposed by the first and second holes.

[0014] In an embodiment, around the ends of the active layer and the second buffer layer, the inorganic layer may directly contact the upper surface of the active layer, the side surface of the active layer, the side surface of the second buffer layer, and a portion of the upper surface of the etch stop layer.

[0015] In an embodiment, the display device may further include: a gate insulating layer disposed on the active layer; a gate electrode disposed on the gate insulating layer; and a contact electrode disposed on the gate insulating layer and in direct contact with a portion of the conductive region.

[0016] In one embodiment, the gate insulating layer includes a third aperture that exposes the second aperture and a portion of the upper surface of the active layer. The size of the third aperture may be larger than the size of the second aperture.

[0017] In an embodiment, each of the first hole and the second hole may be located between the gate electrode and the contact electrode.

[0018] According to an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a first buffer layer on a substrate; forming an etch stop layer on the first buffer layer; forming a second buffer layer on the etch stop layer, the second buffer layer including a first hole exposing at least a portion of the upper surface of the etch stop layer; forming an active layer on the second buffer layer, the active layer including a second hole exposing the first hole; and forming an inorganic layer on the active layer, the inorganic layer filling the first hole and the second hole.

[0019] In one embodiment, forming the second buffer layer may include forming a pre-buffered layer on the etch stop layer. The first via is formed by removing a portion of the pre-buffered layer. Forming the active layer may include forming a pre-active layer on the pre-buffered layer. The second via is formed by removing a portion of the pre-active layer.

[0020] In one embodiment, the formation of the first hole may include removing a portion of the pre-buffer layer in the thickness direction by spraying etching gas onto the pre-buffer layer to expose the upper surface of the etch stop layer.

[0021] In one embodiment, the formation of the first hole can be performed after the formation of the second hole.

[0022] In an embodiment, the method may further include: forming a gate insulating layer on a pre-active layer, the gate insulating layer including a gate aperture exposing a portion of the upper surface of the pre-active layer; forming a gate electrode on the gate insulating layer; and forming a contact electrode on the gate insulating layer, the contact electrode being spaced apart from the gate electrode.

[0023] In this embodiment, the size of the gate aperture is smaller than the size of the second aperture.

[0024] In an embodiment, the method may further include forming a third hole by expanding the gate hole, and the size of the third hole may be larger than the size of the second hole.

[0025] In a display device according to an embodiment of the present disclosure, the display device may include: a first buffer layer disposed on a substrate; an etch stop layer disposed on the first buffer layer; a second buffer layer disposed on the etch stop layer and defining a first hole therein; an active layer disposed on the second buffer layer and defining a second hole therein; and an inorganic layer filling the first hole and the second hole. Since the first hole does not penetrate the etch stop layer in the thickness direction and exposes at least a portion of the upper surface of the etch stop layer, it can prevent the formation of a moisture permeability path through which external moisture flows to the inorganic layer filling the first hole. Accordingly, defects in the display device can be prevented, and the reliability of the display device can be improved. Attached Figure Description

[0026] The illustrative, non-limiting embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 The illustration is based on an embodiment of the present disclosure. Figure 1 A block diagram of the driver for the display device.

[0029] Figure 3 The illustration is based on an embodiment of the present disclosure. Figure 1 The circuit diagram of the pixels.

[0030] Figure 4 The illustration is based on an embodiment of the present disclosure. Figure 1 A planar image of pixels.

[0031] Figure 5 It is according to the embodiments of this disclosure along Figure 4 A cross-sectional view of pixels intercepted by line I-I'.

[0032] Figure 6 It is according to the embodiments of this disclosure along Figure 4 A cross-sectional view of the pixels captured by line II-II'.

[0033] Figure 7 , Figure 8 , Figure 10 , Figure 12 , Figure 13 , Figure 16 and Figure 20 Manufacturing according to embodiments of the present disclosure Figure 1 A plan view of the method for displaying the device.

[0034] Figure 9 , Figure 11 , Figure 14 , Figure 15 , Figure 17 , Figure 18 , Figure 19 , Figure 21 , Figure 22 and Figure 23 Manufacturing according to embodiments of the present disclosure Figure 1 A cross-sectional view of the method for displaying the device. Detailed Implementation

[0035] In the following, the display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts may be omitted for brevity.

[0036] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0037] refer to Figure 1 The display device according to embodiments of the present disclosure may include a display area DA and a peripheral area PA.

[0038] In this specification, a plane may be defined on a first direction DR1 and a second direction DR2. For example, in an embodiment, the second direction DR2 may be perpendicular to the first direction DR1. Additionally, in an embodiment, the third direction DR3 may be perpendicular to the plane. However, the embodiments of this disclosure are not limited to this, and the first direction to the third direction DR1, DR2, DR3 may intersect each other at various different angles.

[0039] The display area DA can be defined as an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. At least one pixel PX can be disposed within the display area DA. The pixel PX can emit light.

[0040] In embodiments, multiple pixels PX can be arranged in a matrix. For example, multiple pixels PX can be arranged along a first direction DR1 and a second direction DR2. Additionally, a pixel PX may include multiple sub-pixels that emit light of different colors. For example, in embodiments, sub-pixels may include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light. However, embodiments of this disclosure are not limited to this, and the number of different sub-pixels and the color of light emitted by the sub-pixels can vary.

[0041] The peripheral area PA can be defined as an area where no image is displayed. The peripheral area PA can be located around the display area DA. For example, the peripheral area PA can (e.g., in the first direction DR1 and the second direction DR2) surround at least a portion of the display area DA.

[0042] In this embodiment, the driver may be located in the peripheral region PA. For example, the driver may drive a pixel PX. The driver may include a data driver, a gate driver, a light-emitting driver, a power supply voltage generator, and a timing controller. The pixel PX may emit light based on signals received from the driver.

[0043] Figure 2 It is a diagram. Figure 1 A block diagram of the driver for the display device.

[0044] refer to Figure 2 The display device DD may include a display panel PN, a data driver DIC, a gate driver GIC, and a controller TC.

[0045] In this embodiment, the controller TC can receive data signals and input control signals from an external device. The controller TC can transmit the data signals to data lines DL and GL. In this embodiment, the image data signals may include red (R) image data, green (G) image data, and blue (B) image data. The controller TC can generate data signals and GL signals based on the image data signals and the input control signals.

[0046] Multiple pixels PX and signal lines that apply electrical signals to the pixels can be disposed on the display panel PN. In an embodiment, the signal lines may include gate lines GL extending in a first direction DR1 and data lines DL extending in a second direction DR2.

[0047] Gate lines GL are arranged to be spaced apart from each other along a second direction DR2 and can transmit gate signals to pixels PX. Data lines DL are arranged to be spaced apart from each other along a first direction DR1 and can transmit data signals to pixels PX. In an embodiment, each pixel PX can be connected to at least one corresponding gate line in the gate lines GL and at least one corresponding data line in the data lines DL.

[0048] In one embodiment, the data driver DIC is connected to the data line DL and can supply data signals to the data line DL in response to a data control signal provided from the controller TC.

[0049] In an embodiment, the gate driver GIC can be connected to the gate line GL, generate gate signals in response to gate control signals provided from the controller TC, and sequentially supply the gate signals to the gate line GL.

[0050] In one embodiment, the power supply PS and the display panel PN can be arranged to be spaced apart from each other along the second direction DR2. The power supply PS can transmit a drive voltage ELVDD, thereby driving the display panel PN. In another embodiment, the power supply PS can also transmit a common voltage ELVSS.

[0051] Figure 3 It is a diagram. Figure 1 The circuit diagram of the pixels.

[0052] refer to Figure 3 A pixel PX may include a pixel circuit PC and a light-emitting element LED electrically connected to the pixel circuit PC. In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, and a third transistor T3, a storage capacitor CST, and a light-emitting capacitor CLED. However, embodiments of this disclosure are not limited thereto.

[0053] The first transistor T1 may include a first electrode, a gate electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. A drive voltage ELVDD may be applied to the first electrode of the first transistor T1. The second electrode of the first transistor T1 may be connected to a second node N2. In an embodiment, the first transistor T1 may receive the drive voltage ELVDD from a drive voltage line in response to the voltage of the first node N1 and supply drive current to the light-emitting element LED. For example, the first transistor T1 may be a drive transistor for driving the light-emitting element LED.

[0054] The second transistor T2 may include a first electrode, a gate electrode, and a second electrode. A first scan signal SC may be applied to the gate electrode of the second transistor T2. A data voltage VDATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the first node N1. In an embodiment, the second transistor T2 is turned on by the first scan signal SC, and the second transistor T2 may electrically connect the data line providing the data voltage VDATA to the first node N1. For example, the second transistor T2 may be a switching transistor.

[0055] The third transistor T3 may include a first electrode, a gate electrode, and a second electrode. A second scan signal SS may be applied to the gate electrode of the third transistor T3. An initialization voltage VINT may be applied to the first electrode of the third transistor T3. The second electrode of the third transistor T3 may be connected to the second node N2. In an embodiment, the third transistor T3 is turned on by the second scan signal SS to electrically connect the initialization voltage line providing the initialization voltage VINT to the second node N2. For example, the third transistor T3 may be an initialization transistor.

[0056] The storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may be connected to a first node N1. The second electrode of the storage capacitor CST may be connected to a second node N2. The storage capacitor CST may store the voltage difference between the gate voltage and the source voltage of the first transistor T1.

[0057] The light-emitting capacitor CLED may include a first electrode and a second electrode. The first electrode of the light-emitting capacitor CLED may be connected to a second node N2. The second electrode of the light-emitting capacitor CLED may be connected to the second electrode of the light-emitting element LED. In an embodiment, the light-emitting capacitor CLED can maintain a constant voltage across the two ends of the light-emitting element LED, thereby enabling the light-emitting element LED to display a constant brightness.

[0058] A light-emitting element (LED) may include a first electrode (e.g., an anode electrode) and a second electrode (e.g., a cathode electrode). The first electrode of the LED may be connected to a second node N2. A common voltage ELVSS may be applied to the second electrode of the LED. The LED may emit light with a brightness corresponding to the drive current supplied from the pixel circuit PC.

[0059] However, embodiments of this disclosure are not necessarily limited to pixels PX having three transistors (e.g., a first transistor T1, a second transistor T2, and a third transistor T3), a storage capacitor CST, and a light-emitting capacitor CLED. Figure 3 The embodiments shown are examples of those shown, and one or more of these elements may vary.

[0060] Furthermore, embodiments of this disclosure are not necessarily limited to those in which pixel PX includes a light-emitting element LED. Figure 3 The embodiments shown are illustrated. For example, in some embodiments, a pixel PX may include two or more light-emitting elements.

[0061] Figure 4 It is a diagram. Figure 1 A planar image of pixels. Figure 5 The diagram is along Figure 4 A cross-sectional view of pixels intercepted by line I-I'.

[0062] refer to Figure 4 and Figure 5 In the embodiments, Figure 1 The display device DD may include a substrate SUB, a light-shielding layer BML, a driving voltage line VDL, a first buffer layer BUF1, a second buffer layer BUF2, an etch stop layer ESL, a third buffer layer BUF3, a transistor TR, a gate insulating layer GI, a contact electrode CTE, an inorganic layer PVX, a through-hole layer VIA, a light-emitting element LED, a pixel defining layer PD, and a packaging layer TFE. The pixel PX may include a transistor TR and a light-emitting element LED.

[0063] In some embodiments, the substrate SUB may include a glass substrate, a metal substrate, and a plastic substrate. However, the embodiments of this disclosure are not limited to these, and in some embodiments, the substrate SUB may be an inorganic layer, an organic layer, or a composite material layer.

[0064] The light-shielding layer BML can be disposed on the substrate SUB (e.g., directly disposed on a third-party DR3). In embodiments, the light-shielding layer BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), etc. These materials can be used alone or in combination with each other. For example, the light-shielding layer BML may be a single layer comprising molybdenum. Alternatively, the light-shielding layer BML may have a bilayer structure in which a first layer comprising molybdenum and a second layer comprising titanium are stacked, or a trilayer structure in which a first layer comprising titanium, a second layer comprising aluminum, and a third layer comprising titanium are stacked. However, the embodiments disclosed herein are not limited to these.

[0065] The drive voltage line VDL can be disposed on the substrate SUB (e.g., directly disposed on the third-party DR3). The drive voltage line VDL can transmit the drive voltage (e.g., Figure 3 The driving voltage (ELVDD) is transmitted to the pixel PX.

[0066] In this embodiment, the driving voltage line VDL may comprise the same material as the light-shielding layer BML. Alternatively, the driving voltage line VDL and the light-shielding layer BML may be disposed on the same layer. In this embodiment, the driving voltage line VDL may be spaced apart from the light-shielding layer BML in a first direction DR1 in a plan view. Different types of electrical signals may be applied to the driving voltage line VDL and the light-shielding layer BML.

[0067] The first buffer layer BUF1 can be disposed on the substrate SUB (e.g., directly disposed on the third-direction DR3). For example, the first buffer layer BUF1 can cover the light-shielding layer BML and the drive voltage line VDL. The first buffer layer BUF1 can prevent impurities such as oxygen and moisture from penetrating into the upper part of the substrate SUB. In addition, when the surface of the substrate SUB is uneven, the first buffer layer BUF1 can increase the flatness of the SUB surface.

[0068] In this embodiment, the first buffer layer BUF1 may include an inorganic insulating material. For example, the inorganic insulating material may include silicon nitride (SiN). x ).

[0069] The second buffer layer BUF2 can be disposed on the first buffer layer BUF1 (e.g., directly disposed on the third-party DR3). For example, the second buffer layer BUF2 can cover the first buffer layer BUF1. The second buffer layer BUF2 may include an inorganic insulating material. For example, in an embodiment, the inorganic insulating material may include silicon oxide (SiO2). x However, the embodiments disclosed herein are not limited thereto.

[0070] In some embodiments, the second buffer layer BUF2 may comprise a different material than the first buffer layer BUF1. For example, the second buffer layer BUF2 may comprise silicon oxide, and the first buffer layer BUF1 may comprise silicon nitride. However, the embodiments of this disclosure are not limited thereto, and in some embodiments, the second buffer layer BUF2 may comprise the same material as the first buffer layer BUF1.

[0071] The etch stop layer ESL can be set on the second buffer layer BUF2 (e.g., directly on the third-party DR3). For example, the etch stop layer ESL can cover the second buffer layer BUF2.

[0072] In an embodiment, the etch stop layer ESL may comprise a silicon nitride (e.g., SiN). x ).

[0073] For example, in one embodiment, the etch stop layer ESL may include silicon nitride (SiN) x O y ).

[0074] In embodiments, the etch stop layer ESL may include silicon (Si) and metal oxides, etc. These materials may be used alone or in combination with each other. For example, in embodiments, the etch stop layer ESL may include materials selected from metal oxides, silicon (Si), silicon nitrides (SiN), etc. x ) and silicon nitride oxide (SiN) x O yAt least one material from the group consisting of ). For example, metal oxides may include aluminum oxide (AlO). x ).

[0075] In some embodiments, the etch stop layer ESL may comprise different materials from the second buffer layer BUF2. For example, the etch stop layer ESL may comprise silicon nitride, and the second buffer layer BUF2 may comprise silicon oxide. However, the embodiments disclosed herein are not necessarily limited to these.

[0076] The third buffer layer BUF3 can be disposed on the etch stop layer ESL (e.g., directly on the third-direction DR3). The third buffer layer BUF3 can cover a portion of the etch stop layer ESL. A first hole H1 exposing a portion of the upper surface of the etch stop layer ESL can be defined in the third buffer layer BUF3.

[0077] In this embodiment, the third buffer layer BUF3 may include an inorganic insulating material. For example, the inorganic insulating material may include silicon oxide.

[0078] In an embodiment, the third buffer layer BUF3 may comprise a different material than the etch stop layer ESL. For example, in an embodiment, the third buffer layer BUF3 may comprise silicon oxide, and the etch stop layer ESL may comprise silicon oxide nitride.

[0079] In an embodiment, during the etching process for forming the first hole H1, an etching gas with lower etch selectivity for the material included in the etch stop layer ESL than for the material included in the third buffer layer BUF3 can be used. For example, in the same process using the etching gas, the etching rate of the etch stop layer ESL can be lower than the etching rate of the third buffer layer BUF3. Accordingly, while the first hole H1 is formed in the third buffer layer BUF3, the etch stop layer ESL may not be etched, and a hole penetrating the etch stop layer ESL may not be formed.

[0080] The transistor TR can be disposed on the third buffer layer BUF3. In an embodiment, the transistor TR may include an active layer ACT and a gate electrode GE. The transistor TR can allow current to flow according to the signal at the gate electrode GE.

[0081] The active layer ACT can be disposed on the third buffer layer BUF3 (e.g., directly disposed on the third-direction D3). In embodiments, the active layer ACT may include an oxide semiconductor. For example, in embodiments, the oxide semiconductor may include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium, titanium, and zinc (Zn), etc. These materials may be used alone or in combination with each other.

[0082] However, embodiments of this disclosure are not limited thereto, and the active layer ACT may include silicon semiconductors or organic semiconductors. For example, silicon semiconductors may include amorphous silicon and polycrystalline silicon, etc.

[0083] The active layer (ACT) can include a source region, a drain region, and a channel region (CHA) located between the source and drain regions.

[0084] In an embodiment, the source and drain regions of the active layer ACT may include conductive regions CA. A second via H2 exposing the first via H1 may be defined within the conductive region CA. In an embodiment, the second via H2 may (e.g., on a third-direction DR3) overlap with the first via H1 and may, together with the first via H1, expose at least a portion of the upper surface of the etch stop layer ESL.

[0085] The conductive region CA can be a region doped with impurities. In an embodiment, the conductive region CA can be doped with N-type impurities. Alternatively, the conductive region CA can be doped with p-type impurities. By doping the conductive region CA with impurities, the active layer ACT can be electrically connected to the contact electrode CTE. However, the channel region CHA can be an undoped region or a region doped at a concentration lower than that of the conductive region CA.

[0086] A gate insulating layer GI can be disposed on the active layer ACT (e.g., directly disposed on the third third-direction DR3). For example, the gate insulating layer GI can cover each of the third buffer layer BUF3 and the active layer ACT. A third hole H3, exposing a portion of the upper surface of the second hole H2 and the etch stop layer ESL, can be defined in the gate insulating layer GI and (e.g., on the third third-direction DR3) overlap with the first hole H1 and the second hole H2. The first hole through the third holes H1, H2 and H3 can form a hole H.

[0087] In this embodiment, the gate insulating layer GI may include an inorganic insulating material. The gate insulating layer GI may have a structure comprising a single layer or multiple layers of inorganic insulating material.

[0088] The gate electrode GE can be disposed on the gate insulating layer GI (e.g., directly disposed on the third-direction DR3). The gate electrode GE can overlap (e.g., on the third-direction DR3) with the channel region CHA of the active layer ACT. In an embodiment, the gate electrode GE can include a first conductive layer GE1, a second conductive layer GE2, and a third conductive layer GE3. The first conductive layer GE1 can be disposed on the gate insulating layer GI (e.g., directly disposed on the third-direction DR3). The second conductive layer GE2 can be disposed on the first conductive layer GE1 (e.g., directly disposed on the third-direction DR3). The third conductive layer GE3 can be disposed on the second conductive layer GE2 (e.g., directly disposed on the third-direction DR3). For example, the gate electrode GE can have a three-layer structure including (e.g., on the third-direction DR3) three conductive layers stacked sequentially.

[0089] In embodiments, each of the first to third conductive layers GE1, GE2, and GE3 may comprise different materials from each other. For example, in an embodiment, the first conductive layer GE1 may comprise titanium, the second conductive layer GE2 may comprise copper, and the third conductive layer GE3 may comprise indium tin oxide (ITO). However, embodiments of this disclosure are not limited thereto, and two or more of the first to third conductive layers GE1, GE2, and GE3 may comprise the same material as each other. Additionally, in Figure 5 In the embodiments shown, the gate electrode GE is depicted as having a three-layer structure. However, in some embodiments, the gate electrode GE may have a single-layer structure or a multilayer structure comprising two, four, or more conductive layers.

[0090] In an embodiment, the contact electrode CTE may be disposed on the gate insulating layer GI. For example, the contact electrode CTE may be disposed on the same layer as the gate electrode GE. Furthermore, the contact electrode CTE and the gate electrode GE may comprise the same material.

[0091] In embodiments, the contact electrode CTE may include a first contact electrode CTE1 and a second contact electrode CTE2. In embodiments where the gate electrode GE has a three-layer structure, each of the first contact electrode CTE1 and the second contact electrode CTE2 may have a three-layer structure including three conductive layers. For example, in an embodiment, the first contact electrode CTE1 may include a first conductive layer CTE1-1, a first conductive layer CTE1-2, and a first conductive layer CTE1-3. The second contact electrode CTE2 may include a second conductive layer CTE2-1, a second conductive layer CTE2-2, and a second conductive layer CTE2-3.

[0092] The first contact electrode CTE1 can be electrically connected to the active layer ACT. For example, in an embodiment, the first conductive layer CTE1-1 can directly contact the conductive region CA of the active layer ACT, and the first contact electrode CTE1 can be electrically connected to the conductive region CA of the active layer ACT.

[0093] The first contact electrode CTE1 can be electrically connected to the light-shielding layer BML. For example, in an embodiment, the first conductive layer CTE1-1 can directly contact the light-shielding layer BML through the first contact hole CNT1 to be electrically connected to the light-shielding layer BML. Since the first contact electrode CTE1 is electrically connected to the light-shielding layer BML, the light-shielding layer BML can have the same voltage as the first contact electrode CTE1.

[0094] The first contact hole CNT1 can be a hole that penetrates the first buffer layer BUF1, the second buffer layer BUF2, the etch stop layer ESL, the third buffer layer BUF3 and the gate insulating layer GI on the third-direction DR3.

[0095] In embodiments, the first contact electrode CTE1 may include materials such as molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, and copper. These materials may be used alone or in combination with each other. However, the embodiments of this disclosure are not limited thereto.

[0096] The second contact electrode CTE2 can be electrically connected to the active layer ACT. For example, in an embodiment, the 2-1 conductive layer CTE2-1 directly contacts the conductive region CA of the active layer ACT, and the second contact electrode CTE2 can be electrically connected to the conductive region CA of the active layer ACT.

[0097] The second contact electrode CTE2 can be electrically connected to the driving voltage line VDL. For example, in an embodiment, the 2-1 conductive layer CTE2-1 can directly contact the driving voltage line VDL through the second contact hole CNT2, and the second contact electrode CTE2 can be electrically connected to the driving voltage line VDL. Since the second contact electrode CTE2 is electrically connected to the driving voltage line VDL, the driving voltage line VDL can have the same voltage as the second contact electrode CTE2.

[0098] The second contact hole CNT2 can be a hole that penetrates the first buffer layer BUF1, the second buffer layer BUF2, the etch stop layer ESL, the third buffer layer BUF3 and the gate insulating layer GI on the third-direction DR3.

[0099] In this embodiment, the second contact electrode CTE2 may comprise substantially the same material as the first contact electrode CTE1. Furthermore, the second contact electrode CTE2 may be disposed in the same layer as the first contact electrode CTE1.

[0100] In an embodiment, the aperture H may (e.g., in the first direction DR1) be located between the gate electrode GE and the contact electrode CTE. For example, the first to third apertures H1, H2, and H3 adjacent to the first contact electrode CTE1 may be located between the gate electrode GE and the first contact electrode CTE1. Additionally, the first aperture H1, the second aperture H2, and the third aperture H3 adjacent to the second contact electrode CTE2 may be located between the gate electrode GE and the second contact electrode CTE2. For example, in an embodiment, two or more apertures H may be located on both sides of the gate electrode GE.

[0101] The inorganic layer PVX can be disposed on the gate insulating layer GI (e.g., directly disposed on the third-party DR3). For example, the inorganic layer PVX can cover the gate insulating layer GI, the gate electrode GE, and the contact electrode CTE. The inorganic layer PVX can include an inorganic insulating material. For example, in embodiments, the inorganic insulating material can include silicon oxide, silicon nitride, and silicon nitride, etc. These materials can be used alone or in combination with each other. However, the embodiments of this disclosure are not limited thereto.

[0102] The via layer VIA can be disposed on the inorganic layer PVX (e.g., directly disposed on the third-party DR3). The via layer VIA may include a substantially flat upper surface. The via layer VIA may include an organic insulating material. For example, in embodiments, the organic insulating material may include photoresist, polyacrylic resin, polyimide resin, and acrylic resin, etc. These materials may be used alone or in combination with each other. However, embodiments of this disclosure are not necessarily limited thereto.

[0103] The light-emitting element (LED) can be disposed on the via layer VIA (e.g., directly disposed on a third-party DR3). For example, in embodiments, the LED may include organic light-emitting elements (OLEDs) and inorganic light-emitting elements, etc. However, the embodiments of this disclosure are not limited thereto.

[0104] The pixel electrode PE can be disposed on the via layer VIA (e.g., directly disposed on the third-party DR3). In an embodiment, the pixel electrode PE can be electrically connected to the first contact electrode CTE1 through a contact hole. The pixel electrode PE can transmit electrical signals to the light-emitting layer EML. In an embodiment, the pixel electrode PE can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. These materials can be used alone or in combination with each other.

[0105] In an embodiment, the first contact electrode CTE1 can be electrically connected to the light-emitting element LED. For example, in an embodiment, the first contact electrode CTE1 can be electrically connected to the light-emitting element LED through a pixel electrode PE that penetrates the via layer VIA and the inorganic layer PVX, so that a signal allowing the pixel PX to emit light can be transmitted.

[0106] An emissive layer (EML) can be disposed on a pixel electrode (PE). In embodiments, each EML can emit light of at least one color selected from blue, red, and green. However, embodiments of this disclosure are not limited to this. For example, in some embodiments, the EML can emit light of a combination of blue, red, and green. The EML can include organic light-emitting materials and quantum dots, etc. However, embodiments of this disclosure are not limited to this.

[0107] The pixel defining layer (PDL) can be disposed on the via layer (VIA) (e.g., directly disposed thereon on the third direction DR3). For example, the pixel defining layer (PDL) can partially cover the pixel electrode (PE). Additionally, an opening exposing at least a portion of the pixel electrode (PE) can be defined in the pixel defining layer (PDL). For example, in an embodiment, the opening in the pixel defining layer (PDL) can (e.g., on the first direction DR1) expose the central portion of the pixel electrode (PE), and the pixel defining layer (PDL) can cover the edges of the pixel electrode (PE), such as the side edges of the pixel electrode (PE).

[0108] The pixel defining layer (PDL) may comprise inorganic or organic materials. In embodiments, the PDL may comprise organic materials such as epoxy resins and silicone resins. These materials may be used alone or in combination with each other. However, embodiments of this disclosure are not limited thereto. In some embodiments, the PDL may further comprise a light-shielding material comprising black pigments and black dyes, etc.

[0109] The common electrode CE can be disposed on the light-emitting layer EML and the pixel defining layer PDL. The common electrode CE can be disposed on the front surface of the display area. In embodiments, the common electrode CE can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. These materials can be used individually or in combination.

[0110] The encapsulation layer TFE can be disposed on the light-emitting element LED (e.g., directly disposed on the third-direction DR3). For example, the encapsulation layer TFE can be disposed on the common electrode CE (e.g., directly disposed on the third-direction DR3). The encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The encapsulation layer TFE can prevent oxygen and moisture from penetrating into the light-emitting element LED.

[0111] In an embodiment, the color conversion layer may be disposed on the encapsulation layer TFE (e.g., directly disposed on a third-party DR3). The color conversion layer may include quantum dots. Due to incident light incident on the quantum dots, electrons included in the quantum dots can transition from the conduction band to the valence band, and accordingly, the quantum dots can emit light of a specific color. However, embodiments of this disclosure are not necessarily limited thereto.

[0112] Figure 6 The diagram is along Figure 4 A cross-sectional view of the pixels captured by line II-II'. Figure 6 This is a cross-sectional view of pixel PX taken along the second direction DR2.

[0113] refer to Figure 6 The inorganic layer PVX can be disposed on the active layer ACT (e.g., directly disposed on the third-direction DR3). For example, the inorganic layer PVX can cover the active layer ACT and can directly contact the conductive region CA. Figure 6 A cross-sectional view can illustrate the removal of the gate insulating layer on the active layer ACT (e.g., Figure 5 The gate insulating layer GI) and the gate electrode (e.g., Figure 5 It is a part of each of the gate electrodes (GE) and forms the region of the first hole H1 and the second hole H2.

[0114] An active layer ACT and a third buffer layer BUF3 can be disposed on an etch stop layer ESL (e.g., continuously disposed on a third directional layer DR3). A first aperture H1, exposing a portion of the upper surface of the etch stop layer ESL, is defined in the active layer ACT, and a second aperture H2, exposing a portion of the upper surface of the etch stop layer ESL, is defined in the third buffer layer BUF3. Figure 5 different, Figure 6 The diagram shows the area without a gate insulating layer, so the inorganic layer PVX can directly contact the etch stop layer ESL through the first hole H1 and the second hole H2.

[0115] The inorganic layer PVX may cover the ends (e.g., side ends in the second direction DR2) of each of the active layer ACT and the third buffer layer BUF3 exposed by the first hole H1 and the second hole H2. The ends of each of the active layer ACT and the third buffer layer BUF3 exposed by the first hole H1 and the second hole H2 may be defined as step regions SP. In an embodiment, in the step region SP, the inorganic layer PVX is formed on the upper surface of the active layer ACT (e.g., directly formed thereon) and directly contacts the upper surface of the active layer ACT, formed on the side surface of the active layer ACT (e.g., sidewall) and directly contacts the side surface of the active layer ACT (e.g., sidewall), formed on the side surface of the third buffer layer BUF3 (e.g., sidewall) and directly contacts the side surface of the third buffer layer BUF3 (e.g., sidewall), and formed on a portion of the upper surface of the etch stop layer ESL and directly contacts that portion of the upper surface of the etch stop layer ESL.

[0116] In one embodiment, the sum of the depths of the first aperture H1 and the second aperture H2, T, can be less than or equal to approximately 30 nm. In another embodiment, the sum of the depths of the first aperture H1 and the second aperture H2, T, can be less than or equal to approximately 20 nm. For example, the sum of the thicknesses of the active layer ACT and the third buffer layer BUF3 can be less than or equal to approximately 30 nm. In another embodiment, the sum of the thicknesses of the active layer ACT and the third buffer layer BUF3 can be less than or equal to approximately 20 nm.

[0117] However, when the sum T of the depths of the first hole H1 and the second hole H2 is greater than approximately 30 nm, the inorganic PVX layer filling the ends of each of the active layer ACT and the third buffer layer BUF3 exposed by the first hole H1 and the second hole H2 may not have a uniform thickness. Accordingly, a moisture-permeable path for external moisture to flow into the inorganic PVX layer may form around the ends, and consequently, this may occur in the display device (e.g., Figure 1 Defects are generated in the display device (DD).

[0118] As described above, the display device may have (e.g., on the third-direction DR3) an etch stop layer ESL disposed between the second buffer layer BUF2 and the third buffer layer BUF3, defining a first hole H1. Since the first hole H1 does not penetrate the etch stop layer ESL in the thickness direction and exposes at least a portion of the upper surface of the etch stop layer ESL, external moisture can be prevented from filling the first hole H1 through the formation of a moisture-permeable path flowing within the inorganic layer PVX. Accordingly, defects in the display device can be prevented, and the reliability of the display device can be improved.

[0119] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23 It is used to explain the manufacturing process. Figure 1 A view of the method of displaying the device. For example, Figure 7 , Figure 8 , Figure 10 , Figure 12 , Figure 13 , Figure 16 and Figure 20 It can be a planar diagram of the area corresponding to pixel PX, and Figure 9 , Figure 11 , Figure 14 , Figure 15 , Figure 17 , Figure 18 , Figure 19 , Figure 21 , Figure 22 and Figure 23 It can be a cross-sectional view of the area corresponding to pixel PX.

[0120] In the following text, for the sake of brevity, references may be omitted or simplified. Figures 4 to 6 The content described is repetitive.

[0121] refer to Figure 7 In this embodiment, a light-shielding layer BML and a driving voltage line VDL can be formed on the substrate SUB (e.g., directly formed on the third-party DR3). For example, each of the light-shielding layer BML and the driving voltage line VDL can cover a portion of the substrate SUB. Furthermore, the light-shielding layer BML and the driving voltage line VDL can comprise the same material as each other. Additionally, the light-shielding layer BML and the driving voltage line VDL can be disposed in the same layer as each other.

[0122] Figure 9 It is along Figure 8 The cross-sectional view taken from line III-III'. (Reference) Figure 8 and Figure 9In this embodiment, a first buffer layer BUF1 can be formed on the light-shielding layer BML and the driving voltage line VDL (e.g., directly formed on the third-direction DR3). A second buffer layer BUF2 can be formed on the first buffer layer BUF1 (e.g., directly formed on the third-direction DR3). For example, the first buffer layer can cover the light-shielding layer BML, the driving voltage line VDL, and the substrate SUB. Additionally, the second buffer layer BUF2 can cover the first buffer layer.

[0123] In an embodiment, an etch stop layer (ESL) may be formed on the second buffer layer BUF2 (e.g., directly on the third-party DR3). For example, the etch stop layer ESL may cover the second buffer layer BUF2. In an embodiment, the etch stop layer ESL may comprise a different material from the second buffer layer BUF2.

[0124] Figure 11 It is along Figure 10 The cross-sectional view taken from line IV-IV'. (Reference) Figure 10 and Figure 11 A pre-buffer layer BUF3' can be formed on the etch stop layer ESL (e.g., directly on the third-direction DR3). A pre-active layer ACT' can be formed on the pre-buffer layer BUF3' (e.g., directly on the third-direction DR3). For example, the pre-buffer layer BUF3' can cover the etch stop layer ESL, and the pre-active layer ACT' can cover a portion of the pre-buffer layer BUF3'.

[0125] The prepared active layer ACT' can be combined with Figure 5 The active layer ACT corresponds to this. The preparatory active layer ACT' can be associated with... Figure 5 The active layer ACT comprises the same material. For example, in an embodiment, the prepared active layer ACT' may include metal oxide semiconductor, silicon semiconductor, and organic semiconductor, etc.

[0126] The prepared active layer ACT' may (e.g., on the third-direction DR3) overlap with a portion of the light-shielding layer BML. Alternatively, in embodiments, the prepared active layer ACT' may (e.g., on the third-direction DR3) not overlap with the drive voltage line VDL. However, embodiments of this disclosure are not necessarily limited thereto.

[0127] The prepared buffer layer BUF3' can be used with Figure 5 This corresponds to the third buffer layer BUF3. In an embodiment, the pre-buffer layer BUF3' may consist of a different material than the etch stop layer ESL.

[0128] refer to Figure 12Conductive regions CA can be formed by doping a portion of the prepared active layer ACT' with impurities. For example, in an embodiment, two conductive regions CA can be formed at locations adjacent to both ends of the prepared active layer ACT'. A channel region CHA can be formed between the conductive regions CA. For example, in an embodiment, the channel region CHA can be formed between the conductive regions CA in a first direction DR1. However, embodiments of this disclosure are not limited to this.

[0129] Figure 14 It is along Figure 13 A cross-sectional view taken from line V-V' extending in the first direction DR1. (Reference) Figure 13 and Figure 14 A gate insulating layer GI can be formed on the prepared active layer ACT'. For example, in an embodiment, after the material for forming the gate insulating layer GI is completely coated on the prepared active layer ACT' and the prepared buffer layer BUF3', a portion of the coated material is removed by an etching process to form the gate insulating layer GI.

[0130] A gate via GH can be defined within a gate insulating layer GI. For example, a gate via GH that exposes a portion of the upper surface of a conductive region CA can be defined within the gate insulating layer GI. In an embodiment, the gate via GH can be located (e.g., in the first direction DR1) between a first contact hole CNT1 and a second contact hole CNT2. The gate via GH can penetrate the gate insulating layer GI in the third direction DR3.

[0131] Each of the first contact hole CNT1 and the second contact hole CNT2 may be a hole that penetrates the first buffer layer BUF1, the second buffer layer BUF2, the etch stop layer ESL, the pre-buffer layer BUF3' and the gate insulating layer GI on the third-direction DR3.

[0132] In one embodiment, the portion of each of the first buffer layer BUF1, the second buffer layer BUF2, the etch stop layer ESL, the pre-buffer layer BUF3', and the gate insulating layer GI adjacent to the conductive region CA may be removed to define a first contact hole CNT1 that exposes a portion of the upper surface of the light-shielding layer BML in a plan view. Similarly, the portion of each of the first buffer layer BUF1, the second buffer layer BUF2, the etch stop layer ESL, the pre-buffer layer BUF3', and the gate insulating layer GI adjacent to the conductive region CA may be removed to define a second contact hole CNT2 that exposes a portion of the upper surface of the drive voltage line VDL in a plan view.

[0133] The prepared active layer ACT' may (e.g., in the first direction DR1) be located between the first contact hole CNT1 and the second contact hole CNT2.

[0134] Figure 15 The diagram is along Figure 13The line VI-VI' extending in the second direction DR2 intercepts the line with Figure 13 A cross-sectional view of a portion of the component adjacent to the GH aperture.

[0135] refer to Figure 15 A gate aperture GH can be defined to expose a portion of the upper surface of the prepared active layer ACT'. A portion of the conductive region CA can be exposed through the gate aperture GH, and other portions of the conductive region CA can be covered by the gate insulating layer GI.

[0136] refer to Figure 16 and Figure 17 A gate electrode GE, a first contact electrode CTE1, and a second contact electrode CTE2 can be formed on the gate insulating layer GI. In an embodiment, the conductive material for forming the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2 can be coated on the gate insulating layer GI to form a conductive layer. The conductive layer can be patterned to form the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2 on the gate insulating layer GI.

[0137] In this embodiment, the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2 may comprise the same material as each other. The gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2 may be disposed on the same layer as each other.

[0138] In this embodiment, the conductive layer may have a three-layer structure. The three layers constituting the conductive layer may include different materials. Accordingly, the gate electrode GE may include a first conductive layer GE1, a second conductive layer GE2, and a third conductive layer GE3 stacked in a three-layer structure. Additionally, the first contact electrode CTE1 may include a first-1 conductive layer CTE1-1, a first-2 conductive layer CTE1-2, and a first-3 conductive layer CTE1-3 stacked in a three-layer structure. Furthermore, the second contact electrode CTE2 may include a second-1 conductive layer CTE2-1, a second-2 conductive layer CTE2-2, and a second-3 conductive layer CTE2-3 stacked in a three-layer structure.

[0139] Can remove Figure 14 A portion of the preparatory active layer ACT' is used to form the active layer ACT. An active via AH, exposing a portion of the upper surface of the preparatory buffer layer BUF3', can be defined within the active layer ACT. The active via AH can be a via penetrating the conductive region CA of the active layer ACT.

[0140] Conductive layers CTE1-1 (first layer) and CTE2-1 (second layer) can directly contact the conductive region CA adjacent to the active via AH. Additionally, conductive layer CTE1-1 can directly contact the light-shielding layer BML, and conductive layer CTE2-1 can directly contact the drive voltage line VDL. For example, conductive layer CTE1-1 can simultaneously directly contact both the light-shielding layer BML and the conductive region CA. Similarly, conductive layer CTE2-1 can simultaneously directly contact both the drive voltage line VDL and the conductive region CA.

[0141] The gate aperture GH can (e.g., in the first direction DR1) be located between the first contact electrode CTE1 and the gate electrode GE. Because Figure 17 A portion of the gate aperture GH is filled by the first contact electrode CTE1, therefore the size of the gate aperture GH can be smaller than [the specified value]. Figure 14 The size of the GH aperture.

[0142] The gate aperture GH can also be located (e.g., in the first direction DR1) between the second contact electrode CTE2 and the gate electrode GE. Because Figure 17 A portion of the gate aperture GH is filled by the second contact electrode CTE2, therefore the size of the gate aperture GH can be smaller than [the specified size]. Figure 14 The size of the GH aperture.

[0143] Figure 18 It is along Figure 16 The line VIII-VIII' extending in the second direction DR2 intercepts the line VIII-VIII' with Figure 16 A cross-sectional view of a portion of the component adjacent to the active aperture AH.

[0144] refer to Figure 18 Remove the conductive regions of the active layer ACT (e.g., Figure 15 The conductive region CA can define the active aperture AH on the upper surface of the exposed pre-buffer layer BUF3'.

[0145] In an embodiment, the size of the gate aperture GH can be smaller than the size of the active aperture AH. For example, along... Figure 16 The cross-section cut by line VII-VII' extending parallel to the first direction DR1. Figure 17 In this case, the boundary of the gate aperture GH can coincide with the boundary of the active aperture AH. However, along... Figure 16 The cross section cut by line VIII-VIII' extending in the second direction DR2. Figure 18 In this configuration, the width of the gate aperture GH can be smaller than the width of the active aperture AH. Accordingly, in the cross-sectional view, the active layer ACT can have an undercut shape together with the gate insulating layer GI.

[0146] refer to Figure 19A photoresist PR can be formed on the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2 (e.g., directly on the third-direction DR3). After forming the photoresist PR, an etching process can be performed to remove a portion of each of the gate insulating layer GI and the pre-buffer layer BUF3'.

[0147] In an embodiment, the photoresist PR can be a positive photoresist. For example, the portion of each of the gate insulating layer GI and the pre-buffer layer BUF3' that does not overlap with the photoresist PR can be removed. Alternatively, the photoresist PR can be a negative photoresist. For example, the portion of each of the gate insulating layer GI and the pre-buffer layer BUF3' that overlaps with the photoresist PR can be removed.

[0148] In an embodiment, an etching process can be performed by spraying etching gas onto each of the gate insulating layer GI and the pre-buffer layer BUF3' to remove a portion of the gate insulating layer GI and a portion of the pre-buffer layer BUF3' in the thickness direction. In an embodiment, the etching gas may include octafluorobutene (C4F8), oxygen (O2), and argon (Ar), etc. These gases may be used alone or in combination. For example, the etching process may be a dry etching process.

[0149] However, in the comparative example in which the pre-buffer layer BUF3' is formed directly on the second buffer layer BUF2 and no etch stop layer ESL is included between the pre-buffer layer BUF3' and the second buffer layer BUF2, the etching gas can be used after all the reactions with the pre-buffer layer BUF3' are completed, and can penetrate the second buffer layer BUF2 in the thickness direction.

[0150] In an embodiment, the etching gas can be a gas with lower etching selectivity for the material included in the etch stop layer ESL than for the material included in the pre-buffer layer BUF3'. For example, in the same process using the etching gas, the etching rate of the etch stop layer ESL can be lower than the etching rate of the pre-buffer layer BUF3'. Accordingly, after removing the pre-buffer layer BUF3' and forming... Figure 20 At the same time as the first hole H1, the etch stop layer ESL can be left unetched.

[0151] refer to Figure 20 and Figure 21 It can remove Figure 19 The photoresist PR is applied to the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2.

[0152] Can remove Figure 19A portion of the preparatory buffer layer BUF3' is used to form the third buffer layer BUF3. A first hole H1, exposing a portion of the upper surface of the etch stop layer ESL, can be defined in the third buffer layer BUF3. Additionally, a second hole H2, connected to the first hole H1 and exposing a portion of the upper surface of the etch stop layer ESL, can be defined in the active layer ACT. The second hole H2 defined in the active layer ACT can be connected to... Figure 19 The active aperture AH corresponds to this. In this embodiment, the formation of the first aperture H1 can be performed after the formation of the second aperture H2.

[0153] The third hole H3 can be extended in the first direction DR1. Figure 19 The gate aperture GH is confined within the gate insulating layer GI. Furthermore, with... Figure 19 By extending the gate via GH, a portion of the gate insulating layer GI can be removed. The active layer ACT exposed by the removed gate insulating layer GI can be doped with impurities to form the conductive region CA.

[0154] Each of the first to third holes H1, H2 and H3 can be connected to each other on the third-direction DR3 to define a hole H that exposes a portion of the upper surface of the etch stop layer ESL.

[0155] Figure 22 It is the intersection of the line parallel to the second direction DR2 and... Figure 20 A cross-sectional view of a portion of the component adjacent to hole H. Figure 23 The illustration was added to cover it. Figure 22 A cross-sectional view of the inorganic layer PVX, which is a portion of each of the active layer ACT, the third buffer layer BUF3, and the etch stop layer ESL in the stepped region SP.

[0156] refer to Figure 22 The stepped region SP can be defined around the first hole H1 and the second hole H2. In an embodiment, the sum T of the depth of the first hole H1 and the depth of the second hole H2 around the stepped region SP can be less than or equal to about 30 nm. For example, in an embodiment, the sum T of the depth of the first hole H1 and the depth of the second hole H2 around the stepped region SP can be less than or equal to about 20 nm.

[0157] In one embodiment, the total thickness of the active layer ACT and the third buffer layer BUF3 around the step region SP can be less than or equal to approximately 30 nm. In another embodiment, the total thickness of the active layer ACT and the third buffer layer BUF3 around the step region SP can be less than or equal to approximately 20 nm.

[0158] refer to Figure 23 An inorganic PVX layer can be formed on the active layer ACT (e.g., directly on it). The inorganic PVX layer can cover... Figure 21 The gate insulating layer GI, the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2. However, Figure 23 The cross-section can be illustrated on the active layer ACT for removal. Figure 21 The area of ​​the gate insulating layer GI, the gate electrode GE, the first contact electrode CTE1, and the second contact electrode CTE2.

[0159] The inorganic layer PVX can cover a portion of each of the active layer ACT, the third buffer layer BUF3, and the etch stop layer ESL in the step region SP. For example, in an embodiment, the inorganic layer PVX can fill the first hole H1 and the second hole H2, and can cover each of the active layer ACT, the third buffer layer BUF3, and the etch stop layer ESL. For example, the inorganic layer PVX can cover the upper surface and side surfaces (e.g., sidewalls) of the active layer ACT, the side surface (e.g., sidewalls) of the third buffer layer BUF3, and the upper surface of the etch stop layer ESL.

[0160] As described above, the reactivity of the etch stop layer ESL to the etch gas can be less than that of the preparatory buffer layer BUF3'. Accordingly, the first hole H1 can penetrate the third buffer layer BUF3, but can remain within the etch stop layer ESL. Consequently, defects in the display device can be prevented, and the reliability of the display device can be improved.

[0161] Further reference Figure 5 A via layer (VIA), a light-emitting element (LED), a pixel-defining layer (PDL), and a packaging layer (TFE) can be sequentially formed on an inorganic PVX layer. Accordingly, it is possible to manufacture... Figure 4 and Figure 5 The display device DD.

[0162] The display apparatus and method according to embodiments of the present disclosure can be applied to electronic devices including computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, or MP3 players.

[0163] Although display apparatus and methods according to non-limiting embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and altered by those skilled in the art without departing from the spirit of this disclosure.

Claims

1. A display device, comprising: The first buffer layer is disposed on the substrate; An etching stop layer is disposed on the first buffer layer; A second buffer layer is disposed on the etch stop layer, the second buffer layer including a first hole exposing at least a portion of the upper surface of the etch stop layer; An active layer is disposed on the second buffer layer, the active layer including a conductive region and a second hole exposing the first hole; as well as An inorganic layer is disposed on the active layer, and the inorganic layer fills the first hole and the second hole.

2. The display device according to claim 1, wherein The etch stop layer is composed of a compound selected from the group consisting of metal oxides, silicon, silicon nitrides, and silicon oxide nitrides. The second buffer layer is composed of silicon oxide.

3. The display device according to claim 1, wherein The display device further includes a third buffer layer disposed between the first buffer layer and the etch stop layer, and The third buffer layer is composed of silicon oxide.

4. The display device according to claim 1, wherein The sum of the depths of the first hole and the second hole is less than or equal to 30 nm.

5. The display device according to claim 1, wherein The etch stop layer directly contacts the inorganic layer through the first hole and the second hole.

6. The display device according to claim 1, wherein The inorganic layer covers the ends of each of the active layer and the second buffer layer that are exposed by the first and second holes.

7. The display device of claim 6, wherein, Around the end of the active layer and the end of the second buffer layer, the inorganic layer directly contacts the upper surface of the active layer, the side surface of the active layer, the side surface of the second buffer layer, and a portion of the upper surface of the etch stop layer.

8. The display device according to any one of claims 1 to 7, further comprising: A gate insulating layer is disposed on the active layer; The gate electrode is disposed on the gate insulating layer; as well as A contact electrode is disposed on the gate insulating layer and directly contacts a portion of the conductive region.

9. The display device according to claim 8, wherein: The gate insulating layer includes a third hole that exposes the second hole and a portion of the upper surface of the active layer; and The size of the third hole is larger than the size of the second hole.

10. The display device of claim 8, wherein, Each of the first hole and the second hole is located between the gate electrode and the contact electrode.

Images