Display device

Abstract

A display device includes: a substrate; a plurality of first electrodes on the substrate; a pixel defining layer defining a plurality of emission regions disposed to respectively correspond to the plurality of first electrodes; a light emitting layer on the plurality of first electrodes; and a second electrode on the light emitting layer, in which each of the plurality of emission regions has a circular shape in a plan view, and the plurality of emission regions have the same size in the plan view.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0023406, filed on February 19, 2024, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to display devices and optical devices, and more specifically, to display devices and optical devices capable of improving light recovery efficiency. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to focus an image at close range in front of the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays magnify images displayed on small display devices using multiple lenses, and display the magnified images. Therefore, it is desirable for display devices used in head-mounted displays to provide high-resolution images, for example, with a resolution of 3000 pixels per inch (PPI) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), which are high-resolution small organic light-emitting display devices, are used as display devices for head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor wafer substrate, on which complementary metal-oxide-semiconductor (CMOS) is disposed. Summary of the Invention

[0005] This disclosure provides a display device and an optical device that can improve light recovery efficiency.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate; a plurality of first electrodes on the substrate; a pixel defining layer defining a plurality of emitting regions respectively configured to correspond to the plurality of first electrodes; a light-emitting layer on the plurality of first electrodes; and a second electrode on the light-emitting layer, wherein, in a plan view, each of the plurality of emitting regions has a circular shape, and in a plan view, the plurality of emitting regions have the same size.

[0007] In an embodiment, the display device may further include a wire grid polarizer on the second electrode.

[0008] In one embodiment, the display device may further include a lens layer on a linear grid polarizer.

[0009] In an embodiment, the display device may further include a color filter layer between the second electrode and the wire grid polarizer.

[0010] In an embodiment, the display device may further include a delay layer between the second electrode and the wire grid polarizer.

[0011] In an embodiment, in a plan view, each of the plurality of first electrodes may have a circular shape.

[0012] In an embodiment, in a plan view, multiple first electrodes may have the same size.

[0013] In an embodiment, the display device may further include: a plurality of reflective electrode layers, each connected to a plurality of first electrodes.

[0014] In an embodiment, in a plan view, each of the plurality of reflective electrode layers may have a circular shape.

[0015] In an embodiment, in a plan view, multiple reflective electrode layers may have the same size.

[0016] In an embodiment, multiple emission regions can be configured to provide light of different colors.

[0017] According to embodiments of this disclosure, an optical device includes: a display device; and an optical path changing member on the display device, wherein the display device includes: a substrate; a plurality of first electrodes on the substrate; a pixel defining layer defining a plurality of emitting regions respectively configured to correspond to the plurality of first electrodes; a light-emitting layer on the plurality of first electrodes; and a second electrode on the light-emitting layer. In a plan view, each of the plurality of emitting regions has a circular shape, and in the plan view, the plurality of emitting regions have the same size.

[0018] In an embodiment, the optical device may further include a wire grid polarizer on the second electrode.

[0019] In an embodiment, the optical device may further include a lens layer on a linear grid polarizer.

[0020] In an embodiment, the optical device may further include a color filter layer between the second electrode and the wire grid polarizer.

[0021] In an embodiment, the optical device may further include a delay layer between the second electrode and the wire grid polarizer.

[0022] In an embodiment, in a plan view, each of the plurality of first electrodes may have a circular shape.

[0023] In an embodiment, in a plan view, multiple first electrodes may have the same size.

[0024] In an embodiment, the optical device may further include: a plurality of reflective electrode layers, each connected to a plurality of first electrodes.

[0025] In an embodiment, in a plan view, each of the plurality of reflective electrode layers may have a circular shape.

[0026] In an embodiment, in a plan view, multiple reflective electrode layers may have the same size.

[0027] In an embodiment, multiple emission regions can be configured to provide light of different colors.

[0028] The display device and optical device disclosed herein can improve light recovery efficiency. Accordingly, the image quality of the display device can be effectively improved.

[0029] However, the effects of the embodiments according to this disclosure are not limited to those illustrated above, and various other effects are included herein. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is an exploded perspective view showing a display device according to one embodiment;

[0032] Figure 2 It is a diagram. Figure 1 The layout diagram of an example display panel shown;

[0033] Figure 3 This is an equivalent circuit diagram of a sub-pixel according to one embodiment;

[0034] Figure 4 This is a layout diagram illustrating an example of a display panel according to one embodiment;

[0035] Figure 5 It is shown Figure 4 A layout diagram of an embodiment of the display area;

[0036] Figure 6 The diagram is along Figure 5 A cross-sectional view of an example display panel taken by line X-X';

[0037] Figure 7 The diagram is along Figure 5 A cross-sectional view of another example of a display panel, taken by line X-X';

[0038] Figure 8 The diagram is along Figure 5A cross-sectional view of another example of a display panel, taken by line X-X';

[0039] Figure 9 The diagram is along Figure 5 A cross-sectional view of another example of a display panel, taken by line X-X';

[0040] Figure 10 It is a diagram used to describe the optical paths of the principal ray and the reflected ray;

[0041] Figure 11 It is a diagram showing various shapes of the emission area;

[0042] Figure 12 It is used to describe according to Figure 11 A graph showing the light recovery efficiency of the principal ray angle (CRA) for each emission region;

[0043] Figures 13A to 13C This shows the ratio of the horizontal to the vertical sides of the corresponding emission area. Figure 11 A graph showing the light recovery efficiency of each emission region in the image;

[0044] Figures 14A to 14E It is a graph used to describe the light recovery efficiency based on the main light and reflected light;

[0045] Figure 15 This is a perspective view illustrating a head-mounted display according to one embodiment;

[0046] Figure 16 It is a diagram. Figure 15 An exploded perspective view of an example of a head-mounted display; and

[0047] Figure 17 This is a perspective view of a head-mounted display according to one embodiment. Detailed Implementation

[0048] The advantages and features of this disclosure, as well as methods of implementing them, will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in a variety of different ways. Exemplary embodiments are provided to make the disclosure thorough and to fully communicate the scope of this disclosure to those skilled in the art. It should be noted that the scope of this disclosure is defined only by the claims.

[0049] As used herein, the phrase "element A on element B" means that element A can be directly disposed on element B, and / or element A can be indirectly disposed on element B via another element C. Throughout the description, the same reference numerals denote the same elements. The figures, dimensions, scales, angles, and number of elements given in the figures are illustrative only and not limiting.

[0050] Although terms such as "first," "second," etc., are used to arbitrarily distinguish between the elements described by these terms, these terms are not necessarily intended to indicate a temporal or other order of priority of these elements. These terms are merely used to distinguish one element from another. Accordingly, as used herein, within the scope of the art disclosed, a first element may be a second element.

[0051] Features of the various exemplary embodiments disclosed herein can be combined in whole or in part. As will be clearly understood by those skilled in the art, various technical interactions and operations are possible. The various exemplary embodiments can be practiced individually or in combination.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. It will be further understood that, when used in this specification, the terms “comprising,” “including,” and variations thereof specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof. Exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0053] Figure 1 This is an exploded perspective view showing a display device according to one embodiment. Figure 2 It is a diagram. Figure 1 The layout diagram of the example display panel shown is shown. Figure 3 This is an equivalent circuit diagram of a sub-pixel according to one embodiment.

[0054] Figure 1 This is an exploded perspective view showing a display device according to one embodiment. Figure 2 This is a block diagram illustrating a display device according to one embodiment.

[0055] refer to Figure 1 and Figure 2According to one embodiment, the display device 10 is a device for displaying moving or still images. The display device 10 according to one embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one embodiment can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. Alternatively, the display device 10 according to one embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0056] According to one embodiment, the display device 10 includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0057] The display panel 100 may have a planar shape similar to a quadrilateral (i.e., a shape in a planar view). For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side with a first direction DR1 and a long side with a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments in this specification are not limited thereto.

[0058] like Figure 2 As shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0059] The display area DAA includes multiple unit pixels (UPX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0060] Multiple unit pixels (UPX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can be set on the second direction DR2 and extend on the first direction DR1. Multiple data lines (DL) can be set on the first direction DR1 and extend on the second direction DR2.

[0061] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines EBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0062] Each of the multiple unit pixels UPX comprises multiple pixels PX1, PX2, and PX3. The multiple pixels PX1, PX2, and PX3 can include, for example: Figure 3 The multiple pixel transistors shown are formed by semiconductor processes and can be disposed on a semiconductor substrate SSUB (see [reference]). Figure 7 For example, the multiple pixel transistors of the data driver 700 can be formed of complementary metal-oxide-semiconductor (CMOS).

[0063] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emitt control lines EL1, any one of the plurality of second emitt control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0064] The non-display area NDA includes a scan driver 610, a transmit driver 620, and a data driver 700.

[0065] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 7 On ), for example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS. Although in Figure 2 The diagram shows that the scan driver 610 is located on the left side of the display area DAA, and the transmit driver 620 is located on the right side of the display area DAA; however, the embodiments described in this specification are not limited to this. For example, the scan driver 610 and the transmit driver 620 may be located on the left and right sides of the display area DAA, respectively.

[0066] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of these units may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals based on the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals based on the scan timing control signal SCS and output them sequentially to the bias scan line EBL.

[0067] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to the first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and outputs it sequentially to the second transmit control line EL2.

[0068] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see [reference]) using semiconductor processes. Figure 7 For example, multiple data transistors can be formed using CMOS.

[0069] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected pixels PX1, PX2, and PX3.

[0070] The heat dissipation layer 200 may overlap the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on its rear surface. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) with high thermal conductivity.

[0071] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [reference]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board with a flexible material or flexible film. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 can be the first pad portion of the circuit board 300 connected to the display panel 100 by means of conductive adhesive members (see PDA1). Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end.

[0072] The timing control circuit 400 can receive digital video data and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output digital video data and the data timing control signal DCS to the data driver 700.

[0073] The power supply circuit 500 can generate multiple panel driving voltages based on the power supply voltage from an external source. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0074] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0075] Alternatively, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 can be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed on a semiconductor substrate SSUB (see [reference]) using semiconductor processes. Figure 7 On the CMOS, for example, multiple timing transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be arranged in the data driver 700 and the first pad portion of PDA1 (see Figure 4 )between.

[0076] Figure 3 This is an equivalent circuit diagram of a sub-pixel according to one embodiment.

[0077] refer to Figure 3 The first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Additionally, the first pixel PX1 can be connected to a first drive voltage line VSL with a first drive voltage VSS corresponding to a low potential voltage, a second drive voltage line VDL with a second drive voltage VDD corresponding to a high potential voltage, and a third drive voltage line VIL with a third drive voltage VINT corresponding to an initialization voltage. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT, and the second drive voltage VDD can be higher than the third drive voltage VINT.

[0078] The first pixel PX1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0079] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current Ids. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and its second electrode can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments in this specification are not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0080] The first transistor T1 may be a drive transistor that controls the source-drain current Ids (hereinafter referred to as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0081] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect that electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage on the data line DL can be applied to that electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to that electrode of the first capacitor CP1.

[0082] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by the write control signal of the write control line GCL to connect the first node N1 to the second node N2. For this purpose, since the gate and source electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the write control line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0083] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Correspondingly, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0084] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0085] A sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal of the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Correspondingly, a second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0086] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0087] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0088] The first node N1 is the junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0089] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but the embodiments described herein are not limited thereto. In another embodiment, each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0090] Despite Figure 3 The diagram illustrates that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2. However, it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to... Figure 3 The example shown. For instance, the number of transistors and capacitors in the first pixel PX1 is not limited to... Figure 3 The example shown.

[0091] Furthermore, the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 can be combined with... Figure 3 The equivalent circuit diagram of the first pixel PX1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 will be omitted in this specification.

[0092] Figure 4 This is a layout diagram illustrating an example of a display panel according to one embodiment.

[0093] refer to Figure 4 According to one embodiment, the display area DAA of the display panel 100 includes a plurality of unit pixels (UPX) arranged in a matrix. According to one embodiment, the non-display area NDA of the display panel 100 includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0094] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, the embodiments of this specification are not limited to this, and in another embodiment, the scan driver 610 and the transmit driver 620 can be disposed on both sides of the first and second sides of the display area DAA.

[0095] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps on the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be located on the third side of the display area DAA. For example, the first pad portion PDA1 may be located on one side of the display area DAA in the second direction DR2.

[0096] The first pad portion of PDA1 can be positioned on the outside of the data driver 700 on the second direction DR2. That is, the first pad portion of PDA1 can be positioned closer to the edge of the display panel 100 than the data driver 700.

[0097] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to fixtures or probes during the inspection process, or they may be connected to a circuit board for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0098] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P data lines DL (P is a positive integer of 2 or greater), and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0099] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each unit pixel UPX in the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be located on the upper side of the display area DAA.

[0100] Figure 5 It is shown Figure 4 A layout diagram of an embodiment of the display area. Figure 5 It is a plan view. As used herein, "plan view" refers to a view on a substrate SSUB (see [link to SSUB]). Figure 6 A view in the thickness direction (i.e., the third direction DR3).

[0101] refer to Figure 5 Each of the multiple unit pixels UPX may include a first emission region EA1 as the emission region of the first pixel PX1, a second emission region EA2 as the emission region of the second pixel PX2, and a third emission region EA3 as the emission region of the third pixel PX3.

[0102] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color of light can be light in the blue band, the second color of light can be light in the green band, and the third color of light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 380 nanometers (nm) to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0103] In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a circular shape. For example, in the plan view, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have the same circular shape.

[0104] In the plan view, the dimensions (e.g., aperture area) of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be the same. Here, the dimensions of each of the emission regions EA1, EA2, and EA3 can refer to the area of ​​the emission region based on its dimensions in the first direction DR1 and the second direction DR2.

[0105] exist Figure 5 The illustration shows that each of the plurality of unit pixels (UPXs) includes three emission regions EA1, EA2, and EA3, but embodiments of this specification are not limited thereto. In another embodiment, each of the plurality of unit pixels (UPXs) may include four emission regions.

[0106] Furthermore, the settings of the emission regions EA1, EA2, and EA3 for multiple unit pixel UPXs are not limited to... Figure 5 The settings are illustrated in the diagram. For example, the emission regions EA1, EA2, and EA3 of multiple unit pixels UPX can be set as a strip structure arranged in the first direction DR1, or as a diamond pattern. structure.

[0107] Each of pixels PX1, PX2, and PX3 may include an anode electrode AND. For example, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include an anode electrode AND. In a planar view, the anode electrode AND of the first pixel PX1 (hereinafter referred to as the first anode electrode), the anode electrode AND of the second pixel PX2 (hereinafter referred to as the second anode electrode), and the anode electrode AND of the third pixel PX3 (hereinafter referred to as the third anode electrode) may each have a circular shape. For example, the first anode electrode may have the same shape as the first emission region EA1, the second anode electrode may have the same shape as the second emission region EA2, and the third anode electrode may have the same shape as the third emission region EA3. In other words, in a planar view, the first anode electrode, the second anode electrode, and the third anode electrode may have the same circular shape.

[0108] In the plan view, the dimensions (e.g., area) of the first anode electrode, the second anode electrode, and the third anode electrode can be the same. Here, the dimension of each anode electrode AND can refer to the area of ​​the anode electrode AND based on its dimensions in the first direction DR1 and the second direction DR2.

[0109] Lens LNS can be disposed on emission regions EA1, EA2, and EA3 respectively. For example, lens LNS can be disposed on each of the first emission region EA1, the second emission region EA2, and the third emission region EA3. In a plan view, lens LNS can have a hexagonal shape.

[0110] A wire-grid polarizer (WGP) can be positioned on the emission regions EA1, EA2, and EA3. The WGP can comprise multiple grid patterns (GP). For example... Figure 5 As shown, each grid pattern GP can have a rectangular shape extending along the second direction DR2. Further, as... Figure 5 As shown, the grid pattern GP can be arranged along the first direction DR1. The grid patterns GP can be arranged to be spaced apart from each other in the first direction DR1. The wire grid polarizer WGP can contain at least one of aluminum (Al), silver (Ag), and gold (Au). For example, each of the grid patterns GP can be made of a material containing at least one of aluminum (Al), silver (Ag), and gold (Au).

[0111] Figure 6 The diagram is along Figure 5 A cross-sectional view of an example of the display panel 100 taken by line X-X'.

[0112] refer to Figure 6 The display panel 100 may include a semiconductor substrate SBP, a light-emitting element substrate EBP, a display element layer EML, a packaging layer TFE, and an optical layer OPL.

[0113] The semiconductor substrate (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating layers covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0114] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0115] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to its drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0116] The lower insulating layer (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating layer (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating layer (SINS) can be disposed on the lower insulating layer (BINS).

[0117] Each of the source region SA and the drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region SA can be located on the other side of the gate electrode GE.

[0118] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating layer BINS, the first low-concentration impurity region LDD1 can be a region with an impurity concentration lower than that of the source region SA. Due to the lower insulating layer BINS, the second low-concentration impurity region LDD2 can be a region with an impurity concentration lower than that of the drain region DA. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0119] The first semiconductor insulating layer SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x The inorganic layer is formed in this way, but the embodiments in this specification are not limited thereto.

[0120] The second semiconductor insulating layer SINS2 can be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be made of silicon oxide (SiO2). x The inorganic layer is formed in this way, but the embodiments in this specification are not limited thereto.

[0121] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating layer (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating layer (SINS1) and the second semiconductor insulating layer (INS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0122] A third semiconductor insulating layer (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating layer (SINS3). The third semiconductor insulating layer (SINS3) can be made of silicon oxide (SiO2). x The inorganic layer is formed in this way, but the embodiments in this specification are not limited thereto.

[0123] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0124] The light-emitting element substrate EBP includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating layers INS1 to INS9. Additionally, the light-emitting element substrate EBP includes multiple insulating layers INS1 to INS11 disposed between the first conductive layer ML1 to the eighth conductive layer ML8.

[0125] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor substrate SBP to achieve Figure 4 The circuitry of the first pixel PX1 shown is illustrated. For example, the first transistors T1 to the sixth transistor T6 are formed solely on the semiconductor substrate SBP, and the connection between the first transistors T1 to the sixth transistor T6, the first capacitor C1, and the second capacitor C2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0126] A first insulating layer INS1 may be disposed on the semiconductor substrate SBP. Each of the first vias VA1 may penetrate the first insulating layer INS1 to connect to a contact terminal CTE exposed from the semiconductor substrate SBP. Each of the first conductive layers ML1 may be disposed on the first insulating layer INS1 and may connect to the first via VA1.

[0127] A second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second vias VA2 may penetrate the second insulating layer INS2 and be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be disposed on the second insulating layer INS2 and may be connected to the second via VA2.

[0128] A third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the third vias VA3 may penetrate the third insulating layer INS3 and be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating layer INS3 and may be connected to the third via VA3.

[0129] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the fourth vias VA4 may penetrate the fourth insulating layer INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may connect to the fourth via VA4.

[0130] A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 may penetrate the fifth insulating layer INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may connect to the fifth via VA5.

[0131] A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 may penetrate the sixth insulating layer INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may connect to the sixth via VA6.

[0132] A seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating layer INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating layer INS7 and can connect to the seventh via VA7.

[0133] An eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 may penetrate the eighth insulating layer INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and may connect to the eighth via VA8.

[0134] The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first through-holes VA1 to VA8 can be made of substantially the same material. The first insulating layers INS1 to INS8 can be made of silicon oxide (SiO2). x The inorganic layer is formed in this way, but the embodiments in this specification are not limited thereto.

[0135] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first through-hole VA1, the second through-hole VA2, the third through-hole VA3, the fourth through-hole VA4, the fifth through-hole VA5, and the sixth through-hole VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately... The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately Furthermore, the thickness of each of the following through holes—VA1, VA2, VA3, VA4, VA5, and VA6—can be approximately [missing information].

[0136]

[0137] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 can be approximately

[0138] The ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be made of silicon oxide (SiO2). x The inorganic layer is formed in this way, but the embodiments in this specification are not limited thereto.

[0139] Each of the ninth vias VA9 can penetrate the ninth insulating layer INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them. The thickness of the ninth via VA9 can be approximately...

[0140] The display element layer EML can be disposed on the light-emitting element base plate EBP. The display element layer EML may include: light-emitting element LE, pixel limiting layer PDL and multiple trench TRC. Each light-emitting element LE includes a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth through hole VA10, an anode electrode AND, a light-emitting stack ES and a cathode electrode CAT.

[0141] The reflective electrode layer RL can be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as... Figure 6 As shown, the reflective electrode layer RL may include a first reflective electrode to a fourth reflective electrode RL1, RL2, RL3 and RL4.

[0142] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth through-hole VA9. The first reflective electrodes RL1 may be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0143] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the second reflective electrode RL2 may include aluminum (Al).

[0144] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0145] The fourth reflective electrode RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0146] Since the second reflective electrode RL2 is the electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately... And the thickness of the second reflective electrode RL2 can be

[0147]

[0148] The tenth insulating layer INS10 can be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 can be disposed between horizontally adjacent reflective electrode layers RL. The tenth insulating layer INS10 can be disposed on the reflective electrode layer RL in the third pixel PX3. The tenth insulating layer INS10 can be made of silicon oxide (SiO2). x The inorganic layer is formed in this way, but the embodiments in this specification are not limited thereto.

[0149] The eleventh insulating layer INS11 can be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments in this specification are not limited thereto. In another embodiment, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light reflected from the light emitted from the light-emitting element LE by the reflective electrode layer RL passes.

[0150] To match the resonant distance of light emitted from the light-emitting element LE in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may not be disposed below the anode electrode AND of the first pixel PX1. The anode electrode AND of the first pixel PX1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating layer INS11 may be disposed below the anode electrode AND of the second pixel PX2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed below the anode electrode AND of the third pixel PX3.

[0151] In summary, the distance between the anode electrode AND and the reflective electrode layer RL can be different in the first pixel PX1, the second pixel PX2, and the third pixel PX3. To adjust the distance from the reflective electrode layer RL to the cathode electrode CAT according to the dominant wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 can be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, in... Figure 6 The figure shows that the distance between the anode electrode AND and the reflective electrode layer RL in the third pixel PX3 is greater than the distance between the anode electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the anode electrode AND and the reflective electrode layer RL in the first pixel PX1. The distance between the anode electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the anode electrode AND and the reflective electrode layer RL in the first pixel PX1. However, the specification of this disclosure is not limited thereto.

[0152] According to one embodiment, in a planar view, the reflective electrode layer RL (hereinafter referred to as the first reflective electrode layer), which is configured to overlap with the first emission region EA1 of the first pixel PX1, the reflective electrode layer RL (hereinafter referred to as the second reflective electrode layer), which is configured to overlap with the second emission region EA2 of the second pixel PX2, and the reflective electrode layer RL (hereinafter referred to as the third reflective electrode layer), which is configured to overlap with the third emission region EA3 of the third pixel PX3, can each have a circular shape. For example, the first reflective electrode layer can have the same shape as the first emission region EA1 (or the first anode electrode), the second reflective electrode layer can have the same shape as the second emission region EA2 (or the second anode electrode), and the third reflective electrode layer can have the same shape as the third emission region EA3 (or the third anode electrode). In other words, in a planar view, the first reflective electrode layer, the second reflective electrode layer, and the third reflective electrode layer can all have the same circular shape.

[0153] In the plan view, the dimensions (e.g., area) of the first reflective electrode layer, the second reflective electrode layer, and the third reflective electrode layer can be the same. Here, the dimension of each reflective electrode layer RL can refer to the area of ​​the reflective electrode layer RL based on its dimensions in the first direction DR1 and the second direction DR2.

[0154] Furthermore, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are illustrated in the embodiments of this specification, a twelfth insulating layer may be added, disposed below the anode electrode AND of the first pixel PX1. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer may be disposed below the anode electrode AND of the second pixel PX2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be disposed below the anode electrode AND of the third pixel PX3.

[0155] Each of the tenth vias VA10 can penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second pixel PX2 and the third pixel PX3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the tenth via VA10 in the second pixel PX2 can be less than the thickness of the tenth via VA10 in the third pixel PX3.

[0156] The anode AND of each of the light-emitting elements LE can be disposed on the tenth insulating layer INS10 and connected to the tenth via VA10. The anode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The anode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. For example, the anode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0157] A pixel defining layer (PDL) can be disposed on a portion of the anode electrode AND of each of the light-emitting elements (LE). The PDL can cover the edge of the anode electrode AND of each of the light-emitting elements (LE). The PDL can be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0158] The first emission region EA1 can be defined as the region in the first pixel PX1 where an anode electrode AND, a light-emitting stack ES, and a cathode electrode CAT are sequentially stacked to emit light. The second emission region EA2 can be defined as the region in the second pixel PX2 where an anode electrode AND, a light-emitting stack ES, and a cathode electrode CAT are sequentially stacked to emit light. The third emission region EA3 can be defined as the region in the third pixel PX3 where an anode electrode AND, a light-emitting stack ES, and a cathode electrode CAT are sequentially stacked to emit light.

[0159] The pixel defining layer PDL may include first pixel defining layers to third pixel defining layers PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 may be disposed on the edge of the anode electrode AND of each of the light-emitting elements LE, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO2). x An inorganic layer of the same type is formed, but the embodiments in this specification are not limited thereto. In another embodiment, the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 may each have approximately The thickness.

[0160] When the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 are formed into a single pixel-defining layer, the height of the single pixel-defining layer increases, making the first encapsulation inorganic layer TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of film coverage on the inclined portion to the degree of film coverage on the flat portion. The lower the step coverage, the more likely the film is to be cut at the inclined portion.

[0161] Therefore, to prevent the first encapsulated inorganic layer TFE1 from being cut off due to step coverage, the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 can have a cross-sectional structure containing the step portion. For example, the width of the first pixel-defining layer PDL1 can be greater than the width of the second pixel-defining layer PDL2 and the width of the third pixel-defining layer PDL3, and the width of the second pixel-defining layer PDL2 can be greater than the width of the third pixel-defining layer PDL3. The width of the first pixel-defining layer PDL1 refers to the horizontal length of the first pixel-defining layer PDL1 defined in the first direction DR1 and the second direction DR2.

[0162] Each of the plurality of trench TRCs can penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. Furthermore, each of the plurality of trench TRCs can penetrate the eleventh insulating layer INS11. The tenth insulating layer INS10 can be partially recessed at each of the plurality of trench TRCs.

[0163] At least one trench TRC can be set between adjacent pixels PX1, PX2, and PX3. Although Figure 6 The illustration shows two trench TRCs positioned between adjacent pixels PX1, PX2, and PX3, but the embodiments described in this specification are not limited thereto.

[0164] A light-emitting stacked ES can include multiple intermediate layers. Figure 6 The illustration shows a three-tiered structure of a light-emitting stack ES, comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3; however, the embodiments described in this specification are not limited to this. For example, the light-emitting stack ES may have a two-tiered structure comprising two intermediate layers.

[0165] In a three-series cascade structure, the light-emitting stack ES can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit light of different colors. For example, the light-emitting stack ES may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a second color, and a third stacked layer IL3 that emits light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0166] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked. In this case, the light-emitting stack can emit white light in which light of the first color (e.g., red light) from the first organic light-emitting layer, light of the second color (e.g., green light) from the second organic light-emitting layer, and light of the third color (e.g., blue light) from the third organic light-emitting layer are mixed. Accordingly, white light can be emitted from each of the first emission region EA1, the second emission region EA2, and the third emission region EA3. Here, white light that has passed through the first emission region EA1 can be incident on the first color filter CF1, white light that has passed through the second emission region EA2 can be incident on the second color filter CF2, and white light that has passed through the third emission region EA3 can be incident on the third color filter CF3.

[0167] A first charge generation layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0168] A second charge generation layer for supplying charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0169] A first stacked layer IL1 can be disposed on the anode electrode AND and the pixel defining layer PDL, and can be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be separated between adjacent pixels PX1, PX2, and PX3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be separated between adjacent pixels PX1, PX2, and PX3. A cavity ESS or empty space can be disposed between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be configured to cover the second stacked layer IL2 in each of the trench TRCs. For example, in a three-in-series structure, each of the plurality of trench TRCs can be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent pixels PX1, PX2, and PX3. In addition, in the two-series structure, each of the trench TRCs can be a structure for cutting off the lower intermediate layer and the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer.

[0170] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To cut the first to third stacked layers IL1, IL2, and IL3 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, an alternative structure can exist to replace the trench TRCs. For example, instead of trench TRCs, inverted conical partition walls can be disposed on the pixel defining layer PDL.

[0171] The number of stacked layers IL1, IL2, and IL3 emitting different colors of light is not limited to Figure 6 The quantities shown are as described. For example, the light-emitting stack ES may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one intermediate layer and supplying charge to the other intermediate layer may be disposed between the two intermediate layers.

[0172] in addition, Figure 6The illustration shows that the first to third stacked layers IL1, IL2, and IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, the embodiments described herein are not limited to this. For example, the first stacked layer IL1 may be disposed in the first emission region EA1, but may not be disposed in the second emission region EA2 and the third emission region EA3. Furthermore, the second stacked layer IL2 may be disposed in the second emission region EA2, but may not be disposed in the first emission region EA1 and the third emission region EA3. Further, the third stacked layer IL3 may be disposed in the third emission region EA3, but may not be disposed in the first emission region EA1 and the second emission region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0173] The cathode electrode CAT can be disposed on the third stacked layer IL3. The cathode electrode CAT can be disposed on the third stacked layer IL3 in each of the multiple trench TRCs. The cathode electrode CAT can be formed of a transparent conductive material (TCO) that is transmissive to light, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the cathode electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be improved in each of the first to third pixels PX1, PX2, and PX3 due to the microcavity effect.

[0174] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE2 for preventing oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0175] The first encapsulation inorganic layer TFE1 can be disposed on the cathode electrode CAT. The first encapsulation inorganic layer TFE1 can be formed in which silicon nitride (SiN) is alternately stacked. x ), silicon oxynitride (SiON) and silicon oxide (SiO) x Multiple layers of one or more inorganic layers in ) . The first encapsulated inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0176] The second encapsulation inorganic layer TFE2 can be disposed on the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO) xThe second encapsulation inorganic layer TFE2 can be formed using atomic layer deposition (ALD) technology, but the embodiments described herein are not limited to this. In another embodiment, the second encapsulation inorganic layer TFE2 can be formed using atomic layer deposition (ALD) technology. The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0177] The organic layer APL can be a layer used to improve the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL can be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0178] The optical layer OPL may include a color filter layer CFL, a lens layer LSL, a filler layer FIL, a capping layer CVL, a delay layer QWP, and a wire grid polarizer WGP.

[0179] The color filter layer CFL may include multiple color filters CF1, CF2, and CF3. These multiple color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the organic layer APL.

[0180] In the planar view, the first color filter CF1 may overlap with the first emission region EA1 (e.g., a red light emission region) of the first pixel PX1. The first color filter CF1 can transmit light of a first color (e.g., light in the red band). The red band may be approximately 600 nm to 750 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0181] In the planar view, the second color filter CF2 may overlap with the second emission region EA2 (e.g., the green light emission region) of the second pixel PX2. The second color filter CF2 can transmit light of a second color (e.g., light in the green band). The green band can be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0182] In a planar view, the third color filter CF3 can overlap with the third emission region EA3 (e.g., the blue light emission region) of the third pixel PX3. The third color filter CF3 can transmit light of a third color (e.g., light in the blue band). The blue band can be approximately 370 nm to 460 nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0183] A retardation layer QWP (or retardation film or retardation plate) can be disposed on the color filter layer CFL. For example, the retardation layer QWP can be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The retardation layer QWP can be a λ / 4 plate (quarter-wave plate), but the embodiments in this specification are not limited thereto. In another embodiment, the stepped portion of the color filter layer CFL can be planarized by the retardation layer.

[0184] A wire-grid polarizer (WGP) can be disposed on a delay layer (QWP). The wire-grid polarizer (WGP) and the delay layer (QWP) can constitute a polarization member. For example, according to one embodiment, the polarization member may include the delay layer (QWP) and the wire-grid polarizer (WGP). The wire-grid polarizer (WGP) may include a plurality of grid patterns (GP) as described above.

[0185] A wire-grid polarizer (WGP) can transmit light with a specific polarization direction while simultaneously reflecting light with another polarization direction to recover it. Such a WGP can be used as a reflective polarizer because it exhibits higher polarization separation performance than other polarizers. For example, a WGP is a device that uses a conductive wire grid to generate polarization and can have a structure in which multiple wires made of conductive material are arranged in a nanoscale parallel and periodic manner on a retardation layer QWP to form a grid pattern GP. In a WGP comprising multiple grid patterns GP, diffraction of the incident light does not occur if the period of the grid pattern GP is smaller than the wavelength of the incident light. Therefore, a WGP can reflect components with vibration directions parallel to the grid pattern GP (such as transverse electric (TE) polarization (e.g., S-wave)) while transmitting components in the incident light with vibration directions perpendicular to the conductive grid pattern GP (such as transverse magnetic (TM) polarization (e.g., P-wave)). In other words, when the arrangement period of the grating pattern GP is shorter than the wavelength of the electromagnetic wave incident on the linear grating polarizer WGP, the WGP can transmit polarization components perpendicular to the grating pattern GP (e.g., P-waves) while reflecting polarization components parallel to the grating pattern GP (e.g., S-waves). Because the WGP uses a grating pattern GP made of metal, its light reflection efficiency is very high. Therefore, since the reflected light can be reflected again, the light can be recovered so that all the light becomes polarized.

[0186] The lens layer LSL can be disposed on the linear grid polarizer WGP. The lens layer LSL may include multiple lenses LNS. The multiple lenses LNS can be disposed on the linear grid polarizer WGP to overlap with the first color filter CF1, the second color filter CF2, and the third color filter CF3 respectively in a planar view. Each of the multiple lenses LNS can be a structure for improving the ratio of light directed in front of the display device 10. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0187] A filler layer (FIL) can be disposed on a lens layer (LSL). For example, a filler layer (FIL) can be disposed on multiple lenses (LNS). The filler layer (FIL) can have a predetermined refractive index such that light propagates in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lenses (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0188] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can serve as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly coated onto the filler layer FIL.

[0189] Figure 7 The diagram is along Figure 5 Another example of a cross-sectional view of the display panel 100 taken by line X-X'.

[0190] Figure 7 Display device and Figure 6 The difference in this display device is that it does not include the aforementioned color filter layer (CFL). The following description will focus primarily on this difference. For example, the aforementioned Figure 6 The display panel 100 may be a "white OLED" type display panel in which the light-emitting stacked ES of pixels PX1, PX2, and PX3 in the unit pixel UPX all provide white light, as will be described later. Figure 7 The display panel 100 may be an "RGB-OLED" type display panel that includes a light-emitting stack ES of pixels PX1, PX2 and PX3 in a unit pixel UPX that respectively provide red light, green light and blue light.

[0191] like Figure 7 As shown, since the display panel 100 does not include the color filter layer CFL, the organic layer APL and the delay layer QWP can contact each other.

[0192] According to one embodiment, Figure 7The light-emitting stacked element (ES) can provide different colors of light for each pixel. For example, the light-emitting stacked ES of the first pixel PX1 may include a red organic light-emitting layer that provides red light, the light-emitting stacked ES of the second pixel PX2 may include a green organic light-emitting layer that provides green light, and the light-emitting stacked ES of the third pixel PX3 may include a blue organic light-emitting layer that provides blue light. In other words, the light-emitting stacked ES may include the aforementioned red organic light-emitting layer in the first emission region EA1 of the first pixel PX1, the aforementioned green organic light-emitting layer in the second emission region EA2 of the second pixel PX2, and the aforementioned blue organic light-emitting layer in the third emission region EA3 of the third pixel PX3. Accordingly, the first pixel PX1 can provide red light generated by the red organic light-emitting layer, the second pixel PX2 can provide green light generated by the green organic light-emitting layer, and the third pixel PX3 can provide blue light generated by the blue organic light-emitting layer.

[0193] Figure 8 The diagram is along Figure 5 Another example of a cross-sectional view of the display panel 100 taken by line X-X'.

[0194] Figure 8 Display device and Figure 6 The difference in this display device is that it does not include the aforementioned lens layer LSL. The following description will focus primarily on this difference.

[0195] like Figure 8 As shown, since the display panel 100 does not include the aforementioned lens layer LSL, the wire grid polarizer WGP and the cover layer CVL can contact each other.

[0196] Figure 9 The diagram is along Figure 5 Another example of a cross-sectional view of the display panel 100, taken by line X-X'.

[0197] Figure 9 Display device and Figure 7 The difference in this display device is that it does not include the aforementioned lens layer LSL. The following description will focus primarily on this difference.

[0198] like Figure 9 As shown, since the display panel 100 does not include the aforementioned lens layer LSL, the wire grid polarizer WGP and the cover layer CVL can contact each other.

[0199] Figure 10 It is a diagram used to describe the optical paths of the principal ray and the reflected ray.

[0200] The light L1 emitted from the light-emitting element (hereinafter referred to as the main light) can pass through the wire grid polarizer WGP and be emitted to the outside.

[0201] Simultaneously, light that has been reflected from the wire grid polarizer WGP but has not passed through it, after passing through the retardation layer QWP and reaching the anode electrode AND, is reflected from the anode electrode AND, and this reflected light L2 passes through the retardation layer QWP again to be incident on the wire grid polarizer WGP. At this point, because the reflected light L2 passes through the retardation layer QWP twice, its polarization direction is changed, so it can pass through the wire grid polarizer WGP and be emitted to the outside. Accordingly, the reflected light L2 can be recovered. In this way, since the reflected light L2 can be recovered by the wire grid polarizer WGP, the light efficiency of the display device can be effectively improved.

[0202] Figure 11 It is a diagram showing various shapes of the emission area, and Figure 12 It is used to describe according to Figure 11 A graph showing the light recovery efficiency of the principal ray angle (CRA) for each emission region.

[0203] Figure 11 The diagram shows a circular emission area EMA1 (hereinafter referred to as the first emission area EMA1), a rectangular emission area EMA2 (hereinafter referred to as the second emission area EMA2) with a ratio of 1:0.7, a square emission area EMA3 (hereinafter referred to as the third emission area EMA3) with a ratio of 1:1, a rectangular emission area EMA4 (hereinafter referred to as the fourth emission area EMA4) with a ratio of 1:1.3, and a rectangular emission area EMA5 (hereinafter referred to as the fifth emission area EMA5) with a ratio of 1:2.5. Here, the ratio refers to... Figure 11 The ratio of the horizontal to the vertical side of the rectangular emission region in the diagram. Meanwhile, Figure 11 The dimensions (e.g., aperture area) of the first emission region EMA1, the second emission region EMA2, the third emission region EMA3, the fourth emission region EMA4, and the fifth emission region EMA5 can be the same.

[0204] exist Figure 12 In the diagram, curve CV1 indicates the light recovery efficiency of the CRA in the first emission region EMA1, curve CV2 indicates the light recovery efficiency of the CRA in the second emission region EMA2, curve CV3 indicates the light recovery efficiency of the CRA in the third emission region EMA3, curve CV4 indicates the light recovery efficiency of the CRA in the fourth emission region EMA4, and curve CV5 indicates the light recovery efficiency of the CRA in the fifth emission region EMA5.

[0205] As mentioned above Figure 10 As shown, CRA can refer to the angle θ between an imaginary line VL perpendicular to the display surface of the display panel 100 and the main light L1 emitted from the display surface. Figure 12 In this diagram, the horizontal axis represents the CRA value of each of eight arbitrary points (e.g., eight points) between the center of the display surface and one of its edges. For example, a value of 0 on the horizontal axis means that the CRA at the center of the display surface is 0 degrees, and a value of 35 on the horizontal axis means that the CRA at one of the edges of the display surface is 35 degrees. The CRA tends to increase as one moves from the center of the display surface toward one of its edges.

[0206] exist Figure 12 In the figure, the vertical axis represents the light recovery efficiency.

[0207] exist Figure 12 In this measurement, the measurement direction may include a first direction DR1 (e.g., left-right direction), a second direction DR2 (e.g., up-down direction), and a fourth direction DR4 (e.g., diagonal direction). Here, the fourth direction DR4 may be a diagonal direction located between the first direction DR1 and the second direction DR2. The measurement direction may be, for example, the direction of CRA.

[0208] exist Figure 12 In the middle, the value is 2.8 square micrometers (μm) 2 ), 5.2μm 2 and 10.2μm 2 These represent the areas of the emission region in the planar diagram. Here, 2.8 μm 2 The emission area can refer to the area of ​​each emission region when it is a red light emission region emitting red light, 5.2μm. 2 The emission area can refer to the area when each emission region is a green light emission region that emits green light, and is 10.2 μm. 2 The emission area can refer to the area when each emission region is a blue light emission region that emits blue light.

[0209] If possible Figure 12 As can be seen, regardless of the measurement direction, the first curve CV1 of the first emission region EMA1 can have essentially the same shape. For example, when the area of ​​the first emission region EMA1 is 2.8 μm... 2When the emission region has a circular shape, the first curve CV1 based on the first direction DR1, the first curve CV1 based on the second direction DR2, and the first curve CV1 based on the fourth direction DR4 can have almost the same shape. In other words, when the emission region has a circular shape, it is found that the light recovery efficiency of each CRA in the first direction DR1, the light recovery efficiency of each CRA in the second direction DR2, and the light recovery efficiency of each CRA in the fourth direction DR4 are almost the same. Therefore, when the emission region has a circular shape, the brightness of the light in the first direction DR1, the second direction DR2, and the fourth direction DR4 can remain almost constant. Accordingly, light with approximately the same brightness can be emitted regardless of the azimuth angle on the display surface (i.e., it is uniform regardless of the azimuth angle), which makes it possible to effectively improve the image quality of the display device.

[0210] At the same time, it can be seen from Figure 12 As can be seen, the second curve CV2 of the second emission region EMA2, the third curve CV3 of the third emission region EMA3, the fourth curve CV4 of the fourth emission region EMA4, and the fifth curve CV5 of the fifth emission region EMA5 have large deviations depending on the measurement directions DR1, DR2, and DR4.

[0211] Figures 13A to 13C This shows the ratio of the horizontal to the vertical sides of the corresponding emission area. Figure 11 A graph showing the light recovery efficiency of each emission region.

[0212] Figure 13A This is a graph showing the light recovery efficiency of each emission region when CRA is measured in the first direction DR1. Figure 13B This is a graph showing the light recovery efficiency of each emission region when CRA is measured in the second direction DR2, and Figure 13C This is a graph showing the light recovery efficiency of each emission region when CRA is measured in the fourth direction DR4.

[0213] exist Figures 13A to 13C In the diagram, the horizontal axis represents the ratio of the horizontal to the vertical sides of the rectangular emission region, and the vertical axis represents the light recovery efficiency.

[0214] exist Figures 13A to 13C In the diagram, the first curve CV1' represents the emission region with a diameter of 10.2 μm. 2 The light recovery efficiency is calculated based on the ratio of the horizontal to the vertical sides of the rectangular emission area. The second curve, CV2', represents the light recovery efficiency when the emission area has a diameter of 5.2 μm. 2 The light recovery efficiency is determined by the ratio of the horizontal to vertical sides of the rectangular emitting area, and the third curve CV3' represents the light recovery efficiency when the emitting area has a diameter of 2.8 μm. 2The light recovery efficiency is determined by the ratio of the horizontal to the vertical sides of the rectangular emission region when the area is large.

[0215] Figures 13A to 13C The points in region A represent the light recovery efficiency of a circular emission region (e.g., EMA1).

[0216] like Figures 13A to 13C As shown, regardless of the measurement direction, the circular emission region can have approximately the same level of light recovery efficiency.

[0217] At the same time, refer to Figures 13A to 13C The curve in the rectangular emission area was found (e.g., set to...). Figures 13A to 13C The curves in regions other than region A have large deviations depending on the measurement direction.

[0218] Figures 14A to 14E It is a graph used to describe the light recovery efficiency based on the main light and reflected light.

[0219] Figure 14A It can be shown above Figure 11 A diagram of the primary light L1 and the reflected light L2 (e.g., the recovered light) in the first emission region EMA1.

[0220] Figure 14B It can be shown above Figure 11 A diagram of the primary light L1 and the reflected light L2 (e.g., the recovered light) in the second emission region EMA2.

[0221] Figure 14C It can be shown above Figure 11 A diagram of the primary light L1 and the reflected light L2 (e.g., the recovered light) in the third emission region EMA3.

[0222] Figure 14D It can be shown above Figure 11 A diagram of the primary light L1 and the reflected light L2 (e.g., the recovered light) in the fourth emission region EMA4.

[0223] Figure 14E It can be shown above Figure 11 A diagram of the primary light L1 and the reflected light L2 (e.g., the recovered light) in the fifth emission region EMA5.

[0224] The larger the overlap area L12 between the main light L1 and the reflected light L2, the higher the light recovery efficiency can be. For example... Figures 14A to 14E As shown, the overlap region L12 between the primary light L1 and the reflected light L2 from the first emission region EMA1, which has a circular shape, is the largest. Therefore, it is demonstrated that the light recovery efficiency is high when the emission region has a circular shape.

[0225] Figure 15This is a perspective view of a head-mounted display according to one embodiment. Figure 16 It is a diagram. Figure 15 An exploded perspective view of an example of a head-mounted display.

[0226] refer to Figure 15 and Figure 16 According to one embodiment, a head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0227] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2 The display devices 10 described are substantially the same, so the descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0228] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0229] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0230] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0231] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0232] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 15 and Figure 16 The illustration shows the first eyepiece 1210 and the second eyepiece 1220 being configured separately, but the embodiments described herein are not limited to this. In another embodiment, the first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0233] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0234] A headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively positioned on the user's left and right eyes. When the display device housing 1100 is implemented to be lightweight and compact, such as... Figure 17 As shown, the head-mounted display 1000 can be provided with an eyeglass frame instead of the headband 1300.

[0235] Additionally, the head-mounted display 1000 may further include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a WiFi module, or a Bluetooth module.

[0236] Figure 17 This is a perspective view of a head-mounted display according to one embodiment.

[0237] refer to Figure 17 According to one embodiment, the head-mounted display 1000_1 can be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. According to one embodiment, the head-mounted display 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path alteration component 1070, and a display device housing 1200_1.

[0238] The display device housing 1200_1 may include a display device 10_3, an optical component 1060, and a light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060, and after its light path is changed by the light path changing component 1070, it can be provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image that combines the virtual image displayed on the display device 10_3 with the real image viewed through the right eye lens 1020.

[0239] Figure 17 The illustration shows the display device housing 1200_1 positioned at the right end of the support frame 1030, but the embodiments described herein are not limited to this. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, in which case the image of the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0240] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the preferred embodiments disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A display device, comprising: substrate; Multiple first electrodes are disposed on the substrate; A pixel defining layer, defining multiple emission regions respectively corresponding to the plurality of first electrodes; A light-emitting layer is disposed on the plurality of first electrodes; as well as The second electrode is located on the light-emitting layer. In the plan view, each of the plurality of emission regions has a circular shape, and In the plan view, the plurality of emission regions have the same size.

2. The display device according to claim 1, further comprising: A wire grid polarizer is located on the second electrode.

3. The display device according to claim 2, further comprising: Lens layer on the linear grid polarizer.

4. The display device according to claim 2, further comprising: A color filter layer is located between the second electrode and the wire grid polarizer.

5. The display device according to claim 2, further comprising: A delay layer is located between the second electrode and the wire grid polarizer.

6. The display device according to claim 1, wherein In the plan view, each of the plurality of first electrodes has a circular shape.

7. The display device of claim 6, wherein, In the plan view, the plurality of first electrodes have the same dimensions.

8. The display device according to any one of claims 1 to 7, further comprising: Multiple reflective electrode layers are respectively connected to the multiple first electrodes.

9. The display device of claim 8, wherein, In the plan view, each of the plurality of reflective electrode layers has a circular shape, and In the plan view, the plurality of reflective electrode layers have the same size.

Images